Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	96.75	96.15	97.00		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	96.75	96.15	97.00		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T111,T167,T168

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T165,T56,T169

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T18,T19,T20

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T71,T72,T170
1	Covered	T71,T72,T170

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T8

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T8

---

FSM Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T5
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T3,T5
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T116,T118,T172
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T117,T190,T193
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T2,T3,T5
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Covered	T165,T214,T215
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T12,T71,T72
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T2,T3,T5
CheckFailError	317	Covered	T71,T72,T170
FsmStateError	289	Covered	T2,T3,T5
MacroEccCorrError	221	Covered	T111,T165,T56
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T2,T3,T5
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T2,T3,T5
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T71,T72,T170
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T3,T5
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T111,T165,T167
MacroEccCorrError->NoError	235	Covered	T56,T169,T212
NoError->AccessError	256	Covered	T2,T3,T5
NoError->CheckFailError	317	Covered	T71,T72,T170
NoError->FsmStateError	289	Covered	T3,T9,T10
NoError->MacroEccCorrError	221	Covered	T111,T165,T56

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T111,T167,T168
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T117,T216,T217
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T33,T102,T93
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T3,T5
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T165,T56,T169
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T165,T214,T215
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T18,T19,T20
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T5,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T3,T5,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T71,T72,T170
1	0	Covered	T71,T72,T170
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	404005320	403132969	0	0
DigestKnown_A	404005320	403132969	0	0
DigestOffsetMustBeRepresentable_A	1139	1139	0	0
EccErrorState_A	404005320	10672	0	0
ErrorKnown_A	404005320	403132969	0	0
FsmStateKnown_A	404005320	403132969	0	0
InitDoneKnown_A	404005320	403132969	0	0
InitReadLocksPartition_A	404005320	78643553	0	0
InitWriteLocksPartition_A	404005320	78643553	0	0
OffsetMustBeBlockAligned_A	1139	1139	0	0
OtpAddrKnown_A	404005320	403132969	0	0
OtpCmdKnown_A	404005320	403132969	0	0
OtpErrorState_A	404005320	37	0	0
OtpReqKnown_A	404005320	403132969	0	0
OtpSizeKnown_A	404005320	403132969	0	0
OtpWdataKnown_A	404005320	403132969	0	0
ReadLockPropagation_A	404005320	155759029	0	0
SizeMustBeBlockAligned_A	1139	1139	0	0
TlulGntKnown_A	404005320	403132969	0	0
TlulRdataKnown_A	404005320	403132969	0	0
TlulReadOnReadLock_A	404005320	8119	0	0
TlulRerrorKnown_A	404005320	403132969	0	0
TlulRvalidKnown_A	404005320	403132969	0	0
WriteLockPropagation_A	404005320	2493125	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	404005320	26959521	0	0
u_state_regs_A	404005320	403132969	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	403132969	0	0
T1	17259	17009	0	0
T2	380768	380755	0	0
T3	639258	639247	0	0
T4	57927	57636	0	0
T5	23059	22792	0	0
T6	19989	19663	0	0
T7	207438	205765	0	0
T8	34677	34359	0	0
T9	9893	9640	0	0
T10	14807	14631	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	403132969	0	0
T1	17259	17009	0	0
T2	380768	380755	0	0
T3	639258	639247	0	0
T4	57927	57636	0	0
T5	23059	22792	0	0
T6	19989	19663	0	0
T7	207438	205765	0	0
T8	34677	34359	0	0
T9	9893	9640	0	0
T10	14807	14631	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1139	1139	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	10672	0	0
T42	905786	0	0	0
T71	16144	3956	0	0
T72	0	2699	0	0
T93	50761	0	0	0
T108	20259	0	0	0
T110	12373	0	0	0
T111	11806	0	0	0
T119	67674	0	0	0
T129	59566	0	0	0
T164	563152	0	0	0
T170	0	4017	0	0
T188	11593	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	403132969	0	0
T1	17259	17009	0	0
T2	380768	380755	0	0
T3	639258	639247	0	0
T4	57927	57636	0	0
T5	23059	22792	0	0
T6	19989	19663	0	0
T7	207438	205765	0	0
T8	34677	34359	0	0
T9	9893	9640	0	0
T10	14807	14631	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	403132969	0	0
T1	17259	17009	0	0
T2	380768	380755	0	0
T3	639258	639247	0	0
T4	57927	57636	0	0
T5	23059	22792	0	0
T6	19989	19663	0	0
T7	207438	205765	0	0
T8	34677	34359	0	0
T9	9893	9640	0	0
T10	14807	14631	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	403132969	0	0
T1	17259	17009	0	0
T2	380768	380755	0	0
T3	639258	639247	0	0
T4	57927	57636	0	0
T5	23059	22792	0	0
T6	19989	19663	0	0
T7	207438	205765	0	0
T8	34677	34359	0	0
T9	9893	9640	0	0
T10	14807	14631	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	78643553	0	0
T1	17259	924	0	0
T2	380768	140552	0	0
T3	639258	381892	0	0
T4	57927	43209	0	0
T5	23059	13922	0	0
T6	19989	560	0	0
T7	207438	8382	0	0
T8	34677	383	0	0
T9	9893	4451	0	0
T10	14807	4307	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	78643553	0	0
T1	17259	924	0	0
T2	380768	140552	0	0
T3	639258	381892	0	0
T4	57927	43209	0	0
T5	23059	13922	0	0
T6	19989	560	0	0
T7	207438	8382	0	0
T8	34677	383	0	0
T9	9893	4451	0	0
T10	14807	4307	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1139	1139	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	403132969	0	0
T1	17259	17009	0	0
T2	380768	380755	0	0
T3	639258	639247	0	0
T4	57927	57636	0	0
T5	23059	22792	0	0
T6	19989	19663	0	0
T7	207438	205765	0	0
T8	34677	34359	0	0
T9	9893	9640	0	0
T10	14807	14631	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	403132969	0	0
T1	17259	17009	0	0
T2	380768	380755	0	0
T3	639258	639247	0	0
T4	57927	57636	0	0
T5	23059	22792	0	0
T6	19989	19663	0	0
T7	207438	205765	0	0
T8	34677	34359	0	0
T9	9893	9640	0	0
T10	14807	14631	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	37	0	0
T13	251791	0	0	0
T27	17157	0	0	0
T42	905786	0	0	0
T71	16144	0	0	0
T93	50761	0	0	0
T117	10942	1	0	0
T118	14412	0	0	0
T165	0	1	0	0
T172	11316	0	0	0
T188	11593	0	0	0
T202	20062	0	0	0
T216	0	1	0	0
T217	0	1	0	0
T218	0	1	0	0
T219	0	1	0	0
T220	0	1	0	0
T221	0	1	0	0
T222	0	1	0	0
T223	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	403132969	0	0
T1	17259	17009	0	0
T2	380768	380755	0	0
T3	639258	639247	0	0
T4	57927	57636	0	0
T5	23059	22792	0	0
T6	19989	19663	0	0
T7	207438	205765	0	0
T8	34677	34359	0	0
T9	9893	9640	0	0
T10	14807	14631	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	403132969	0	0
T1	17259	17009	0	0
T2	380768	380755	0	0
T3	639258	639247	0	0
T4	57927	57636	0	0
T5	23059	22792	0	0
T6	19989	19663	0	0
T7	207438	205765	0	0
T8	34677	34359	0	0
T9	9893	9640	0	0
T10	14807	14631	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	403132969	0	0
T1	17259	17009	0	0
T2	380768	380755	0	0
T3	639258	639247	0	0
T4	57927	57636	0	0
T5	23059	22792	0	0
T6	19989	19663	0	0
T7	207438	205765	0	0
T8	34677	34359	0	0
T9	9893	9640	0	0
T10	14807	14631	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	155759029	0	0
T2	380768	235762	0	0
T3	639258	396104	0	0
T4	57927	47338	0	0
T5	23059	14969	0	0
T6	19989	0	0	0
T7	207438	10283	0	0
T8	34677	6092	0	0
T9	9893	0	0	0
T10	14807	0	0	0
T11	0	154426	0	0
T12	0	55091	0	0
T33	0	5451	0	0
T34	0	18322	0	0
T106	67146	0	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1139	1139	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	403132969	0	0
T1	17259	17009	0	0
T2	380768	380755	0	0
T3	639258	639247	0	0
T4	57927	57636	0	0
T5	23059	22792	0	0
T6	19989	19663	0	0
T7	207438	205765	0	0
T8	34677	34359	0	0
T9	9893	9640	0	0
T10	14807	14631	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	403132969	0	0
T1	17259	17009	0	0
T2	380768	380755	0	0
T3	639258	639247	0	0
T4	57927	57636	0	0
T5	23059	22792	0	0
T6	19989	19663	0	0
T7	207438	205765	0	0
T8	34677	34359	0	0
T9	9893	9640	0	0
T10	14807	14631	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	8119	0	0
T2	380768	60	0	0
T3	639258	8	0	0
T4	57927	9	0	0
T5	23059	10	0	0
T6	19989	0	0	0
T7	207438	3	0	0
T8	34677	0	0	0
T9	9893	0	0	0
T10	14807	0	0	0
T11	0	56	0	0
T12	0	38	0	0
T33	0	8	0	0
T34	0	3	0	0
T106	67146	1	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	403132969	0	0
T1	17259	17009	0	0
T2	380768	380755	0	0
T3	639258	639247	0	0
T4	57927	57636	0	0
T5	23059	22792	0	0
T6	19989	19663	0	0
T7	207438	205765	0	0
T8	34677	34359	0	0
T9	9893	9640	0	0
T10	14807	14631	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	403132969	0	0
T1	17259	17009	0	0
T2	380768	380755	0	0
T3	639258	639247	0	0
T4	57927	57636	0	0
T5	23059	22792	0	0
T6	19989	19663	0	0
T7	207438	205765	0	0
T8	34677	34359	0	0
T9	9893	9640	0	0
T10	14807	14631	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	2493125	0	0
T7	207438	4410	0	0
T8	34677	5151	0	0
T9	9893	0	0	0
T10	14807	0	0	0
T12	585954	31007	0	0
T41	12668	0	0	0
T50	12795	0	0	0
T64	11560	0	0	0
T93	0	759	0	0
T95	0	22611	0	0
T100	7811	0	0	0
T102	0	3636	0	0
T103	0	3812	0	0
T106	67146	0	0	0
T129	0	10824	0	0
T134	0	767	0	0
T135	0	20741	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	26959521	0	0
T4	57927	0	0	0
T5	23059	2884	0	0
T6	19989	0	0	0
T7	207438	41447	0	0
T8	34677	17904	0	0
T9	9893	0	0	0
T10	14807	0	0	0
T12	585954	389365	0	0
T33	0	43525	0	0
T34	0	68907	0	0
T41	12668	0	0	0
T101	0	14130	0	0
T102	0	42768	0	0
T106	67146	5742	0	0
T117	0	3962	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	403132969	0	0
T1	17259	17009	0	0
T2	380768	380755	0	0
T3	639258	639247	0	0
T4	57927	57636	0	0
T5	23059	22792	0	0
T6	19989	19663	0	0
T7	207438	205765	0	0
T8	34677	34359	0	0
T9	9893	9640	0	0
T10	14807	14631	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T41,T64,T21

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T106,T56,T94

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T18,T19,T20

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T171
1	Covered	T171

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T34,T101

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T34,T101

---

FSM Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T5
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T3,T5
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T116,T118,T172
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T117,T110,T111
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T2,T3,T7
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Covered	T106,T94,T161
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T12,T71,T72
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T2,T3,T7
CheckFailError	317	Covered	T171
FsmStateError	289	Covered	T2,T3,T5
MacroEccCorrError	221	Covered	T106,T41,T64
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T2,T3,T12
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T2,T3,T7
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T171
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T3,T5
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T106,T41,T64
MacroEccCorrError->NoError	235	Covered	T106,T56,T94
NoError->AccessError	256	Covered	T2,T3,T7
NoError->CheckFailError	317	Covered	T171
NoError->FsmStateError	289	Covered	T5,T4,T9
NoError->MacroEccCorrError	221	Covered	T106,T41,T64

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T34,T101
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T41,T64,T21
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T110,T111,T112
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T2,T7,T33
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T3,T7
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T106,T56,T94
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T106,T94,T161
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T18,T19,T20
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T5,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T3,T5,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T171
1	0	Covered	T171
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	404005320	403132969	0	0
DigestKnown_A	404005320	403132969	0	0
DigestOffsetMustBeRepresentable_A	1139	1139	0	0
EccErrorState_A	404005320	2441	0	0
ErrorKnown_A	404005320	403132969	0	0
FsmStateKnown_A	404005320	403132969	0	0
InitDoneKnown_A	404005320	403132969	0	0
InitReadLocksPartition_A	404005320	78824079	0	0
InitWriteLocksPartition_A	404005320	78824079	0	0
OffsetMustBeBlockAligned_A	1139	1139	0	0
OtpAddrKnown_A	404005320	403132969	0	0
OtpCmdKnown_A	404005320	403132969	0	0
OtpErrorState_A	404005320	42	0	0
OtpReqKnown_A	404005320	403132969	0	0
OtpSizeKnown_A	404005320	403132969	0	0
OtpWdataKnown_A	404005320	403132969	0	0
ReadLockPropagation_A	404005320	155856932	0	0
SizeMustBeBlockAligned_A	1139	1139	0	0
TlulGntKnown_A	404005320	403132969	0	0
TlulRdataKnown_A	404005320	403132969	0	0
TlulReadOnReadLock_A	404005320	7608	0	0
TlulRerrorKnown_A	404005320	403132969	0	0
TlulRvalidKnown_A	404005320	403132969	0	0
WriteLockPropagation_A	404005320	1197585	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	404005320	12284492	0	0
u_state_regs_A	404005320	403132969	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	403132969	0	0
T1	17259	17009	0	0
T2	380768	380755	0	0
T3	639258	639247	0	0
T4	57927	57636	0	0
T5	23059	22792	0	0
T6	19989	19663	0	0
T7	207438	205765	0	0
T8	34677	34359	0	0
T9	9893	9640	0	0
T10	14807	14631	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	403132969	0	0
T1	17259	17009	0	0
T2	380768	380755	0	0
T3	639258	639247	0	0
T4	57927	57636	0	0
T5	23059	22792	0	0
T6	19989	19663	0	0
T7	207438	205765	0	0
T8	34677	34359	0	0
T9	9893	9640	0	0
T10	14807	14631	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1139	1139	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	2441	0	0
T36	42646	0	0	0
T171	13071	2441	0	0
T180	16850	0	0	0
T181	47821	0	0	0
T182	14186	0	0	0
T183	15932	0	0	0
T184	12751	0	0	0
T185	27690	0	0	0
T186	13375	0	0	0
T187	20790	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	403132969	0	0
T1	17259	17009	0	0
T2	380768	380755	0	0
T3	639258	639247	0	0
T4	57927	57636	0	0
T5	23059	22792	0	0
T6	19989	19663	0	0
T7	207438	205765	0	0
T8	34677	34359	0	0
T9	9893	9640	0	0
T10	14807	14631	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	403132969	0	0
T1	17259	17009	0	0
T2	380768	380755	0	0
T3	639258	639247	0	0
T4	57927	57636	0	0
T5	23059	22792	0	0
T6	19989	19663	0	0
T7	207438	205765	0	0
T8	34677	34359	0	0
T9	9893	9640	0	0
T10	14807	14631	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	403132969	0	0
T1	17259	17009	0	0
T2	380768	380755	0	0
T3	639258	639247	0	0
T4	57927	57636	0	0
T5	23059	22792	0	0
T6	19989	19663	0	0
T7	207438	205765	0	0
T8	34677	34359	0	0
T9	9893	9640	0	0
T10	14807	14631	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	78824079	0	0
T1	17259	992	0	0
T2	380768	140570	0	0
T3	639258	381902	0	0
T4	57927	43260	0	0
T5	23059	13973	0	0
T6	19989	628	0	0
T7	207438	8671	0	0
T8	34677	451	0	0
T9	9893	4485	0	0
T10	14807	4341	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	78824079	0	0
T1	17259	992	0	0
T2	380768	140570	0	0
T3	639258	381902	0	0
T4	57927	43260	0	0
T5	23059	13973	0	0
T6	19989	628	0	0
T7	207438	8671	0	0
T8	34677	451	0	0
T9	9893	4485	0	0
T10	14807	4341	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1139	1139	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	403132969	0	0
T1	17259	17009	0	0
T2	380768	380755	0	0
T3	639258	639247	0	0
T4	57927	57636	0	0
T5	23059	22792	0	0
T6	19989	19663	0	0
T7	207438	205765	0	0
T8	34677	34359	0	0
T9	9893	9640	0	0
T10	14807	14631	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	403132969	0	0
T1	17259	17009	0	0
T2	380768	380755	0	0
T3	639258	639247	0	0
T4	57927	57636	0	0
T5	23059	22792	0	0
T6	19989	19663	0	0
T7	207438	205765	0	0
T8	34677	34359	0	0
T9	9893	9640	0	0
T10	14807	14631	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	42	0	0
T11	218120	0	0	0
T12	585954	0	0	0
T33	54001	0	0	0
T34	92955	0	0	0
T41	12668	0	0	0
T50	12795	0	0	0
T64	11560	0	0	0
T94	0	1	0	0
T100	7811	0	0	0
T101	21195	0	0	0
T106	67146	1	0	0
T110	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T224	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	403132969	0	0
T1	17259	17009	0	0
T2	380768	380755	0	0
T3	639258	639247	0	0
T4	57927	57636	0	0
T5	23059	22792	0	0
T6	19989	19663	0	0
T7	207438	205765	0	0
T8	34677	34359	0	0
T9	9893	9640	0	0
T10	14807	14631	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	403132969	0	0
T1	17259	17009	0	0
T2	380768	380755	0	0
T3	639258	639247	0	0
T4	57927	57636	0	0
T5	23059	22792	0	0
T6	19989	19663	0	0
T7	207438	205765	0	0
T8	34677	34359	0	0
T9	9893	9640	0	0
T10	14807	14631	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	403132969	0	0
T1	17259	17009	0	0
T2	380768	380755	0	0
T3	639258	639247	0	0
T4	57927	57636	0	0
T5	23059	22792	0	0
T6	19989	19663	0	0
T7	207438	205765	0	0
T8	34677	34359	0	0
T9	9893	9640	0	0
T10	14807	14631	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	155856932	0	0
T2	380768	235909	0	0
T3	639258	396099	0	0
T4	57927	47331	0	0
T5	23059	12876	0	0
T6	19989	0	0	0
T7	207438	11020	0	0
T8	34677	0	0	0
T9	9893	0	0	0
T10	14807	0	0	0
T11	0	147188	0	0
T12	0	76277	0	0
T33	0	5225	0	0
T34	0	23254	0	0
T106	67146	5011	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1139	1139	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	403132969	0	0
T1	17259	17009	0	0
T2	380768	380755	0	0
T3	639258	639247	0	0
T4	57927	57636	0	0
T5	23059	22792	0	0
T6	19989	19663	0	0
T7	207438	205765	0	0
T8	34677	34359	0	0
T9	9893	9640	0	0
T10	14807	14631	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	403132969	0	0
T1	17259	17009	0	0
T2	380768	380755	0	0
T3	639258	639247	0	0
T4	57927	57636	0	0
T5	23059	22792	0	0
T6	19989	19663	0	0
T7	207438	205765	0	0
T8	34677	34359	0	0
T9	9893	9640	0	0
T10	14807	14631	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	7608	0	0
T2	380768	69	0	0
T3	639258	19	0	0
T4	57927	9	0	0
T5	23059	13	0	0
T6	19989	0	0	0
T7	207438	2	0	0
T8	34677	0	0	0
T9	9893	0	0	0
T10	14807	0	0	0
T11	0	39	0	0
T12	0	61	0	0
T33	0	8	0	0
T34	0	4	0	0
T102	0	1	0	0
T106	67146	0	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	403132969	0	0
T1	17259	17009	0	0
T2	380768	380755	0	0
T3	639258	639247	0	0
T4	57927	57636	0	0
T5	23059	22792	0	0
T6	19989	19663	0	0
T7	207438	205765	0	0
T8	34677	34359	0	0
T9	9893	9640	0	0
T10	14807	14631	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	403132969	0	0
T1	17259	17009	0	0
T2	380768	380755	0	0
T3	639258	639247	0	0
T4	57927	57636	0	0
T5	23059	22792	0	0
T6	19989	19663	0	0
T7	207438	205765	0	0
T8	34677	34359	0	0
T9	9893	9640	0	0
T10	14807	14631	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	1197585	0	0
T11	218120	0	0	0
T12	585954	10333	0	0
T33	54001	0	0	0
T34	92955	0	0	0
T41	12668	0	0	0
T50	12795	0	0	0
T58	0	20812	0	0
T64	11560	0	0	0
T96	0	8563	0	0
T100	7811	0	0	0
T101	21195	0	0	0
T102	57836	0	0	0
T104	0	9379	0	0
T126	0	5282	0	0
T129	0	8257	0	0
T135	0	21806	0	0
T207	0	3443	0	0
T225	0	573	0	0
T226	0	285492	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	12284492	0	0
T11	218120	0	0	0
T12	585954	133210	0	0
T33	54001	0	0	0
T34	92955	78944	0	0
T41	12668	0	0	0
T50	12795	0	0	0
T64	11560	0	0	0
T100	7811	0	0	0
T101	21195	14062	0	0
T102	57836	0	0	0
T110	0	3648	0	0
T111	0	2767	0	0
T112	0	3765	0	0
T129	0	42074	0	0
T134	0	13202	0	0
T135	0	161370	0	0
T152	0	2861	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404005320	403132969	0	0
T1	17259	17009	0	0
T2	380768	380755	0	0
T3	639258	639247	0	0
T4	57927	57636	0	0
T5	23059	22792	0	0
T6	19989	19663	0	0
T7	207438	205765	0	0
T8	34677	34359	0	0
T9	9893	9640	0	0
T10	14807	14631	0	0