Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7892988	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

8065555

1

T1

3998

T2

155

T3

80

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	9024224	1			T1	7059		T2	324		T3	381
values[0x0]	2622143	1			T1	667		T2	93		T3	16
values[0x1]	4312176	1			T1	704		T2	94		T3	13

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5060643	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

10897900

1

T1

4904

T2

250

T3

182

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	58592	1			T1	34		T2	3		T6	5
valid_sources[0x01]	59763	1			T1	50		T3	6		T6	2
valid_sources[0x02]	58368	1			T1	23		T2	4		T3	4
valid_sources[0x03]	68562	1			T1	30		T2	5		T3	3
valid_sources[0x04]	55758	1			T1	43		T2	3		T3	3
valid_sources[0x05]	63630	1			T1	24		T2	5		T3	1
valid_sources[0x06]	60883	1			T1	18		T2	2		T6	5
valid_sources[0x07]	56790	1			T1	26		T2	1		T6	1
valid_sources[0x08]	57153	1			T1	33		T3	2		T6	7
valid_sources[0x09]	56450	1			T1	29		T2	2		T6	1
valid_sources[0x0a]	63361	1			T1	38		T2	4		T6	3
valid_sources[0x0b]	134615	1			T1	34		T2	2		T6	4
valid_sources[0x0c]	56942	1			T1	38		T2	2		T3	5
valid_sources[0x0d]	62044	1			T1	29		T6	2		T4	743
valid_sources[0x0e]	55715	1			T1	19		T2	3		T4	593
valid_sources[0x0f]	80844	1			T1	44		T2	7		T6	3
valid_sources[0x10]	55206	1			T1	15		T2	2		T6	2
valid_sources[0x11]	54966	1			T1	28		T2	2		T6	4
valid_sources[0x12]	59017	1			T1	16		T2	1		T6	2
valid_sources[0x13]	63780	1			T1	30		T2	5		T6	13
valid_sources[0x14]	57891	1			T1	52		T2	3		T6	4
valid_sources[0x15]	58410	1			T1	45		T2	2		T4	732
valid_sources[0x16]	68337	1			T1	37		T2	3		T3	3
valid_sources[0x17]	54100	1			T1	44		T2	1		T3	4
valid_sources[0x18]	84939	1			T1	20		T6	4		T4	822
valid_sources[0x19]	54123	1			T1	43		T2	2		T6	4
valid_sources[0x1a]	55788	1			T1	64		T2	5		T6	4
valid_sources[0x1b]	61993	1			T1	22		T3	1		T4	760
valid_sources[0x1c]	64171	1			T1	31		T4	670		T5	36
valid_sources[0x1d]	57239	1			T1	41		T2	2		T4	566
valid_sources[0x1e]	63669	1			T1	40		T4	490		T5	34
valid_sources[0x1f]	61336	1			T1	14		T3	14		T6	2
valid_sources[0x20]	71023	1			T1	41		T3	1		T4	733
valid_sources[0x21]	70570	1			T1	10		T6	2		T4	684
valid_sources[0x22]	64048	1			T1	27		T2	3		T3	8
valid_sources[0x23]	58286	1			T1	34		T2	4		T6	4
valid_sources[0x24]	58113	1			T1	49		T2	2		T6	1
valid_sources[0x25]	56530	1			T1	42		T2	2		T3	13
valid_sources[0x26]	57379	1			T1	52		T2	2		T6	3
valid_sources[0x27]	55391	1			T1	38		T2	1		T3	3
valid_sources[0x28]	64612	1			T1	40		T2	1		T3	2
valid_sources[0x29]	57192	1			T1	18		T2	2		T3	9
valid_sources[0x2a]	55824	1			T1	35		T2	3		T6	3
valid_sources[0x2b]	64184	1			T1	33		T2	3		T6	2
valid_sources[0x2c]	55332	1			T1	11		T2	1		T3	3
valid_sources[0x2d]	65034	1			T1	25		T2	1		T6	3
valid_sources[0x2e]	56256	1			T1	13		T4	659		T5	28
valid_sources[0x2f]	62223	1			T1	50		T2	2		T3	4
valid_sources[0x30]	64293	1			T1	36		T2	1		T4	743
valid_sources[0x31]	55393	1			T1	32		T2	2		T4	642
valid_sources[0x32]	54333	1			T1	33		T6	1		T4	764
valid_sources[0x33]	54856	1			T1	22		T2	1		T4	669
valid_sources[0x34]	56890	1			T1	34		T2	1		T3	7
valid_sources[0x35]	56805	1			T1	20		T2	3		T3	9
valid_sources[0x36]	59174	1			T1	37		T2	4		T3	1
valid_sources[0x37]	56865	1			T1	56		T2	3		T3	6
valid_sources[0x38]	63273	1			T1	24		T2	2		T6	1
valid_sources[0x39]	66873	1			T1	13		T2	1		T3	5
valid_sources[0x3a]	62432	1			T1	45		T2	1		T6	6
valid_sources[0x3b]	64736	1			T1	16		T2	3		T3	3
valid_sources[0x3c]	53998	1			T1	37		T2	2		T3	1
valid_sources[0x3d]	56303	1			T1	27		T3	1		T6	2
valid_sources[0x3e]	60016	1			T1	33		T2	6		T4	742
valid_sources[0x3f]	59044	1			T1	39		T2	3		T3	9
valid_sources[0x40]	83887	1			T1	28		T2	2		T6	3
valid_sources[0x41]	59469	1			T1	34		T2	1		T6	2
valid_sources[0x42]	56984	1			T1	25		T2	1		T6	4
valid_sources[0x43]	59997	1			T1	31		T2	1		T6	3
valid_sources[0x44]	56560	1			T1	47		T2	2		T6	2
valid_sources[0x45]	54474	1			T1	38		T3	2		T6	1
valid_sources[0x46]	56474	1			T1	51		T2	2		T6	3
valid_sources[0x47]	58771	1			T1	51		T2	3		T6	4
valid_sources[0x48]	67748	1			T1	37		T2	6		T3	1
valid_sources[0x49]	58140	1			T1	30		T2	3		T3	1
valid_sources[0x4a]	59604	1			T1	41		T2	2		T3	5
valid_sources[0x4b]	57009	1			T1	24		T2	3		T3	8
valid_sources[0x4c]	57325	1			T1	28		T2	4		T6	3
valid_sources[0x4d]	73666	1			T1	29		T2	3		T3	1
valid_sources[0x4e]	56933	1			T1	28		T2	2		T3	9
valid_sources[0x4f]	62419	1			T1	46		T2	1		T6	3
valid_sources[0x50]	64916	1			T1	53		T2	1		T6	1
valid_sources[0x51]	56717	1			T1	47		T2	4		T6	2
valid_sources[0x52]	61109	1			T1	24		T2	1		T4	721
valid_sources[0x53]	150115	1			T1	12		T2	2		T6	2
valid_sources[0x54]	68632	1			T1	38		T4	716		T5	29
valid_sources[0x55]	57277	1			T1	21		T2	1		T6	4
valid_sources[0x56]	72542	1			T1	30		T2	2		T6	2
valid_sources[0x57]	54846	1			T1	18		T2	1		T4	658
valid_sources[0x58]	56006	1			T1	26		T2	3		T6	7
valid_sources[0x59]	58519	1			T1	45		T2	4		T6	3
valid_sources[0x5a]	59413	1			T1	35		T2	2		T3	24
valid_sources[0x5b]	57369	1			T1	12		T2	3		T6	5
valid_sources[0x5c]	65991	1			T1	35		T6	3		T4	653
valid_sources[0x5d]	57306	1			T1	50		T2	2		T6	2
valid_sources[0x5e]	74365	1			T1	54		T2	4		T6	3
valid_sources[0x5f]	90200	1			T1	34		T2	1		T3	4
valid_sources[0x60]	59788	1			T1	40		T2	1		T6	2
valid_sources[0x61]	65003	1			T1	64		T2	3		T6	4
valid_sources[0x62]	56307	1			T1	32		T2	5		T6	2
valid_sources[0x63]	52755	1			T1	30		T2	4		T6	2
valid_sources[0x64]	55488	1			T1	26		T2	1		T6	3
valid_sources[0x65]	76024	1			T1	37		T2	1		T6	4
valid_sources[0x66]	55329	1			T1	43		T2	4		T3	2
valid_sources[0x67]	57068	1			T1	83		T2	3		T6	2
valid_sources[0x68]	57741	1			T1	37		T3	2		T6	4
valid_sources[0x69]	55077	1			T1	31		T2	4		T4	805
valid_sources[0x6a]	54266	1			T1	25		T2	3		T6	2
valid_sources[0x6b]	55771	1			T1	19		T2	1		T3	5
valid_sources[0x6c]	57652	1			T1	54		T2	1		T6	2
valid_sources[0x6d]	60039	1			T1	10		T2	2		T6	1
valid_sources[0x6e]	56594	1			T1	14		T6	2		T4	738
valid_sources[0x6f]	59245	1			T1	48		T2	2		T6	3
valid_sources[0x70]	56744	1			T1	26		T2	3		T6	3
valid_sources[0x71]	65256	1			T1	31		T2	2		T4	784
valid_sources[0x72]	57766	1			T1	28		T2	1		T6	2
valid_sources[0x73]	65036	1			T1	25		T2	2		T6	3
valid_sources[0x74]	59788	1			T1	30		T2	2		T3	2
valid_sources[0x75]	143872	1			T1	50		T2	1		T3	8
valid_sources[0x76]	60256	1			T1	43		T2	2		T4	774
valid_sources[0x77]	68556	1			T1	41		T2	1		T4	644
valid_sources[0x78]	69930	1			T1	49		T2	3		T3	9
valid_sources[0x79]	54566	1			T1	48		T2	3		T3	1
valid_sources[0x7a]	62866	1			T1	34		T2	2		T6	1
valid_sources[0x7b]	55170	1			T1	40		T2	2		T6	5
valid_sources[0x7c]	57789	1			T1	36		T2	1		T6	4
valid_sources[0x7d]	55326	1			T1	33		T2	3		T3	1
valid_sources[0x7e]	64502	1			T1	25		T2	3		T6	1
valid_sources[0x7f]	53525	1			T1	38		T2	2		T6	3
valid_sources[0x80]	57052	1			T1	28		T2	3		T4	603

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3751933

1

T1

3360

T2

71

T3

69

values[0x0]

all_enables

biggest_size

2196695

1

T1

351

T2

46

T3

8

values[0x1]

all_enables

biggest_size

2116927

1

T1

287

T2

38

T3

3

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	292071	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

10377297

1

T1

20

T3

20

T4

200957

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2650563	1			T1	10		T3	10		T4	50800
values[0x0]	3891616	1			T1	8		T3	6		T4	75272
values[0x1]	4127189	1			T1	2		T3	4		T4	80445

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	105552	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

10563816

1

T1

20

T3

20

T4

204625

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	40893	1			T4	686		T34	3		T11	1023
valid_sources[0x01]	44445	1			T4	785		T9	1		T11	263
valid_sources[0x02]	44828	1			T4	919		T100	1		T126	2
valid_sources[0x03]	40791	1			T4	954		T7	3		T9	1
valid_sources[0x04]	43992	1			T4	882		T5	1		T7	2
valid_sources[0x05]	41440	1			T4	772		T11	214		T12	288
valid_sources[0x06]	40037	1			T4	701		T9	1		T34	10
valid_sources[0x07]	40471	1			T4	787		T100	1		T34	3
valid_sources[0x08]	42319	1			T4	923		T7	1		T100	2
valid_sources[0x09]	38775	1			T4	795		T5	5		T101	3
valid_sources[0x0a]	39711	1			T4	730		T34	3		T12	252
valid_sources[0x0b]	40710	1			T4	876		T5	1		T11	759
valid_sources[0x0c]	38452	1			T4	798		T100	2		T34	5
valid_sources[0x0d]	37912	1			T4	766		T12	248		T18	906
valid_sources[0x0e]	41313	1			T4	815		T11	237		T126	1
valid_sources[0x0f]	39684	1			T4	660		T34	24		T11	7
valid_sources[0x10]	47253	1			T4	854		T5	1		T10	2
valid_sources[0x11]	40511	1			T4	812		T100	1		T11	386
valid_sources[0x12]	43487	1			T4	848		T9	1		T11	975
valid_sources[0x13]	42476	1			T4	784		T101	1		T34	9
valid_sources[0x14]	39812	1			T4	777		T9	2		T34	12
valid_sources[0x15]	42275	1			T3	5		T4	829		T100	1
valid_sources[0x16]	41061	1			T4	782		T34	8		T11	103
valid_sources[0x17]	42009	1			T4	738		T9	2		T101	1
valid_sources[0x18]	44003	1			T4	757		T12	277		T18	904
valid_sources[0x19]	44520	1			T4	877		T7	2		T100	1
valid_sources[0x1a]	41223	1			T4	864		T100	1		T34	1
valid_sources[0x1b]	39546	1			T4	920		T11	92		T12	266
valid_sources[0x1c]	42659	1			T4	801		T5	1		T100	1
valid_sources[0x1d]	44992	1			T4	797		T9	1		T101	1
valid_sources[0x1e]	40244	1			T4	827		T34	7		T11	228
valid_sources[0x1f]	39906	1			T4	732		T12	251		T373	2
valid_sources[0x20]	40048	1			T4	779		T9	1		T34	6
valid_sources[0x21]	41021	1			T4	775		T5	2		T11	131
valid_sources[0x22]	41651	1			T4	763		T11	648		T126	4
valid_sources[0x23]	38146	1			T4	755		T34	7		T12	286
valid_sources[0x24]	38927	1			T4	772		T34	1		T11	454
valid_sources[0x25]	39212	1			T4	860		T12	261		T71	1
valid_sources[0x26]	39385	1			T4	875		T11	433		T126	6
valid_sources[0x27]	43096	1			T4	743		T9	1		T100	1
valid_sources[0x28]	40170	1			T4	792		T9	1		T100	1
valid_sources[0x29]	41150	1			T4	932		T13	1		T34	11
valid_sources[0x2a]	42373	1			T4	797		T34	9		T11	481
valid_sources[0x2b]	43517	1			T4	829		T5	5		T7	1
valid_sources[0x2c]	41546	1			T4	712		T100	1		T104	1
valid_sources[0x2d]	43463	1			T4	850		T7	4		T34	6
valid_sources[0x2e]	43514	1			T4	890		T101	1		T11	74
valid_sources[0x2f]	39974	1			T1	1		T4	805		T10	1
valid_sources[0x30]	45145	1			T4	760		T5	2		T34	5
valid_sources[0x31]	40848	1			T4	864		T5	2		T101	3
valid_sources[0x32]	45106	1			T4	767		T34	18		T11	1222
valid_sources[0x33]	43190	1			T4	753		T5	3		T34	3
valid_sources[0x34]	40573	1			T4	742		T7	5		T11	107
valid_sources[0x35]	39248	1			T4	707		T5	1		T100	1
valid_sources[0x36]	38749	1			T4	1004		T10	1		T34	9
valid_sources[0x37]	39610	1			T4	709		T9	1		T34	6
valid_sources[0x38]	40090	1			T4	832		T100	2		T34	8
valid_sources[0x39]	41851	1			T4	776		T34	7		T11	121
valid_sources[0x3a]	43131	1			T4	888		T100	1		T34	15
valid_sources[0x3b]	45677	1			T4	721		T100	1		T34	1
valid_sources[0x3c]	43096	1			T4	664		T11	163		T12	271
valid_sources[0x3d]	42903	1			T4	781		T7	5		T100	1
valid_sources[0x3e]	41235	1			T4	699		T9	1		T101	1
valid_sources[0x3f]	41620	1			T4	775		T9	1		T101	1
valid_sources[0x40]	41227	1			T4	785		T5	1		T100	1
valid_sources[0x41]	42457	1			T4	790		T12	272		T65	7
valid_sources[0x42]	41294	1			T4	824		T13	1		T12	289
valid_sources[0x43]	42768	1			T4	808		T5	2		T100	2
valid_sources[0x44]	38882	1			T3	3		T4	738		T100	1
valid_sources[0x45]	43611	1			T4	749		T5	1		T10	3
valid_sources[0x46]	41017	1			T4	919		T5	2		T100	1
valid_sources[0x47]	41229	1			T4	961		T5	5		T10	3
valid_sources[0x48]	43722	1			T4	844		T34	5		T126	7
valid_sources[0x49]	41962	1			T4	853		T34	8		T11	278
valid_sources[0x4a]	41200	1			T4	746		T10	1		T100	1
valid_sources[0x4b]	43889	1			T4	821		T5	2		T12	266
valid_sources[0x4c]	43313	1			T4	803		T9	1		T11	378
valid_sources[0x4d]	41051	1			T4	1002		T5	3		T9	1
valid_sources[0x4e]	41423	1			T4	828		T5	1		T34	20
valid_sources[0x4f]	38601	1			T4	860		T9	1		T34	2
valid_sources[0x50]	40214	1			T4	838		T101	2		T34	11
valid_sources[0x51]	43200	1			T3	12		T4	703		T5	2
valid_sources[0x52]	40439	1			T4	820		T13	2		T11	125
valid_sources[0x53]	41640	1			T4	899		T100	1		T34	6
valid_sources[0x54]	40816	1			T4	855		T34	15		T126	1
valid_sources[0x55]	43510	1			T4	871		T5	2		T9	1
valid_sources[0x56]	42091	1			T4	782		T34	5		T169	2
valid_sources[0x57]	42868	1			T4	797		T5	4		T100	1
valid_sources[0x58]	41534	1			T4	901		T101	1		T34	1
valid_sources[0x59]	40866	1			T4	852		T10	2		T13	1
valid_sources[0x5a]	39389	1			T4	804		T100	1		T34	6
valid_sources[0x5b]	39992	1			T4	883		T7	3		T34	7
valid_sources[0x5c]	40941	1			T4	748		T5	1		T10	6
valid_sources[0x5d]	41422	1			T4	831		T9	1		T10	4
valid_sources[0x5e]	42401	1			T4	784		T11	131		T12	258
valid_sources[0x5f]	39275	1			T1	1		T4	670		T7	2
valid_sources[0x60]	42544	1			T4	666		T5	2		T11	150
valid_sources[0x61]	41541	1			T4	820		T7	1		T34	5
valid_sources[0x62]	40039	1			T4	849		T9	1		T104	1
valid_sources[0x63]	40042	1			T4	789		T12	271		T246	1
valid_sources[0x64]	41921	1			T4	820		T5	1		T34	12
valid_sources[0x65]	44029	1			T4	686		T20	100		T11	217
valid_sources[0x66]	43467	1			T4	818		T11	134		T42	1
valid_sources[0x67]	40319	1			T4	742		T9	1		T100	2
valid_sources[0x68]	42308	1			T4	807		T101	1		T12	262
valid_sources[0x69]	41570	1			T4	764		T34	2		T11	66
valid_sources[0x6a]	41771	1			T4	920		T9	1		T10	1
valid_sources[0x6b]	40421	1			T4	793		T5	2		T10	1
valid_sources[0x6c]	42949	1			T4	748		T42	1		T12	285
valid_sources[0x6d]	38987	1			T4	786		T102	180		T11	616
valid_sources[0x6e]	43441	1			T4	727		T9	1		T12	319
valid_sources[0x6f]	41885	1			T4	709		T101	2		T126	1
valid_sources[0x70]	40169	1			T4	856		T5	1		T34	3
valid_sources[0x71]	44705	1			T4	743		T5	2		T42	1
valid_sources[0x72]	40946	1			T4	801		T5	3		T100	1
valid_sources[0x73]	43300	1			T4	735		T7	5		T101	1
valid_sources[0x74]	43188	1			T4	861		T7	1		T9	1
valid_sources[0x75]	41958	1			T4	920		T7	2		T100	1
valid_sources[0x76]	43099	1			T4	877		T34	3		T42	1
valid_sources[0x77]	39966	1			T4	852		T10	1		T34	6
valid_sources[0x78]	43495	1			T4	938		T12	273		T18	875
valid_sources[0x79]	40932	1			T4	812		T5	4		T42	1
valid_sources[0x7a]	42707	1			T4	782		T13	1		T12	260
valid_sources[0x7b]	41804	1			T4	701		T101	2		T34	5
valid_sources[0x7c]	42291	1			T4	873		T9	1		T100	1
valid_sources[0x7d]	39018	1			T4	883		T9	2		T11	53
valid_sources[0x7e]	44342	1			T4	846		T5	3		T34	11
valid_sources[0x7f]	40874	1			T4	792		T5	2		T9	1
valid_sources[0x80]	41293	1			T4	904		T100	1		T34	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2635059

1

T1

10

T3

10

T4

50762

values[0x0]

all_enables

biggest_size

3871557

1

T1

8

T3

6

T4

74852

values[0x1]

all_enables

biggest_size

3870681

1

T1

2

T3

4

T4

75343