Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

29006794

1

T1

4432

T2

356

T3

330

full_word

9349267

1

T1

3998

T2

155

T3

80

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	38355731	1			T1	8430		T2	511		T3	410
auto[TlIntgErrCmd]	107	1			T263	7		T264	7		T265	8
auto[TlIntgErrData]	99	1			T263	6		T264	4		T265	4
auto[TlIntgErrBoth]	124	1			T263	7		T264	9		T265	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10566517

1

T1

7059

T2

324

T3

381

auto[1]

27789544

1

T1

1371

T2

187

T3

29

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6657758	1			T1	3699		T2	253		T3	312
auto[TlIntgErrNone]	partial	auto[1]	22348738	1			T1	733		T2	103		T3	18
auto[TlIntgErrNone]	full_word	auto[0]	3908615	1			T1	3360		T2	71		T3	69
auto[TlIntgErrNone]	full_word	auto[1]	5440620	1			T1	638		T2	84		T3	11
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T263	3		T264	1		T265	6
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T263	3		T264	6		T265	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T263	1		T356	1		T269	2
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T265	1		T352	1		T357	1
auto[TlIntgErrData]	partial	auto[0]	42	1			T263	4		T264	2		T265	3
auto[TlIntgErrData]	partial	auto[1]	45	1			T263	2		T264	2		T265	1
auto[TlIntgErrData]	full_word	auto[0]	8	1			T351	1		T355	1		T356	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T351	1		T358	1		T359	1
auto[TlIntgErrBoth]	partial	auto[0]	46	1			T263	3		T264	3		T265	5
auto[TlIntgErrBoth]	partial	auto[1]	68	1			T263	3		T264	5		T265	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T360	2		T269	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T263	1		T264	1		T353	3