Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.95	98.05	96.15	96.96		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	519505586	9346899	0	0
check_regwen_rd_A	519505586	5026	0	0
check_timeout_rd_A	519505586	4115	0	0
check_trigger_regwen_rd_A	519505586	5253	0	0
consistency_check_period_rd_A	519505586	5391	0	0
creator_sw_cfg_read_lock_rd_A	519505586	4134	0	0
direct_access_address_rd_A	519505586	3024	0	0
direct_access_wdata_0_rd_A	519505586	1905	0	0
direct_access_wdata_1_rd_A	519505586	2343	0	0
integrity_check_period_rd_A	519505586	4988	0	0
intr_enable_rd_A	519505586	5990	0	0
owner_sw_cfg_read_lock_rd_A	519505586	3624	0	0
rot_creator_auth_codesign_read_lock_rd_A	519505586	4232	0	0
rot_creator_auth_state_read_lock_rd_A	519505586	3809	0	0
vendor_test_read_lock_rd_A	519505586	3752	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519505586	9346899	0	0
T4	866644	181004	0	0
T5	111724	0	0	0
T7	147884	0	0	0
T8	18642	0	0	0
T9	27010	0	0	0
T10	19808	0	0	0
T11	0	39052	0	0
T12	0	58483	0	0
T18	0	192776	0	0
T19	53153	0	0	0
T21	59439	0	0	0
T68	0	184648	0	0
T99	6597	0	0	0
T100	10841	0	0	0
T122	0	117613	0	0
T129	0	127303	0	0
T130	0	266313	0	0
T209	0	226396	0	0
T275	0	101264	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519505586	5026	0	0
T11	243916	48	0	0
T12	311461	58	0	0
T35	55381	0	0	0
T42	53728	0	0	0
T65	521736	0	0	0
T68	0	167	0	0
T94	349516	0	0	0
T104	11332	0	0	0
T122	0	80	0	0
T125	62443	0	0	0
T126	139555	0	0	0
T131	0	71	0	0
T169	37757	0	0	0
T235	0	147	0	0
T262	0	72	0	0
T284	0	80	0	0
T335	0	49	0	0
T336	0	34	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519505586	4115	0	0
T11	243916	45	0	0
T12	311461	52	0	0
T35	55381	0	0	0
T42	53728	0	0	0
T65	521736	0	0	0
T68	0	178	0	0
T94	349516	0	0	0
T104	11332	0	0	0
T122	0	197	0	0
T125	62443	0	0	0
T126	139555	0	0	0
T131	0	116	0	0
T169	37757	0	0	0
T235	0	261	0	0
T262	0	89	0	0
T284	0	132	0	0
T335	0	26	0	0
T336	0	58	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519505586	5253	0	0
T11	243916	38	0	0
T12	311461	75	0	0
T35	55381	0	0	0
T42	53728	0	0	0
T65	521736	0	0	0
T68	0	247	0	0
T94	349516	0	0	0
T104	11332	0	0	0
T122	0	102	0	0
T125	62443	0	0	0
T126	139555	0	0	0
T131	0	106	0	0
T169	37757	0	0	0
T235	0	222	0	0
T262	0	67	0	0
T284	0	74	0	0
T335	0	28	0	0
T336	0	46	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519505586	5391	0	0
T11	243916	62	0	0
T12	311461	113	0	0
T35	55381	0	0	0
T42	53728	0	0	0
T65	521736	0	0	0
T68	0	279	0	0
T94	349516	0	0	0
T104	11332	0	0	0
T122	0	155	0	0
T125	62443	0	0	0
T126	139555	0	0	0
T131	0	77	0	0
T169	37757	0	0	0
T235	0	172	0	0
T262	0	61	0	0
T284	0	131	0	0
T335	0	51	0	0
T336	0	56	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519505586	4134	0	0
T11	243916	69	0	0
T12	311461	80	0	0
T35	55381	0	0	0
T42	53728	0	0	0
T65	521736	0	0	0
T68	0	207	0	0
T94	349516	0	0	0
T104	11332	0	0	0
T122	0	123	0	0
T125	62443	0	0	0
T126	139555	0	0	0
T131	0	79	0	0
T169	37757	0	0	0
T235	0	196	0	0
T262	0	85	0	0
T284	0	113	0	0
T335	0	32	0	0
T336	0	55	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519505586	3024	0	0
T11	243916	95	0	0
T12	311461	66	0	0
T35	55381	0	0	0
T42	53728	0	0	0
T65	521736	0	0	0
T68	0	161	0	0
T94	349516	0	0	0
T104	11332	0	0	0
T122	0	114	0	0
T125	62443	0	0	0
T126	139555	0	0	0
T131	0	105	0	0
T169	37757	0	0	0
T235	0	179	0	0
T262	0	79	0	0
T284	0	160	0	0
T335	0	35	0	0
T336	0	41	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519505586	1905	0	0
T11	243916	37	0	0
T12	311461	65	0	0
T35	55381	0	0	0
T42	53728	0	0	0
T65	521736	0	0	0
T68	0	160	0	0
T94	349516	0	0	0
T104	11332	0	0	0
T122	0	84	0	0
T125	62443	0	0	0
T126	139555	0	0	0
T131	0	39	0	0
T169	37757	0	0	0
T235	0	144	0	0
T262	0	64	0	0
T284	0	60	0	0
T335	0	26	0	0
T336	0	24	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519505586	2343	0	0
T11	243916	44	0	0
T12	311461	57	0	0
T35	55381	0	0	0
T42	53728	0	0	0
T65	521736	0	0	0
T68	0	201	0	0
T94	349516	0	0	0
T104	11332	0	0	0
T122	0	151	0	0
T125	62443	0	0	0
T126	139555	0	0	0
T131	0	70	0	0
T169	37757	0	0	0
T235	0	143	0	0
T262	0	79	0	0
T284	0	104	0	0
T335	0	39	0	0
T336	0	13	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519505586	4988	0	0
T11	243916	54	0	0
T12	311461	94	0	0
T35	55381	0	0	0
T42	53728	0	0	0
T65	521736	0	0	0
T68	0	156	0	0
T94	349516	0	0	0
T104	11332	0	0	0
T122	0	99	0	0
T125	62443	0	0	0
T126	139555	0	0	0
T131	0	97	0	0
T169	37757	0	0	0
T235	0	165	0	0
T262	0	67	0	0
T284	0	84	0	0
T335	0	47	0	0
T336	0	18	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519505586	5990	0	0
T11	243916	79	0	0
T12	311461	69	0	0
T35	55381	0	0	0
T42	53728	0	0	0
T65	521736	0	0	0
T68	0	204	0	0
T94	349516	0	0	0
T104	11332	0	0	0
T122	0	150	0	0
T125	62443	0	0	0
T126	139555	0	0	0
T131	0	134	0	0
T169	37757	0	0	0
T178	0	4	0	0
T262	0	68	0	0
T335	0	35	0	0
T336	0	96	0	0
T337	0	10	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519505586	3624	0	0
T11	243916	61	0	0
T12	311461	47	0	0
T35	55381	0	0	0
T42	53728	0	0	0
T65	521736	0	0	0
T68	0	155	0	0
T94	349516	0	0	0
T104	11332	0	0	0
T122	0	110	0	0
T125	62443	0	0	0
T126	139555	0	0	0
T131	0	71	0	0
T169	37757	0	0	0
T235	0	155	0	0
T262	0	94	0	0
T284	0	99	0	0
T335	0	11	0	0
T336	0	56	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519505586	4232	0	0
T11	243916	56	0	0
T12	311461	84	0	0
T35	55381	0	0	0
T42	53728	0	0	0
T65	521736	0	0	0
T68	0	279	0	0
T94	349516	0	0	0
T104	11332	0	0	0
T122	0	136	0	0
T125	62443	0	0	0
T126	139555	0	0	0
T131	0	74	0	0
T169	37757	0	0	0
T235	0	195	0	0
T262	0	118	0	0
T284	0	115	0	0
T335	0	34	0	0
T336	0	44	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519505586	3809	0	0
T11	243916	57	0	0
T12	311461	52	0	0
T35	55381	0	0	0
T42	53728	0	0	0
T65	521736	0	0	0
T68	0	201	0	0
T94	349516	0	0	0
T104	11332	0	0	0
T122	0	144	0	0
T125	62443	0	0	0
T126	139555	0	0	0
T131	0	93	0	0
T169	37757	0	0	0
T235	0	133	0	0
T262	0	69	0	0
T284	0	69	0	0
T335	0	46	0	0
T336	0	34	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519505586	3752	0	0
T11	243916	56	0	0
T12	311461	102	0	0
T35	55381	0	0	0
T42	53728	0	0	0
T65	521736	0	0	0
T68	0	223	0	0
T94	349516	0	0	0
T104	11332	0	0	0
T122	0	118	0	0
T125	62443	0	0	0
T126	139555	0	0	0
T131	0	79	0	0
T169	37757	0	0	0
T235	0	171	0	0
T262	0	52	0	0
T284	0	113	0	0
T335	0	42	0	0
T336	0	23	0	0