Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[6].gen_buffered.u_part_buf

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.65	95.45	92.86		91.67	90.91	82.35

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.35	96.65	92.86	100.00	91.67	92.54	86.36

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.95	98.05	96.15	96.96		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
u_otp_ctrl_ecc_reg	100.00	100.00		100.00		100.00	100.00
u_prim_count	100.00			100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf

	Line No.	Total	Covered	Percent
TOTAL		132	126	95.45
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
ALWAYS	206	112	106	94.64
CONT_ASSIGN	636	1	1	100.00
CONT_ASSIGN	641	1	1	100.00
CONT_ASSIGN	642	1	1	100.00
CONT_ASSIGN	646	1	1	100.00
CONT_ASSIGN	652	1	1	100.00
CONT_ASSIGN	675	1	1	100.00
CONT_ASSIGN	678	1	1	100.00
CONT_ASSIGN	680	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	743	1	1	100.00
ALWAYS	750	3	3	100.00
ALWAYS	753	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
182	1	1
193	1	1
206	1	1
209	1	1
212	1	1
215	1	1
218	1	1
219	1	1
220	1	1
221	1	1
224	1	1
225	1	1
226	1	1
229	1	1
230	1	1
233	1	1
234	1	1
237	1	1
238	1	1
240	1	1
245	1	1
246	1	1
			MISSING_ELSE
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
265	1	1
266	1	1
267	1	1
271	1	1
272	1	1
275	1	1
276		unreachable
278	1	1
279	1	1
282	1	1
283	1	1
			MISSING_ELSE
286	1	1
287	1	1
			MISSING_ELSE
298		excluded
			Exclude Annotation: VC_COV_UNR
299		excluded
			Exclude Annotation: VC_COV_UNR
300		excluded
			Exclude Annotation: VC_COV_UNR
301		excluded
			Exclude Annotation: VC_COV_UNR
302		excluded
			Exclude Annotation: VC_COV_UNR
303		excluded
			Exclude Annotation: VC_COV_UNR
			==> MISSING_ELSE
311		excluded
			Exclude Annotation: VC_COV_UNR
312		excluded
			Exclude Annotation: VC_COV_UNR
313		excluded
			Exclude Annotation: VC_COV_UNR
314		excluded
			Exclude Annotation: VC_COV_UNR
315		excluded
			Exclude Annotation: VC_COV_UNR
316		excluded
			Exclude Annotation: VC_COV_UNR
317		excluded
			Exclude Annotation: VC_COV_UNR
			==> MISSING_ELSE
324	1	1
325	1	1
326	1	1
331		unreachable
333	1	1
334	1	1
335	1	1
			MISSING_ELSE
343	1	1
348	1	1
349	1	1
			==> MISSING_ELSE
351	1	1
352	1	1
			MISSING_ELSE
362	1	1
363	1	1
366	1	1
368	1	1
369	1	1
370	1	1
373	0	1
374	0	1
376	0	1
381		unreachable
385		unreachable
386		unreachable
387		unreachable
390		unreachable
391		unreachable
394		unreachable
395		unreachable
397		unreachable
401	1	1
402	1	1
			MISSING_ELSE
405	1	1
406	1	1
408	1	1
			MISSING_ELSE
417	1	1
418	1	1
419	1	1
420	1	1
423	1	1
424	1	1
425		unreachable
426		unreachable
427		unreachable
			==> MISSING_ELSE
432	1	1
433	1	1
434	1	1
			MISSING_ELSE
443		unreachable
444		unreachable
445		unreachable
			==> MISSING_ELSE
455		excluded
			Exclude Annotation: VC_COV_UNR
456		excluded
			Exclude Annotation: VC_COV_UNR
457		excluded
			Exclude Annotation: VC_COV_UNR
458		excluded
			Exclude Annotation: VC_COV_UNR
459		excluded
			Exclude Annotation: VC_COV_UNR
460		excluded
			Exclude Annotation: VC_COV_UNR
			==> MISSING_ELSE
467		excluded
			Exclude Annotation: VC_COV_UNR
468		excluded
			Exclude Annotation: VC_COV_UNR
469		excluded
			Exclude Annotation: VC_COV_UNR
470		excluded
			Exclude Annotation: VC_COV_UNR
			==> MISSING_ELSE
480	1	1
481	1	1
482	1	1
483	1	1
485	1	1
489	1	1
490		excluded
			Exclude Annotation: VC_COV_UNR
491		excluded
			Exclude Annotation: VC_COV_UNR
493	1	1
494	1	1
498	0	1
499	0	1
			==> MISSING_ELSE
503	0	1
504		unreachable
			==> MISSING_ELSE
			==> MISSING_ELSE
516	1	1
517	1	1
518	1	1
519	1	1
520	1	1
			==> MISSING_ELSE
528	1	1
529	1	1
530	1	1
531	1	1
532	1	1
			MISSING_ELSE
542	1	1
543	1	1
544	1	1
547	1	1
548	1	1
551	1	1
552	1	1
556	1	1
560	1	1
561	1	1
563	1	1
			MISSING_ELSE
572	1	1
573	1	1
574	1	1
			MISSING_ELSE
578	1	1
579	1	1
595	1	1
596		excluded
			Exclude Annotation: VC_COV_UNR
597		excluded
			Exclude Annotation: VC_COV_UNR
598		excluded
			Exclude Annotation: VC_COV_UNR
			==> MISSING_ELSE
			MISSING_ELSE
602	1	1
603	1	1
604	1	1
605	1	1
606	1	1
			MISSING_ELSE
			MISSING_ELSE
636	1	1
641	1	1
642	1	1
646	1	1
652	1	1
675	1	1
678	1	1
680	1	1
709	1	1
743	1	1
750	3	3
753	1	1
754	1	1
756	1	1
758	1	1
759	1	1

---

Cond Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf

	Total	Covered	Percent
Conditions	42	39	92.86
Logical	42	39	92.86
Non-Logical	0	0
Event	0	0

 LINE       271
 EXPRESSION (cnt == LastScrmblBlock)
            ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       282
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T39,T40,T41

 LINE       302
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Excluded		VC_COV_UNR

 LINE       368
 EXPRESSION ((digest_o == data_mux) || (digest_o == '0))
             -----------1----------    --------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T4,T11,T12
1	0	Covered	T5,T19,T20

 LINE       368
 SUB-EXPRESSION (digest_o == data_mux)
                -----------1----------

-1-	Status	Tests
0	Covered	T4,T11,T12
1	Covered	T4,T5,T10

 LINE       368
 SUB-EXPRESSION (digest_o == '0)
                --------1-------

-1-	Status	Tests
0	Covered	T5,T19,T20
1	Covered	T4,T5,T10

 LINE       385
 EXPRESSION (cnt == LastScrmblBlock)
            ------------1-----------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       401
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T5,T10
1	Covered	T42,T22,T43

 LINE       426
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Unreachable
1	1	Unreachable

 LINE       433
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       485
 EXPRESSION (cnt == PenultimateScrmblBlock)
            ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       547
 EXPRESSION ((digest_o == data_mux) || (digest_o == '0))
             -----------1----------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T6,T44,T45
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T7

 LINE       547
 SUB-EXPRESSION (digest_o == data_mux)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T7

 LINE       547
 SUB-EXPRESSION (digest_o == '0)
                --------1-------

-1-	Status	Tests
0	Covered	T3,T6,T5
1	Covered	T1,T2,T3

 LINE       573
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T28,T29,T30

 LINE       597
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Excluded		VC_COV_UNR

 LINE       605
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T4

 LINE       636
 EXPRESSION ((base_sel == DigOffset) ? DigestOffset : 11'b11011000000)
             -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T10

 LINE       636
 SUB-EXPRESSION (base_sel == DigOffset)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T10

 LINE       652
 EXPRESSION ((data_sel == ScrmblData) ? scrmbl_data_i : otp_rdata_i)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       652
 SUB-EXPRESSION (data_sel == ScrmblData)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       678
 EXPRESSION (init_done_o ? data : DataDefault)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       709
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T6,T5

 LINE       709
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T6,T5

---

FSM Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	19	18	94.74
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests	Exclude Annotation
CnstyReadSt	334	Covered	T4,T5,T10
CnstyReadWaitSt	352	Covered	T4,T5,T10
ErrorSt	286	Covered	T1,T2,T6
IdleSt	369	Covered	T1,T2,T3
InitDescrSt	276	Excluded		VC_COV_UNR
InitDescrWaitSt	303	Excluded		VC_COV_UNR
InitSt	246	Covered	T1,T2,T3
InitWaitSt	256	Covered	T1,T2,T3
IntegDigClrSt	272	Covered	T1,T2,T3
IntegDigFinSt	491	Covered	T1,T2,T3
IntegDigPadSt	493	Excluded	T1,T2,T3
IntegDigSt	434	Covered	T1,T2,T3
IntegDigWaitSt	532	Covered	T1,T2,T3
IntegScrSt	427	Excluded		VC_COV_UNR
IntegScrWaitSt	460	Excluded		VC_COV_UNR
ResetSt	244	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
CnstyReadSt->CnstyReadWaitSt	352	Covered	T4,T5,T10
CnstyReadSt->ErrorSt	596	Covered	T5,T34,T12
CnstyReadWaitSt->CnstyReadSt	390	Excluded		VC_COV_UNR
CnstyReadWaitSt->ErrorSt	373	Covered	T53,T77,T22
CnstyReadWaitSt->IdleSt	369	Covered	T4,T5,T10
IdleSt->CnstyReadSt	334	Covered	T4,T5,T10
IdleSt->ErrorSt	596	Covered	T1,T4,T7
IdleSt->IntegDigClrSt	326	Covered	T4,T5,T9
InitDescrSt->ErrorSt	596	Excluded
InitDescrSt->InitDescrWaitSt	303	Excluded
InitDescrWaitSt->ErrorSt	596	Excluded
InitDescrWaitSt->InitSt	315	Excluded
InitSt->ErrorSt	596	Covered	T8,T110,T111
InitSt->InitWaitSt	256	Covered	T1,T2,T3
InitWaitSt->ErrorSt	286	Covered	T64,T76,T112
InitWaitSt->InitDescrSt	276	Excluded
InitWaitSt->InitSt	278	Excluded	T1,T2,T3
InitWaitSt->IntegDigClrSt	272	Covered	T1,T2,T3
IntegDigClrSt->ErrorSt	596	Covered	T35,T42,T65
IntegDigClrSt->IdleSt	443	Excluded		VC_COV_UNR
IntegDigClrSt->IntegDigSt	434	Excluded	T1,T2,T3
IntegDigClrSt->IntegScrSt	427	Excluded
IntegDigFinSt->ErrorSt	596	Covered	T2,T66,T67
IntegDigFinSt->IntegDigWaitSt	532	Covered	T1,T2,T3
IntegDigPadSt->ErrorSt	596	Excluded
IntegDigPadSt->IntegDigFinSt	520	Excluded	T1,T2,T3
IntegDigSt->ErrorSt	596	Not Covered
IntegDigSt->IntegDigFinSt	491	Excluded		VC_COV_UNR
IntegDigSt->IntegDigPadSt	493	Excluded	T1,T2,T3
IntegDigSt->IntegScrSt	504	Excluded
IntegDigWaitSt->ErrorSt	560	Covered	T6,T44,T45
IntegDigWaitSt->IdleSt	548	Covered	T1,T2,T3
IntegScrSt->ErrorSt	596	Excluded
IntegScrSt->IntegScrWaitSt	460	Excluded
IntegScrWaitSt->ErrorSt	596	Excluded
IntegScrWaitSt->IntegDigSt	470	Excluded
ResetSt->ErrorSt	596	Covered	T72,T73,T74
ResetSt->InitSt	246	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	5	4	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
CheckFailError	374	Covered	T6,T44,T45
FsmStateError	574	Covered	T1,T2,T4
MacroEccCorrError	283	Covered	T42,T39,T40
NoError	573	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
CheckFailError->FsmStateError	606	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	283	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	374	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	283	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	374	Not Covered
MacroEccCorrError->FsmStateError	606	Covered	T39,T40,T41
NoError->CheckFailError	374	Covered	T6,T44,T45
NoError->FsmStateError	574	Covered	T1,T2,T4
NoError->MacroEccCorrError	283	Covered	T42,T39,T40

---

Branch Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf

	Line No.	Total	Covered	Percent
Branches		55	50	90.91
TERNARY	636	2	2	100.00
TERNARY	652	2	2	100.00
TERNARY	678	2	2	100.00
TERNARY	709	2	2	100.00
CASE	240	39	34	87.18
IF	595	1	1	100.00
IF	602	3	3	100.00
IF	750	2	2	100.00
IF	753	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	636	((base_sel == DigOffset)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	652	((data_sel == ScrmblData)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	678	(init_done_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	709	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	240	case (state_q)
-2-:	245	if (init_req_i)
-3-:	255	if (otp_gnt_i)
-4-:	265	if (otp_rvalid_i)
-5-:	267	if ((otp_err inside {NoError, MacroEccCorrError}))
-6-:	271	if ((cnt == LastScrmblBlock))
-7-:	275	if (1'b0)
-8-:	282	if ((otp_err != NoError))
-9-:	302	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-10-:	314	if (scrmbl_valid_i)
-11-:	324	if (integ_chk_req_i)
-12-:	325	if (1'b1)
-13-:	333	if (cnsty_chk_req_i)
-14-:	348	if (1'b1)
-15-:	351	if (otp_gnt_i)
-16-:	362	if (otp_rvalid_i)
-17-:	363	if ((otp_err inside {NoError, MacroEccCorrError}))
-18-:	366	if (1'b1)
-19-:	368	if (((digest_o == data_mux) || (digest_o == '0)))
-20-:	381	if (((scrmbl_data_o == data_mux) || lc_ctrl_pkg::lc_tx_test_true_strict(check_byp_en_i)))
-21-:	385	if ((cnt == LastScrmblBlock))
-22-:	401	if ((otp_err != NoError))
-23-:	417	if (1'b1)
-24-:	424	if (1'b0)
-25-:	426	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-26-:	433	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-27-:	444	if (prim_mubi_pkg::mubi8_test_true_strict(dout_locked_q))
-28-:	459	if (scrmbl_ready_i)
-29-:	469	if (scrmbl_valid_i)
-30-:	482	if (scrmbl_ready_i)
-31-:	485	if ((cnt == PenultimateScrmblBlock))
-32-:	489	if (cnt[0])
-33-:	498	if (cnt[0])
-34-:	503	if (1'b0)
-35-:	519	if (scrmbl_ready_i)
-36-:	531	if (scrmbl_ready_i)
-37-:	544	if (scrmbl_valid_i)
-38-:	547	if (((digest_o == data_mux) || (digest_o == '0)))
-39-:	551	if (prim_mubi_pkg::mubi8_test_true_strict(dout_locked_q))
-40-:	573	if ((error_q == NoError))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	-29-	-30-	-31-	-32-	-33-	-34-	-35-	-36-	-37-	-38-	-39-	-40-	Status	Tests	Exclude Annotation
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
InitWaitSt	-	-	1	1	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T39,T40,T41
InitWaitSt	-	-	1	1	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T64,T76,T112
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitDescrSt	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitDescrSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitDescrWaitSt	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitDescrWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
IdleSt	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T9
IdleSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IdleSt	-	-	-	-	-	-	-	-	-	0	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T10
IdleSt	-	-	-	-	-	-	-	-	-	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
CnstyReadSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T10
CnstyReadSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
CnstyReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T10
CnstyReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T10
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T10
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T42,T22,T43
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T10
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T77,T37,T113
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T10
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
IntegScrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
IntegScrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
IntegScrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
IntegScrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	1	-	-	-	-	-	-	-	Not Covered
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	0	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	1	-	-	-	-	-	-	Unreachable
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	0	-	-	-	-	-	-	Not Covered
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegDigPadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T2,T3
IntegDigPadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Not Covered
IntegDigFinSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T2,T3
IntegDigFinSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T3
IntegDigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	Covered	T1,T2,T3
IntegDigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	Covered	T4,T5,T9
IntegDigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T6,T44,T45
IntegDigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T28,T29,T30
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T6
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T28,T29,T30

	LineNo.	Expression
-1-:	595	if (ecc_err)
-2-:	597	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	602	if ((lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || cnt_err))
-2-:	605	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T6
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	750	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	753	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	34	33	97.06	28	82.35
Cover properties	0	0		0
Cover sequences	0	0		0
Total	34	33	97.06	28	82.35

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	516265254	515410973	0	0
BypassEnable0_A	516265254	0	0	0
BypassEnable1_A	516265254	515410973	0	0
CnstyChkAckKnown_A	516265254	515410973	0	0
DataKnown_A	516265254	515410973	0	0
DigestKnown_A	516265254	515410973	0	0
DigestOffsetMustBeRepresentable_A	1149	1149	0	0
EccErrorState_A	516265254	0	0	0
ErrorKnown_A	516265254	515410973	0	0
InitDoneKnown_A	516265254	515410973	0	0
InitReadLocksPartition_A	516265254	108190200	0	0
InitWriteLocksPartition_A	516265254	108190200	0	0
IntegChkAckKnown_A	516265254	515410973	0	0
OffsetMustBeBlockAligned_A	1149	1149	0	0
OtpAddrKnown_A	516265254	515410973	0	0
OtpCmdKnown_A	516265254	515410973	0	0
OtpErrorState_A	0	0	0	0
OtpReqKnown_A	516265254	515410973	0	0
OtpSizeKnown_A	516265254	515410973	0	0
OtpWdataKnown_A	516265254	515410973	0	0
ReadLockImpliesDigest_A	516265254	515410973	0	0
ReadLockPropagation_A	516265254	0	0	0
ScrambledImpliesDigest_A	516265254	0	0	0
ScrmblCmdKnown_A	516265254	515410973	0	0
ScrmblDataKnown_A	516017751	515163470	0	0
ScrmblModeKnown_A	516265254	515410973	0	0
ScrmblMtxReqKnown_A	516265254	515410973	0	0
ScrmblSelKnown_A	516265254	515410973	0	0
ScrmblValidKnown_A	516265254	515410973	0	0
SizeMustBeBlockAligned_A	1149	1149	0	0
WriteLockImpliesDigest_A	516265254	0	0	0
WriteLockPropagation_A	516265254	3178440	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	516265254	28862237	0	0
u_state_regs_A	516265254	515410973	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516265254	515410973	0	0
T1	67273	67003	0	0
T2	10108	9860	0	0
T3	11547	11294	0	0
T4	866644	866633	0	0
T5	111724	110861	0	0
T6	13442	13170	0	0
T7	147884	147096	0	0
T8	18642	18371	0	0
T9	27010	26515	0	0
T10	19808	19512	0	0

BypassEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516265254	0	0	0

BypassEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516265254	515410973	0	0
T1	67273	67003	0	0
T2	10108	9860	0	0
T3	11547	11294	0	0
T4	866644	866633	0	0
T5	111724	110861	0	0
T6	13442	13170	0	0
T7	147884	147096	0	0
T8	18642	18371	0	0
T9	27010	26515	0	0
T10	19808	19512	0	0

CnstyChkAckKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516265254	515410973	0	0
T1	67273	67003	0	0
T2	10108	9860	0	0
T3	11547	11294	0	0
T4	866644	866633	0	0
T5	111724	110861	0	0
T6	13442	13170	0	0
T7	147884	147096	0	0
T8	18642	18371	0	0
T9	27010	26515	0	0
T10	19808	19512	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516265254	515410973	0	0
T1	67273	67003	0	0
T2	10108	9860	0	0
T3	11547	11294	0	0
T4	866644	866633	0	0
T5	111724	110861	0	0
T6	13442	13170	0	0
T7	147884	147096	0	0
T8	18642	18371	0	0
T9	27010	26515	0	0
T10	19808	19512	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516265254	515410973	0	0
T1	67273	67003	0	0
T2	10108	9860	0	0
T3	11547	11294	0	0
T4	866644	866633	0	0
T5	111724	110861	0	0
T6	13442	13170	0	0
T7	147884	147096	0	0
T8	18642	18371	0	0
T9	27010	26515	0	0
T10	19808	19512	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516265254	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516265254	515410973	0	0
T1	67273	67003	0	0
T2	10108	9860	0	0
T3	11547	11294	0	0
T4	866644	866633	0	0
T5	111724	110861	0	0
T6	13442	13170	0	0
T7	147884	147096	0	0
T8	18642	18371	0	0
T9	27010	26515	0	0
T10	19808	19512	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516265254	515410973	0	0
T1	67273	67003	0	0
T2	10108	9860	0	0
T3	11547	11294	0	0
T4	866644	866633	0	0
T5	111724	110861	0	0
T6	13442	13170	0	0
T7	147884	147096	0	0
T8	18642	18371	0	0
T9	27010	26515	0	0
T10	19808	19512	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516265254	108190200	0	0
T1	67273	54865	0	0
T2	10108	3903	0	0
T3	11547	715	0	0
T4	866644	400591	0	0
T5	111724	4637	0	0
T6	13442	4159	0	0
T7	147884	78218	0	0
T8	18642	9740	0	0
T9	27010	1425	0	0
T10	19808	11042	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516265254	108190200	0	0
T1	67273	54865	0	0
T2	10108	3903	0	0
T3	11547	715	0	0
T4	866644	400591	0	0
T5	111724	4637	0	0
T6	13442	4159	0	0
T7	147884	78218	0	0
T8	18642	9740	0	0
T9	27010	1425	0	0
T10	19808	11042	0	0

IntegChkAckKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516265254	515410973	0	0
T1	67273	67003	0	0
T2	10108	9860	0	0
T3	11547	11294	0	0
T4	866644	866633	0	0
T5	111724	110861	0	0
T6	13442	13170	0	0
T7	147884	147096	0	0
T8	18642	18371	0	0
T9	27010	26515	0	0
T10	19808	19512	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516265254	515410973	0	0
T1	67273	67003	0	0
T2	10108	9860	0	0
T3	11547	11294	0	0
T4	866644	866633	0	0
T5	111724	110861	0	0
T6	13442	13170	0	0
T7	147884	147096	0	0
T8	18642	18371	0	0
T9	27010	26515	0	0
T10	19808	19512	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516265254	515410973	0	0
T1	67273	67003	0	0
T2	10108	9860	0	0
T3	11547	11294	0	0
T4	866644	866633	0	0
T5	111724	110861	0	0
T6	13442	13170	0	0
T7	147884	147096	0	0
T8	18642	18371	0	0
T9	27010	26515	0	0
T10	19808	19512	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516265254	515410973	0	0
T1	67273	67003	0	0
T2	10108	9860	0	0
T3	11547	11294	0	0
T4	866644	866633	0	0
T5	111724	110861	0	0
T6	13442	13170	0	0
T7	147884	147096	0	0
T8	18642	18371	0	0
T9	27010	26515	0	0
T10	19808	19512	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516265254	515410973	0	0
T1	67273	67003	0	0
T2	10108	9860	0	0
T3	11547	11294	0	0
T4	866644	866633	0	0
T5	111724	110861	0	0
T6	13442	13170	0	0
T7	147884	147096	0	0
T8	18642	18371	0	0
T9	27010	26515	0	0
T10	19808	19512	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516265254	515410973	0	0
T1	67273	67003	0	0
T2	10108	9860	0	0
T3	11547	11294	0	0
T4	866644	866633	0	0
T5	111724	110861	0	0
T6	13442	13170	0	0
T7	147884	147096	0	0
T8	18642	18371	0	0
T9	27010	26515	0	0
T10	19808	19512	0	0

ReadLockImpliesDigest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516265254	515410973	0	0
T1	67273	67003	0	0
T2	10108	9860	0	0
T3	11547	11294	0	0
T4	866644	866633	0	0
T5	111724	110861	0	0
T6	13442	13170	0	0
T7	147884	147096	0	0
T8	18642	18371	0	0
T9	27010	26515	0	0
T10	19808	19512	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516265254	0	0	0

ScrambledImpliesDigest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516265254	0	0	0

ScrmblCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516265254	515410973	0	0
T1	67273	67003	0	0
T2	10108	9860	0	0
T3	11547	11294	0	0
T4	866644	866633	0	0
T5	111724	110861	0	0
T6	13442	13170	0	0
T7	147884	147096	0	0
T8	18642	18371	0	0
T9	27010	26515	0	0
T10	19808	19512	0	0

ScrmblDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516017751	515163470	0	0
T1	67273	67003	0	0
T2	10108	9860	0	0
T3	11547	11294	0	0
T4	866644	866633	0	0
T5	111724	110861	0	0
T6	13442	13170	0	0
T7	147884	147096	0	0
T8	18642	18371	0	0
T9	27010	26515	0	0
T10	19808	19512	0	0

ScrmblModeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516265254	515410973	0	0
T1	67273	67003	0	0
T2	10108	9860	0	0
T3	11547	11294	0	0
T4	866644	866633	0	0
T5	111724	110861	0	0
T6	13442	13170	0	0
T7	147884	147096	0	0
T8	18642	18371	0	0
T9	27010	26515	0	0
T10	19808	19512	0	0

ScrmblMtxReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516265254	515410973	0	0
T1	67273	67003	0	0
T2	10108	9860	0	0
T3	11547	11294	0	0
T4	866644	866633	0	0
T5	111724	110861	0	0
T6	13442	13170	0	0
T7	147884	147096	0	0
T8	18642	18371	0	0
T9	27010	26515	0	0
T10	19808	19512	0	0

ScrmblSelKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516265254	515410973	0	0
T1	67273	67003	0	0
T2	10108	9860	0	0
T3	11547	11294	0	0
T4	866644	866633	0	0
T5	111724	110861	0	0
T6	13442	13170	0	0
T7	147884	147096	0	0
T8	18642	18371	0	0
T9	27010	26515	0	0
T10	19808	19512	0	0

ScrmblValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516265254	515410973	0	0
T1	67273	67003	0	0
T2	10108	9860	0	0
T3	11547	11294	0	0
T4	866644	866633	0	0
T5	111724	110861	0	0
T6	13442	13170	0	0
T7	147884	147096	0	0
T8	18642	18371	0	0
T9	27010	26515	0	0
T10	19808	19512	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

WriteLockImpliesDigest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516265254	0	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516265254	3178440	0	0
T11	243916	0	0	0
T13	61860	0	0	0
T19	53153	936	0	0
T20	44048	0	0	0
T21	59439	0	0	0
T34	123865	79778	0	0
T35	55381	0	0	0
T53	0	7101	0	0
T65	0	13057	0	0
T71	0	14532	0	0
T90	0	28266	0	0
T94	0	8979	0	0
T95	0	959	0	0
T98	0	12725	0	0
T100	10841	0	0	0
T101	9996	0	0	0
T102	81641	0	0	0
T103	0	1566	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516265254	28862237	0	0
T3	11547	5303	0	0
T4	866644	0	0	0
T5	111724	28248	0	0
T6	13442	2745	0	0
T7	147884	12959	0	0
T8	18642	0	0	0
T9	27010	6984	0	0
T10	19808	0	0	0
T19	53153	35667	0	0
T20	0	27367	0	0
T34	0	556901	0	0
T35	0	4163	0	0
T42	0	6485	0	0
T99	6597	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516265254	515410973	0	0
T1	67273	67003	0	0
T2	10108	9860	0	0
T3	11547	11294	0	0
T4	866644	866633	0	0
T5	111724	110861	0	0
T6	13442	13170	0	0
T7	147884	147096	0	0
T8	18642	18371	0	0
T9	27010	26515	0	0
T10	19808	19512	0	0