Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

22875614

1

T1

1281

T2

1132

T3

4453

full_word

7537504

1

T1

233

T2

919

T3

197

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	30412798	1			T1	1514		T2	2051		T3	4650
auto[TlIntgErrCmd]	95	1			T243	4		T244	6		T245	2
auto[TlIntgErrData]	109	1			T243	1		T244	3		T245	6
auto[TlIntgErrBoth]	116	1			T243	5		T244	1		T245	12

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9466019

1

T1

1345

T2

1824

T3

4536

auto[1]

20947099

1

T1

169

T2

227

T3

114

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6071781	1			T1	1184		T2	1004		T3	4394
auto[TlIntgErrNone]	partial	auto[1]	16803543	1			T1	97		T2	128		T3	59
auto[TlIntgErrNone]	full_word	auto[0]	3394082	1			T1	161		T2	820		T3	142
auto[TlIntgErrNone]	full_word	auto[1]	4143392	1			T1	72		T2	99		T3	55
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T243	1		T245	2		T250	4
auto[TlIntgErrCmd]	partial	auto[1]	45	1			T243	2		T244	6		T250	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T243	1		T250	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T334	1		T339	1		T251	1
auto[TlIntgErrData]	partial	auto[0]	49	1			T245	3		T250	6		T334	5
auto[TlIntgErrData]	partial	auto[1]	47	1			T243	1		T244	2		T245	3
auto[TlIntgErrData]	full_word	auto[0]	7	1			T244	1		T339	1		T343	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T337	1		T344	1		T341	1
auto[TlIntgErrBoth]	partial	auto[0]	51	1			T243	1		T245	7		T334	2
auto[TlIntgErrBoth]	partial	auto[1]	55	1			T243	4		T244	1		T245	4
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T250	1		T335	1		T336	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T245	1		T340	1		T335	1