Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.82	97.40	96.15	96.96		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	403025375	6977276	0	0
check_regwen_rd_A	403025375	3915	0	0
check_timeout_rd_A	403025375	3208	0	0
check_trigger_regwen_rd_A	403025375	4122	0	0
consistency_check_period_rd_A	403025375	4100	0	0
creator_sw_cfg_read_lock_rd_A	403025375	3207	0	0
direct_access_address_rd_A	403025375	2170	0	0
direct_access_wdata_0_rd_A	403025375	1349	0	0
direct_access_wdata_1_rd_A	403025375	1502	0	0
integrity_check_period_rd_A	403025375	3764	0	0
intr_enable_rd_A	403025375	4636	0	0
owner_sw_cfg_read_lock_rd_A	403025375	2771	0	0
rot_creator_auth_codesign_read_lock_rd_A	403025375	2930	0	0
rot_creator_auth_state_read_lock_rd_A	403025375	3005	0	0
vendor_test_read_lock_rd_A	403025375	2882	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403025375	6977276	0	0
T6	739260	162508	0	0
T7	27558	0	0	0
T9	25330	0	0	0
T10	17432	0	0	0
T11	0	271372	0	0
T12	0	184648	0	0
T22	54725	0	0	0
T31	0	19595	0	0
T61	7787	0	0	0
T87	0	84718	0	0
T95	12835	0	0	0
T96	13671	0	0	0
T97	49851	0	0	0
T103	11410	0	0	0
T144	0	38149	0	0
T145	0	41474	0	0
T146	0	143938	0	0
T170	0	156106	0	0
T252	0	145338	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403025375	3915	0	0
T48	10301	0	0	0
T128	12941	0	0	0
T146	840965	184	0	0
T148	0	151	0	0
T156	9383	0	0	0
T173	60749	0	0	0
T232	0	13	0	0
T252	0	83	0	0
T306	0	27	0	0
T312	0	78	0	0
T313	0	62	0	0
T314	0	93	0	0
T315	0	30	0	0
T316	0	33	0	0
T317	5156	0	0	0
T318	16321	0	0	0
T319	11278	0	0	0
T320	20409	0	0	0
T321	8347	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403025375	3208	0	0
T48	10301	0	0	0
T128	12941	0	0	0
T146	840965	195	0	0
T148	0	194	0	0
T156	9383	0	0	0
T173	60749	0	0	0
T232	0	16	0	0
T252	0	99	0	0
T306	0	19	0	0
T312	0	67	0	0
T313	0	77	0	0
T314	0	97	0	0
T315	0	25	0	0
T316	0	38	0	0
T317	5156	0	0	0
T318	16321	0	0	0
T319	11278	0	0	0
T320	20409	0	0	0
T321	8347	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403025375	4122	0	0
T48	10301	0	0	0
T128	12941	0	0	0
T146	840965	159	0	0
T148	0	179	0	0
T156	9383	0	0	0
T173	60749	0	0	0
T232	0	34	0	0
T252	0	92	0	0
T306	0	29	0	0
T312	0	90	0	0
T313	0	37	0	0
T314	0	128	0	0
T315	0	45	0	0
T316	0	49	0	0
T317	5156	0	0	0
T318	16321	0	0	0
T319	11278	0	0	0
T320	20409	0	0	0
T321	8347	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403025375	4100	0	0
T48	10301	0	0	0
T128	12941	0	0	0
T146	840965	152	0	0
T148	0	190	0	0
T156	9383	0	0	0
T173	60749	0	0	0
T232	0	41	0	0
T252	0	100	0	0
T306	0	15	0	0
T312	0	101	0	0
T313	0	59	0	0
T314	0	112	0	0
T315	0	55	0	0
T316	0	15	0	0
T317	5156	0	0	0
T318	16321	0	0	0
T319	11278	0	0	0
T320	20409	0	0	0
T321	8347	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403025375	3207	0	0
T48	10301	0	0	0
T128	12941	0	0	0
T146	840965	161	0	0
T148	0	182	0	0
T156	9383	0	0	0
T173	60749	0	0	0
T232	0	59	0	0
T252	0	82	0	0
T306	0	38	0	0
T312	0	80	0	0
T313	0	39	0	0
T314	0	124	0	0
T315	0	31	0	0
T316	0	33	0	0
T317	5156	0	0	0
T318	16321	0	0	0
T319	11278	0	0	0
T320	20409	0	0	0
T321	8347	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403025375	2170	0	0
T48	10301	0	0	0
T128	12941	0	0	0
T146	840965	152	0	0
T148	0	166	0	0
T156	9383	0	0	0
T173	60749	0	0	0
T232	0	53	0	0
T252	0	94	0	0
T306	0	16	0	0
T312	0	71	0	0
T313	0	17	0	0
T314	0	108	0	0
T315	0	72	0	0
T316	0	65	0	0
T317	5156	0	0	0
T318	16321	0	0	0
T319	11278	0	0	0
T320	20409	0	0	0
T321	8347	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403025375	1349	0	0
T48	10301	0	0	0
T128	12941	0	0	0
T146	840965	151	0	0
T148	0	157	0	0
T156	9383	0	0	0
T173	60749	0	0	0
T232	0	9	0	0
T252	0	45	0	0
T306	0	11	0	0
T312	0	81	0	0
T313	0	28	0	0
T314	0	78	0	0
T315	0	37	0	0
T316	0	17	0	0
T317	5156	0	0	0
T318	16321	0	0	0
T319	11278	0	0	0
T320	20409	0	0	0
T321	8347	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403025375	1502	0	0
T48	10301	0	0	0
T128	12941	0	0	0
T146	840965	155	0	0
T148	0	145	0	0
T156	9383	0	0	0
T173	60749	0	0	0
T232	0	35	0	0
T252	0	86	0	0
T306	0	13	0	0
T312	0	46	0	0
T313	0	29	0	0
T314	0	70	0	0
T315	0	47	0	0
T316	0	38	0	0
T317	5156	0	0	0
T318	16321	0	0	0
T319	11278	0	0	0
T320	20409	0	0	0
T321	8347	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403025375	3764	0	0
T48	10301	0	0	0
T128	12941	0	0	0
T146	840965	128	0	0
T148	0	126	0	0
T156	9383	0	0	0
T173	60749	0	0	0
T232	0	40	0	0
T252	0	83	0	0
T306	0	27	0	0
T312	0	120	0	0
T313	0	46	0	0
T314	0	74	0	0
T315	0	64	0	0
T316	0	46	0	0
T317	5156	0	0	0
T318	16321	0	0	0
T319	11278	0	0	0
T320	20409	0	0	0
T321	8347	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403025375	4636	0	0
T43	15210	0	0	0
T110	826113	10	0	0
T114	30137	0	0	0
T128	12941	0	0	0
T143	11017	0	0	0
T144	180918	0	0	0
T145	242897	0	0	0
T146	840965	149	0	0
T148	0	167	0	0
T232	0	45	0	0
T252	0	106	0	0
T306	0	37	0	0
T312	0	115	0	0
T313	0	46	0	0
T317	5156	0	0	0
T318	16321	0	0	0
T322	0	27	0	0
T323	0	5	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403025375	2771	0	0
T48	10301	0	0	0
T128	12941	0	0	0
T146	840965	145	0	0
T148	0	128	0	0
T156	9383	0	0	0
T173	60749	0	0	0
T232	0	41	0	0
T252	0	122	0	0
T306	0	25	0	0
T312	0	97	0	0
T313	0	27	0	0
T314	0	71	0	0
T315	0	58	0	0
T316	0	25	0	0
T317	5156	0	0	0
T318	16321	0	0	0
T319	11278	0	0	0
T320	20409	0	0	0
T321	8347	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403025375	2930	0	0
T48	10301	0	0	0
T128	12941	0	0	0
T146	840965	212	0	0
T148	0	179	0	0
T156	9383	0	0	0
T173	60749	0	0	0
T232	0	36	0	0
T252	0	106	0	0
T306	0	29	0	0
T312	0	90	0	0
T313	0	44	0	0
T314	0	81	0	0
T315	0	20	0	0
T316	0	17	0	0
T317	5156	0	0	0
T318	16321	0	0	0
T319	11278	0	0	0
T320	20409	0	0	0
T321	8347	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403025375	3005	0	0
T48	10301	0	0	0
T128	12941	0	0	0
T146	840965	187	0	0
T148	0	207	0	0
T156	9383	0	0	0
T173	60749	0	0	0
T232	0	34	0	0
T252	0	117	0	0
T306	0	15	0	0
T312	0	78	0	0
T313	0	40	0	0
T314	0	121	0	0
T315	0	58	0	0
T316	0	18	0	0
T317	5156	0	0	0
T318	16321	0	0	0
T319	11278	0	0	0
T320	20409	0	0	0
T321	8347	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403025375	2882	0	0
T48	10301	0	0	0
T128	12941	0	0	0
T146	840965	143	0	0
T148	0	171	0	0
T156	9383	0	0	0
T173	60749	0	0	0
T232	0	21	0	0
T252	0	113	0	0
T306	0	25	0	0
T312	0	114	0	0
T313	0	35	0	0
T314	0	110	0	0
T315	0	36	0	0
T316	0	25	0	0
T317	5156	0	0	0
T318	16321	0	0	0
T319	11278	0	0	0
T320	20409	0	0	0
T321	8347	0	0	0