Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

25368888

1

T1

489

T2

738

T3

2539

full_word

8302004

1

T1

210

T2

216

T3

2374

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	33670592	1			T1	699		T2	954		T3	4913
auto[TlIntgErrCmd]	105	1			T265	6		T266	10		T267	7
auto[TlIntgErrData]	112	1			T266	6		T267	5		T273	6
auto[TlIntgErrBoth]	83	1			T265	4		T266	4		T267	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9601177

1

T1

420

T2

670

T3

4428

auto[1]

24069715

1

T1

279

T2

284

T3

485

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5997433	1			T1	315		T2	565		T3	2231
auto[TlIntgErrNone]	partial	auto[1]	19371178	1			T1	174		T2	173		T3	308
auto[TlIntgErrNone]	full_word	auto[0]	3603611	1			T1	105		T2	105		T3	2197
auto[TlIntgErrNone]	full_word	auto[1]	4698370	1			T1	105		T2	111		T3	177
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T265	3		T266	5		T267	1
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T265	3		T266	5		T267	4
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T267	2		T384	1		T380	2
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T383	1		T381	1		T386	1
auto[TlIntgErrData]	partial	auto[0]	41	1			T266	1		T267	1		T273	2
auto[TlIntgErrData]	partial	auto[1]	59	1			T266	3		T267	3		T273	4
auto[TlIntgErrData]	full_word	auto[0]	6	1			T266	1		T267	1		T383	2
auto[TlIntgErrData]	full_word	auto[1]	6	1			T266	1		T383	1		T382	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T265	2		T266	1		T267	3
auto[TlIntgErrBoth]	partial	auto[1]	41	1			T265	2		T266	3		T267	5
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T381	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T383	1		T381	1		-	-