Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.85	97.40	96.15	97.10		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	481904453	8022953	0	0
check_regwen_rd_A	481904453	2749	0	0
check_timeout_rd_A	481904453	2565	0	0
check_trigger_regwen_rd_A	481904453	2678	0	0
consistency_check_period_rd_A	481904453	3403	0	0
creator_sw_cfg_read_lock_rd_A	481904453	2572	0	0
direct_access_address_rd_A	481904453	2268	0	0
direct_access_wdata_0_rd_A	481904453	1417	0	0
direct_access_wdata_1_rd_A	481904453	1671	0	0
integrity_check_period_rd_A	481904453	3226	0	0
intr_enable_rd_A	481904453	3849	0	0
owner_sw_cfg_read_lock_rd_A	481904453	2260	0	0
rot_creator_auth_codesign_read_lock_rd_A	481904453	2458	0	0
rot_creator_auth_state_read_lock_rd_A	481904453	2297	0	0
vendor_test_read_lock_rd_A	481904453	2401	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481904453	8022953	0	0
T4	280607	76642	0	0
T5	70923	0	0	0
T6	103716	0	0	0
T7	556173	171851	0	0
T8	0	101538	0	0
T10	48953	0	0	0
T11	49957	0	0	0
T12	18520	0	0	0
T14	0	141988	0	0
T16	0	144577	0	0
T25	0	6447	0	0
T33	40418	0	0	0
T65	12967	0	0	0
T111	8574	0	0	0
T169	0	76793	0	0
T232	0	39923	0	0
T274	0	93005	0	0
T275	0	47167	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481904453	2749	0	0
T55	18172	0	0	0
T68	0	63	0	0
T193	15326	0	0	0
T212	12174	0	0	0
T216	31792	0	0	0
T217	15518	0	0	0
T254	20508	0	0	0
T274	543571	117	0	0
T280	0	128	0	0
T347	0	16	0	0
T348	0	41	0	0
T349	0	170	0	0
T350	0	70	0	0
T351	0	66	0	0
T352	0	67	0	0
T353	0	104	0	0
T354	175198	0	0	0
T355	3395	0	0	0
T356	74103	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481904453	2565	0	0
T55	18172	0	0	0
T68	0	61	0	0
T193	15326	0	0	0
T212	12174	0	0	0
T216	31792	0	0	0
T217	15518	0	0	0
T254	20508	0	0	0
T274	543571	123	0	0
T280	0	211	0	0
T347	0	17	0	0
T348	0	61	0	0
T349	0	201	0	0
T350	0	78	0	0
T351	0	85	0	0
T352	0	72	0	0
T353	0	122	0	0
T354	175198	0	0	0
T355	3395	0	0	0
T356	74103	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481904453	2678	0	0
T55	18172	0	0	0
T68	0	67	0	0
T193	15326	0	0	0
T212	12174	0	0	0
T216	31792	0	0	0
T217	15518	0	0	0
T254	20508	0	0	0
T274	543571	118	0	0
T280	0	167	0	0
T347	0	39	0	0
T348	0	41	0	0
T349	0	139	0	0
T350	0	93	0	0
T351	0	82	0	0
T352	0	50	0	0
T353	0	115	0	0
T354	175198	0	0	0
T355	3395	0	0	0
T356	74103	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481904453	3403	0	0
T55	18172	0	0	0
T68	0	49	0	0
T193	15326	0	0	0
T212	12174	0	0	0
T216	31792	0	0	0
T217	15518	0	0	0
T254	20508	0	0	0
T274	543571	182	0	0
T280	0	223	0	0
T347	0	9	0	0
T348	0	61	0	0
T349	0	198	0	0
T350	0	126	0	0
T351	0	81	0	0
T352	0	104	0	0
T353	0	126	0	0
T354	175198	0	0	0
T355	3395	0	0	0
T356	74103	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481904453	2572	0	0
T55	18172	0	0	0
T68	0	33	0	0
T193	15326	0	0	0
T212	12174	0	0	0
T216	31792	0	0	0
T217	15518	0	0	0
T254	20508	0	0	0
T274	543571	124	0	0
T280	0	197	0	0
T347	0	15	0	0
T348	0	48	0	0
T349	0	187	0	0
T350	0	119	0	0
T351	0	108	0	0
T352	0	71	0	0
T353	0	103	0	0
T354	175198	0	0	0
T355	3395	0	0	0
T356	74103	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481904453	2268	0	0
T55	18172	0	0	0
T68	0	36	0	0
T193	15326	0	0	0
T212	12174	0	0	0
T216	31792	0	0	0
T217	15518	0	0	0
T254	20508	0	0	0
T274	543571	120	0	0
T280	0	189	0	0
T347	0	6	0	0
T348	0	13	0	0
T349	0	194	0	0
T350	0	109	0	0
T351	0	67	0	0
T352	0	95	0	0
T353	0	119	0	0
T354	175198	0	0	0
T355	3395	0	0	0
T356	74103	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481904453	1417	0	0
T55	18172	0	0	0
T68	0	53	0	0
T193	15326	0	0	0
T212	12174	0	0	0
T216	31792	0	0	0
T217	15518	0	0	0
T254	20508	0	0	0
T274	543571	85	0	0
T280	0	134	0	0
T347	0	14	0	0
T348	0	19	0	0
T349	0	172	0	0
T350	0	50	0	0
T351	0	36	0	0
T352	0	43	0	0
T353	0	72	0	0
T354	175198	0	0	0
T355	3395	0	0	0
T356	74103	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481904453	1671	0	0
T55	18172	0	0	0
T68	0	27	0	0
T193	15326	0	0	0
T212	12174	0	0	0
T216	31792	0	0	0
T217	15518	0	0	0
T254	20508	0	0	0
T274	543571	101	0	0
T280	0	110	0	0
T347	0	9	0	0
T348	0	37	0	0
T349	0	157	0	0
T350	0	53	0	0
T351	0	70	0	0
T352	0	47	0	0
T353	0	118	0	0
T354	175198	0	0	0
T355	3395	0	0	0
T356	74103	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481904453	3226	0	0
T55	18172	0	0	0
T68	0	56	0	0
T193	15326	0	0	0
T212	12174	0	0	0
T216	31792	0	0	0
T217	15518	0	0	0
T254	20508	0	0	0
T274	543571	157	0	0
T280	0	169	0	0
T347	0	39	0	0
T348	0	21	0	0
T349	0	203	0	0
T350	0	126	0	0
T351	0	60	0	0
T352	0	69	0	0
T353	0	161	0	0
T354	175198	0	0	0
T355	3395	0	0	0
T356	74103	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481904453	3849	0	0
T55	18172	0	0	0
T165	0	62	0	0
T166	0	13	0	0
T193	15326	0	0	0
T212	12174	0	0	0
T216	31792	0	0	0
T217	15518	0	0	0
T254	20508	0	0	0
T260	0	33	0	0
T274	543571	160	0	0
T347	0	39	0	0
T348	0	44	0	0
T349	0	155	0	0
T350	0	158	0	0
T354	175198	0	0	0
T355	3395	0	0	0
T356	74103	0	0	0
T357	0	25	0	0
T358	0	37	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481904453	2260	0	0
T55	18172	0	0	0
T68	0	48	0	0
T193	15326	0	0	0
T212	12174	0	0	0
T216	31792	0	0	0
T217	15518	0	0	0
T254	20508	0	0	0
T274	543571	105	0	0
T280	0	134	0	0
T347	0	7	0	0
T348	0	37	0	0
T349	0	207	0	0
T350	0	94	0	0
T351	0	92	0	0
T352	0	94	0	0
T353	0	98	0	0
T354	175198	0	0	0
T355	3395	0	0	0
T356	74103	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481904453	2458	0	0
T55	18172	0	0	0
T68	0	37	0	0
T193	15326	0	0	0
T212	12174	0	0	0
T216	31792	0	0	0
T217	15518	0	0	0
T254	20508	0	0	0
T274	543571	99	0	0
T280	0	194	0	0
T347	0	16	0	0
T348	0	48	0	0
T349	0	104	0	0
T350	0	79	0	0
T351	0	98	0	0
T352	0	104	0	0
T353	0	109	0	0
T354	175198	0	0	0
T355	3395	0	0	0
T356	74103	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481904453	2297	0	0
T55	18172	0	0	0
T68	0	36	0	0
T193	15326	0	0	0
T212	12174	0	0	0
T216	31792	0	0	0
T217	15518	0	0	0
T254	20508	0	0	0
T274	543571	126	0	0
T280	0	168	0	0
T347	0	8	0	0
T348	0	50	0	0
T349	0	118	0	0
T350	0	60	0	0
T351	0	112	0	0
T352	0	77	0	0
T353	0	92	0	0
T354	175198	0	0	0
T355	3395	0	0	0
T356	74103	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481904453	2401	0	0
T55	18172	0	0	0
T68	0	30	0	0
T193	15326	0	0	0
T212	12174	0	0	0
T216	31792	0	0	0
T217	15518	0	0	0
T254	20508	0	0	0
T274	543571	123	0	0
T280	0	243	0	0
T347	0	17	0	0
T348	0	16	0	0
T349	0	147	0	0
T350	0	108	0	0
T351	0	67	0	0
T352	0	65	0	0
T353	0	117	0	0
T354	175198	0	0	0
T355	3395	0	0	0
T356	74103	0	0	0