Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

23281294

1

T1

6211

T2

2422

T3

1286

full_word

7687988

1

T1

5721

T2

801

T3

614

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	30968992	1			T1	11932		T2	3223		T3	1900
auto[TlIntgErrCmd]	86	1			T262	9		T263	2		T264	2
auto[TlIntgErrData]	87	1			T262	5		T263	3		T264	3
auto[TlIntgErrBoth]	117	1			T262	6		T263	5		T264	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9303245

1

T1

10131

T2

2935

T3

1739

auto[1]

21666037

1

T1

1801

T2

288

T3

161

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5870288	1			T1	5198		T2	2245		T3	1201
auto[TlIntgErrNone]	partial	auto[1]	17410747	1			T1	1013		T2	177		T3	85
auto[TlIntgErrNone]	full_word	auto[0]	3432820	1			T1	4933		T2	690		T3	538
auto[TlIntgErrNone]	full_word	auto[1]	4255137	1			T1	788		T2	111		T3	76
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T262	6		T263	2		T264	1
auto[TlIntgErrCmd]	partial	auto[1]	42	1			T262	3		T264	1		T268	3
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T267	1		T357	2		T360	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T362	1		T360	1		T363	1
auto[TlIntgErrData]	partial	auto[0]	42	1			T262	3		T263	2		T264	2
auto[TlIntgErrData]	partial	auto[1]	34	1			T262	1		T263	1		T264	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T268	1		T267	1		T266	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T262	1		T364	1		T266	1
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T262	3		T263	4		T264	2
auto[TlIntgErrBoth]	partial	auto[1]	62	1			T262	3		T263	1		T264	3
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T266	1		T361	1		T365	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T366	2		T360	2		T367	1