Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.82	97.40	96.15	96.92		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	429542957	7218466	0	0
check_regwen_rd_A	429542957	3196	0	0
check_timeout_rd_A	429542957	1973	0	0
check_trigger_regwen_rd_A	429542957	3080	0	0
consistency_check_period_rd_A	429542957	3364	0	0
creator_sw_cfg_read_lock_rd_A	429542957	2029	0	0
direct_access_address_rd_A	429542957	1565	0	0
direct_access_wdata_0_rd_A	429542957	1037	0	0
direct_access_wdata_1_rd_A	429542957	1204	0	0
integrity_check_period_rd_A	429542957	3122	0	0
intr_enable_rd_A	429542957	4103	0	0
owner_sw_cfg_read_lock_rd_A	429542957	1736	0	0
rot_creator_auth_codesign_read_lock_rd_A	429542957	2074	0	0
rot_creator_auth_state_read_lock_rd_A	429542957	1808	0	0
vendor_test_read_lock_rd_A	429542957	2030	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429542957	7218466	0	0
T5	291101	64105	0	0
T6	319264	8901	0	0
T7	0	59845	0	0
T10	14777	0	0	0
T11	14354	0	0	0
T12	67539	0	0	0
T16	0	30622	0	0
T17	0	162889	0	0
T18	0	189703	0	0
T26	0	176377	0	0
T45	92004	0	0	0
T70	13652	0	0	0
T71	8970	0	0	0
T88	10857	0	0	0
T89	24762	0	0	0
T215	0	99872	0	0
T225	0	239342	0	0
T270	0	29766	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429542957	3196	0	0
T113	0	64	0	0
T119	54260	0	0	0
T180	74035	0	0	0
T192	11371	0	0	0
T219	106761	0	0	0
T238	646803	0	0	0
T284	645857	125	0	0
T285	484491	0	0	0
T288	0	68	0	0
T294	64504	0	0	0
T295	109459	46	0	0
T296	25041	0	0	0
T345	0	166	0	0
T346	0	55	0	0
T347	0	47	0	0
T348	0	42	0	0
T349	0	47	0	0
T350	0	72	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429542957	1973	0	0
T113	0	41	0	0
T119	54260	0	0	0
T180	74035	0	0	0
T192	11371	0	0	0
T219	106761	0	0	0
T238	646803	0	0	0
T284	645857	204	0	0
T285	484491	0	0	0
T288	0	83	0	0
T294	64504	0	0	0
T295	109459	37	0	0
T296	25041	0	0	0
T345	0	180	0	0
T346	0	64	0	0
T347	0	50	0	0
T348	0	52	0	0
T349	0	63	0	0
T350	0	52	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429542957	3080	0	0
T113	0	25	0	0
T119	54260	0	0	0
T180	74035	0	0	0
T192	11371	0	0	0
T219	106761	0	0	0
T238	646803	0	0	0
T284	645857	148	0	0
T285	484491	0	0	0
T288	0	86	0	0
T294	64504	0	0	0
T295	109459	79	0	0
T296	25041	0	0	0
T345	0	150	0	0
T346	0	45	0	0
T347	0	30	0	0
T348	0	49	0	0
T349	0	65	0	0
T350	0	89	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429542957	3364	0	0
T113	0	54	0	0
T119	54260	0	0	0
T180	74035	0	0	0
T192	11371	0	0	0
T219	106761	0	0	0
T238	646803	0	0	0
T284	645857	147	0	0
T285	484491	0	0	0
T288	0	126	0	0
T294	64504	0	0	0
T295	109459	46	0	0
T296	25041	0	0	0
T345	0	136	0	0
T346	0	67	0	0
T347	0	41	0	0
T348	0	92	0	0
T349	0	22	0	0
T350	0	62	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429542957	2029	0	0
T113	0	43	0	0
T119	54260	0	0	0
T180	74035	0	0	0
T192	11371	0	0	0
T219	106761	0	0	0
T238	646803	0	0	0
T284	645857	187	0	0
T285	484491	0	0	0
T288	0	88	0	0
T294	64504	0	0	0
T295	109459	39	0	0
T296	25041	0	0	0
T345	0	105	0	0
T346	0	60	0	0
T347	0	35	0	0
T348	0	50	0	0
T349	0	36	0	0
T350	0	84	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429542957	1565	0	0
T113	0	42	0	0
T119	54260	0	0	0
T180	74035	0	0	0
T192	11371	0	0	0
T219	106761	0	0	0
T238	646803	0	0	0
T284	645857	112	0	0
T285	484491	0	0	0
T288	0	72	0	0
T294	64504	0	0	0
T295	109459	35	0	0
T296	25041	0	0	0
T345	0	148	0	0
T346	0	49	0	0
T347	0	53	0	0
T348	0	40	0	0
T349	0	48	0	0
T350	0	41	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429542957	1037	0	0
T113	0	25	0	0
T119	54260	0	0	0
T180	74035	0	0	0
T192	11371	0	0	0
T219	106761	0	0	0
T238	646803	0	0	0
T284	645857	118	0	0
T285	484491	0	0	0
T288	0	46	0	0
T294	64504	0	0	0
T295	109459	12	0	0
T296	25041	0	0	0
T345	0	82	0	0
T346	0	17	0	0
T347	0	62	0	0
T348	0	44	0	0
T349	0	54	0	0
T350	0	29	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429542957	1204	0	0
T113	0	18	0	0
T119	54260	0	0	0
T180	74035	0	0	0
T192	11371	0	0	0
T219	106761	0	0	0
T238	646803	0	0	0
T284	645857	131	0	0
T285	484491	0	0	0
T288	0	56	0	0
T294	64504	0	0	0
T295	109459	7	0	0
T296	25041	0	0	0
T345	0	148	0	0
T346	0	50	0	0
T347	0	32	0	0
T348	0	62	0	0
T349	0	46	0	0
T350	0	37	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429542957	3122	0	0
T113	0	50	0	0
T119	54260	0	0	0
T180	74035	0	0	0
T192	11371	0	0	0
T219	106761	0	0	0
T238	646803	0	0	0
T284	645857	175	0	0
T285	484491	0	0	0
T288	0	94	0	0
T294	64504	0	0	0
T295	109459	27	0	0
T296	25041	0	0	0
T345	0	116	0	0
T346	0	48	0	0
T347	0	61	0	0
T348	0	50	0	0
T349	0	44	0	0
T350	0	75	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429542957	4103	0	0
T14	121696	23	0	0
T26	774515	0	0	0
T52	12631	0	0	0
T76	0	77	0	0
T90	378796	30	0	0
T91	66442	0	0	0
T92	63848	0	0	0
T93	0	21	0	0
T102	12120	0	0	0
T103	20079	0	0	0
T104	13543	0	0	0
T105	40293	0	0	0
T113	0	70	0	0
T171	0	25	0	0
T284	0	114	0	0
T295	0	49	0	0
T345	0	145	0	0
T346	0	64	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429542957	1736	0	0
T113	0	57	0	0
T119	54260	0	0	0
T180	74035	0	0	0
T192	11371	0	0	0
T219	106761	0	0	0
T238	646803	0	0	0
T284	645857	153	0	0
T285	484491	0	0	0
T288	0	74	0	0
T294	64504	0	0	0
T295	109459	36	0	0
T296	25041	0	0	0
T345	0	123	0	0
T346	0	46	0	0
T347	0	33	0	0
T348	0	54	0	0
T349	0	32	0	0
T350	0	43	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429542957	2074	0	0
T113	0	56	0	0
T119	54260	0	0	0
T180	74035	0	0	0
T192	11371	0	0	0
T219	106761	0	0	0
T238	646803	0	0	0
T284	645857	201	0	0
T285	484491	0	0	0
T288	0	88	0	0
T294	64504	0	0	0
T295	109459	39	0	0
T296	25041	0	0	0
T345	0	193	0	0
T346	0	61	0	0
T347	0	60	0	0
T348	0	68	0	0
T349	0	66	0	0
T350	0	61	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429542957	1808	0	0
T113	0	52	0	0
T119	54260	0	0	0
T180	74035	0	0	0
T192	11371	0	0	0
T219	106761	0	0	0
T238	646803	0	0	0
T284	645857	153	0	0
T285	484491	0	0	0
T288	0	53	0	0
T294	64504	0	0	0
T295	109459	59	0	0
T296	25041	0	0	0
T345	0	89	0	0
T346	0	49	0	0
T347	0	57	0	0
T348	0	47	0	0
T349	0	34	0	0
T350	0	75	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429542957	2030	0	0
T113	0	53	0	0
T119	54260	0	0	0
T180	74035	0	0	0
T192	11371	0	0	0
T219	106761	0	0	0
T238	646803	0	0	0
T284	645857	172	0	0
T285	484491	0	0	0
T288	0	131	0	0
T294	64504	0	0	0
T295	109459	38	0	0
T296	25041	0	0	0
T345	0	122	0	0
T346	0	51	0	0
T347	0	86	0	0
T348	0	70	0	0
T349	0	17	0	0
T350	0	50	0	0