Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.23	100.00	100.00		90.00	100.00	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.56	100.00	100.00	100.00	90.00	98.15	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.82	97.40	96.15	96.92		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.82	97.40	96.15	96.92		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.82	97.40	96.15	96.92		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		86	86	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	61	61	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
153	1	1
154	1	1
156	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			==> MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
224		excluded
			Exclude Annotation: VC_COV_UNR
225		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
276		excluded
			Exclude Annotation: VC_COV_UNR
277		excluded
			Exclude Annotation: VC_COV_UNR
279		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
339	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T2,T3,T4
1	Excluded		VC_COV_UNR

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T4,T8
1	Covered	T20,T21,T22

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T126,T128
1	Covered	T126,T128

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T4,T8
1	Covered	T1,T4,T8

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T2,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T9

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T9

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	11	84.62
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T4,T8
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T3,T4
ReadWaitSt	252	Covered	T2,T3,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T4,T8
IdleSt->ReadSt	236	Covered	T2,T3,T4
InitSt->ErrorSt	315	Covered	T172,T173,T174
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T169,T175,T176
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T4,T5,T89
ReadSt->ReadWaitSt	252	Covered	T2,T3,T4
ReadWaitSt->ErrorSt	276	Not Covered
ReadWaitSt->IdleSt	270	Covered	T2,T3,T4
ResetSt->ErrorSt	315	Covered	T77,T78,T79
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests	Exclude Annotation
AccessError	256	Covered	T4,T5,T89
CheckFailError	317	Covered	T126,T128
FsmStateError	289	Covered	T1,T4,T8
MacroEccCorrError	221	Excluded		VC_COV_UNR
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded
AccessError->FsmStateError	325	Covered	T5,T7,T13
AccessError->MacroEccCorrError	221	Excluded
AccessError->NoError	235	Covered	T4,T5,T89
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded
CheckFailError->NoError	235	Covered	T126,T128
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded
FsmStateError->NoError	235	Covered	T1,T4,T8
MacroEccCorrError->AccessError	256	Excluded
MacroEccCorrError->CheckFailError	317	Excluded
MacroEccCorrError->FsmStateError	325	Excluded
MacroEccCorrError->NoError	235	Excluded
NoError->AccessError	256	Covered	T4,T5,T89
NoError->CheckFailError	317	Covered	T126,T128
NoError->FsmStateError	289	Covered	T1,T4,T8
NoError->MacroEccCorrError	221	Excluded

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	18	18	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests	Exclude Annotation
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T5,T14,T76
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T4,T5,T89
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T21,T22
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T4,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T4,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T4,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T4,T8
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T126,T128
1	0	Covered	T126,T128
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T4,T8
1	0	Covered	T1,T4,T8
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	426621337	425752618	0	0
DigestKnown_A	426621337	425752618	0	0
DigestOffsetMustBeRepresentable_A	1148	1148	0	0
EccErrorState_A	426621337	6667	0	0
ErrorKnown_A	426621337	425752618	0	0
FsmStateKnown_A	426621337	425752618	0	0
InitDoneKnown_A	426621337	425752618	0	0
InitReadLocksPartition_A	426621337	100602445	0	0
InitWriteLocksPartition_A	426621337	100602445	0	0
OffsetMustBeBlockAligned_A	1148	1148	0	0
OtpAddrKnown_A	426621337	425752618	0	0
OtpCmdKnown_A	426621337	425752618	0	0
OtpErrorState_A	426621337	0	0	0
OtpReqKnown_A	426621337	425752618	0	0
OtpSizeKnown_A	426621337	425752618	0	0
OtpWdataKnown_A	426621337	425752618	0	0
ReadLockPropagation_A	426621337	169358987	0	0
SizeMustBeBlockAligned_A	1148	1148	0	0
TlulGntKnown_A	426621337	425752618	0	0
TlulRdataKnown_A	426621337	425752618	0	0
TlulReadOnReadLock_A	426621337	7632	0	0
TlulRerrorKnown_A	426621337	425752618	0	0
TlulRvalidKnown_A	426621337	425752618	0	0
WriteLockPropagation_A	426621337	2349074	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	426621337	25001602	0	0
u_state_regs_A	426621337	425752618	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	6667	0	0
T38	44940	0	0	0
T126	10422	3318	0	0
T128	0	3349	0	0
T135	16027	0	0	0
T136	11945	0	0	0
T137	23447	0	0	0
T138	13761	0	0	0
T139	14482	0	0	0
T140	6934	0	0	0
T141	85726	0	0	0
T142	30799	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	100602445	0	0
T1	142926	117951	0	0
T2	58932	620	0	0
T3	12687	151	0	0
T4	17374	6559	0	0
T5	291101	534349	0	0
T8	11496	4377	0	0
T9	13135	4819	0	0
T10	14777	181	0	0
T11	14354	940	0	0
T12	67539	464	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	100602445	0	0
T1	142926	117951	0	0
T2	58932	620	0	0
T3	12687	151	0	0
T4	17374	6559	0	0
T5	291101	534349	0	0
T8	11496	4377	0	0
T9	13135	4819	0	0
T10	14777	181	0	0
T11	14354	940	0	0
T12	67539	464	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	169358987	0	0
T1	142926	125133	0	0
T2	58932	1820	0	0
T3	12687	0	0	0
T4	17374	3381	0	0
T5	291101	172783	0	0
T6	0	202084	0	0
T7	0	133724	0	0
T8	11496	0	0	0
T9	13135	0	0	0
T10	14777	0	0	0
T11	14354	0	0	0
T12	67539	7841	0	0
T15	0	8023	0	0
T45	0	559	0	0
T89	0	2836	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	7632	0	0
T1	142926	20	0	0
T2	58932	0	0	0
T3	12687	0	0	0
T4	17374	8	0	0
T5	291101	7	0	0
T6	0	32	0	0
T7	0	51	0	0
T8	11496	0	0	0
T9	13135	0	0	0
T10	14777	0	0	0
T11	14354	0	0	0
T12	67539	0	0	0
T13	0	15	0	0
T14	0	39	0	0
T27	0	1	0	0
T89	0	2	0	0
T96	0	2	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	2349074	0	0
T2	58932	5695	0	0
T3	12687	0	0	0
T4	17374	0	0	0
T5	291101	0	0	0
T8	11496	0	0	0
T9	13135	0	0	0
T10	14777	0	0	0
T11	14354	0	0	0
T12	67539	0	0	0
T14	0	92098	0	0
T27	0	3463	0	0
T35	0	1627	0	0
T70	13652	0	0	0
T75	0	4672	0	0
T90	0	14560	0	0
T91	0	5164	0	0
T92	0	6879	0	0
T93	0	6772	0	0
T105	0	7465	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	25001602	0	0
T2	58932	43631	0	0
T3	12687	0	0	0
T4	17374	7118	0	0
T5	291101	0	0	0
T8	11496	0	0	0
T9	13135	2848	0	0
T10	14777	0	0	0
T11	14354	0	0	0
T12	67539	55420	0	0
T15	0	3920	0	0
T27	0	49115	0	0
T45	0	2488	0	0
T70	13652	3392	0	0
T88	0	2576	0	0
T89	0	8326	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T88,T104

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T8,T9
1	Covered	T45,T27,T75

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T4,T8
1	Covered	T20,T21,T22

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T126,T129
1	Covered	T126,T129

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T4,T8
1	Covered	T1,T4,T8

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T8,T9

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T3,T8,T9

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T3,T8,T9
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T3,T8,T9
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T12

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T12

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T4,T8
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T3,T8
ReadWaitSt	252	Covered	T3,T8,T9
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T4,T8
IdleSt->ReadSt	236	Covered	T2,T3,T8
InitSt->ErrorSt	315	Covered	T169,T175,T172
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T98,T130,T131
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T2,T5,T12
ReadSt->ReadWaitSt	252	Covered	T3,T8,T9
ReadWaitSt->ErrorSt	276	Covered	T132,T177,T178
ReadWaitSt->IdleSt	270	Covered	T3,T8,T9
ResetSt->ErrorSt	315	Covered	T77,T78,T79
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T2,T5,T12
CheckFailError	317	Covered	T126,T129
FsmStateError	289	Covered	T1,T4,T8
MacroEccCorrError	221	Covered	T8,T45,T88
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T5,T7,T13
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T2,T5,T12
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T126,T129
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T4,T8
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T8,T88,T104
MacroEccCorrError->NoError	235	Covered	T45,T27,T75
NoError->AccessError	256	Covered	T2,T5,T12
NoError->CheckFailError	317	Covered	T126,T129
NoError->FsmStateError	289	Covered	T1,T4,T9
NoError->MacroEccCorrError	221	Covered	T8,T45,T88

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T8,T9

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T8,T9

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T8,T88,T104
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T98,T130,T131
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T8
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T3,T8,T9
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T89,T14,T76
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T5,T12
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T45,T27,T75
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T3,T8,T9
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T132,T177,T178
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T3,T8,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T21,T22
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T4,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T4,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T4,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T4,T8
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T126,T129
1	0	Covered	T126,T129
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T4,T8
1	0	Covered	T1,T4,T8
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	426621337	425752618	0	0
DigestKnown_A	426621337	425752618	0	0
DigestOffsetMustBeRepresentable_A	1148	1148	0	0
EccErrorState_A	426621337	5529	0	0
ErrorKnown_A	426621337	425752618	0	0
FsmStateKnown_A	426621337	425752618	0	0
InitDoneKnown_A	426621337	425752618	0	0
InitReadLocksPartition_A	426621337	100783914	0	0
InitWriteLocksPartition_A	426621337	100783914	0	0
OffsetMustBeBlockAligned_A	1148	1148	0	0
OtpAddrKnown_A	426621337	425752618	0	0
OtpCmdKnown_A	426621337	425752618	0	0
OtpErrorState_A	426621337	66	0	0
OtpReqKnown_A	426621337	425752618	0	0
OtpSizeKnown_A	426621337	425752618	0	0
OtpWdataKnown_A	426621337	425752618	0	0
ReadLockPropagation_A	426621337	173525453	0	0
SizeMustBeBlockAligned_A	1148	1148	0	0
TlulGntKnown_A	426621337	425752618	0	0
TlulRdataKnown_A	426621337	425752618	0	0
TlulReadOnReadLock_A	426621337	7908	0	0
TlulRerrorKnown_A	426621337	425752618	0	0
TlulRvalidKnown_A	426621337	425752618	0	0
WriteLockPropagation_A	426621337	2148717	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	426621337	25033086	0	0
u_state_regs_A	426621337	425752618	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	5529	0	0
T38	44940	0	0	0
T126	10422	3318	0	0
T129	0	2211	0	0
T135	16027	0	0	0
T136	11945	0	0	0
T137	23447	0	0	0
T138	13761	0	0	0
T139	14482	0	0	0
T140	6934	0	0	0
T141	85726	0	0	0
T142	30799	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	100783914	0	0
T1	142926	118019	0	0
T2	58932	824	0	0
T3	12687	202	0	0
T4	17374	6627	0	0
T5	291101	534536	0	0
T8	11496	4411	0	0
T9	13135	4870	0	0
T10	14777	232	0	0
T11	14354	991	0	0
T12	67539	617	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	100783914	0	0
T1	142926	118019	0	0
T2	58932	824	0	0
T3	12687	202	0	0
T4	17374	6627	0	0
T5	291101	534536	0	0
T8	11496	4411	0	0
T9	13135	4870	0	0
T10	14777	232	0	0
T11	14354	991	0	0
T12	67539	617	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	66	0	0
T14	121696	0	0	0
T26	774515	0	0	0
T35	60322	0	0	0
T49	12090	0	0	0
T90	378796	0	0	0
T91	66442	0	0	0
T92	63848	0	0	0
T98	11050	1	0	0
T101	13692	0	0	0
T102	12120	0	0	0
T130	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0
T156	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0
T165	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	173525453	0	0
T1	142926	125129	0	0
T2	58932	3175	0	0
T3	12687	0	0	0
T4	17374	517	0	0
T5	291101	775304	0	0
T6	0	43166	0	0
T7	0	133428	0	0
T8	11496	0	0	0
T9	13135	0	0	0
T10	14777	0	0	0
T11	14354	0	0	0
T12	67539	21059	0	0
T15	0	6328	0	0
T45	0	789	0	0
T89	0	2785	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	7908	0	0
T1	142926	22	0	0
T2	58932	1	0	0
T3	12687	0	0	0
T4	17374	8	0	0
T5	291101	11	0	0
T6	0	32	0	0
T7	0	55	0	0
T8	11496	0	0	0
T9	13135	0	0	0
T10	14777	0	0	0
T11	14354	0	0	0
T12	67539	5	0	0
T15	0	1	0	0
T27	0	2	0	0
T89	0	2	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	2148717	0	0
T2	58932	2076	0	0
T3	12687	0	0	0
T4	17374	0	0	0
T5	291101	0	0	0
T8	11496	0	0	0
T9	13135	0	0	0
T10	14777	0	0	0
T11	14354	0	0	0
T12	67539	6384	0	0
T14	0	125190	0	0
T70	13652	0	0	0
T75	0	10291	0	0
T76	0	59507	0	0
T90	0	3500	0	0
T91	0	9593	0	0
T92	0	6879	0	0
T93	0	6822	0	0
T105	0	6951	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	25033086	0	0
T2	58932	15067	0	0
T3	12687	0	0	0
T4	17374	7084	0	0
T5	291101	0	0	0
T8	11496	0	0	0
T9	13135	0	0	0
T10	14777	0	0	0
T11	14354	0	0	0
T12	67539	55284	0	0
T15	0	3886	0	0
T27	0	48911	0	0
T35	0	46253	0	0
T45	0	11364	0	0
T70	13652	0	0	0
T89	0	8258	0	0
T96	0	2691	0	0
T98	0	3864	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T71,T108,T80

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T8
1	Covered	T45,T27,T75

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T4,T8
1	Covered	T20,T21,T22

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T127,T129,T128
1	Covered	T127,T129,T128

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T4,T8
1	Covered	T1,T4,T8

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T3,T8

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00111101000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T8
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T8
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T45,T88

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T45,T88

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T4,T8
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T2,T3,T8
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T4,T8
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T169,T179,T175
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T88,T98,T102
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T2,T4
ReadSt->ReadWaitSt	252	Covered	T2,T3,T8
ReadWaitSt->ErrorSt	276	Covered	T180,T181,T182
ReadWaitSt->IdleSt	270	Covered	T2,T3,T8
ResetSt->ErrorSt	315	Covered	T77,T78,T79
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T2,T4
CheckFailError	317	Covered	T127,T129,T128
FsmStateError	289	Covered	T1,T4,T8
MacroEccCorrError	221	Covered	T45,T71,T27
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T1,T7,T14
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T2,T4,T5
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T127,T129,T128
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T4,T8
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T71,T108,T80
MacroEccCorrError->NoError	235	Covered	T45,T27,T75
NoError->AccessError	256	Covered	T1,T2,T4
NoError->CheckFailError	317	Covered	T127,T129,T128
NoError->FsmStateError	289	Covered	T4,T8,T9
NoError->MacroEccCorrError	221	Covered	T45,T71,T27

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T8

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T8

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T45,T88
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T71,T108,T80
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T88,T102,T104
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T8
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T5,T89,T14
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T45,T27,T75
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T8
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T180,T181,T182
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T21,T22
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T4,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T4,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T4,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T4,T8
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T127,T129,T128
1	0	Covered	T127,T129,T128
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T4,T8
1	0	Covered	T1,T4,T8
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	426621337	425752618	0	0
DigestKnown_A	426621337	425752618	0	0
DigestOffsetMustBeRepresentable_A	1148	1148	0	0
EccErrorState_A	426621337	9186	0	0
ErrorKnown_A	426621337	425752618	0	0
FsmStateKnown_A	426621337	425752618	0	0
InitDoneKnown_A	426621337	425752618	0	0
InitReadLocksPartition_A	426621337	100964148	0	0
InitWriteLocksPartition_A	426621337	100964148	0	0
OffsetMustBeBlockAligned_A	1148	1148	0	0
OtpAddrKnown_A	426621337	425752618	0	0
OtpCmdKnown_A	426621337	425752618	0	0
OtpErrorState_A	426621337	61	0	0
OtpReqKnown_A	426621337	425752618	0	0
OtpSizeKnown_A	426621337	425752618	0	0
OtpWdataKnown_A	426621337	425752618	0	0
ReadLockPropagation_A	426621337	166779195	0	0
SizeMustBeBlockAligned_A	1148	1148	0	0
TlulGntKnown_A	426621337	425752618	0	0
TlulRdataKnown_A	426621337	425752618	0	0
TlulReadOnReadLock_A	426621337	8327	0	0
TlulRerrorKnown_A	426621337	425752618	0	0
TlulRvalidKnown_A	426621337	425752618	0	0
WriteLockPropagation_A	426621337	1843839	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	426621337	17654051	0	0
u_state_regs_A	426621337	425752618	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	9186	0	0
T127	10775	3626	0	0
T128	0	3349	0	0
T129	0	2211	0	0
T143	679305	0	0	0
T144	19461	0	0	0
T145	11390	0	0	0
T146	34424	0	0	0
T147	7106	0	0	0
T148	78811	0	0	0
T149	942142	0	0	0
T150	20812	0	0	0
T151	968860	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	100964148	0	0
T1	142926	118087	0	0
T2	58932	1028	0	0
T3	12687	253	0	0
T4	17374	6695	0	0
T5	291101	534723	0	0
T8	11496	4445	0	0
T9	13135	4921	0	0
T10	14777	283	0	0
T11	14354	1042	0	0
T12	67539	770	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	100964148	0	0
T1	142926	118087	0	0
T2	58932	1028	0	0
T3	12687	253	0	0
T4	17374	6695	0	0
T5	291101	534723	0	0
T8	11496	4445	0	0
T9	13135	4921	0	0
T10	14777	283	0	0
T11	14354	1042	0	0
T12	67539	770	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	61	0	0
T7	201547	0	0	0
T15	17375	0	0	0
T27	56858	0	0	0
T31	13693	0	0	0
T42	15594	0	0	0
T77	12994	0	0	0
T88	10857	1	0	0
T89	24762	0	0	0
T95	8637	0	0	0
T96	23628	0	0	0
T102	0	1	0	0
T104	0	1	0	0
T152	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T157	0	1	0	0
T160	0	1	0	0
T163	0	1	0	0
T164	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	166779195	0	0
T1	142926	123106	0	0
T2	58932	2591	0	0
T3	12687	0	0	0
T4	17374	3379	0	0
T5	291101	735799	0	0
T6	0	202078	0	0
T7	0	133719	0	0
T8	11496	0	0	0
T9	13135	0	0	0
T10	14777	0	0	0
T11	14354	0	0	0
T12	67539	17559	0	0
T15	0	10055	0	0
T45	0	1306	0	0
T89	0	2788	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	8327	0	0
T1	142926	18	0	0
T2	58932	2	0	0
T3	12687	0	0	0
T4	17374	13	0	0
T5	291101	11	0	0
T6	0	30	0	0
T8	11496	0	0	0
T9	13135	0	0	0
T10	14777	0	0	0
T11	14354	1	0	0
T12	67539	2	0	0
T15	0	2	0	0
T45	0	3	0	0
T89	0	3	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	1843839	0	0
T14	121696	5216	0	0
T26	774515	0	0	0
T46	0	1700	0	0
T52	12631	0	0	0
T76	0	2705	0	0
T90	378796	0	0	0
T91	66442	2882	0	0
T92	63848	0	0	0
T93	0	11296	0	0
T102	12120	0	0	0
T103	20079	0	0	0
T104	13543	0	0	0
T105	40293	0	0	0
T167	0	3769	0	0
T168	0	10905	0	0
T169	0	8486	0	0
T170	0	13829	0	0
T171	0	18949	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	17654051	0	0
T4	17374	7050	0	0
T5	291101	0	0	0
T6	319264	0	0	0
T8	11496	0	0	0
T9	13135	0	0	0
T10	14777	0	0	0
T11	14354	0	0	0
T12	67539	0	0	0
T14	0	561967	0	0
T15	0	3852	0	0
T35	0	46083	0	0
T45	92004	8859	0	0
T70	13652	0	0	0
T88	0	2554	0	0
T90	0	3698	0	0
T91	0	54496	0	0
T92	0	43233	0	0
T96	0	2674	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0