Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.82	97.40	96.15	96.92		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.82	97.40	96.15	96.92		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T71,T80

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T75,T46,T36

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T4,T8
1	Covered	T20,T21,T22

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T79,T126,T127
1	Covered	T79,T126,T127

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T4,T8
1	Covered	T1,T4,T8

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T2,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T12,T45

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T12,T45

---

FSM Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T4,T8
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T2,T3,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T4,T8
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T98,T130,T131
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T88,T102,T104
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T4,T5
ReadSt->ReadWaitSt	252	Covered	T2,T3,T4
ReadWaitSt->ErrorSt	276	Covered	T133,T134,T183
ReadWaitSt->IdleSt	270	Covered	T2,T3,T4
ResetSt->ErrorSt	315	Covered	T77,T78,T79
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T4,T5
CheckFailError	317	Covered	T79,T126,T127
FsmStateError	289	Covered	T1,T4,T8
MacroEccCorrError	221	Covered	T9,T71,T75
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T1,T7,T14
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T4,T5,T12
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T79,T126,T127
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T4,T8
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T9,T71,T80
MacroEccCorrError->NoError	235	Covered	T75,T46,T36
NoError->AccessError	256	Covered	T1,T4,T5
NoError->CheckFailError	317	Covered	T79,T126,T127
NoError->FsmStateError	289	Covered	T4,T8,T5
NoError->MacroEccCorrError	221	Covered	T9,T71,T75

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T12,T45
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T9,T71,T80
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T153,T184,T185
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T89,T14,T76
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T4,T5
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T75,T46,T36
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T133,T134,T183
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T21,T22
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T4,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T4,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T4,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T4,T8
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T79,T126,T127
1	0	Covered	T79,T126,T127
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T4,T8
1	0	Covered	T1,T4,T8
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	426621337	425752618	0	0
DigestKnown_A	426621337	425752618	0	0
DigestOffsetMustBeRepresentable_A	1148	1148	0	0
EccErrorState_A	426621337	12733	0	0
ErrorKnown_A	426621337	425752618	0	0
FsmStateKnown_A	426621337	425752618	0	0
InitDoneKnown_A	426621337	425752618	0	0
InitReadLocksPartition_A	426621337	101143345	0	0
InitWriteLocksPartition_A	426621337	101143345	0	0
OffsetMustBeBlockAligned_A	1148	1148	0	0
OtpAddrKnown_A	426621337	425752618	0	0
OtpCmdKnown_A	426621337	425752618	0	0
OtpErrorState_A	426621337	47	0	0
OtpReqKnown_A	426621337	425752618	0	0
OtpSizeKnown_A	426621337	425752618	0	0
OtpWdataKnown_A	426621337	425752618	0	0
ReadLockPropagation_A	426621337	170524547	0	0
SizeMustBeBlockAligned_A	1148	1148	0	0
TlulGntKnown_A	426621337	425752618	0	0
TlulRdataKnown_A	426621337	425752618	0	0
TlulReadOnReadLock_A	426621337	8064	0	0
TlulRerrorKnown_A	426621337	425752618	0	0
TlulRvalidKnown_A	426621337	425752618	0	0
WriteLockPropagation_A	426621337	2413451	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	426621337	25180813	0	0
u_state_regs_A	426621337	425752618	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	12733	0	0
T23	9756	0	0	0
T79	8918	2440	0	0
T114	9535	0	0	0
T126	0	3318	0	0
T127	0	3626	0	0
T128	0	3349	0	0
T183	48781	0	0	0
T185	13679	0	0	0
T186	80572	0	0	0
T187	88741	0	0	0
T188	399844	0	0	0
T189	5983	0	0	0
T190	18875	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	101143345	0	0
T1	142926	118155	0	0
T2	58932	1232	0	0
T3	12687	304	0	0
T4	17374	6763	0	0
T5	291101	534910	0	0
T8	11496	4479	0	0
T9	13135	4972	0	0
T10	14777	334	0	0
T11	14354	1093	0	0
T12	67539	923	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	101143345	0	0
T1	142926	118155	0	0
T2	58932	1232	0	0
T3	12687	304	0	0
T4	17374	6763	0	0
T5	291101	534910	0	0
T8	11496	4479	0	0
T9	13135	4972	0	0
T10	14777	334	0	0
T11	14354	1093	0	0
T12	67539	923	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	47	0	0
T36	85405	0	0	0
T100	266583	0	0	0
T108	9351	0	0	0
T130	13406	0	0	0
T133	0	1	0	0
T134	0	1	0	0
T153	12413	1	0	0
T154	15716	0	0	0
T183	0	1	0	0
T184	0	1	0	0
T185	0	1	0	0
T191	0	1	0	0
T192	0	1	0	0
T193	0	1	0	0
T194	0	1	0	0
T195	3473	0	0	0
T196	102490	0	0	0
T197	42126	0	0	0
T198	8379	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	170524547	0	0
T1	142926	125117	0	0
T2	58932	3141	0	0
T3	12687	0	0	0
T4	17374	2532	0	0
T5	291101	341583	0	0
T6	0	43162	0	0
T7	0	133162	0	0
T8	11496	0	0	0
T9	13135	0	0	0
T10	14777	0	0	0
T11	14354	0	0	0
T12	67539	23908	0	0
T15	0	8008	0	0
T45	0	781	0	0
T89	0	2640	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	8064	0	0
T1	142926	22	0	0
T2	58932	0	0	0
T3	12687	0	0	0
T4	17374	7	0	0
T5	291101	4	0	0
T6	0	29	0	0
T7	0	58	0	0
T8	11496	0	0	0
T9	13135	0	0	0
T10	14777	0	0	0
T11	14354	0	0	0
T12	67539	6	0	0
T15	0	2	0	0
T27	0	2	0	0
T89	0	1	0	0
T96	0	3	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	2413451	0	0
T14	121696	90221	0	0
T26	774515	0	0	0
T35	60322	2141	0	0
T76	0	31851	0	0
T90	378796	14709	0	0
T91	66442	3480	0	0
T92	63848	6879	0	0
T93	0	3624	0	0
T99	0	2618	0	0
T100	0	2392	0	0
T101	13692	0	0	0
T102	12120	0	0	0
T103	20079	0	0	0
T104	13543	0	0	0
T166	0	13789	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	25180813	0	0
T4	17374	7016	0	0
T5	291101	0	0	0
T6	319264	0	0	0
T8	11496	0	0	0
T9	13135	0	0	0
T10	14777	0	0	0
T11	14354	0	0	0
T12	67539	55012	0	0
T14	0	619231	0	0
T15	0	3818	0	0
T35	0	45913	0	0
T45	92004	8825	0	0
T70	13652	0	0	0
T89	0	14408	0	0
T90	0	145256	0	0
T91	0	54309	0	0
T96	0	2657	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T52,T108

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T8
1	Covered	T27,T75,T46

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T4,T8
1	Covered	T20,T21,T22

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T77,T78,T126
1	Covered	T77,T78,T126

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T4,T8
1	Covered	T1,T4,T8

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T2,T3,T8

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T8
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T8
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T12,T45

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T12,T45

---

FSM Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T4,T8
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T2,T3,T8
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T4,T8
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T88,T98,T102
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T153,T184,T199
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T4,T5
ReadSt->ReadWaitSt	252	Covered	T2,T3,T8
ReadWaitSt->ErrorSt	276	Covered	T180,T200,T201
ReadWaitSt->IdleSt	270	Covered	T2,T3,T8
ResetSt->ErrorSt	315	Covered	T77,T78,T79
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T4,T5
CheckFailError	317	Covered	T77,T78,T126
FsmStateError	289	Covered	T1,T4,T8
MacroEccCorrError	221	Covered	T8,T27,T52
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T1,T6,T7
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T4,T5,T12
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T77,T78,T126
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T4,T8
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T8,T52,T108
MacroEccCorrError->NoError	235	Covered	T27,T75,T46
NoError->AccessError	256	Covered	T1,T4,T5
NoError->CheckFailError	317	Covered	T77,T78,T126
NoError->FsmStateError	289	Covered	T4,T9,T5
NoError->MacroEccCorrError	221	Covered	T8,T27,T52

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T8

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T8

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T12,T45
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T8,T52,T108
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T199,T202,T203
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T8
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T89,T14,T76
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T4,T5
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T27,T75,T46
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T8
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T180,T200,T201
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T21,T22
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T4,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T4,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T4,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T4,T8
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T77,T78,T126
1	0	Covered	T77,T78,T126
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T4,T8
1	0	Covered	T1,T4,T8
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	426621337	425752618	0	0
DigestKnown_A	426621337	425752618	0	0
DigestOffsetMustBeRepresentable_A	1148	1148	0	0
EccErrorState_A	426621337	16576	0	0
ErrorKnown_A	426621337	425752618	0	0
FsmStateKnown_A	426621337	425752618	0	0
InitDoneKnown_A	426621337	425752618	0	0
InitReadLocksPartition_A	426621337	101321755	0	0
InitWriteLocksPartition_A	426621337	101321755	0	0
OffsetMustBeBlockAligned_A	1148	1148	0	0
OtpAddrKnown_A	426621337	425752618	0	0
OtpCmdKnown_A	426621337	425752618	0	0
OtpErrorState_A	426621337	36	0	0
OtpReqKnown_A	426621337	425752618	0	0
OtpSizeKnown_A	426621337	425752618	0	0
OtpWdataKnown_A	426621337	425752618	0	0
ReadLockPropagation_A	426621337	168867619	0	0
SizeMustBeBlockAligned_A	1148	1148	0	0
TlulGntKnown_A	426621337	425752618	0	0
TlulRdataKnown_A	426621337	425752618	0	0
TlulReadOnReadLock_A	426621337	7726	0	0
TlulRerrorKnown_A	426621337	425752618	0	0
TlulRvalidKnown_A	426621337	425752618	0	0
WriteLockPropagation_A	426621337	1049878	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	426621337	9179185	0	0
u_state_regs_A	426621337	425752618	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	16576	0	0
T13	80472	0	0	0
T16	999100	0	0	0
T27	56858	0	0	0
T31	13693	0	0	0
T42	15594	0	0	0
T77	12994	2832	0	0
T78	0	3451	0	0
T95	8637	0	0	0
T96	23628	0	0	0
T97	15395	0	0	0
T98	11050	0	0	0
T126	0	3318	0	0
T127	0	3626	0	0
T128	0	3349	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	101321755	0	0
T1	142926	118223	0	0
T2	58932	1436	0	0
T3	12687	355	0	0
T4	17374	6831	0	0
T5	291101	535097	0	0
T8	11496	4513	0	0
T9	13135	5023	0	0
T10	14777	385	0	0
T11	14354	1144	0	0
T12	67539	1076	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	101321755	0	0
T1	142926	118223	0	0
T2	58932	1436	0	0
T3	12687	355	0	0
T4	17374	6831	0	0
T5	291101	535097	0	0
T8	11496	4513	0	0
T9	13135	5023	0	0
T10	14777	385	0	0
T11	14354	1144	0	0
T12	67539	1076	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	36	0	0
T32	19092	0	0	0
T68	19829	0	0	0
T78	13162	0	0	0
T163	10994	0	0	0
T164	19460	0	0	0
T180	0	1	0	0
T199	14234	1	0	0
T200	0	1	0	0
T201	0	1	0	0
T202	16017	1	0	0
T203	0	1	0	0
T204	0	1	0	0
T205	0	1	0	0
T206	0	1	0	0
T207	0	1	0	0
T208	15764	0	0	0
T209	43993	0	0	0
T210	32083	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	168867619	0	0
T1	142926	123089	0	0
T2	58932	2558	0	0
T3	12687	0	0	0
T4	17374	3377	0	0
T5	291101	278973	0	0
T6	0	201965	0	0
T7	0	132405	0	0
T8	11496	0	0	0
T9	13135	0	0	0
T10	14777	0	0	0
T11	14354	0	0	0
T12	67539	17904	0	0
T15	0	10041	0	0
T45	0	686	0	0
T89	0	2832	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	7726	0	0
T1	142926	11	0	0
T2	58932	0	0	0
T3	12687	0	0	0
T4	17374	11	0	0
T5	291101	13	0	0
T6	0	33	0	0
T7	0	51	0	0
T8	11496	0	0	0
T9	13135	0	0	0
T10	14777	0	0	0
T11	14354	0	0	0
T12	67539	6	0	0
T15	0	1	0	0
T27	0	4	0	0
T45	0	1	0	0
T89	0	2	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	1049878	0	0
T2	58932	1624	0	0
T3	12687	0	0	0
T4	17374	0	0	0
T5	291101	0	0	0
T8	11496	0	0	0
T9	13135	0	0	0
T10	14777	0	0	0
T11	14354	0	0	0
T12	67539	0	0	0
T70	13652	0	0	0
T76	0	1636	0	0
T90	0	1312	0	0
T94	0	3437	0	0
T99	0	3026	0	0
T100	0	9448	0	0
T105	0	7465	0	0
T211	0	10956	0	0
T212	0	1125	0	0
T213	0	10337	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	9179185	0	0
T2	58932	49431	0	0
T3	12687	0	0	0
T4	17374	0	0	0
T5	291101	0	0	0
T8	11496	0	0	0
T9	13135	0	0	0
T10	14777	0	0	0
T11	14354	0	0	0
T12	67539	54876	0	0
T14	0	104737	0	0
T27	0	48299	0	0
T45	0	2420	0	0
T70	13652	0	0	0
T75	0	56000	0	0
T89	0	14323	0	0
T90	0	51324	0	0
T103	0	2589	0	0
T105	0	26202	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426621337	425752618	0	0
T1	142926	142662	0	0
T2	58932	57784	0	0
T3	12687	12489	0	0
T4	17374	16981	0	0
T5	291101	291083	0	0
T8	11496	11265	0	0
T9	13135	12867	0	0
T10	14777	14504	0	0
T11	14354	14084	0	0
T12	67539	66869	0	0