Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7393871	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7514691

1

T1

256

T2

4505

T3

200

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8534237	1			T1	540		T2	8614		T3	537
values[0x0]	2421504	1			T1	155		T2	425		T3	38
values[0x1]	3952821	1			T1	166		T2	413		T3	40

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4777742	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

10130820

1

T1

393

T2

5504

T3

292

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	65389	1			T1	5		T2	40		T11	6
valid_sources[0x01]	58511	1			T1	5		T2	57		T11	4
valid_sources[0x02]	50282	1			T1	8		T2	28		T11	3
valid_sources[0x03]	66286	1			T1	5		T2	35		T11	1
valid_sources[0x04]	61266	1			T1	1		T2	32		T11	2
valid_sources[0x05]	51555	1			T1	4		T2	37		T11	1
valid_sources[0x06]	53022	1			T1	5		T2	35		T11	1
valid_sources[0x07]	58610	1			T1	3		T2	39		T11	3
valid_sources[0x08]	50172	1			T1	4		T2	31		T11	3
valid_sources[0x09]	53765	1			T1	2		T2	30		T11	3
valid_sources[0x0a]	56498	1			T2	46		T11	2		T12	5
valid_sources[0x0b]	49925	1			T1	3		T2	41		T11	2
valid_sources[0x0c]	69749	1			T1	3		T2	37		T11	6
valid_sources[0x0d]	66641	1			T1	5		T2	35		T11	2
valid_sources[0x0e]	50837	1			T1	1		T2	50		T11	4
valid_sources[0x0f]	72910	1			T1	3		T2	45		T11	3
valid_sources[0x10]	61041	1			T1	4		T2	32		T11	1
valid_sources[0x11]	56981	1			T1	3		T2	39		T11	1
valid_sources[0x12]	53946	1			T1	2		T2	42		T11	1
valid_sources[0x13]	54017	1			T1	1		T2	20		T11	5
valid_sources[0x14]	50503	1			T1	2		T2	37		T11	4
valid_sources[0x15]	58815	1			T1	3		T2	29		T11	2
valid_sources[0x16]	50453	1			T1	6		T2	33		T11	3
valid_sources[0x17]	53367	1			T1	2		T2	40		T11	3
valid_sources[0x18]	57816	1			T1	2		T2	46		T11	1
valid_sources[0x19]	53598	1			T1	3		T2	34		T12	3
valid_sources[0x1a]	56237	1			T1	5		T2	42		T11	3
valid_sources[0x1b]	53050	1			T1	5		T2	43		T11	1
valid_sources[0x1c]	65692	1			T1	4		T2	32		T11	3
valid_sources[0x1d]	109670	1			T1	1		T2	30		T11	1
valid_sources[0x1e]	59718	1			T1	3		T2	40		T12	1
valid_sources[0x1f]	52357	1			T1	7		T2	31		T11	1
valid_sources[0x20]	114305	1			T1	8		T2	29		T11	2
valid_sources[0x21]	51143	1			T1	7		T2	36		T11	2
valid_sources[0x22]	57333	1			T1	3		T2	41		T11	1
valid_sources[0x23]	51783	1			T1	4		T2	29		T11	2
valid_sources[0x24]	48122	1			T1	3		T2	34		T11	3
valid_sources[0x25]	52424	1			T1	4		T2	37		T12	2
valid_sources[0x26]	47621	1			T1	4		T2	40		T11	3
valid_sources[0x27]	160233	1			T1	7		T2	39		T11	1
valid_sources[0x28]	50669	1			T1	4		T2	44		T11	2
valid_sources[0x29]	62208	1			T1	5		T2	36		T11	4
valid_sources[0x2a]	53806	1			T1	7		T2	35		T11	1
valid_sources[0x2b]	49624	1			T2	33		T11	2		T12	6
valid_sources[0x2c]	51849	1			T1	1		T2	39		T11	3
valid_sources[0x2d]	66658	1			T1	3		T2	31		T11	3
valid_sources[0x2e]	61516	1			T1	2		T2	43		T11	3
valid_sources[0x2f]	52373	1			T1	3		T2	38		T11	2
valid_sources[0x30]	55533	1			T1	2		T2	31		T11	2
valid_sources[0x31]	50933	1			T1	3		T2	43		T11	2
valid_sources[0x32]	49694	1			T1	4		T2	27		T11	1
valid_sources[0x33]	54786	1			T1	5		T2	44		T11	1
valid_sources[0x34]	54456	1			T1	5		T2	36		T11	1
valid_sources[0x35]	49701	1			T1	2		T2	33		T11	1
valid_sources[0x36]	51827	1			T1	2		T2	42		T11	1
valid_sources[0x37]	61414	1			T1	6		T2	37		T11	2
valid_sources[0x38]	55367	1			T1	2		T2	28		T12	3
valid_sources[0x39]	56115	1			T1	1		T2	27		T11	2
valid_sources[0x3a]	50855	1			T1	1		T2	26		T11	4
valid_sources[0x3b]	49832	1			T1	1		T2	38		T11	3
valid_sources[0x3c]	53100	1			T1	4		T2	46		T11	1
valid_sources[0x3d]	54856	1			T1	2		T2	36		T11	2
valid_sources[0x3e]	51170	1			T1	4		T2	34		T11	2
valid_sources[0x3f]	88605	1			T1	5		T2	39		T12	19
valid_sources[0x40]	51183	1			T1	7		T2	40		T11	3
valid_sources[0x41]	60828	1			T1	2		T2	34		T11	1
valid_sources[0x42]	51468	1			T1	4		T2	47		T11	4
valid_sources[0x43]	54470	1			T1	2		T2	27		T11	1
valid_sources[0x44]	53590	1			T1	1		T2	37		T11	3
valid_sources[0x45]	50174	1			T1	1		T2	44		T11	4
valid_sources[0x46]	49219	1			T1	1		T2	44		T11	2
valid_sources[0x47]	54034	1			T1	1		T2	37		T11	4
valid_sources[0x48]	59923	1			T1	2		T2	32		T11	1
valid_sources[0x49]	53711	1			T1	4		T2	32		T11	2
valid_sources[0x4a]	94044	1			T1	1		T2	36		T11	4
valid_sources[0x4b]	61458	1			T1	5		T2	47		T11	2
valid_sources[0x4c]	50013	1			T1	2		T2	35		T12	2
valid_sources[0x4d]	51051	1			T1	3		T2	27		T11	2
valid_sources[0x4e]	56883	1			T1	1		T2	40		T12	4
valid_sources[0x4f]	52052	1			T1	5		T2	38		T11	3
valid_sources[0x50]	57728	1			T1	3		T2	37		T11	3
valid_sources[0x51]	49739	1			T1	4		T2	32		T12	4
valid_sources[0x52]	52945	1			T1	3		T2	38		T12	3
valid_sources[0x53]	55250	1			T1	5		T2	43		T11	4
valid_sources[0x54]	49685	1			T1	3		T2	38		T11	2
valid_sources[0x55]	57983	1			T1	4		T2	30		T11	4
valid_sources[0x56]	97476	1			T1	2		T2	43		T11	1
valid_sources[0x57]	54322	1			T1	2		T2	25		T12	7
valid_sources[0x58]	54757	1			T1	3		T2	46		T11	5
valid_sources[0x59]	50168	1			T1	5		T2	33		T12	7
valid_sources[0x5a]	54735	1			T1	5		T2	48		T11	4
valid_sources[0x5b]	52322	1			T1	4		T2	36		T11	2
valid_sources[0x5c]	49406	1			T1	8		T2	38		T11	4
valid_sources[0x5d]	51723	1			T1	2		T2	17		T11	2
valid_sources[0x5e]	54146	1			T1	4		T2	36		T11	3
valid_sources[0x5f]	54166	1			T1	1		T2	30		T12	3
valid_sources[0x60]	51958	1			T1	3		T2	45		T11	3
valid_sources[0x61]	49893	1			T1	6		T2	43		T12	2
valid_sources[0x62]	51222	1			T1	2		T2	42		T11	4
valid_sources[0x63]	49692	1			T1	4		T2	33		T12	14
valid_sources[0x64]	62832	1			T2	36		T11	2		T12	1
valid_sources[0x65]	51910	1			T1	1		T2	48		T11	1
valid_sources[0x66]	79294	1			T1	1		T2	43		T11	4
valid_sources[0x67]	48609	1			T2	32		T11	3		T12	9
valid_sources[0x68]	48820	1			T1	2		T2	31		T11	4
valid_sources[0x69]	176465	1			T1	3		T2	44		T11	3
valid_sources[0x6a]	53890	1			T1	5		T2	39		T11	4
valid_sources[0x6b]	57580	1			T1	5		T2	39		T12	10
valid_sources[0x6c]	50657	1			T1	5		T2	40		T11	3
valid_sources[0x6d]	57534	1			T1	2		T2	31		T10	4
valid_sources[0x6e]	57055	1			T1	3		T2	41		T11	2
valid_sources[0x6f]	56543	1			T1	3		T2	43		T11	2
valid_sources[0x70]	64313	1			T1	4		T2	27		T11	2
valid_sources[0x71]	50482	1			T1	7		T2	34		T11	1
valid_sources[0x72]	48723	1			T1	3		T2	30		T11	2
valid_sources[0x73]	53749	1			T1	2		T2	34		T11	2
valid_sources[0x74]	53648	1			T1	2		T2	37		T11	1
valid_sources[0x75]	63603	1			T1	2		T2	50		T11	4
valid_sources[0x76]	86444	1			T1	2		T2	34		T11	3
valid_sources[0x77]	50758	1			T1	2		T2	36		T11	1
valid_sources[0x78]	52741	1			T1	3		T2	36		T11	4
valid_sources[0x79]	59524	1			T1	7		T2	37		T11	3
valid_sources[0x7a]	73911	1			T1	4		T2	49		T11	1
valid_sources[0x7b]	48673	1			T1	1		T2	33		T11	1
valid_sources[0x7c]	64580	1			T1	3		T2	40		T11	3
valid_sources[0x7d]	56500	1			T1	7		T2	38		T11	1
valid_sources[0x7e]	56145	1			T1	5		T2	41		T11	2
valid_sources[0x7f]	58720	1			T1	4		T2	32		T11	4
valid_sources[0x80]	51853	1			T1	6		T2	44		T11	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3576095

1

T1

128

T2

4180

T3

169

values[0x0]

all_enables

biggest_size

2010412

1

T1

70

T2

200

T3

17

values[0x1]

all_enables

biggest_size

1928184

1

T1

58

T2

125

T3

14

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	265236	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

9417708

1

T2

200

T3

20

T4

80

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2406975	1			T2	100		T3	10		T4	40
values[0x0]	3530036	1			T2	58		T3	5		T4	22
values[0x1]	3745933	1			T2	42		T3	5		T4	18

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	95169	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

9587775

1

T2

200

T3

20

T4

80

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	38013	1			T5	1		T8	1		T127	2
valid_sources[0x01]	38350	1			T5	2		T8	6		T55	1
valid_sources[0x02]	37248	1			T5	2		T32	1		T8	5
valid_sources[0x03]	40214	1			T6	1		T8	4		T127	1
valid_sources[0x04]	41324	1			T8	8		T130	2		T9	360
valid_sources[0x05]	37985	1			T6	1		T8	4		T130	1
valid_sources[0x06]	38056	1			T8	2		T101	1		T55	2
valid_sources[0x07]	33980	1			T8	3		T127	1		T211	1
valid_sources[0x08]	39427	1			T6	1		T32	1		T161	20
valid_sources[0x09]	40286	1			T4	1		T32	4		T16	3
valid_sources[0x0a]	37333	1			T4	1		T5	1		T70	1
valid_sources[0x0b]	38345	1			T3	5		T5	1		T8	5
valid_sources[0x0c]	36317	1			T8	2		T127	1		T55	1
valid_sources[0x0d]	38568	1			T5	1		T8	7		T127	2
valid_sources[0x0e]	36478	1			T2	1		T19	1		T8	5
valid_sources[0x0f]	40717	1			T5	1		T32	2		T19	1
valid_sources[0x10]	35819	1			T5	1		T32	2		T17	1
valid_sources[0x11]	41198	1			T5	1		T32	1		T16	7
valid_sources[0x12]	38755	1			T32	1		T17	2		T8	2
valid_sources[0x13]	39590	1			T5	1		T8	3		T127	1
valid_sources[0x14]	39456	1			T5	1		T32	1		T8	2
valid_sources[0x15]	38031	1			T4	1		T70	2		T19	1
valid_sources[0x16]	39188	1			T5	2		T19	1		T8	1
valid_sources[0x17]	37358	1			T8	4		T9	368		T235	1
valid_sources[0x18]	38281	1			T5	1		T32	1		T19	1
valid_sources[0x19]	41618	1			T4	2		T8	1		T127	1
valid_sources[0x1a]	34840	1			T4	1		T5	1		T19	1
valid_sources[0x1b]	36130	1			T8	3		T101	3		T55	1
valid_sources[0x1c]	37982	1			T4	2		T5	1		T8	4
valid_sources[0x1d]	36261	1			T19	1		T8	3		T55	3
valid_sources[0x1e]	35293	1			T5	5		T32	1		T16	1
valid_sources[0x1f]	39566	1			T32	3		T8	1		T101	11
valid_sources[0x20]	37567	1			T8	3		T127	1		T130	1
valid_sources[0x21]	38337	1			T32	2		T8	3		T9	358
valid_sources[0x22]	36222	1			T4	4		T5	1		T32	1
valid_sources[0x23]	34170	1			T8	3		T127	2		T101	1
valid_sources[0x24]	37298	1			T32	2		T8	6		T127	1
valid_sources[0x25]	36630	1			T8	2		T127	1		T101	3
valid_sources[0x26]	36111	1			T5	2		T6	2		T32	1
valid_sources[0x27]	38726	1			T3	2		T8	1		T55	1
valid_sources[0x28]	42102	1			T4	1		T6	1		T8	1
valid_sources[0x29]	36264	1			T4	1		T8	10		T9	312
valid_sources[0x2a]	38032	1			T4	1		T5	2		T32	4
valid_sources[0x2b]	36913	1			T70	3		T8	5		T127	2
valid_sources[0x2c]	36071	1			T5	4		T17	2		T19	1
valid_sources[0x2d]	38701	1			T2	9		T32	2		T70	2
valid_sources[0x2e]	41030	1			T3	3		T8	4		T127	1
valid_sources[0x2f]	36297	1			T32	2		T70	2		T19	1
valid_sources[0x30]	37115	1			T8	2		T9	356		T104	2
valid_sources[0x31]	38266	1			T6	1		T17	5		T8	4
valid_sources[0x32]	37515	1			T4	1		T5	1		T8	5
valid_sources[0x33]	37353	1			T4	1		T8	4		T127	2
valid_sources[0x34]	37267	1			T5	1		T17	3		T8	4
valid_sources[0x35]	39767	1			T4	1		T32	1		T8	4
valid_sources[0x36]	36502	1			T17	1		T19	2		T8	1
valid_sources[0x37]	38725	1			T32	2		T17	1		T19	1
valid_sources[0x38]	37784	1			T2	2		T4	2		T5	1
valid_sources[0x39]	35313	1			T4	1		T5	1		T8	4
valid_sources[0x3a]	38391	1			T5	1		T8	3		T127	1
valid_sources[0x3b]	35163	1			T5	2		T32	1		T8	3
valid_sources[0x3c]	38615	1			T2	12		T5	3		T32	3
valid_sources[0x3d]	37813	1			T5	1		T8	2		T127	2
valid_sources[0x3e]	37423	1			T32	3		T19	1		T8	5
valid_sources[0x3f]	36112	1			T6	1		T32	1		T8	6
valid_sources[0x40]	36344	1			T6	1		T17	3		T8	4
valid_sources[0x41]	36920	1			T5	1		T16	2		T8	3
valid_sources[0x42]	35788	1			T4	2		T6	1		T8	5
valid_sources[0x43]	37697	1			T4	1		T5	2		T32	6
valid_sources[0x44]	39252	1			T4	1		T6	3		T32	1
valid_sources[0x45]	37437	1			T8	4		T127	1		T211	1
valid_sources[0x46]	39072	1			T5	1		T32	2		T17	1
valid_sources[0x47]	39447	1			T8	4		T101	2		T211	1
valid_sources[0x48]	35587	1			T5	2		T70	10		T19	1
valid_sources[0x49]	37134	1			T5	2		T8	2		T211	1
valid_sources[0x4a]	39862	1			T6	1		T32	1		T8	3
valid_sources[0x4b]	37639	1			T8	3		T101	6		T55	2
valid_sources[0x4c]	37425	1			T32	2		T8	3		T55	2
valid_sources[0x4d]	36433	1			T3	1		T32	1		T70	5
valid_sources[0x4e]	38308	1			T5	1		T32	2		T8	3
valid_sources[0x4f]	37067	1			T8	4		T127	1		T211	1
valid_sources[0x50]	36305	1			T5	1		T8	2		T9	321
valid_sources[0x51]	36820	1			T32	1		T19	1		T8	5
valid_sources[0x52]	40079	1			T5	1		T19	1		T8	4
valid_sources[0x53]	37884	1			T4	1		T5	3		T8	4
valid_sources[0x54]	38187	1			T5	3		T19	1		T8	2
valid_sources[0x55]	38902	1			T4	1		T8	4		T101	4
valid_sources[0x56]	33131	1			T5	1		T6	1		T19	1
valid_sources[0x57]	40685	1			T19	1		T8	8		T101	2
valid_sources[0x58]	39190	1			T32	1		T8	6		T101	1
valid_sources[0x59]	37589	1			T5	1		T8	4		T127	1
valid_sources[0x5a]	38200	1			T5	1		T32	4		T8	2
valid_sources[0x5b]	37642	1			T5	5		T6	1		T32	2
valid_sources[0x5c]	41471	1			T6	2		T8	1		T127	1
valid_sources[0x5d]	37348	1			T2	8		T5	3		T32	2
valid_sources[0x5e]	36399	1			T19	1		T8	5		T127	1
valid_sources[0x5f]	40760	1			T8	2		T211	1		T9	306
valid_sources[0x60]	36724	1			T4	1		T8	5		T127	1
valid_sources[0x61]	39834	1			T5	1		T8	6		T211	2
valid_sources[0x62]	36636	1			T5	1		T17	1		T8	2
valid_sources[0x63]	39126	1			T5	1		T70	2		T19	1
valid_sources[0x64]	39054	1			T5	1		T8	4		T211	1
valid_sources[0x65]	39939	1			T70	1		T8	8		T127	1
valid_sources[0x66]	41358	1			T4	1		T8	2		T127	1
valid_sources[0x67]	37925	1			T5	2		T8	6		T9	342
valid_sources[0x68]	38114	1			T6	1		T32	1		T8	1
valid_sources[0x69]	40192	1			T5	1		T32	5		T8	2
valid_sources[0x6a]	40267	1			T19	1		T8	9		T211	1
valid_sources[0x6b]	36608	1			T5	1		T8	2		T55	1
valid_sources[0x6c]	35105	1			T6	1		T32	1		T70	2
valid_sources[0x6d]	36586	1			T5	2		T32	2		T19	1
valid_sources[0x6e]	38724	1			T5	1		T6	2		T32	1
valid_sources[0x6f]	37173	1			T8	2		T127	1		T101	5
valid_sources[0x70]	36727	1			T8	3		T127	1		T101	2
valid_sources[0x71]	36843	1			T2	3		T5	1		T32	1
valid_sources[0x72]	36429	1			T4	1		T19	2		T8	4
valid_sources[0x73]	35602	1			T4	2		T5	1		T8	3
valid_sources[0x74]	38834	1			T4	1		T19	1		T8	4
valid_sources[0x75]	37932	1			T4	2		T5	2		T17	2
valid_sources[0x76]	36552	1			T3	3		T70	1		T19	1
valid_sources[0x77]	38069	1			T3	3		T5	2		T70	4
valid_sources[0x78]	36261	1			T2	4		T32	2		T17	1
valid_sources[0x79]	36550	1			T4	1		T8	2		T9	317
valid_sources[0x7a]	38608	1			T5	1		T6	1		T19	2
valid_sources[0x7b]	37193	1			T5	1		T32	2		T8	4
valid_sources[0x7c]	35970	1			T4	1		T5	1		T6	1
valid_sources[0x7d]	36719	1			T4	2		T32	1		T70	2
valid_sources[0x7e]	39737	1			T5	1		T8	2		T127	1
valid_sources[0x7f]	37759	1			T6	1		T8	2		T55	1
valid_sources[0x80]	35682	1			T5	2		T32	1		T127	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2393442

1

T2

100

T3

10

T4

40

values[0x0]

all_enables

biggest_size

3511964

1

T2

58

T3

5

T4

22

values[0x1]

all_enables

biggest_size

3512302

1

T2

42

T3

5

T4

18