Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

26559500

1

T1

605

T2

4947

T3

415

full_word

8678144

1

T1

256

T2

4505

T3

200

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	35237314	1			T1	861		T2	9452		T3	615
auto[TlIntgErrCmd]	101	1			T279	10		T280	6		T281	7
auto[TlIntgErrData]	124	1			T279	7		T280	6		T281	7
auto[TlIntgErrBoth]	105	1			T279	3		T280	8		T281	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9931721

1

T1

540

T2

8614

T3

537

auto[1]

25305923

1

T1

321

T2

838

T3

78

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6213833	1			T1	412		T2	4434		T3	368
auto[TlIntgErrNone]	partial	auto[1]	20345370	1			T1	193		T2	513		T3	47
auto[TlIntgErrNone]	full_word	auto[0]	3717739	1			T1	128		T2	4180		T3	169
auto[TlIntgErrNone]	full_word	auto[1]	4960372	1			T1	128		T2	325		T3	31
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T279	3		T280	2		T281	4
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T279	5		T280	3		T281	3
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T279	1		T280	1		T286	1
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T279	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	56	1			T279	3		T280	4		T281	4
auto[TlIntgErrData]	partial	auto[1]	52	1			T279	3		T280	1		T281	2
auto[TlIntgErrData]	full_word	auto[0]	7	1			T279	1		T280	1		T376	2
auto[TlIntgErrData]	full_word	auto[1]	9	1			T281	1		T377	1		T375	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T279	1		T280	5		T281	1
auto[TlIntgErrBoth]	partial	auto[1]	61	1			T279	1		T280	2		T281	5
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T371	1		T373	1		T376	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T279	1		T280	1		T373	1