Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.60	96.10	96.15	97.16		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	507208943	8479660	0	0
check_regwen_rd_A	507208943	3526	0	0
check_timeout_rd_A	507208943	3388	0	0
check_trigger_regwen_rd_A	507208943	3381	0	0
consistency_check_period_rd_A	507208943	3674	0	0
creator_sw_cfg_read_lock_rd_A	507208943	3521	0	0
direct_access_address_rd_A	507208943	2388	0	0
direct_access_wdata_0_rd_A	507208943	1586	0	0
direct_access_wdata_1_rd_A	507208943	2004	0	0
integrity_check_period_rd_A	507208943	3371	0	0
intr_enable_rd_A	507208943	4676	0	0
owner_sw_cfg_read_lock_rd_A	507208943	3174	0	0
rot_creator_auth_codesign_read_lock_rd_A	507208943	3278	0	0
rot_creator_auth_state_read_lock_rd_A	507208943	2986	0	0
vendor_test_read_lock_rd_A	507208943	3080	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507208943	8479660	0	0
T9	341471	80286	0	0
T14	0	85674	0	0
T15	0	113218	0	0
T21	0	105559	0	0
T42	0	75758	0	0
T53	12360	0	0	0
T96	0	161156	0	0
T117	8797	0	0	0
T120	0	20579	0	0
T131	32345	0	0	0
T132	24684	0	0	0
T143	0	22439	0	0
T165	60430	0	0	0
T169	229370	0	0	0
T223	0	132108	0	0
T234	18253	0	0	0
T235	18929	0	0	0
T236	4346	0	0	0
T247	0	30883	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507208943	3526	0	0
T21	562146	113	0	0
T22	0	56	0	0
T36	14384	0	0	0
T75	0	78	0	0
T96	0	210	0	0
T113	13943	0	0	0
T120	0	36	0	0
T124	57869	0	0	0
T143	0	39	0	0
T171	142041	0	0	0
T206	38114	0	0	0
T207	23369	0	0	0
T208	70963	0	0	0
T253	0	71	0	0
T273	22746	0	0	0
T346	0	35	0	0
T347	0	83	0	0
T348	0	64	0	0
T349	6967	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507208943	3388	0	0
T21	562146	125	0	0
T22	0	72	0	0
T36	14384	0	0	0
T75	0	192	0	0
T96	0	283	0	0
T113	13943	0	0	0
T120	0	51	0	0
T124	57869	0	0	0
T143	0	50	0	0
T171	142041	0	0	0
T206	38114	0	0	0
T207	23369	0	0	0
T208	70963	0	0	0
T253	0	77	0	0
T273	22746	0	0	0
T346	0	31	0	0
T347	0	49	0	0
T348	0	91	0	0
T349	6967	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507208943	3381	0	0
T21	562146	82	0	0
T22	0	33	0	0
T36	14384	0	0	0
T75	0	131	0	0
T96	0	132	0	0
T113	13943	0	0	0
T120	0	30	0	0
T124	57869	0	0	0
T143	0	17	0	0
T171	142041	0	0	0
T206	38114	0	0	0
T207	23369	0	0	0
T208	70963	0	0	0
T253	0	41	0	0
T273	22746	0	0	0
T346	0	26	0	0
T347	0	93	0	0
T348	0	87	0	0
T349	6967	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507208943	3674	0	0
T21	562146	119	0	0
T22	0	66	0	0
T36	14384	0	0	0
T75	0	99	0	0
T96	0	185	0	0
T113	13943	0	0	0
T120	0	41	0	0
T124	57869	0	0	0
T143	0	55	0	0
T171	142041	0	0	0
T206	38114	0	0	0
T207	23369	0	0	0
T208	70963	0	0	0
T253	0	79	0	0
T273	22746	0	0	0
T346	0	25	0	0
T347	0	47	0	0
T348	0	139	0	0
T349	6967	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507208943	3521	0	0
T21	562146	132	0	0
T22	0	53	0	0
T36	14384	0	0	0
T75	0	153	0	0
T96	0	225	0	0
T113	13943	0	0	0
T120	0	62	0	0
T124	57869	0	0	0
T143	0	23	0	0
T171	142041	0	0	0
T206	38114	0	0	0
T207	23369	0	0	0
T208	70963	0	0	0
T253	0	77	0	0
T273	22746	0	0	0
T346	0	34	0	0
T347	0	73	0	0
T348	0	106	0	0
T349	6967	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507208943	2388	0	0
T21	562146	128	0	0
T22	0	87	0	0
T36	14384	0	0	0
T75	0	106	0	0
T96	0	197	0	0
T113	13943	0	0	0
T120	0	53	0	0
T124	57869	0	0	0
T143	0	28	0	0
T171	142041	0	0	0
T206	38114	0	0	0
T207	23369	0	0	0
T208	70963	0	0	0
T253	0	82	0	0
T273	22746	0	0	0
T346	0	40	0	0
T347	0	75	0	0
T348	0	104	0	0
T349	6967	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507208943	1586	0	0
T21	562146	80	0	0
T22	0	33	0	0
T36	14384	0	0	0
T75	0	96	0	0
T96	0	112	0	0
T113	13943	0	0	0
T120	0	17	0	0
T124	57869	0	0	0
T143	0	13	0	0
T171	142041	0	0	0
T206	38114	0	0	0
T207	23369	0	0	0
T208	70963	0	0	0
T253	0	47	0	0
T273	22746	0	0	0
T346	0	18	0	0
T347	0	46	0	0
T348	0	79	0	0
T349	6967	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507208943	2004	0	0
T21	562146	96	0	0
T22	0	88	0	0
T36	14384	0	0	0
T75	0	92	0	0
T96	0	135	0	0
T113	13943	0	0	0
T120	0	8	0	0
T124	57869	0	0	0
T143	0	7	0	0
T171	142041	0	0	0
T206	38114	0	0	0
T207	23369	0	0	0
T208	70963	0	0	0
T253	0	112	0	0
T273	22746	0	0	0
T346	0	11	0	0
T347	0	61	0	0
T348	0	137	0	0
T349	6967	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507208943	3371	0	0
T21	562146	108	0	0
T22	0	75	0	0
T36	14384	0	0	0
T75	0	137	0	0
T96	0	196	0	0
T113	13943	0	0	0
T120	0	34	0	0
T124	57869	0	0	0
T143	0	56	0	0
T171	142041	0	0	0
T206	38114	0	0	0
T207	23369	0	0	0
T208	70963	0	0	0
T253	0	77	0	0
T273	22746	0	0	0
T346	0	22	0	0
T347	0	35	0	0
T348	0	78	0	0
T349	6967	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507208943	4676	0	0
T8	955274	21	0	0
T20	502921	0	0	0
T21	0	121	0	0
T22	0	93	0	0
T55	136905	0	0	0
T59	12372	0	0	0
T96	0	222	0	0
T101	66311	0	0	0
T102	56165	0	0	0
T120	0	53	0	0
T127	71256	0	0	0
T128	73688	0	0	0
T129	18304	0	0	0
T130	207144	15	0	0
T143	0	70	0	0
T251	0	37	0	0
T253	0	63	0	0
T350	0	6	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507208943	3174	0	0
T21	562146	109	0	0
T22	0	47	0	0
T36	14384	0	0	0
T75	0	89	0	0
T96	0	147	0	0
T113	13943	0	0	0
T120	0	41	0	0
T124	57869	0	0	0
T143	0	26	0	0
T171	142041	0	0	0
T206	38114	0	0	0
T207	23369	0	0	0
T208	70963	0	0	0
T253	0	62	0	0
T273	22746	0	0	0
T346	0	52	0	0
T347	0	66	0	0
T348	0	96	0	0
T349	6967	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507208943	3278	0	0
T21	562146	119	0	0
T22	0	46	0	0
T36	14384	0	0	0
T75	0	155	0	0
T96	0	238	0	0
T113	13943	0	0	0
T120	0	44	0	0
T124	57869	0	0	0
T143	0	38	0	0
T171	142041	0	0	0
T206	38114	0	0	0
T207	23369	0	0	0
T208	70963	0	0	0
T253	0	60	0	0
T273	22746	0	0	0
T346	0	17	0	0
T347	0	79	0	0
T348	0	124	0	0
T349	6967	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507208943	2986	0	0
T21	562146	82	0	0
T22	0	30	0	0
T36	14384	0	0	0
T75	0	97	0	0
T96	0	239	0	0
T113	13943	0	0	0
T120	0	38	0	0
T124	57869	0	0	0
T143	0	36	0	0
T171	142041	0	0	0
T206	38114	0	0	0
T207	23369	0	0	0
T208	70963	0	0	0
T253	0	70	0	0
T273	22746	0	0	0
T346	0	33	0	0
T347	0	55	0	0
T348	0	82	0	0
T349	6967	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507208943	3080	0	0
T21	562146	134	0	0
T22	0	41	0	0
T36	14384	0	0	0
T75	0	101	0	0
T96	0	194	0	0
T113	13943	0	0	0
T120	0	13	0	0
T124	57869	0	0	0
T143	0	24	0	0
T171	142041	0	0	0
T206	38114	0	0	0
T207	23369	0	0	0
T208	70963	0	0	0
T253	0	99	0	0
T273	22746	0	0	0
T346	0	31	0	0
T347	0	64	0	0
T348	0	91	0	0
T349	6967	0	0	0