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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.13 93.99 96.66 95.89 92.12 97.56 96.33 93.35


Total test records in report: 1329
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T1263 /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.3705130508 Mar 21 02:33:27 PM PDT 24 Mar 21 02:33:30 PM PDT 24 139373759 ps
T1264 /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.3681966210 Mar 21 02:32:27 PM PDT 24 Mar 21 02:32:28 PM PDT 24 76624643 ps
T1265 /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.3792944887 Mar 21 02:33:44 PM PDT 24 Mar 21 02:33:46 PM PDT 24 48981767 ps
T1266 /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.3685553843 Mar 21 02:33:27 PM PDT 24 Mar 21 02:33:30 PM PDT 24 60656186 ps
T1267 /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.3590226634 Mar 21 02:33:27 PM PDT 24 Mar 21 02:33:32 PM PDT 24 1061270861 ps
T1268 /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.853920184 Mar 21 02:33:33 PM PDT 24 Mar 21 02:33:35 PM PDT 24 71670561 ps
T376 /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.1641090936 Mar 21 02:33:45 PM PDT 24 Mar 21 02:33:56 PM PDT 24 737076278 ps
T1269 /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.445738186 Mar 21 02:33:38 PM PDT 24 Mar 21 02:33:39 PM PDT 24 43703133 ps
T1270 /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.899839506 Mar 21 02:32:41 PM PDT 24 Mar 21 02:32:49 PM PDT 24 1195608294 ps
T1271 /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.2233777288 Mar 21 02:33:40 PM PDT 24 Mar 21 02:33:42 PM PDT 24 78931919 ps
T1272 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.1359167609 Mar 21 02:32:46 PM PDT 24 Mar 21 02:32:51 PM PDT 24 1669850413 ps
T313 /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.4253249336 Mar 21 02:33:25 PM PDT 24 Mar 21 02:33:26 PM PDT 24 51319870 ps
T1273 /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.1374516276 Mar 21 02:33:38 PM PDT 24 Mar 21 02:33:39 PM PDT 24 37867278 ps
T1274 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.1688763849 Mar 21 02:33:15 PM PDT 24 Mar 21 02:33:21 PM PDT 24 397836886 ps
T1275 /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.4047902470 Mar 21 02:33:38 PM PDT 24 Mar 21 02:33:40 PM PDT 24 74297118 ps
T372 /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.379319819 Mar 21 02:33:27 PM PDT 24 Mar 21 02:33:50 PM PDT 24 2470840451 ps
T1276 /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.1887006251 Mar 21 02:32:46 PM PDT 24 Mar 21 02:32:48 PM PDT 24 73065927 ps
T314 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.2693201647 Mar 21 02:32:30 PM PDT 24 Mar 21 02:32:32 PM PDT 24 564997984 ps
T1277 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.471670503 Mar 21 02:33:31 PM PDT 24 Mar 21 02:33:34 PM PDT 24 137631697 ps
T1278 /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.3455027334 Mar 21 02:32:59 PM PDT 24 Mar 21 02:33:02 PM PDT 24 66857823 ps
T1279 /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.4063645934 Mar 21 02:32:42 PM PDT 24 Mar 21 02:32:43 PM PDT 24 37935328 ps
T1280 /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.747865911 Mar 21 02:33:00 PM PDT 24 Mar 21 02:33:03 PM PDT 24 50500104 ps
T1281 /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.1371167235 Mar 21 02:32:31 PM PDT 24 Mar 21 02:32:34 PM PDT 24 197001129 ps
T315 /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.272775272 Mar 21 02:33:25 PM PDT 24 Mar 21 02:33:27 PM PDT 24 170103741 ps
T1282 /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.3691801597 Mar 21 02:33:54 PM PDT 24 Mar 21 02:33:55 PM PDT 24 554028094 ps
T317 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.1361326014 Mar 21 02:32:42 PM PDT 24 Mar 21 02:32:46 PM PDT 24 99009776 ps
T1283 /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.1119131832 Mar 21 02:33:02 PM PDT 24 Mar 21 02:33:06 PM PDT 24 1069496833 ps
T318 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.619626560 Mar 21 02:32:47 PM PDT 24 Mar 21 02:32:51 PM PDT 24 114473667 ps
T1284 /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.2021499336 Mar 21 02:32:28 PM PDT 24 Mar 21 02:32:46 PM PDT 24 1220733639 ps
T1285 /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.206222126 Mar 21 02:33:13 PM PDT 24 Mar 21 02:33:16 PM PDT 24 48970112 ps
T1286 /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.4186882044 Mar 21 02:33:23 PM PDT 24 Mar 21 02:33:26 PM PDT 24 569364347 ps
T319 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.3196982479 Mar 21 02:32:43 PM PDT 24 Mar 21 02:32:45 PM PDT 24 175762290 ps
T1287 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.1016120547 Mar 21 02:32:30 PM PDT 24 Mar 21 02:32:34 PM PDT 24 97128187 ps
T1288 /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.4059605620 Mar 21 02:33:39 PM PDT 24 Mar 21 02:33:41 PM PDT 24 145985326 ps
T1289 /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.3549798553 Mar 21 02:33:29 PM PDT 24 Mar 21 02:33:36 PM PDT 24 313318847 ps
T1290 /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.1006602401 Mar 21 02:33:13 PM PDT 24 Mar 21 02:33:17 PM PDT 24 103246550 ps
T1291 /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.4186694232 Mar 21 02:33:22 PM PDT 24 Mar 21 02:33:23 PM PDT 24 41849704 ps
T1292 /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.1142966862 Mar 21 02:32:27 PM PDT 24 Mar 21 02:32:29 PM PDT 24 52910711 ps
T1293 /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.4283716149 Mar 21 02:32:48 PM PDT 24 Mar 21 02:32:49 PM PDT 24 70936380 ps
T1294 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.3542992570 Mar 21 02:32:31 PM PDT 24 Mar 21 02:32:36 PM PDT 24 86900812 ps
T1295 /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.1151494754 Mar 21 02:33:28 PM PDT 24 Mar 21 02:33:31 PM PDT 24 133898078 ps
T1296 /workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.2014219622 Mar 21 02:33:45 PM PDT 24 Mar 21 02:33:46 PM PDT 24 50627827 ps
T1297 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.3382226853 Mar 21 02:32:59 PM PDT 24 Mar 21 02:33:03 PM PDT 24 98376737 ps
T1298 /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.2727260004 Mar 21 02:32:42 PM PDT 24 Mar 21 02:32:44 PM PDT 24 74363195 ps
T1299 /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.3252497502 Mar 21 02:33:31 PM PDT 24 Mar 21 02:33:34 PM PDT 24 88563805 ps
T1300 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.3185247737 Mar 21 02:32:59 PM PDT 24 Mar 21 02:33:02 PM PDT 24 68565338 ps
T1301 /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.1747567507 Mar 21 02:32:29 PM PDT 24 Mar 21 02:32:41 PM PDT 24 2446033775 ps
T1302 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.1051116965 Mar 21 02:32:25 PM PDT 24 Mar 21 02:32:27 PM PDT 24 82783215 ps
T1303 /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.3526468196 Mar 21 02:33:38 PM PDT 24 Mar 21 02:33:40 PM PDT 24 146847280 ps
T1304 /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.132743009 Mar 21 02:33:12 PM PDT 24 Mar 21 02:33:14 PM PDT 24 559999221 ps
T1305 /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.2729067040 Mar 21 02:33:23 PM PDT 24 Mar 21 02:33:26 PM PDT 24 105830386 ps
T1306 /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.2213915866 Mar 21 02:32:29 PM PDT 24 Mar 21 02:32:31 PM PDT 24 38169277 ps
T1307 /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.2960661057 Mar 21 02:33:31 PM PDT 24 Mar 21 02:33:34 PM PDT 24 169888353 ps
T1308 /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.3049764499 Mar 21 02:32:43 PM PDT 24 Mar 21 02:32:47 PM PDT 24 195047128 ps
T1309 /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.1008577314 Mar 21 02:33:29 PM PDT 24 Mar 21 02:33:53 PM PDT 24 19220466991 ps
T1310 /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.2011686486 Mar 21 02:33:24 PM PDT 24 Mar 21 02:33:26 PM PDT 24 76658721 ps
T1311 /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.505026380 Mar 21 02:32:42 PM PDT 24 Mar 21 02:32:44 PM PDT 24 57135880 ps
T330 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.509964359 Mar 21 02:32:30 PM PDT 24 Mar 21 02:32:35 PM PDT 24 401410588 ps
T1312 /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.3636487067 Mar 21 02:33:31 PM PDT 24 Mar 21 02:33:35 PM PDT 24 166485129 ps
T1313 /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.253914081 Mar 21 02:33:33 PM PDT 24 Mar 21 02:33:34 PM PDT 24 38780218 ps
T1314 /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.1895925996 Mar 21 02:33:12 PM PDT 24 Mar 21 02:33:14 PM PDT 24 88138611 ps
T320 /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.715258968 Mar 21 02:33:00 PM PDT 24 Mar 21 02:33:02 PM PDT 24 48036162 ps
T1315 /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.2008256232 Mar 21 02:33:12 PM PDT 24 Mar 21 02:33:17 PM PDT 24 1268198227 ps
T1316 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.1949125936 Mar 21 02:32:26 PM PDT 24 Mar 21 02:32:33 PM PDT 24 747530830 ps
T321 /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.3602837932 Mar 21 02:33:38 PM PDT 24 Mar 21 02:33:40 PM PDT 24 44104991 ps
T1317 /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.334382147 Mar 21 02:33:12 PM PDT 24 Mar 21 02:33:16 PM PDT 24 213637833 ps
T1318 /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.3858227866 Mar 21 02:33:33 PM PDT 24 Mar 21 02:33:36 PM PDT 24 175939154 ps
T1319 /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.868385803 Mar 21 02:32:41 PM PDT 24 Mar 21 02:32:45 PM PDT 24 91893654 ps
T1320 /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.2113416858 Mar 21 02:32:41 PM PDT 24 Mar 21 02:32:43 PM PDT 24 37721284 ps
T1321 /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.261422916 Mar 21 02:32:59 PM PDT 24 Mar 21 02:33:01 PM PDT 24 133548644 ps
T1322 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.3370942435 Mar 21 02:32:47 PM PDT 24 Mar 21 02:32:51 PM PDT 24 243134146 ps
T1323 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.1192564626 Mar 21 02:32:27 PM PDT 24 Mar 21 02:32:31 PM PDT 24 1673954287 ps
T1324 /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.2450538861 Mar 21 02:33:30 PM PDT 24 Mar 21 02:33:32 PM PDT 24 154154710 ps
T374 /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.599797970 Mar 21 02:32:41 PM PDT 24 Mar 21 02:33:02 PM PDT 24 1319242755 ps
T1325 /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.1905246744 Mar 21 02:33:30 PM PDT 24 Mar 21 02:33:50 PM PDT 24 1259619548 ps
T1326 /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.2564936725 Mar 21 02:33:22 PM PDT 24 Mar 21 02:33:45 PM PDT 24 3725485042 ps
T1327 /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.415654532 Mar 21 02:33:32 PM PDT 24 Mar 21 02:33:51 PM PDT 24 9767531190 ps
T1328 /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.2905077893 Mar 21 02:33:46 PM PDT 24 Mar 21 02:33:48 PM PDT 24 132936206 ps
T1329 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.1333385452 Mar 21 02:33:28 PM PDT 24 Mar 21 02:33:31 PM PDT 24 159688024 ps

Test location /workspace/coverage/default/4.otp_ctrl_macro_errs.2196299904
Short name T5
Test name
Test status
Simulation time 6246218326 ps
CPU time 57.69 seconds
Started Mar 21 03:27:15 PM PDT 24
Finished Mar 21 03:28:13 PM PDT 24
Peak memory 258720 kb
Host smart-8439dda9-d192-4a40-9448-f6e5cfa86c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196299904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.2196299904
Directory /workspace/4.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all.2794501927
Short name T8
Test name
Test status
Simulation time 49832976810 ps
CPU time 231.64 seconds
Started Mar 21 03:27:10 PM PDT 24
Finished Mar 21 03:31:02 PM PDT 24
Peak memory 266480 kb
Host smart-60096503-d47d-4b4c-b67d-887846af115a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794501927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all.
2794501927
Directory /workspace/4.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/90.otp_ctrl_stress_all_with_rand_reset.578302998
Short name T9
Test name
Test status
Simulation time 34843796443 ps
CPU time 880.69 seconds
Started Mar 21 03:30:04 PM PDT 24
Finished Mar 21 03:44:46 PM PDT 24
Peak memory 326056 kb
Host smart-947cad9d-28a9-4ed5-bef8-b90f8a7debe1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578302998 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_stress_all_with_rand_reset.578302998
Directory /workspace/90.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all.1184538247
Short name T105
Test name
Test status
Simulation time 65723174439 ps
CPU time 184.06 seconds
Started Mar 21 03:29:04 PM PDT 24
Finished Mar 21 03:32:08 PM PDT 24
Peak memory 258176 kb
Host smart-e0483a6a-db3e-4ca1-bf2b-bcf5d56f12d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184538247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all
.1184538247
Directory /workspace/43.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all.2910568618
Short name T4
Test name
Test status
Simulation time 965945904 ps
CPU time 21.09 seconds
Started Mar 21 03:28:48 PM PDT 24
Finished Mar 21 03:29:09 PM PDT 24
Peak memory 241552 kb
Host smart-a6a28c66-e084-4843-8ab1-9670c89e5edf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910568618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all
.2910568618
Directory /workspace/40.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/65.otp_ctrl_init_fail.1363449553
Short name T79
Test name
Test status
Simulation time 480268443 ps
CPU time 4.01 seconds
Started Mar 21 03:29:30 PM PDT 24
Finished Mar 21 03:29:34 PM PDT 24
Peak memory 241372 kb
Host smart-cf5caba5-f590-4431-ae74-42128fd1b2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363449553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.1363449553
Directory /workspace/65.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_sec_cm.1284641109
Short name T26
Test name
Test status
Simulation time 11871316935 ps
CPU time 195.02 seconds
Started Mar 21 03:27:02 PM PDT 24
Finished Mar 21 03:30:17 PM PDT 24
Peak memory 270684 kb
Host smart-1b4ad64b-0b90-4c58-af62-55996d57ffab
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284641109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.1284641109
Directory /workspace/2.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all.3629768530
Short name T20
Test name
Test status
Simulation time 7982888302 ps
CPU time 121.89 seconds
Started Mar 21 03:28:11 PM PDT 24
Finished Mar 21 03:30:13 PM PDT 24
Peak memory 248796 kb
Host smart-c751eafa-ab58-440f-bf06-c06fa6e01211
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629768530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all
.3629768530
Directory /workspace/24.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all_with_rand_reset.3734678824
Short name T223
Test name
Test status
Simulation time 120364324678 ps
CPU time 1876.83 seconds
Started Mar 21 03:29:04 PM PDT 24
Finished Mar 21 04:00:21 PM PDT 24
Peak memory 533448 kb
Host smart-41b63f13-8452-4ce0-a907-963faf210355
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734678824 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all_with_rand_reset.3734678824
Directory /workspace/45.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.otp_ctrl_check_fail.1935756092
Short name T33
Test name
Test status
Simulation time 645369486 ps
CPU time 18.55 seconds
Started Mar 21 03:28:50 PM PDT 24
Finished Mar 21 03:29:08 PM PDT 24
Peak memory 242240 kb
Host smart-2a583c89-e4aa-45b1-8fd4-ad461e55c749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935756092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.1935756092
Directory /workspace/41.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/148.otp_ctrl_init_fail.503532720
Short name T54
Test name
Test status
Simulation time 2920522793 ps
CPU time 6.87 seconds
Started Mar 21 03:30:16 PM PDT 24
Finished Mar 21 03:30:24 PM PDT 24
Peak memory 241776 kb
Host smart-97479262-ac33-4852-b4c7-567d00c0bbf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503532720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.503532720
Directory /workspace/148.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.3544065272
Short name T279
Test name
Test status
Simulation time 3681196019 ps
CPU time 23.1 seconds
Started Mar 21 02:33:13 PM PDT 24
Finished Mar 21 02:33:36 PM PDT 24
Peak memory 244136 kb
Host smart-661a1396-2817-4108-8076-a10d4036724e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544065272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_i
ntg_err.3544065272
Directory /workspace/11.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/124.otp_ctrl_init_fail.1292481532
Short name T52
Test name
Test status
Simulation time 316897044 ps
CPU time 4.62 seconds
Started Mar 21 03:30:18 PM PDT 24
Finished Mar 21 03:30:23 PM PDT 24
Peak memory 241468 kb
Host smart-0be3431d-2472-4320-ad81-7b145e7ff5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292481532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.1292481532
Directory /workspace/124.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all_with_rand_reset.2165422990
Short name T75
Test name
Test status
Simulation time 51308830424 ps
CPU time 982.24 seconds
Started Mar 21 03:28:50 PM PDT 24
Finished Mar 21 03:45:12 PM PDT 24
Peak memory 264820 kb
Host smart-5ecfb7db-887c-4cd0-80b5-18d29e32e281
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165422990 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all_with_rand_reset.2165422990
Directory /workspace/38.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.otp_ctrl_macro_errs.2006084524
Short name T169
Test name
Test status
Simulation time 9557212726 ps
CPU time 58.78 seconds
Started Mar 21 03:28:10 PM PDT 24
Finished Mar 21 03:29:09 PM PDT 24
Peak memory 261820 kb
Host smart-1831d9b8-b563-42b2-9233-95731f8c27d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006084524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.2006084524
Directory /workspace/27.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all.496832241
Short name T185
Test name
Test status
Simulation time 17936305412 ps
CPU time 214.41 seconds
Started Mar 21 03:27:43 PM PDT 24
Finished Mar 21 03:31:18 PM PDT 24
Peak memory 258192 kb
Host smart-dab82a60-c1eb-45c6-8ebc-8e027dcbf7b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496832241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all.
496832241
Directory /workspace/13.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/225.otp_ctrl_init_fail.764979858
Short name T28
Test name
Test status
Simulation time 263873840 ps
CPU time 3.72 seconds
Started Mar 21 03:31:09 PM PDT 24
Finished Mar 21 03:31:13 PM PDT 24
Peak memory 241660 kb
Host smart-f5c4e3a1-9586-49ae-a0e1-6f52f963dac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764979858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.764979858
Directory /workspace/225.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/128.otp_ctrl_init_fail.3891192373
Short name T81
Test name
Test status
Simulation time 376021624 ps
CPU time 3.61 seconds
Started Mar 21 03:30:09 PM PDT 24
Finished Mar 21 03:30:13 PM PDT 24
Peak memory 241344 kb
Host smart-b01295eb-dd2d-42c7-8309-52558bd3359b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891192373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.3891192373
Directory /workspace/128.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/294.otp_ctrl_init_fail.439469132
Short name T39
Test name
Test status
Simulation time 260090725 ps
CPU time 3.95 seconds
Started Mar 21 03:31:22 PM PDT 24
Finished Mar 21 03:31:27 PM PDT 24
Peak memory 241420 kb
Host smart-8d024805-aa7f-44d8-ba35-b7997c57bf36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439469132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.439469132
Directory /workspace/294.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_alert_test.732065621
Short name T432
Test name
Test status
Simulation time 268272819 ps
CPU time 1.85 seconds
Started Mar 21 03:27:00 PM PDT 24
Finished Mar 21 03:27:02 PM PDT 24
Peak memory 239820 kb
Host smart-72ebb93a-56c2-4dc9-95db-0bc8dc13f451
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732065621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.732065621
Directory /workspace/0.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.otp_ctrl_check_fail.2944922994
Short name T74
Test name
Test status
Simulation time 2414997301 ps
CPU time 35.33 seconds
Started Mar 21 03:29:25 PM PDT 24
Finished Mar 21 03:30:00 PM PDT 24
Peak memory 248392 kb
Host smart-4cc5691b-3a88-4f61-ab4f-daa13fad9dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944922994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_check_fail.2944922994
Directory /workspace/47.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/75.otp_ctrl_stress_all_with_rand_reset.1989976317
Short name T144
Test name
Test status
Simulation time 180231138762 ps
CPU time 689.23 seconds
Started Mar 21 03:29:41 PM PDT 24
Finished Mar 21 03:41:11 PM PDT 24
Peak memory 293536 kb
Host smart-47755426-3ee0-418c-a597-e7095b8da7c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989976317 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_stress_all_with_rand_reset.1989976317
Directory /workspace/75.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/151.otp_ctrl_init_fail.529745742
Short name T68
Test name
Test status
Simulation time 429978456 ps
CPU time 5.44 seconds
Started Mar 21 03:30:12 PM PDT 24
Finished Mar 21 03:30:17 PM PDT 24
Peak memory 241428 kb
Host smart-a61e237e-d06c-4a64-98e1-d2b358e7cbfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529745742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.529745742
Directory /workspace/151.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/120.otp_ctrl_parallel_lc_esc.4092973039
Short name T147
Test name
Test status
Simulation time 863950283 ps
CPU time 11.89 seconds
Started Mar 21 03:30:16 PM PDT 24
Finished Mar 21 03:30:28 PM PDT 24
Peak memory 241236 kb
Host smart-66598214-cb75-4d21-9b6d-c03f4a51c79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092973039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.4092973039
Directory /workspace/120.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/157.otp_ctrl_init_fail.635899621
Short name T172
Test name
Test status
Simulation time 149488431 ps
CPU time 3.6 seconds
Started Mar 21 03:30:28 PM PDT 24
Finished Mar 21 03:30:32 PM PDT 24
Peak memory 241440 kb
Host smart-c581a2a6-5f38-4c67-b48f-e2a1a50634c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635899621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.635899621
Directory /workspace/157.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_key_req.272370546
Short name T210
Test name
Test status
Simulation time 1500415771 ps
CPU time 30.3 seconds
Started Mar 21 03:28:49 PM PDT 24
Finished Mar 21 03:29:19 PM PDT 24
Peak memory 241356 kb
Host smart-ed361812-3378-4031-91a5-0a28a6c2bc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272370546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.272370546
Directory /workspace/39.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/120.otp_ctrl_init_fail.2232750880
Short name T58
Test name
Test status
Simulation time 580691915 ps
CPU time 4.24 seconds
Started Mar 21 03:30:19 PM PDT 24
Finished Mar 21 03:30:23 PM PDT 24
Peak memory 241792 kb
Host smart-3bc0b85d-f2a8-4007-ad92-b62fc5341119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232750880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.2232750880
Directory /workspace/120.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_macro_errs.63110066
Short name T220
Test name
Test status
Simulation time 4629327269 ps
CPU time 31.35 seconds
Started Mar 21 03:27:35 PM PDT 24
Finished Mar 21 03:28:06 PM PDT 24
Peak memory 248308 kb
Host smart-b0627e99-699c-4103-b58f-1e5576b2486d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63110066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.63110066
Directory /workspace/18.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/278.otp_ctrl_init_fail.1072543901
Short name T36
Test name
Test status
Simulation time 2397615255 ps
CPU time 4.41 seconds
Started Mar 21 03:31:04 PM PDT 24
Finished Mar 21 03:31:09 PM PDT 24
Peak memory 241808 kb
Host smart-8fa8dd2e-097f-4cb7-9b12-f0ca83dfddc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072543901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.1072543901
Directory /workspace/278.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/133.otp_ctrl_init_fail.810401156
Short name T192
Test name
Test status
Simulation time 163170163 ps
CPU time 4.87 seconds
Started Mar 21 03:30:11 PM PDT 24
Finished Mar 21 03:30:16 PM PDT 24
Peak memory 241520 kb
Host smart-ddf70284-5263-4942-ae8c-63ea81a4b49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810401156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.810401156
Directory /workspace/133.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/118.otp_ctrl_init_fail.2591504414
Short name T44
Test name
Test status
Simulation time 788076314 ps
CPU time 6.82 seconds
Started Mar 21 03:30:10 PM PDT 24
Finished Mar 21 03:30:17 PM PDT 24
Peak memory 241620 kb
Host smart-9d9bc44a-8e7f-42e1-8e91-96f992ca45ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591504414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.2591504414
Directory /workspace/118.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all.1141700309
Short name T525
Test name
Test status
Simulation time 154463538447 ps
CPU time 413.35 seconds
Started Mar 21 03:27:58 PM PDT 24
Finished Mar 21 03:34:52 PM PDT 24
Peak memory 273024 kb
Host smart-2bbcc74d-bce0-4720-b917-3ded932c8431
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141700309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all
.1141700309
Directory /workspace/23.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/84.otp_ctrl_stress_all_with_rand_reset.221121501
Short name T293
Test name
Test status
Simulation time 975412862635 ps
CPU time 3532.25 seconds
Started Mar 21 03:29:56 PM PDT 24
Finished Mar 21 04:28:49 PM PDT 24
Peak memory 494212 kb
Host smart-743f96a5-3703-42c4-93e4-3226e9fd9ea9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221121501 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_stress_all_with_rand_reset.221121501
Directory /workspace/84.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.otp_ctrl_parallel_lc_esc.389141193
Short name T77
Test name
Test status
Simulation time 2455662112 ps
CPU time 5.51 seconds
Started Mar 21 03:29:47 PM PDT 24
Finished Mar 21 03:29:53 PM PDT 24
Peak memory 241540 kb
Host smart-44c522e5-2f0e-4589-bbe3-d4a67074d08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389141193 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.389141193
Directory /workspace/73.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/27.otp_ctrl_regwen.2104213588
Short name T382
Test name
Test status
Simulation time 472283693 ps
CPU time 8.2 seconds
Started Mar 21 03:28:14 PM PDT 24
Finished Mar 21 03:28:22 PM PDT 24
Peak memory 241284 kb
Host smart-13a420f9-eafa-4008-92fc-bdd358f89423
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2104213588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.2104213588
Directory /workspace/27.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all.797586438
Short name T255
Test name
Test status
Simulation time 25987813282 ps
CPU time 195.67 seconds
Started Mar 21 03:28:25 PM PDT 24
Finished Mar 21 03:31:40 PM PDT 24
Peak memory 245460 kb
Host smart-9ca3a859-9f1f-4457-9833-ec9a2a1bc366
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797586438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all.
797586438
Directory /workspace/28.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.otp_ctrl_init_fail.2024958770
Short name T117
Test name
Test status
Simulation time 88001810 ps
CPU time 3.32 seconds
Started Mar 21 03:27:49 PM PDT 24
Finished Mar 21 03:27:52 PM PDT 24
Peak memory 241308 kb
Host smart-26220adb-989d-41f2-92eb-9d105be4971f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024958770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.2024958770
Directory /workspace/16.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/123.otp_ctrl_init_fail.9390135
Short name T177
Test name
Test status
Simulation time 117768404 ps
CPU time 3.36 seconds
Started Mar 21 03:30:12 PM PDT 24
Finished Mar 21 03:30:15 PM PDT 24
Peak memory 241320 kb
Host smart-b8e3e7b2-8e23-4d9e-a18c-65240a6884fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9390135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.9390135
Directory /workspace/123.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_check_fail.1140593607
Short name T50
Test name
Test status
Simulation time 690802592 ps
CPU time 14.05 seconds
Started Mar 21 03:28:50 PM PDT 24
Finished Mar 21 03:29:04 PM PDT 24
Peak memory 242296 kb
Host smart-6b9742a6-118e-4a89-bd9a-86d5b5f67a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140593607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.1140593607
Directory /workspace/37.otp_ctrl_check_fail/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.1736464791
Short name T371
Test name
Test status
Simulation time 1296108864 ps
CPU time 18.36 seconds
Started Mar 21 02:33:02 PM PDT 24
Finished Mar 21 02:33:20 PM PDT 24
Peak memory 243516 kb
Host smart-f26abb1a-1b29-4162-816d-74907fa0e833
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736464791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_in
tg_err.1736464791
Directory /workspace/5.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/125.otp_ctrl_parallel_lc_esc.3339667518
Short name T277
Test name
Test status
Simulation time 698039411 ps
CPU time 7.5 seconds
Started Mar 21 03:30:20 PM PDT 24
Finished Mar 21 03:30:27 PM PDT 24
Peak memory 241540 kb
Host smart-9a6a29bd-8b4b-43e0-928e-f74d3d830d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339667518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.3339667518
Directory /workspace/125.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/83.otp_ctrl_stress_all_with_rand_reset.1647958642
Short name T325
Test name
Test status
Simulation time 108869693223 ps
CPU time 962.81 seconds
Started Mar 21 03:30:06 PM PDT 24
Finished Mar 21 03:46:09 PM PDT 24
Peak memory 322252 kb
Host smart-5513ac8a-a7c5-4965-80f5-263a14519892
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647958642 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_stress_all_with_rand_reset.1647958642
Directory /workspace/83.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/114.otp_ctrl_init_fail.930034677
Short name T30
Test name
Test status
Simulation time 626714391 ps
CPU time 3.81 seconds
Started Mar 21 03:30:11 PM PDT 24
Finished Mar 21 03:30:14 PM PDT 24
Peak memory 241448 kb
Host smart-66c52b05-a943-4bdb-90a3-45d506dc3c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930034677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.930034677
Directory /workspace/114.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_check_fail.2690247115
Short name T135
Test name
Test status
Simulation time 1038326369 ps
CPU time 14.16 seconds
Started Mar 21 03:29:18 PM PDT 24
Finished Mar 21 03:29:32 PM PDT 24
Peak memory 241380 kb
Host smart-85983c5d-3a29-4628-9958-8bfade456da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690247115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.2690247115
Directory /workspace/49.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_init_fail.930740400
Short name T205
Test name
Test status
Simulation time 1724551796 ps
CPU time 6.39 seconds
Started Mar 21 03:27:28 PM PDT 24
Finished Mar 21 03:27:34 PM PDT 24
Peak memory 241304 kb
Host smart-85732ac8-e756-46ef-a6b0-2a5b8c89f559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930740400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.930740400
Directory /workspace/13.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/153.otp_ctrl_parallel_lc_esc.1175823387
Short name T266
Test name
Test status
Simulation time 306457721 ps
CPU time 4.71 seconds
Started Mar 21 03:30:31 PM PDT 24
Finished Mar 21 03:30:36 PM PDT 24
Peak memory 241312 kb
Host smart-a13f825f-f398-43db-93f8-af1b0a38376c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175823387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.1175823387
Directory /workspace/153.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all.1729846947
Short name T875
Test name
Test status
Simulation time 45889735492 ps
CPU time 257.81 seconds
Started Mar 21 03:28:21 PM PDT 24
Finished Mar 21 03:32:40 PM PDT 24
Peak memory 279136 kb
Host smart-93750ca4-2fe4-4841-a597-892905d3eacf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729846947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all
.1729846947
Directory /workspace/31.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all_with_rand_reset.2743896298
Short name T22
Test name
Test status
Simulation time 71835867260 ps
CPU time 1468.01 seconds
Started Mar 21 03:28:37 PM PDT 24
Finished Mar 21 03:53:05 PM PDT 24
Peak memory 365456 kb
Host smart-ed203697-5c6a-4b6d-9180-7f2ec0c7da87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743896298 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all_with_rand_reset.2743896298
Directory /workspace/34.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/141.otp_ctrl_parallel_lc_esc.1180869188
Short name T164
Test name
Test status
Simulation time 1195103224 ps
CPU time 20.02 seconds
Started Mar 21 03:30:19 PM PDT 24
Finished Mar 21 03:30:40 PM PDT 24
Peak memory 241320 kb
Host smart-998e83bc-927d-47c1-a37c-8cace32362e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180869188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.1180869188
Directory /workspace/141.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/22.otp_ctrl_check_fail.3199938750
Short name T56
Test name
Test status
Simulation time 10615560273 ps
CPU time 31.9 seconds
Started Mar 21 03:28:04 PM PDT 24
Finished Mar 21 03:28:36 PM PDT 24
Peak memory 244624 kb
Host smart-ba509633-ad7d-4342-a45f-99fb90a76fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199938750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.3199938750
Directory /workspace/22.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_stress_all.2542025617
Short name T151
Test name
Test status
Simulation time 1538553871 ps
CPU time 61.85 seconds
Started Mar 21 03:27:42 PM PDT 24
Finished Mar 21 03:28:44 PM PDT 24
Peak memory 244332 kb
Host smart-32d29988-7b06-4025-b9ad-5811bdd7babc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542025617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all
.2542025617
Directory /workspace/15.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/104.otp_ctrl_parallel_lc_esc.3298690209
Short name T263
Test name
Test status
Simulation time 605781239 ps
CPU time 8.35 seconds
Started Mar 21 03:30:01 PM PDT 24
Finished Mar 21 03:30:09 PM PDT 24
Peak memory 241480 kb
Host smart-a4263e24-f22c-4cff-b415-92603a21fbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298690209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.3298690209
Directory /workspace/104.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_esc.3021855339
Short name T884
Test name
Test status
Simulation time 1004469234 ps
CPU time 13.2 seconds
Started Mar 21 03:27:31 PM PDT 24
Finished Mar 21 03:27:44 PM PDT 24
Peak memory 241200 kb
Host smart-8ef918ba-eae6-4100-ada0-ec852ab3391d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021855339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.3021855339
Directory /workspace/12.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/167.otp_ctrl_parallel_lc_esc.1150018909
Short name T71
Test name
Test status
Simulation time 4481072990 ps
CPU time 12.66 seconds
Started Mar 21 03:30:30 PM PDT 24
Finished Mar 21 03:30:43 PM PDT 24
Peak memory 241800 kb
Host smart-6f8e7c99-cfbf-4a50-92ab-cfdeb750a140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150018909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.1150018909
Directory /workspace/167.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/193.otp_ctrl_parallel_lc_esc.721057990
Short name T213
Test name
Test status
Simulation time 894742633 ps
CPU time 7.69 seconds
Started Mar 21 03:30:54 PM PDT 24
Finished Mar 21 03:31:02 PM PDT 24
Peak memory 241344 kb
Host smart-10c506b8-9cdd-46e8-9638-eab2aef0fb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721057990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.721057990
Directory /workspace/193.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/202.otp_ctrl_init_fail.1928835106
Short name T41
Test name
Test status
Simulation time 3293590854 ps
CPU time 7.78 seconds
Started Mar 21 03:30:46 PM PDT 24
Finished Mar 21 03:30:53 PM PDT 24
Peak memory 241836 kb
Host smart-0e8a294d-8ee7-4d2b-ba8e-52e163f80db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928835106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.1928835106
Directory /workspace/202.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_macro_errs.1986752898
Short name T998
Test name
Test status
Simulation time 3730294757 ps
CPU time 49.53 seconds
Started Mar 21 03:28:13 PM PDT 24
Finished Mar 21 03:29:03 PM PDT 24
Peak memory 256860 kb
Host smart-1d2f727d-4443-4241-85f7-41273abca580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986752898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.1986752898
Directory /workspace/26.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all.2042434476
Short name T119
Test name
Test status
Simulation time 55324023980 ps
CPU time 199.22 seconds
Started Mar 21 03:28:21 PM PDT 24
Finished Mar 21 03:31:41 PM PDT 24
Peak memory 261568 kb
Host smart-3c7b2ed0-fd53-4c42-9d2d-3d2249034890
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042434476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all
.2042434476
Directory /workspace/29.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/86.otp_ctrl_stress_all_with_rand_reset.1026213905
Short name T76
Test name
Test status
Simulation time 58055762995 ps
CPU time 924.13 seconds
Started Mar 21 03:29:58 PM PDT 24
Finished Mar 21 03:45:22 PM PDT 24
Peak memory 378256 kb
Host smart-47950729-afc7-4b35-8833-4031db09d955
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026213905 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_stress_all_with_rand_reset.1026213905
Directory /workspace/86.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.otp_ctrl_parallel_lc_esc.937134271
Short name T437
Test name
Test status
Simulation time 2600938862 ps
CPU time 9.34 seconds
Started Mar 21 03:29:42 PM PDT 24
Finished Mar 21 03:29:52 PM PDT 24
Peak memory 241684 kb
Host smart-561ad5e0-eb42-46e2-84a0-bdb9008e1491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937134271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.937134271
Directory /workspace/80.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.2693201647
Short name T314
Test name
Test status
Simulation time 564997984 ps
CPU time 1.86 seconds
Started Mar 21 02:32:30 PM PDT 24
Finished Mar 21 02:32:32 PM PDT 24
Peak memory 240660 kb
Host smart-f777ce5e-555d-46a8-a10e-c2b6aff5434f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693201647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.2693201647
Directory /workspace/1.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_req.2567810581
Short name T244
Test name
Test status
Simulation time 1200294516 ps
CPU time 20.64 seconds
Started Mar 21 03:28:21 PM PDT 24
Finished Mar 21 03:28:43 PM PDT 24
Peak memory 241612 kb
Host smart-227d6dac-17f1-4b72-9883-e87ce19bd37b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2567810581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.2567810581
Directory /workspace/29.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_check_fail.4075766362
Short name T85
Test name
Test status
Simulation time 2750568988 ps
CPU time 23.66 seconds
Started Mar 21 03:28:18 PM PDT 24
Finished Mar 21 03:28:42 PM PDT 24
Peak memory 243976 kb
Host smart-fe2a9f15-99fb-482e-ab67-5b374ffa6cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075766362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.4075766362
Directory /workspace/28.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_init_fail.1221927034
Short name T113
Test name
Test status
Simulation time 581032507 ps
CPU time 4.58 seconds
Started Mar 21 03:29:04 PM PDT 24
Finished Mar 21 03:29:08 PM PDT 24
Peak memory 241612 kb
Host smart-4c2a16c3-6150-4e0e-b158-af4a19050dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221927034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.1221927034
Directory /workspace/45.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_check_fail.3866845331
Short name T64
Test name
Test status
Simulation time 1450695269 ps
CPU time 9.77 seconds
Started Mar 21 03:27:27 PM PDT 24
Finished Mar 21 03:27:37 PM PDT 24
Peak memory 241344 kb
Host smart-c8d96ff1-6aaf-4cf6-897a-1f596788e120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866845331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.3866845331
Directory /workspace/12.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_check_fail.3989568948
Short name T43
Test name
Test status
Simulation time 2732848300 ps
CPU time 23.18 seconds
Started Mar 21 03:28:36 PM PDT 24
Finished Mar 21 03:29:00 PM PDT 24
Peak memory 248364 kb
Host smart-21532b0e-0e21-4fd7-8893-a69adc11471c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989568948 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.3989568948
Directory /workspace/34.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_regwen.606062235
Short name T272
Test name
Test status
Simulation time 912614033 ps
CPU time 7.87 seconds
Started Mar 21 03:27:40 PM PDT 24
Finished Mar 21 03:27:48 PM PDT 24
Peak memory 241292 kb
Host smart-30fab951-88ba-4629-9384-93c74b99ed45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=606062235 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.606062235
Directory /workspace/15.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/25.otp_ctrl_regwen.1685292614
Short name T386
Test name
Test status
Simulation time 581974922 ps
CPU time 6.25 seconds
Started Mar 21 03:28:11 PM PDT 24
Finished Mar 21 03:28:18 PM PDT 24
Peak memory 241448 kb
Host smart-ef87147b-5976-4e00-8efd-516c7171a77a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1685292614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.1685292614
Directory /workspace/25.otp_ctrl_regwen/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.2337391079
Short name T282
Test name
Test status
Simulation time 376928101 ps
CPU time 3.42 seconds
Started Mar 21 02:32:29 PM PDT 24
Finished Mar 21 02:32:32 PM PDT 24
Peak memory 238616 kb
Host smart-9cc6d65d-b2eb-42f1-b861-e3eecc98111a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337391079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_c
trl_same_csr_outstanding.2337391079
Directory /workspace/1.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/38.otp_ctrl_init_fail.88374267
Short name T90
Test name
Test status
Simulation time 659238325 ps
CPU time 5.17 seconds
Started Mar 21 03:28:49 PM PDT 24
Finished Mar 21 03:28:54 PM PDT 24
Peak memory 241640 kb
Host smart-9dc1cb49-1e26-49f2-aa20-971facc89071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88374267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.88374267
Directory /workspace/38.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/271.otp_ctrl_init_fail.1885714613
Short name T80
Test name
Test status
Simulation time 252379649 ps
CPU time 4.88 seconds
Started Mar 21 03:31:03 PM PDT 24
Finished Mar 21 03:31:08 PM PDT 24
Peak memory 241668 kb
Host smart-7b7698fb-8e00-4212-9425-094ed20443c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885714613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.1885714613
Directory /workspace/271.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all.667230146
Short name T251
Test name
Test status
Simulation time 30204245498 ps
CPU time 95.1 seconds
Started Mar 21 03:29:07 PM PDT 24
Finished Mar 21 03:30:43 PM PDT 24
Peak memory 248412 kb
Host smart-1f38c298-4400-4270-88f2-589494ee9831
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667230146 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all.
667230146
Directory /workspace/44.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_errs.3742281504
Short name T915
Test name
Test status
Simulation time 517075077 ps
CPU time 17.13 seconds
Started Mar 21 03:28:09 PM PDT 24
Finished Mar 21 03:28:26 PM PDT 24
Peak memory 241408 kb
Host smart-c8138426-ac4a-4df4-8729-5ad0132ca9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742281504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.3742281504
Directory /workspace/28.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_check_fail.3706049103
Short name T851
Test name
Test status
Simulation time 1916069931 ps
CPU time 23.01 seconds
Started Mar 21 03:27:59 PM PDT 24
Finished Mar 21 03:28:22 PM PDT 24
Peak memory 242884 kb
Host smart-b2ba2b16-0e99-4ea7-b899-9e48d029fd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706049103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.3706049103
Directory /workspace/20.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_init_fail.751839341
Short name T239
Test name
Test status
Simulation time 159657250 ps
CPU time 4.2 seconds
Started Mar 21 03:26:57 PM PDT 24
Finished Mar 21 03:27:01 PM PDT 24
Peak memory 241804 kb
Host smart-7cd6ecf0-3bd3-4d61-af03-a6e57500fd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751839341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.751839341
Directory /workspace/0.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.2499566978
Short name T373
Test name
Test status
Simulation time 1338569197 ps
CPU time 19.35 seconds
Started Mar 21 02:33:13 PM PDT 24
Finished Mar 21 02:33:32 PM PDT 24
Peak memory 238640 kb
Host smart-5ee7887b-ac18-4a02-847b-e3795792e69c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499566978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_i
ntg_err.2499566978
Directory /workspace/10.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.otp_ctrl_regwen.90574717
Short name T860
Test name
Test status
Simulation time 646030438 ps
CPU time 7.36 seconds
Started Mar 21 03:26:58 PM PDT 24
Finished Mar 21 03:27:06 PM PDT 24
Peak memory 241268 kb
Host smart-c137d116-a557-4418-8442-baa3d73e0185
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=90574717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.90574717
Directory /workspace/1.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all_with_rand_reset.3588529270
Short name T23
Test name
Test status
Simulation time 148507131043 ps
CPU time 1216.56 seconds
Started Mar 21 03:28:08 PM PDT 24
Finished Mar 21 03:48:25 PM PDT 24
Peak memory 256720 kb
Host smart-73ec73e1-647b-4842-8227-c97757be7e4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588529270 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all_with_rand_reset.3588529270
Directory /workspace/25.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.745620778
Short name T294
Test name
Test status
Simulation time 94892907898 ps
CPU time 2413.64 seconds
Started Mar 21 03:30:03 PM PDT 24
Finished Mar 21 04:10:17 PM PDT 24
Peak memory 309732 kb
Host smart-1b5ed713-e0db-4e6a-9a41-1a96d0f5fd4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745620778 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_stress_all_with_rand_reset.745620778
Directory /workspace/98.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.otp_ctrl_test_access.1717549312
Short name T92
Test name
Test status
Simulation time 7816443781 ps
CPU time 16.02 seconds
Started Mar 21 03:28:34 PM PDT 24
Finished Mar 21 03:28:51 PM PDT 24
Peak memory 241496 kb
Host smart-9d6b9247-477d-4e0a-8206-d2a5afef0b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717549312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.1717549312
Directory /workspace/33.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_req.4175326065
Short name T257
Test name
Test status
Simulation time 828028736 ps
CPU time 20.81 seconds
Started Mar 21 03:27:47 PM PDT 24
Finished Mar 21 03:28:08 PM PDT 24
Peak memory 248084 kb
Host smart-6cb31a32-7d10-4f90-b735-b190275ab51f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4175326065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.4175326065
Directory /workspace/17.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/255.otp_ctrl_init_fail.2930847938
Short name T84
Test name
Test status
Simulation time 291272288 ps
CPU time 3.74 seconds
Started Mar 21 03:31:06 PM PDT 24
Finished Mar 21 03:31:10 PM PDT 24
Peak memory 241300 kb
Host smart-12e47849-0aeb-4a1a-86e3-ae0a524d6407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930847938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.2930847938
Directory /workspace/255.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/100.otp_ctrl_init_fail.2908252634
Short name T89
Test name
Test status
Simulation time 154777134 ps
CPU time 4.27 seconds
Started Mar 21 03:30:04 PM PDT 24
Finished Mar 21 03:30:09 PM PDT 24
Peak memory 241704 kb
Host smart-3d3d7190-68d3-4467-90ff-b17569b01183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908252634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.2908252634
Directory /workspace/100.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all.3746834261
Short name T160
Test name
Test status
Simulation time 99328181463 ps
CPU time 260.54 seconds
Started Mar 21 03:26:57 PM PDT 24
Finished Mar 21 03:31:18 PM PDT 24
Peak memory 256512 kb
Host smart-9432b7ae-ab93-4364-b9d7-e95423bed183
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746834261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all.
3746834261
Directory /workspace/3.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/182.otp_ctrl_init_fail.3622542599
Short name T87
Test name
Test status
Simulation time 360401635 ps
CPU time 3.96 seconds
Started Mar 21 03:30:47 PM PDT 24
Finished Mar 21 03:30:52 PM PDT 24
Peak memory 241384 kb
Host smart-826b6ba6-467a-4dde-b6dc-dab9f90598ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622542599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.3622542599
Directory /workspace/182.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all.3368038164
Short name T245
Test name
Test status
Simulation time 32617361955 ps
CPU time 126.07 seconds
Started Mar 21 03:28:04 PM PDT 24
Finished Mar 21 03:30:10 PM PDT 24
Peak memory 264464 kb
Host smart-fafe54dc-2401-4cfc-946b-71698bc598ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368038164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all
.3368038164
Directory /workspace/20.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/147.otp_ctrl_parallel_lc_esc.1979692852
Short name T215
Test name
Test status
Simulation time 244529001 ps
CPU time 11.28 seconds
Started Mar 21 03:30:16 PM PDT 24
Finished Mar 21 03:30:28 PM PDT 24
Peak memory 241256 kb
Host smart-16b9344b-3e8e-4bf2-8d77-8c0c51babeed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979692852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.1979692852
Directory /workspace/147.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/234.otp_ctrl_init_fail.1369458032
Short name T29
Test name
Test status
Simulation time 278166838 ps
CPU time 4.38 seconds
Started Mar 21 03:31:09 PM PDT 24
Finished Mar 21 03:31:14 PM PDT 24
Peak memory 241660 kb
Host smart-325dde64-8324-4dd1-beb0-bf539b8918a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369458032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.1369458032
Directory /workspace/234.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/256.otp_ctrl_init_fail.3525493699
Short name T88
Test name
Test status
Simulation time 422771110 ps
CPU time 4.14 seconds
Started Mar 21 03:31:05 PM PDT 24
Finished Mar 21 03:31:09 PM PDT 24
Peak memory 241616 kb
Host smart-05208ddf-dd3f-4b3a-9df5-e001790f7cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525493699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.3525493699
Directory /workspace/256.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_test_access.875617933
Short name T1186
Test name
Test status
Simulation time 264016247 ps
CPU time 6.74 seconds
Started Mar 21 03:29:05 PM PDT 24
Finished Mar 21 03:29:12 PM PDT 24
Peak memory 241364 kb
Host smart-716faa6a-72b0-4216-bd34-33ae88b912aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875617933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.875617933
Directory /workspace/43.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/169.otp_ctrl_init_fail.2012353165
Short name T1182
Test name
Test status
Simulation time 381124908 ps
CPU time 4.97 seconds
Started Mar 21 03:30:28 PM PDT 24
Finished Mar 21 03:30:33 PM PDT 24
Peak memory 241424 kb
Host smart-ae0ee495-373f-4b5b-884c-316b0b4d9185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012353165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.2012353165
Directory /workspace/169.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all.4209923678
Short name T350
Test name
Test status
Simulation time 16702597021 ps
CPU time 115.77 seconds
Started Mar 21 03:26:58 PM PDT 24
Finished Mar 21 03:28:54 PM PDT 24
Peak memory 244612 kb
Host smart-14ee971b-e393-4900-9983-c53cb11f9ed4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209923678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all.
4209923678
Directory /workspace/0.otp_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.1949125936
Short name T1316
Test name
Test status
Simulation time 747530830 ps
CPU time 6.86 seconds
Started Mar 21 02:32:26 PM PDT 24
Finished Mar 21 02:32:33 PM PDT 24
Peak memory 238620 kb
Host smart-3b4c9f7c-c0dd-415a-8d6d-f7262ee99689
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949125936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_alia
sing.1949125936
Directory /workspace/0.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.1596433197
Short name T309
Test name
Test status
Simulation time 496235095 ps
CPU time 7.57 seconds
Started Mar 21 02:32:30 PM PDT 24
Finished Mar 21 02:32:38 PM PDT 24
Peak memory 238688 kb
Host smart-b52d3e9e-9f95-4e03-b0d1-66bbd1f72bc7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596433197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_
bash.1596433197
Directory /workspace/0.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.887893250
Short name T1226
Test name
Test status
Simulation time 102523946 ps
CPU time 2.42 seconds
Started Mar 21 02:32:25 PM PDT 24
Finished Mar 21 02:32:28 PM PDT 24
Peak memory 240676 kb
Host smart-f7133b28-2c35-41c3-a722-9f6238a0fa0e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887893250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_re
set.887893250
Directory /workspace/0.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.1192564626
Short name T1323
Test name
Test status
Simulation time 1673954287 ps
CPU time 4.15 seconds
Started Mar 21 02:32:27 PM PDT 24
Finished Mar 21 02:32:31 PM PDT 24
Peak memory 246920 kb
Host smart-bb1aa882-6457-4995-a26a-aa3537729bbd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192564626 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.otp_ctrl_csr_mem_rw_with_rand_reset.1192564626
Directory /workspace/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.1051116965
Short name T1302
Test name
Test status
Simulation time 82783215 ps
CPU time 1.79 seconds
Started Mar 21 02:32:25 PM PDT 24
Finished Mar 21 02:32:27 PM PDT 24
Peak memory 241016 kb
Host smart-86e60d45-96b8-4e29-8785-00511b64ee16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051116965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.1051116965
Directory /workspace/0.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.2005099132
Short name T1246
Test name
Test status
Simulation time 64574555 ps
CPU time 1.42 seconds
Started Mar 21 02:32:12 PM PDT 24
Finished Mar 21 02:32:13 PM PDT 24
Peak memory 230476 kb
Host smart-aca7ed05-4c30-499d-b87e-8b65e5cd0fac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005099132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.2005099132
Directory /workspace/0.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.2213915866
Short name T1306
Test name
Test status
Simulation time 38169277 ps
CPU time 1.39 seconds
Started Mar 21 02:32:29 PM PDT 24
Finished Mar 21 02:32:31 PM PDT 24
Peak memory 230280 kb
Host smart-d6034824-d1de-46c7-8d1a-e13b27f23a6f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213915866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctr
l_mem_partial_access.2213915866
Directory /workspace/0.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.3681966210
Short name T1264
Test name
Test status
Simulation time 76624643 ps
CPU time 1.36 seconds
Started Mar 21 02:32:27 PM PDT 24
Finished Mar 21 02:32:28 PM PDT 24
Peak memory 229336 kb
Host smart-039c9d37-49fd-47f8-a251-9a13277cebee
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681966210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk
.3681966210
Directory /workspace/0.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.1142966862
Short name T1292
Test name
Test status
Simulation time 52910711 ps
CPU time 1.92 seconds
Started Mar 21 02:32:27 PM PDT 24
Finished Mar 21 02:32:29 PM PDT 24
Peak memory 238676 kb
Host smart-3d6f2568-30b1-422a-8539-fd118cc2320d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142966862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_c
trl_same_csr_outstanding.1142966862
Directory /workspace/0.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.1115577908
Short name T1231
Test name
Test status
Simulation time 332979640 ps
CPU time 4.51 seconds
Started Mar 21 02:32:12 PM PDT 24
Finished Mar 21 02:32:17 PM PDT 24
Peak memory 245516 kb
Host smart-1fc80736-b812-4312-8edf-c61ca91c6ecf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115577908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.1115577908
Directory /workspace/0.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.864862734
Short name T1220
Test name
Test status
Simulation time 1327021246 ps
CPU time 12.31 seconds
Started Mar 21 02:32:12 PM PDT 24
Finished Mar 21 02:32:25 PM PDT 24
Peak memory 243172 kb
Host smart-7d8dd713-dcf1-4770-85bc-d9c61b01c7f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864862734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_int
g_err.864862734
Directory /workspace/0.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.2187614541
Short name T1222
Test name
Test status
Simulation time 908722501 ps
CPU time 3.57 seconds
Started Mar 21 02:32:27 PM PDT 24
Finished Mar 21 02:32:31 PM PDT 24
Peak memory 238616 kb
Host smart-ee7e9271-9e87-4273-be27-73cbaa1312ae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187614541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_alia
sing.2187614541
Directory /workspace/1.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.476304352
Short name T343
Test name
Test status
Simulation time 429164457 ps
CPU time 5.47 seconds
Started Mar 21 02:32:28 PM PDT 24
Finished Mar 21 02:32:34 PM PDT 24
Peak memory 238628 kb
Host smart-4b55e66a-21e1-4628-8e64-8fb16ce4ef07
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476304352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_b
ash.476304352
Directory /workspace/1.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.1399050583
Short name T1219
Test name
Test status
Simulation time 186942278 ps
CPU time 2.44 seconds
Started Mar 21 02:32:29 PM PDT 24
Finished Mar 21 02:32:31 PM PDT 24
Peak memory 238608 kb
Host smart-4ba0965c-8916-4143-a649-7346e49e4810
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399050583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_r
eset.1399050583
Directory /workspace/1.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.1016120547
Short name T1287
Test name
Test status
Simulation time 97128187 ps
CPU time 2.93 seconds
Started Mar 21 02:32:30 PM PDT 24
Finished Mar 21 02:32:34 PM PDT 24
Peak memory 246228 kb
Host smart-6e48918a-5bd6-455e-9180-24b78ae3a8f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016120547 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.otp_ctrl_csr_mem_rw_with_rand_reset.1016120547
Directory /workspace/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.3762891572
Short name T1223
Test name
Test status
Simulation time 146296886 ps
CPU time 1.54 seconds
Started Mar 21 02:32:25 PM PDT 24
Finished Mar 21 02:32:27 PM PDT 24
Peak memory 229572 kb
Host smart-2d0bfaf3-ea54-4f5b-b408-fdbb11749dc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762891572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.3762891572
Directory /workspace/1.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.3481006620
Short name T1245
Test name
Test status
Simulation time 68836121 ps
CPU time 1.36 seconds
Started Mar 21 02:32:28 PM PDT 24
Finished Mar 21 02:32:29 PM PDT 24
Peak memory 229316 kb
Host smart-66b354b5-74c3-4d2b-8956-64536e5f600d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481006620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctr
l_mem_partial_access.3481006620
Directory /workspace/1.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.1196933301
Short name T1254
Test name
Test status
Simulation time 39831898 ps
CPU time 1.36 seconds
Started Mar 21 02:32:28 PM PDT 24
Finished Mar 21 02:32:29 PM PDT 24
Peak memory 230464 kb
Host smart-e46fd1ee-518f-489d-8bab-d20ef3ea9913
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196933301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk
.1196933301
Directory /workspace/1.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.84951599
Short name T1227
Test name
Test status
Simulation time 178400296 ps
CPU time 2.91 seconds
Started Mar 21 02:32:27 PM PDT 24
Finished Mar 21 02:32:30 PM PDT 24
Peak memory 238752 kb
Host smart-ade877bc-7482-4f6c-add9-c985b53546bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84951599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.84951599
Directory /workspace/1.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.1747567507
Short name T1301
Test name
Test status
Simulation time 2446033775 ps
CPU time 11.95 seconds
Started Mar 21 02:32:29 PM PDT 24
Finished Mar 21 02:32:41 PM PDT 24
Peak memory 243200 kb
Host smart-85370e95-c46e-4052-a1d6-232304943e4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747567507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_in
tg_err.1747567507
Directory /workspace/1.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.1892941835
Short name T389
Test name
Test status
Simulation time 98879609 ps
CPU time 3.11 seconds
Started Mar 21 02:33:26 PM PDT 24
Finished Mar 21 02:33:32 PM PDT 24
Peak memory 246876 kb
Host smart-60b20e6f-0395-4480-9076-5d9a2f43be5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892941835 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.otp_ctrl_csr_mem_rw_with_rand_reset.1892941835
Directory /workspace/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.1369542351
Short name T312
Test name
Test status
Simulation time 99495316 ps
CPU time 1.71 seconds
Started Mar 21 02:33:13 PM PDT 24
Finished Mar 21 02:33:16 PM PDT 24
Peak memory 240652 kb
Host smart-a0aac213-2f69-4073-80aa-9ca7ff86979e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369542351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.1369542351
Directory /workspace/10.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.4186694232
Short name T1291
Test name
Test status
Simulation time 41849704 ps
CPU time 1.41 seconds
Started Mar 21 02:33:22 PM PDT 24
Finished Mar 21 02:33:23 PM PDT 24
Peak memory 229588 kb
Host smart-773ffd63-7f7a-4b64-8bdb-3a5e3ada2c5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186694232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.4186694232
Directory /workspace/10.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.2482131995
Short name T333
Test name
Test status
Simulation time 156507751 ps
CPU time 2.01 seconds
Started Mar 21 02:33:24 PM PDT 24
Finished Mar 21 02:33:26 PM PDT 24
Peak memory 238576 kb
Host smart-426e0e29-7d05-42d7-b72b-d4b6dd651a74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482131995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_
ctrl_same_csr_outstanding.2482131995
Directory /workspace/10.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.2008256232
Short name T1315
Test name
Test status
Simulation time 1268198227 ps
CPU time 4.76 seconds
Started Mar 21 02:33:12 PM PDT 24
Finished Mar 21 02:33:17 PM PDT 24
Peak memory 238772 kb
Host smart-be1337d3-62ec-45ae-9dc3-fdf9cd437ad9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008256232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.2008256232
Directory /workspace/10.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.2396053682
Short name T1233
Test name
Test status
Simulation time 249417765 ps
CPU time 3.03 seconds
Started Mar 21 02:33:13 PM PDT 24
Finished Mar 21 02:33:16 PM PDT 24
Peak memory 246888 kb
Host smart-64d165ec-7932-42ae-b82f-cf71c727fbcd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396053682 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.otp_ctrl_csr_mem_rw_with_rand_reset.2396053682
Directory /workspace/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.272775272
Short name T315
Test name
Test status
Simulation time 170103741 ps
CPU time 1.85 seconds
Started Mar 21 02:33:25 PM PDT 24
Finished Mar 21 02:33:27 PM PDT 24
Peak memory 240340 kb
Host smart-53a27bab-d05f-4b36-818a-da3cd6c5aa62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272775272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.272775272
Directory /workspace/11.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.2011686486
Short name T1310
Test name
Test status
Simulation time 76658721 ps
CPU time 1.53 seconds
Started Mar 21 02:33:24 PM PDT 24
Finished Mar 21 02:33:26 PM PDT 24
Peak memory 229572 kb
Host smart-a2ed8bb8-56da-49ca-b5b2-325cb6d27245
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011686486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.2011686486
Directory /workspace/11.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.2483849425
Short name T331
Test name
Test status
Simulation time 54905357 ps
CPU time 2.38 seconds
Started Mar 21 02:33:23 PM PDT 24
Finished Mar 21 02:33:25 PM PDT 24
Peak memory 238624 kb
Host smart-351fd629-1b92-4f83-9c2d-46ac7572804b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483849425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_
ctrl_same_csr_outstanding.2483849425
Directory /workspace/11.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.2818104031
Short name T1210
Test name
Test status
Simulation time 97316493 ps
CPU time 4.49 seconds
Started Mar 21 02:33:14 PM PDT 24
Finished Mar 21 02:33:19 PM PDT 24
Peak memory 245752 kb
Host smart-87842550-2fbe-48eb-a660-6afb7e12ab10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818104031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.2818104031
Directory /workspace/11.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.3590226634
Short name T1267
Test name
Test status
Simulation time 1061270861 ps
CPU time 3.29 seconds
Started Mar 21 02:33:27 PM PDT 24
Finished Mar 21 02:33:32 PM PDT 24
Peak memory 243408 kb
Host smart-49c10680-d0fe-4c7d-ba06-f92580ed5c88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590226634 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.otp_ctrl_csr_mem_rw_with_rand_reset.3590226634
Directory /workspace/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.3021665921
Short name T310
Test name
Test status
Simulation time 556181364 ps
CPU time 1.71 seconds
Started Mar 21 02:33:23 PM PDT 24
Finished Mar 21 02:33:25 PM PDT 24
Peak memory 238604 kb
Host smart-2b1b888d-e784-4b53-beeb-4a97160a48da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021665921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.3021665921
Directory /workspace/12.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.132743009
Short name T1304
Test name
Test status
Simulation time 559999221 ps
CPU time 1.91 seconds
Started Mar 21 02:33:12 PM PDT 24
Finished Mar 21 02:33:14 PM PDT 24
Peak memory 229880 kb
Host smart-4bd0315a-7c59-4539-94ae-46f79175e444
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132743009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.132743009
Directory /workspace/12.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.3683401977
Short name T338
Test name
Test status
Simulation time 73375137 ps
CPU time 2.46 seconds
Started Mar 21 02:33:13 PM PDT 24
Finished Mar 21 02:33:15 PM PDT 24
Peak memory 241428 kb
Host smart-8cb6e0f9-1d7e-41d1-84ed-856198eef310
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683401977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_
ctrl_same_csr_outstanding.3683401977
Directory /workspace/12.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.1006602401
Short name T1290
Test name
Test status
Simulation time 103246550 ps
CPU time 4.29 seconds
Started Mar 21 02:33:13 PM PDT 24
Finished Mar 21 02:33:17 PM PDT 24
Peak memory 238708 kb
Host smart-e68cde18-1d8c-47eb-a73f-532692be513d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006602401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.1006602401
Directory /workspace/12.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.2564936725
Short name T1326
Test name
Test status
Simulation time 3725485042 ps
CPU time 22.83 seconds
Started Mar 21 02:33:22 PM PDT 24
Finished Mar 21 02:33:45 PM PDT 24
Peak memory 238772 kb
Host smart-53e9e41f-1dc1-4512-9576-387843f444ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564936725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_i
ntg_err.2564936725
Directory /workspace/12.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.3759699010
Short name T1209
Test name
Test status
Simulation time 102262990 ps
CPU time 2.55 seconds
Started Mar 21 02:33:27 PM PDT 24
Finished Mar 21 02:33:31 PM PDT 24
Peak memory 245892 kb
Host smart-8ce7ee3f-5b13-44dd-9844-c3c1aef9ec0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759699010 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.otp_ctrl_csr_mem_rw_with_rand_reset.3759699010
Directory /workspace/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.2450538861
Short name T1324
Test name
Test status
Simulation time 154154710 ps
CPU time 1.96 seconds
Started Mar 21 02:33:30 PM PDT 24
Finished Mar 21 02:33:32 PM PDT 24
Peak memory 238616 kb
Host smart-7063e66f-5ad8-4b0f-97b8-b18ae760addc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450538861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.2450538861
Directory /workspace/13.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.3705130508
Short name T1263
Test name
Test status
Simulation time 139373759 ps
CPU time 1.47 seconds
Started Mar 21 02:33:27 PM PDT 24
Finished Mar 21 02:33:30 PM PDT 24
Peak memory 230444 kb
Host smart-c6a78ad0-56da-4b9d-a3de-6ff8eb4d7b33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705130508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.3705130508
Directory /workspace/13.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.1688117675
Short name T339
Test name
Test status
Simulation time 177845977 ps
CPU time 1.95 seconds
Started Mar 21 02:33:28 PM PDT 24
Finished Mar 21 02:33:31 PM PDT 24
Peak memory 241468 kb
Host smart-3e772007-5e00-4ae2-ad06-905fa75b252a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688117675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_
ctrl_same_csr_outstanding.1688117675
Directory /workspace/13.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.3326698103
Short name T1259
Test name
Test status
Simulation time 60702734 ps
CPU time 3.83 seconds
Started Mar 21 02:33:29 PM PDT 24
Finished Mar 21 02:33:34 PM PDT 24
Peak memory 245504 kb
Host smart-23ff8792-f2fb-4248-a2a5-209e30a88325
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326698103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.3326698103
Directory /workspace/13.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.379319819
Short name T372
Test name
Test status
Simulation time 2470840451 ps
CPU time 21.14 seconds
Started Mar 21 02:33:27 PM PDT 24
Finished Mar 21 02:33:50 PM PDT 24
Peak memory 243828 kb
Host smart-e4591548-89f3-4e15-ad48-0c3ecee21841
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379319819 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_in
tg_err.379319819
Directory /workspace/13.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.799825088
Short name T1236
Test name
Test status
Simulation time 121379450 ps
CPU time 2.91 seconds
Started Mar 21 02:33:30 PM PDT 24
Finished Mar 21 02:33:34 PM PDT 24
Peak memory 246896 kb
Host smart-6745fae1-bf11-48e8-9614-559a37a8dc08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799825088 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.otp_ctrl_csr_mem_rw_with_rand_reset.799825088
Directory /workspace/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.1333385452
Short name T1329
Test name
Test status
Simulation time 159688024 ps
CPU time 1.72 seconds
Started Mar 21 02:33:28 PM PDT 24
Finished Mar 21 02:33:31 PM PDT 24
Peak memory 240688 kb
Host smart-42995a4c-56f1-42aa-9605-25bd40d10d9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333385452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.1333385452
Directory /workspace/14.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.1487575191
Short name T1212
Test name
Test status
Simulation time 57152629 ps
CPU time 1.44 seconds
Started Mar 21 02:33:28 PM PDT 24
Finished Mar 21 02:33:31 PM PDT 24
Peak memory 229832 kb
Host smart-25267643-fff3-4d8a-b432-449eba958f3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487575191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.1487575191
Directory /workspace/14.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.1151494754
Short name T1295
Test name
Test status
Simulation time 133898078 ps
CPU time 2.29 seconds
Started Mar 21 02:33:28 PM PDT 24
Finished Mar 21 02:33:31 PM PDT 24
Peak memory 241524 kb
Host smart-168f7cb4-71d2-47ed-a99f-5aa9014ed052
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151494754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_
ctrl_same_csr_outstanding.1151494754
Directory /workspace/14.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.3124159878
Short name T1238
Test name
Test status
Simulation time 97696841 ps
CPU time 5.03 seconds
Started Mar 21 02:33:29 PM PDT 24
Finished Mar 21 02:33:34 PM PDT 24
Peak memory 245664 kb
Host smart-21a62de0-3114-40bc-a3c7-e4b7ac475952
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124159878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.3124159878
Directory /workspace/14.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.1007512957
Short name T375
Test name
Test status
Simulation time 4774578716 ps
CPU time 22.72 seconds
Started Mar 21 02:33:28 PM PDT 24
Finished Mar 21 02:33:52 PM PDT 24
Peak memory 244088 kb
Host smart-528ee8c2-6899-4b9d-91bc-3f95ce01a7c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007512957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_i
ntg_err.1007512957
Directory /workspace/14.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.4270510925
Short name T1228
Test name
Test status
Simulation time 67686808 ps
CPU time 2.06 seconds
Started Mar 21 02:33:30 PM PDT 24
Finished Mar 21 02:33:32 PM PDT 24
Peak memory 238740 kb
Host smart-b3d9ecff-f737-494a-82ef-b635d5f752ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270510925 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.otp_ctrl_csr_mem_rw_with_rand_reset.4270510925
Directory /workspace/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.4237673380
Short name T283
Test name
Test status
Simulation time 40698217 ps
CPU time 1.56 seconds
Started Mar 21 02:33:27 PM PDT 24
Finished Mar 21 02:33:30 PM PDT 24
Peak memory 240276 kb
Host smart-668a08ad-f570-42a6-a4b1-d0d04ad9751b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237673380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.4237673380
Directory /workspace/15.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.3685553843
Short name T1266
Test name
Test status
Simulation time 60656186 ps
CPU time 1.39 seconds
Started Mar 21 02:33:27 PM PDT 24
Finished Mar 21 02:33:30 PM PDT 24
Peak memory 229624 kb
Host smart-14120b94-042d-4bbc-a001-fe4cefae92c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685553843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.3685553843
Directory /workspace/15.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.3858227866
Short name T1318
Test name
Test status
Simulation time 175939154 ps
CPU time 2.16 seconds
Started Mar 21 02:33:33 PM PDT 24
Finished Mar 21 02:33:36 PM PDT 24
Peak memory 238688 kb
Host smart-f71e25d9-b483-4bf2-823e-489f2ff2d446
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858227866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_
ctrl_same_csr_outstanding.3858227866
Directory /workspace/15.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.1410788115
Short name T1253
Test name
Test status
Simulation time 138035807 ps
CPU time 5.43 seconds
Started Mar 21 02:33:30 PM PDT 24
Finished Mar 21 02:33:36 PM PDT 24
Peak memory 238812 kb
Host smart-614e2d11-91db-499e-88bc-fcadea6dcf93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410788115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.1410788115
Directory /workspace/15.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.2703471371
Short name T281
Test name
Test status
Simulation time 2416136592 ps
CPU time 18.37 seconds
Started Mar 21 02:33:30 PM PDT 24
Finished Mar 21 02:33:49 PM PDT 24
Peak memory 243940 kb
Host smart-7bcb07ca-64af-4b7f-81e3-0ff5c916abbd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703471371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_i
ntg_err.2703471371
Directory /workspace/15.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.471670503
Short name T1277
Test name
Test status
Simulation time 137631697 ps
CPU time 2.2 seconds
Started Mar 21 02:33:31 PM PDT 24
Finished Mar 21 02:33:34 PM PDT 24
Peak memory 238716 kb
Host smart-97e611ea-bff6-4d23-a523-245cbd342942
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471670503 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.otp_ctrl_csr_mem_rw_with_rand_reset.471670503
Directory /workspace/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.780229896
Short name T337
Test name
Test status
Simulation time 44031160 ps
CPU time 1.58 seconds
Started Mar 21 02:33:29 PM PDT 24
Finished Mar 21 02:33:32 PM PDT 24
Peak memory 238540 kb
Host smart-1f1f4768-9cd6-4d5a-a5a0-ff564f99d52f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780229896 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.780229896
Directory /workspace/16.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.1713716502
Short name T1252
Test name
Test status
Simulation time 62867176 ps
CPU time 1.47 seconds
Started Mar 21 02:33:32 PM PDT 24
Finished Mar 21 02:33:34 PM PDT 24
Peak memory 229820 kb
Host smart-ca01a67a-9419-477e-8237-1d70627850c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713716502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.1713716502
Directory /workspace/16.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.4284650282
Short name T332
Test name
Test status
Simulation time 1015904225 ps
CPU time 3.11 seconds
Started Mar 21 02:33:29 PM PDT 24
Finished Mar 21 02:33:33 PM PDT 24
Peak memory 238576 kb
Host smart-c37dcb27-81ed-44a6-a9df-943fcf7c2ad9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284650282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_
ctrl_same_csr_outstanding.4284650282
Directory /workspace/16.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.80850286
Short name T1225
Test name
Test status
Simulation time 998710932 ps
CPU time 5.96 seconds
Started Mar 21 02:33:29 PM PDT 24
Finished Mar 21 02:33:35 PM PDT 24
Peak memory 245732 kb
Host smart-55e84ae4-f08b-4712-b71b-ce53e7865948
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80850286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.80850286
Directory /workspace/16.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.1905246744
Short name T1325
Test name
Test status
Simulation time 1259619548 ps
CPU time 19.5 seconds
Started Mar 21 02:33:30 PM PDT 24
Finished Mar 21 02:33:50 PM PDT 24
Peak memory 243444 kb
Host smart-fe65c760-ff0f-4662-98a8-52a6c171cc7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905246744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_i
ntg_err.1905246744
Directory /workspace/16.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.2138051554
Short name T1215
Test name
Test status
Simulation time 140085962 ps
CPU time 2.29 seconds
Started Mar 21 02:33:31 PM PDT 24
Finished Mar 21 02:33:34 PM PDT 24
Peak memory 245100 kb
Host smart-22b3a084-be6d-416d-90c7-57799357480b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138051554 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.otp_ctrl_csr_mem_rw_with_rand_reset.2138051554
Directory /workspace/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.2960661057
Short name T1307
Test name
Test status
Simulation time 169888353 ps
CPU time 2.13 seconds
Started Mar 21 02:33:31 PM PDT 24
Finished Mar 21 02:33:34 PM PDT 24
Peak memory 240872 kb
Host smart-14aa4c61-22e9-4a15-9322-f1087978a696
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960661057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.2960661057
Directory /workspace/17.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.853920184
Short name T1268
Test name
Test status
Simulation time 71670561 ps
CPU time 1.45 seconds
Started Mar 21 02:33:33 PM PDT 24
Finished Mar 21 02:33:35 PM PDT 24
Peak memory 229900 kb
Host smart-d2fb17d8-cec8-420b-9ead-a46493e18d6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853920184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.853920184
Directory /workspace/17.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.1250286068
Short name T1256
Test name
Test status
Simulation time 126291925 ps
CPU time 2.47 seconds
Started Mar 21 02:33:33 PM PDT 24
Finished Mar 21 02:33:35 PM PDT 24
Peak memory 238596 kb
Host smart-11c844bf-d114-4795-bff9-8da621619479
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250286068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_
ctrl_same_csr_outstanding.1250286068
Directory /workspace/17.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.4092636496
Short name T1203
Test name
Test status
Simulation time 618427247 ps
CPU time 6.99 seconds
Started Mar 21 02:33:32 PM PDT 24
Finished Mar 21 02:33:39 PM PDT 24
Peak memory 245868 kb
Host smart-a713938c-53d6-40ac-a89e-3b00d453bd91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092636496 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.4092636496
Directory /workspace/17.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.1008577314
Short name T1309
Test name
Test status
Simulation time 19220466991 ps
CPU time 23.11 seconds
Started Mar 21 02:33:29 PM PDT 24
Finished Mar 21 02:33:53 PM PDT 24
Peak memory 244108 kb
Host smart-c1362cd9-97f7-4ecd-acb0-80dc74970759
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008577314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_i
ntg_err.1008577314
Directory /workspace/17.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.3636487067
Short name T1312
Test name
Test status
Simulation time 166485129 ps
CPU time 2.99 seconds
Started Mar 21 02:33:31 PM PDT 24
Finished Mar 21 02:33:35 PM PDT 24
Peak memory 246416 kb
Host smart-1506fb43-7c49-47ab-823c-a3fbe37a0c31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636487067 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.otp_ctrl_csr_mem_rw_with_rand_reset.3636487067
Directory /workspace/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.253914081
Short name T1313
Test name
Test status
Simulation time 38780218 ps
CPU time 1.52 seconds
Started Mar 21 02:33:33 PM PDT 24
Finished Mar 21 02:33:34 PM PDT 24
Peak memory 238648 kb
Host smart-c91562d5-47a6-4557-81d2-76a033ad7aa6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253914081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.253914081
Directory /workspace/18.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.581138322
Short name T1229
Test name
Test status
Simulation time 145245539 ps
CPU time 1.4 seconds
Started Mar 21 02:33:32 PM PDT 24
Finished Mar 21 02:33:34 PM PDT 24
Peak memory 229836 kb
Host smart-37f8103e-075d-4043-b7e9-6d9451a5954f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581138322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.581138322
Directory /workspace/18.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.3252497502
Short name T1299
Test name
Test status
Simulation time 88563805 ps
CPU time 2.22 seconds
Started Mar 21 02:33:31 PM PDT 24
Finished Mar 21 02:33:34 PM PDT 24
Peak memory 238636 kb
Host smart-d03cbf1f-2af5-4f6e-9b2a-f645437776ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252497502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_
ctrl_same_csr_outstanding.3252497502
Directory /workspace/18.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.2040573301
Short name T1211
Test name
Test status
Simulation time 1052044380 ps
CPU time 5.95 seconds
Started Mar 21 02:33:33 PM PDT 24
Finished Mar 21 02:33:40 PM PDT 24
Peak memory 245684 kb
Host smart-73ddd903-a7f0-47dd-bba5-b271aeb387e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040573301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.2040573301
Directory /workspace/18.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.415654532
Short name T1327
Test name
Test status
Simulation time 9767531190 ps
CPU time 19.76 seconds
Started Mar 21 02:33:32 PM PDT 24
Finished Mar 21 02:33:51 PM PDT 24
Peak memory 243768 kb
Host smart-5f582913-d5f1-405d-8dd9-771579e10889
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415654532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_in
tg_err.415654532
Directory /workspace/18.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.3602837932
Short name T321
Test name
Test status
Simulation time 44104991 ps
CPU time 1.63 seconds
Started Mar 21 02:33:38 PM PDT 24
Finished Mar 21 02:33:40 PM PDT 24
Peak memory 238572 kb
Host smart-60a12b75-33f1-4137-be90-e87cb061e9e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602837932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.3602837932
Directory /workspace/19.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.3317567333
Short name T1217
Test name
Test status
Simulation time 102525046 ps
CPU time 1.65 seconds
Started Mar 21 02:33:42 PM PDT 24
Finished Mar 21 02:33:44 PM PDT 24
Peak memory 229508 kb
Host smart-4387ce56-372b-412c-99f0-b74bdd980cd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317567333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.3317567333
Directory /workspace/19.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.134481620
Short name T336
Test name
Test status
Simulation time 272536702 ps
CPU time 3.77 seconds
Started Mar 21 02:33:45 PM PDT 24
Finished Mar 21 02:33:49 PM PDT 24
Peak memory 241488 kb
Host smart-a016525b-3432-453c-bc9f-ec332d580963
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134481620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_c
trl_same_csr_outstanding.134481620
Directory /workspace/19.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.3549798553
Short name T1289
Test name
Test status
Simulation time 313318847 ps
CPU time 6.55 seconds
Started Mar 21 02:33:29 PM PDT 24
Finished Mar 21 02:33:36 PM PDT 24
Peak memory 238784 kb
Host smart-6525d9a1-16ab-4ef3-a851-f1a7aaacaee3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549798553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.3549798553
Directory /workspace/19.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.1641090936
Short name T376
Test name
Test status
Simulation time 737076278 ps
CPU time 10.33 seconds
Started Mar 21 02:33:45 PM PDT 24
Finished Mar 21 02:33:56 PM PDT 24
Peak memory 243144 kb
Host smart-2b1bbdbf-9b39-4af9-987e-92354e4fcede
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641090936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_i
ntg_err.1641090936
Directory /workspace/19.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.509964359
Short name T330
Test name
Test status
Simulation time 401410588 ps
CPU time 4.54 seconds
Started Mar 21 02:32:30 PM PDT 24
Finished Mar 21 02:32:35 PM PDT 24
Peak memory 238632 kb
Host smart-faa3d14d-b476-4ca3-8115-1c3754f5347a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509964359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_alias
ing.509964359
Directory /workspace/2.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.3542992570
Short name T1294
Test name
Test status
Simulation time 86900812 ps
CPU time 4.03 seconds
Started Mar 21 02:32:31 PM PDT 24
Finished Mar 21 02:32:36 PM PDT 24
Peak memory 238616 kb
Host smart-a2116fcb-1a83-4648-a596-dadfda11a9f6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542992570 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_
bash.3542992570
Directory /workspace/2.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.2864372901
Short name T1237
Test name
Test status
Simulation time 215596904 ps
CPU time 2.5 seconds
Started Mar 21 02:32:32 PM PDT 24
Finished Mar 21 02:32:35 PM PDT 24
Peak memory 240356 kb
Host smart-080c7853-0988-4f0b-a41d-321ed3610025
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864372901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_r
eset.2864372901
Directory /workspace/2.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.4167127178
Short name T1239
Test name
Test status
Simulation time 71009167 ps
CPU time 2.21 seconds
Started Mar 21 02:32:32 PM PDT 24
Finished Mar 21 02:32:34 PM PDT 24
Peak memory 243992 kb
Host smart-c5ff08af-b82a-4bd5-a114-191cbc3e1b1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167127178 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.otp_ctrl_csr_mem_rw_with_rand_reset.4167127178
Directory /workspace/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.3403280782
Short name T344
Test name
Test status
Simulation time 180018540 ps
CPU time 1.8 seconds
Started Mar 21 02:32:30 PM PDT 24
Finished Mar 21 02:32:32 PM PDT 24
Peak memory 237704 kb
Host smart-6d096395-4d93-48c3-8666-4c842b686aaf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403280782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.3403280782
Directory /workspace/2.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.2346433972
Short name T1261
Test name
Test status
Simulation time 138222701 ps
CPU time 1.43 seconds
Started Mar 21 02:32:28 PM PDT 24
Finished Mar 21 02:32:30 PM PDT 24
Peak memory 229544 kb
Host smart-ef48119e-acdc-465d-b6cd-08d948fd01b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346433972 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.2346433972
Directory /workspace/2.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.3574713955
Short name T1247
Test name
Test status
Simulation time 38517717 ps
CPU time 1.32 seconds
Started Mar 21 02:32:30 PM PDT 24
Finished Mar 21 02:32:32 PM PDT 24
Peak memory 229344 kb
Host smart-cbaf2e63-f3bb-45f2-ade9-1002302e62d7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574713955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctr
l_mem_partial_access.3574713955
Directory /workspace/2.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.4263659186
Short name T1200
Test name
Test status
Simulation time 65475715 ps
CPU time 1.44 seconds
Started Mar 21 02:32:31 PM PDT 24
Finished Mar 21 02:32:32 PM PDT 24
Peak memory 229364 kb
Host smart-f37b1a19-d9c1-4ab5-9b46-e49c63e9bcd1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263659186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk
.4263659186
Directory /workspace/2.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.1371167235
Short name T1281
Test name
Test status
Simulation time 197001129 ps
CPU time 3.01 seconds
Started Mar 21 02:32:31 PM PDT 24
Finished Mar 21 02:32:34 PM PDT 24
Peak memory 238660 kb
Host smart-03b742f9-6344-4ecf-a7fb-158e40b1a4d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371167235 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_c
trl_same_csr_outstanding.1371167235
Directory /workspace/2.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.220386542
Short name T1204
Test name
Test status
Simulation time 102410525 ps
CPU time 3.7 seconds
Started Mar 21 02:32:30 PM PDT 24
Finished Mar 21 02:32:34 PM PDT 24
Peak memory 238740 kb
Host smart-140c1fbd-a6d6-4626-b330-25d72d1919ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220386542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.220386542
Directory /workspace/2.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.2021499336
Short name T1284
Test name
Test status
Simulation time 1220733639 ps
CPU time 17.67 seconds
Started Mar 21 02:32:28 PM PDT 24
Finished Mar 21 02:32:46 PM PDT 24
Peak memory 243588 kb
Host smart-f36b92ec-931c-47ba-b216-5d62ecf1e55f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021499336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_in
tg_err.2021499336
Directory /workspace/2.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.3185756574
Short name T1243
Test name
Test status
Simulation time 45392958 ps
CPU time 1.46 seconds
Started Mar 21 02:33:39 PM PDT 24
Finished Mar 21 02:33:40 PM PDT 24
Peak memory 230436 kb
Host smart-85657bd1-502f-42c9-9e7e-0743bdfe940b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185756574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.3185756574
Directory /workspace/20.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.2777589866
Short name T1232
Test name
Test status
Simulation time 80197909 ps
CPU time 1.47 seconds
Started Mar 21 02:33:45 PM PDT 24
Finished Mar 21 02:33:47 PM PDT 24
Peak memory 230440 kb
Host smart-85dcdd11-06e0-48e4-b466-bd0851f94f23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777589866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.2777589866
Directory /workspace/21.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.4049037699
Short name T1221
Test name
Test status
Simulation time 76391601 ps
CPU time 1.56 seconds
Started Mar 21 02:33:39 PM PDT 24
Finished Mar 21 02:33:41 PM PDT 24
Peak memory 229588 kb
Host smart-a0e409bf-5386-4500-b364-a76de53556e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049037699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.4049037699
Directory /workspace/22.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.2014219622
Short name T1296
Test name
Test status
Simulation time 50627827 ps
CPU time 1.45 seconds
Started Mar 21 02:33:45 PM PDT 24
Finished Mar 21 02:33:46 PM PDT 24
Peak memory 230436 kb
Host smart-6930f216-db35-4827-95b9-b63fb33e62df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014219622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.2014219622
Directory /workspace/23.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.4036532928
Short name T1235
Test name
Test status
Simulation time 38642306 ps
CPU time 1.5 seconds
Started Mar 21 02:33:46 PM PDT 24
Finished Mar 21 02:33:48 PM PDT 24
Peak memory 229568 kb
Host smart-07d730d0-caa1-4698-b201-ec783cf06964
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036532928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.4036532928
Directory /workspace/24.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.3007150377
Short name T1224
Test name
Test status
Simulation time 141003875 ps
CPU time 1.39 seconds
Started Mar 21 02:33:46 PM PDT 24
Finished Mar 21 02:33:47 PM PDT 24
Peak memory 229872 kb
Host smart-5d9b8d07-df0c-4fde-9782-34e94fb002e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007150377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.3007150377
Directory /workspace/25.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.3526468196
Short name T1303
Test name
Test status
Simulation time 146847280 ps
CPU time 1.55 seconds
Started Mar 21 02:33:38 PM PDT 24
Finished Mar 21 02:33:40 PM PDT 24
Peak memory 229576 kb
Host smart-2a8970c2-a35c-4d47-9dd3-8d53ee2da030
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526468196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.3526468196
Directory /workspace/26.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.3351577751
Short name T1260
Test name
Test status
Simulation time 114102569 ps
CPU time 1.51 seconds
Started Mar 21 02:33:45 PM PDT 24
Finished Mar 21 02:33:47 PM PDT 24
Peak memory 230344 kb
Host smart-8d5f7448-1876-425c-9b7c-a6f612f97f9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351577751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.3351577751
Directory /workspace/27.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.3552270568
Short name T1248
Test name
Test status
Simulation time 84347438 ps
CPU time 1.48 seconds
Started Mar 21 02:33:45 PM PDT 24
Finished Mar 21 02:33:46 PM PDT 24
Peak memory 229504 kb
Host smart-fb4581d1-cf58-4288-bff3-1895442d6cee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552270568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.3552270568
Directory /workspace/28.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.2638003992
Short name T1240
Test name
Test status
Simulation time 51407108 ps
CPU time 1.47 seconds
Started Mar 21 02:33:44 PM PDT 24
Finished Mar 21 02:33:45 PM PDT 24
Peak memory 230492 kb
Host smart-4d9f0ac7-b0fd-4a6e-b224-9425c52516ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638003992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.2638003992
Directory /workspace/29.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.1361326014
Short name T317
Test name
Test status
Simulation time 99009776 ps
CPU time 3.67 seconds
Started Mar 21 02:32:42 PM PDT 24
Finished Mar 21 02:32:46 PM PDT 24
Peak memory 230360 kb
Host smart-0e49d0ca-13d9-477a-8929-c24a122e0b98
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361326014 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_alia
sing.1361326014
Directory /workspace/3.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.3370942435
Short name T1322
Test name
Test status
Simulation time 243134146 ps
CPU time 4 seconds
Started Mar 21 02:32:47 PM PDT 24
Finished Mar 21 02:32:51 PM PDT 24
Peak memory 238608 kb
Host smart-4504ef4b-ebe5-4750-bc81-c3b87584493c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370942435 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_
bash.3370942435
Directory /workspace/3.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.2172584739
Short name T1214
Test name
Test status
Simulation time 67923576 ps
CPU time 1.91 seconds
Started Mar 21 02:32:42 PM PDT 24
Finished Mar 21 02:32:44 PM PDT 24
Peak memory 238648 kb
Host smart-2994f51d-bc2b-4312-b746-8b455e75cff3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172584739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_r
eset.2172584739
Directory /workspace/3.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.1359167609
Short name T1272
Test name
Test status
Simulation time 1669850413 ps
CPU time 3.91 seconds
Started Mar 21 02:32:46 PM PDT 24
Finished Mar 21 02:32:51 PM PDT 24
Peak memory 245264 kb
Host smart-c2030ef6-9a4a-4423-bc1d-b91995a69694
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359167609 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.otp_ctrl_csr_mem_rw_with_rand_reset.1359167609
Directory /workspace/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.3979287508
Short name T334
Test name
Test status
Simulation time 41664264 ps
CPU time 1.58 seconds
Started Mar 21 02:32:46 PM PDT 24
Finished Mar 21 02:32:48 PM PDT 24
Peak memory 240440 kb
Host smart-ba21403c-9677-4929-9cb8-c4b59f0d0921
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979287508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.3979287508
Directory /workspace/3.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.4063645934
Short name T1279
Test name
Test status
Simulation time 37935328 ps
CPU time 1.39 seconds
Started Mar 21 02:32:42 PM PDT 24
Finished Mar 21 02:32:43 PM PDT 24
Peak memory 229800 kb
Host smart-8d86eaf0-7230-494d-a69b-8d69cd26d6c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063645934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.4063645934
Directory /workspace/3.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.2113416858
Short name T1320
Test name
Test status
Simulation time 37721284 ps
CPU time 1.39 seconds
Started Mar 21 02:32:41 PM PDT 24
Finished Mar 21 02:32:43 PM PDT 24
Peak memory 229508 kb
Host smart-22ec3103-42f5-4641-86bc-e0cd3f87ec77
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113416858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctr
l_mem_partial_access.2113416858
Directory /workspace/3.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.2727260004
Short name T1298
Test name
Test status
Simulation time 74363195 ps
CPU time 1.36 seconds
Started Mar 21 02:32:42 PM PDT 24
Finished Mar 21 02:32:44 PM PDT 24
Peak memory 229628 kb
Host smart-b06f3bef-6ba2-40d6-a0ed-a73379689a5e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727260004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk
.2727260004
Directory /workspace/3.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.1896041527
Short name T1250
Test name
Test status
Simulation time 142156769 ps
CPU time 3.05 seconds
Started Mar 21 02:32:43 PM PDT 24
Finished Mar 21 02:32:46 PM PDT 24
Peak memory 238564 kb
Host smart-03c4c758-f6cd-465d-9e03-4d230df69d25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896041527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_c
trl_same_csr_outstanding.1896041527
Directory /workspace/3.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.899839506
Short name T1270
Test name
Test status
Simulation time 1195608294 ps
CPU time 7.34 seconds
Started Mar 21 02:32:41 PM PDT 24
Finished Mar 21 02:32:49 PM PDT 24
Peak memory 238692 kb
Host smart-3525c865-aee5-4dc2-b6b7-026b17f1f510
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899839506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.899839506
Directory /workspace/3.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.3253596478
Short name T377
Test name
Test status
Simulation time 712217466 ps
CPU time 10.47 seconds
Started Mar 21 02:32:42 PM PDT 24
Finished Mar 21 02:32:53 PM PDT 24
Peak memory 243200 kb
Host smart-ae06f36a-fae3-4826-ba7e-4029b6faed13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253596478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_in
tg_err.3253596478
Directory /workspace/3.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.597491532
Short name T1199
Test name
Test status
Simulation time 75579049 ps
CPU time 1.44 seconds
Started Mar 21 02:33:37 PM PDT 24
Finished Mar 21 02:33:39 PM PDT 24
Peak memory 229500 kb
Host smart-29ff4456-a75a-41dc-8e42-06f7241de98e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597491532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.597491532
Directory /workspace/30.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.1095787464
Short name T1242
Test name
Test status
Simulation time 41149502 ps
CPU time 1.56 seconds
Started Mar 21 02:33:41 PM PDT 24
Finished Mar 21 02:33:42 PM PDT 24
Peak memory 229596 kb
Host smart-07accfb2-3514-4e4c-90b1-ee87304a0f7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095787464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.1095787464
Directory /workspace/31.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.4059605620
Short name T1288
Test name
Test status
Simulation time 145985326 ps
CPU time 1.64 seconds
Started Mar 21 02:33:39 PM PDT 24
Finished Mar 21 02:33:41 PM PDT 24
Peak memory 229840 kb
Host smart-8456bcf5-df9e-4294-a644-ab85894691b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059605620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.4059605620
Directory /workspace/32.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.139560389
Short name T1208
Test name
Test status
Simulation time 39929085 ps
CPU time 1.38 seconds
Started Mar 21 02:33:45 PM PDT 24
Finished Mar 21 02:33:46 PM PDT 24
Peak memory 230492 kb
Host smart-4c98dc9a-1600-4943-9c8b-998325f58fc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139560389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.139560389
Directory /workspace/33.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.217639669
Short name T1251
Test name
Test status
Simulation time 134189159 ps
CPU time 1.4 seconds
Started Mar 21 02:33:40 PM PDT 24
Finished Mar 21 02:33:41 PM PDT 24
Peak memory 229616 kb
Host smart-85857e1c-e7b2-42a4-95cc-6898ce47a894
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217639669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.217639669
Directory /workspace/34.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.2966214468
Short name T1218
Test name
Test status
Simulation time 74423746 ps
CPU time 1.38 seconds
Started Mar 21 02:33:43 PM PDT 24
Finished Mar 21 02:33:44 PM PDT 24
Peak memory 229600 kb
Host smart-2ba3c6a7-7ae5-4d58-b9e3-8a3846f98d58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966214468 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.2966214468
Directory /workspace/35.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.3792944887
Short name T1265
Test name
Test status
Simulation time 48981767 ps
CPU time 1.46 seconds
Started Mar 21 02:33:44 PM PDT 24
Finished Mar 21 02:33:46 PM PDT 24
Peak memory 229532 kb
Host smart-89779d30-5eab-4ea3-a360-a4c6ca4b6301
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792944887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.3792944887
Directory /workspace/36.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.2233777288
Short name T1271
Test name
Test status
Simulation time 78931919 ps
CPU time 1.47 seconds
Started Mar 21 02:33:40 PM PDT 24
Finished Mar 21 02:33:42 PM PDT 24
Peak memory 229544 kb
Host smart-7dbdf580-abb2-45d8-9d5b-d53cb6df00d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233777288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.2233777288
Directory /workspace/37.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.4047902470
Short name T1275
Test name
Test status
Simulation time 74297118 ps
CPU time 1.4 seconds
Started Mar 21 02:33:38 PM PDT 24
Finished Mar 21 02:33:40 PM PDT 24
Peak memory 229524 kb
Host smart-668208e4-514f-45bd-94c0-be2f02ae0b0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047902470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.4047902470
Directory /workspace/38.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.1374516276
Short name T1273
Test name
Test status
Simulation time 37867278 ps
CPU time 1.38 seconds
Started Mar 21 02:33:38 PM PDT 24
Finished Mar 21 02:33:39 PM PDT 24
Peak memory 230472 kb
Host smart-28f44efb-e7f7-4ce7-86f3-27c72df45927
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374516276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.1374516276
Directory /workspace/39.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.619626560
Short name T318
Test name
Test status
Simulation time 114473667 ps
CPU time 3.83 seconds
Started Mar 21 02:32:47 PM PDT 24
Finished Mar 21 02:32:51 PM PDT 24
Peak memory 238612 kb
Host smart-a2db35b0-a956-44a8-84e4-6d71e3ba7961
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619626560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_alias
ing.619626560
Directory /workspace/4.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.3905333317
Short name T1257
Test name
Test status
Simulation time 332835254 ps
CPU time 5.54 seconds
Started Mar 21 02:32:49 PM PDT 24
Finished Mar 21 02:32:55 PM PDT 24
Peak memory 239940 kb
Host smart-ed1ecf56-d497-4351-8944-8645e3ac40ca
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905333317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_
bash.3905333317
Directory /workspace/4.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.2106564699
Short name T285
Test name
Test status
Simulation time 136421330 ps
CPU time 1.92 seconds
Started Mar 21 02:32:43 PM PDT 24
Finished Mar 21 02:32:45 PM PDT 24
Peak memory 240516 kb
Host smart-f366c87c-b570-46e2-93c7-dd8e1cabe660
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106564699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_r
eset.2106564699
Directory /workspace/4.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.3185247737
Short name T1300
Test name
Test status
Simulation time 68565338 ps
CPU time 2.39 seconds
Started Mar 21 02:32:59 PM PDT 24
Finished Mar 21 02:33:02 PM PDT 24
Peak memory 246680 kb
Host smart-35105b8c-3a04-42fe-8dec-17d6cce27663
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185247737 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.otp_ctrl_csr_mem_rw_with_rand_reset.3185247737
Directory /workspace/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.3196982479
Short name T319
Test name
Test status
Simulation time 175762290 ps
CPU time 1.78 seconds
Started Mar 21 02:32:43 PM PDT 24
Finished Mar 21 02:32:45 PM PDT 24
Peak memory 240680 kb
Host smart-4c1cb479-a41f-4464-8730-633ac768568d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196982479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.3196982479
Directory /workspace/4.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.505026380
Short name T1311
Test name
Test status
Simulation time 57135880 ps
CPU time 1.5 seconds
Started Mar 21 02:32:42 PM PDT 24
Finished Mar 21 02:32:44 PM PDT 24
Peak memory 229580 kb
Host smart-94353463-2591-4213-a8c0-1b8b807f36b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505026380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.505026380
Directory /workspace/4.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.1887006251
Short name T1276
Test name
Test status
Simulation time 73065927 ps
CPU time 1.44 seconds
Started Mar 21 02:32:46 PM PDT 24
Finished Mar 21 02:32:48 PM PDT 24
Peak memory 229528 kb
Host smart-220a2882-1707-4f23-a77e-3e3eec5162d6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887006251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctr
l_mem_partial_access.1887006251
Directory /workspace/4.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.4283716149
Short name T1293
Test name
Test status
Simulation time 70936380 ps
CPU time 1.44 seconds
Started Mar 21 02:32:48 PM PDT 24
Finished Mar 21 02:32:49 PM PDT 24
Peak memory 229576 kb
Host smart-8de739fa-1fec-4c3f-bc17-d3ee9c459116
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283716149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk
.4283716149
Directory /workspace/4.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.3049764499
Short name T1308
Test name
Test status
Simulation time 195047128 ps
CPU time 3.48 seconds
Started Mar 21 02:32:43 PM PDT 24
Finished Mar 21 02:32:47 PM PDT 24
Peak memory 238488 kb
Host smart-3d70a720-a818-4f70-95e3-20cdc78de4c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049764499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_c
trl_same_csr_outstanding.3049764499
Directory /workspace/4.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.868385803
Short name T1319
Test name
Test status
Simulation time 91893654 ps
CPU time 3.86 seconds
Started Mar 21 02:32:41 PM PDT 24
Finished Mar 21 02:32:45 PM PDT 24
Peak memory 245640 kb
Host smart-8bc747ee-bb0a-4970-94e5-933d5159f0b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868385803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.868385803
Directory /workspace/4.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.599797970
Short name T374
Test name
Test status
Simulation time 1319242755 ps
CPU time 20.8 seconds
Started Mar 21 02:32:41 PM PDT 24
Finished Mar 21 02:33:02 PM PDT 24
Peak memory 244524 kb
Host smart-86e52f10-ecf8-42de-9680-ad333992ee26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599797970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_int
g_err.599797970
Directory /workspace/4.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.3394431730
Short name T1262
Test name
Test status
Simulation time 39175815 ps
CPU time 1.36 seconds
Started Mar 21 02:33:40 PM PDT 24
Finished Mar 21 02:33:42 PM PDT 24
Peak memory 230492 kb
Host smart-719aa184-011d-45d4-a3cd-6f4bebc465b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394431730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.3394431730
Directory /workspace/40.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.2016705788
Short name T1205
Test name
Test status
Simulation time 81918627 ps
CPU time 1.4 seconds
Started Mar 21 02:33:41 PM PDT 24
Finished Mar 21 02:33:42 PM PDT 24
Peak memory 229560 kb
Host smart-c918b0a4-ff91-411e-a6e1-745d445a2587
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016705788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.2016705788
Directory /workspace/41.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.2905077893
Short name T1328
Test name
Test status
Simulation time 132936206 ps
CPU time 1.42 seconds
Started Mar 21 02:33:46 PM PDT 24
Finished Mar 21 02:33:48 PM PDT 24
Peak memory 230440 kb
Host smart-289daf76-65e1-40db-9555-069152e1a3b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905077893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.2905077893
Directory /workspace/42.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.3227253639
Short name T1216
Test name
Test status
Simulation time 40750128 ps
CPU time 1.42 seconds
Started Mar 21 02:33:46 PM PDT 24
Finished Mar 21 02:33:47 PM PDT 24
Peak memory 229512 kb
Host smart-b6bd6537-6642-421a-9b32-d43423c4c4a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227253639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.3227253639
Directory /workspace/43.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.445738186
Short name T1269
Test name
Test status
Simulation time 43703133 ps
CPU time 1.43 seconds
Started Mar 21 02:33:38 PM PDT 24
Finished Mar 21 02:33:39 PM PDT 24
Peak memory 229892 kb
Host smart-e5460caf-3102-4fc1-917c-fb49e0c8676f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445738186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.445738186
Directory /workspace/44.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.1051300943
Short name T1206
Test name
Test status
Simulation time 68834412 ps
CPU time 1.46 seconds
Started Mar 21 02:33:40 PM PDT 24
Finished Mar 21 02:33:41 PM PDT 24
Peak memory 230416 kb
Host smart-130e6026-2c9e-4487-9bf3-686a17818d5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051300943 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.1051300943
Directory /workspace/45.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.3161915174
Short name T1213
Test name
Test status
Simulation time 40061574 ps
CPU time 1.43 seconds
Started Mar 21 02:33:45 PM PDT 24
Finished Mar 21 02:33:46 PM PDT 24
Peak memory 229528 kb
Host smart-c5bd3a16-3ce1-43de-919d-2e41da079f19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161915174 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.3161915174
Directory /workspace/46.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.237678598
Short name T1202
Test name
Test status
Simulation time 40846142 ps
CPU time 1.42 seconds
Started Mar 21 02:33:42 PM PDT 24
Finished Mar 21 02:33:44 PM PDT 24
Peak memory 230448 kb
Host smart-86c18e16-dc2a-47d4-a249-8524bdaffddb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237678598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.237678598
Directory /workspace/47.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.160039764
Short name T1244
Test name
Test status
Simulation time 82640455 ps
CPU time 1.5 seconds
Started Mar 21 02:33:38 PM PDT 24
Finished Mar 21 02:33:40 PM PDT 24
Peak memory 230372 kb
Host smart-88310d71-f787-483d-9570-764375043d61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160039764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.160039764
Directory /workspace/48.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.3691801597
Short name T1282
Test name
Test status
Simulation time 554028094 ps
CPU time 1.75 seconds
Started Mar 21 02:33:54 PM PDT 24
Finished Mar 21 02:33:55 PM PDT 24
Peak memory 229584 kb
Host smart-72a5ecc8-30ec-4b8f-a8c6-4cf2fb683b6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691801597 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.3691801597
Directory /workspace/49.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.2832723025
Short name T390
Test name
Test status
Simulation time 75243433 ps
CPU time 2.2 seconds
Started Mar 21 02:33:02 PM PDT 24
Finished Mar 21 02:33:05 PM PDT 24
Peak memory 243668 kb
Host smart-2e5ef7d2-8997-436c-b3ee-7feeae604587
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832723025 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.otp_ctrl_csr_mem_rw_with_rand_reset.2832723025
Directory /workspace/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.2870266058
Short name T1255
Test name
Test status
Simulation time 39632539 ps
CPU time 1.6 seconds
Started Mar 21 02:33:01 PM PDT 24
Finished Mar 21 02:33:04 PM PDT 24
Peak memory 240800 kb
Host smart-f7f85e91-da95-49da-9387-9018bca4aa55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870266058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.2870266058
Directory /workspace/5.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.1862980953
Short name T1230
Test name
Test status
Simulation time 38272291 ps
CPU time 1.49 seconds
Started Mar 21 02:33:00 PM PDT 24
Finished Mar 21 02:33:01 PM PDT 24
Peak memory 229880 kb
Host smart-46e0a17f-d48d-4cab-b254-933d61dcfeb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862980953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.1862980953
Directory /workspace/5.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.3455027334
Short name T1278
Test name
Test status
Simulation time 66857823 ps
CPU time 2.45 seconds
Started Mar 21 02:32:59 PM PDT 24
Finished Mar 21 02:33:02 PM PDT 24
Peak memory 238612 kb
Host smart-779e7734-bc2a-43c9-9b81-5f14bde6317f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455027334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_c
trl_same_csr_outstanding.3455027334
Directory /workspace/5.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.3739355223
Short name T1201
Test name
Test status
Simulation time 1627351409 ps
CPU time 6.68 seconds
Started Mar 21 02:33:01 PM PDT 24
Finished Mar 21 02:33:09 PM PDT 24
Peak memory 238688 kb
Host smart-505c3281-7fe8-45db-93ac-c938a0123735
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739355223 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.3739355223
Directory /workspace/5.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.1119131832
Short name T1283
Test name
Test status
Simulation time 1069496833 ps
CPU time 3.09 seconds
Started Mar 21 02:33:02 PM PDT 24
Finished Mar 21 02:33:06 PM PDT 24
Peak memory 243584 kb
Host smart-9b82ca38-9ac8-4dd0-a9fd-6e78c0c6fdf3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119131832 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.otp_ctrl_csr_mem_rw_with_rand_reset.1119131832
Directory /workspace/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.715258968
Short name T320
Test name
Test status
Simulation time 48036162 ps
CPU time 1.86 seconds
Started Mar 21 02:33:00 PM PDT 24
Finished Mar 21 02:33:02 PM PDT 24
Peak memory 240724 kb
Host smart-d4c7a80e-89b0-4d19-b56f-7c2b24cbd807
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715258968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.715258968
Directory /workspace/6.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.261422916
Short name T1321
Test name
Test status
Simulation time 133548644 ps
CPU time 1.41 seconds
Started Mar 21 02:32:59 PM PDT 24
Finished Mar 21 02:33:01 PM PDT 24
Peak memory 229632 kb
Host smart-375891c4-d8b9-4bde-aeed-0a0811ac43d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261422916 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.261422916
Directory /workspace/6.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.1274696388
Short name T1258
Test name
Test status
Simulation time 805765507 ps
CPU time 3.69 seconds
Started Mar 21 02:33:02 PM PDT 24
Finished Mar 21 02:33:06 PM PDT 24
Peak memory 238680 kb
Host smart-5bcc6396-3e85-4f00-bf27-2cacd4f092d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274696388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_c
trl_same_csr_outstanding.1274696388
Directory /workspace/6.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.747865911
Short name T1280
Test name
Test status
Simulation time 50500104 ps
CPU time 3.14 seconds
Started Mar 21 02:33:00 PM PDT 24
Finished Mar 21 02:33:03 PM PDT 24
Peak memory 245304 kb
Host smart-d0690690-412c-422d-b513-a1b4a4a276b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747865911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.747865911
Directory /workspace/6.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.3503792758
Short name T370
Test name
Test status
Simulation time 10764226451 ps
CPU time 10.95 seconds
Started Mar 21 02:33:02 PM PDT 24
Finished Mar 21 02:33:14 PM PDT 24
Peak memory 243912 kb
Host smart-37c831df-c6fb-40af-ab99-c0c973b01c83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503792758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_in
tg_err.3503792758
Directory /workspace/6.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.2625976269
Short name T1207
Test name
Test status
Simulation time 1536701075 ps
CPU time 3.9 seconds
Started Mar 21 02:33:12 PM PDT 24
Finished Mar 21 02:33:16 PM PDT 24
Peak memory 246536 kb
Host smart-cd3a2edc-2374-4c5d-8f77-a58483f7c0bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625976269 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.otp_ctrl_csr_mem_rw_with_rand_reset.2625976269
Directory /workspace/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.318687015
Short name T311
Test name
Test status
Simulation time 545793425 ps
CPU time 2.2 seconds
Started Mar 21 02:33:14 PM PDT 24
Finished Mar 21 02:33:17 PM PDT 24
Peak memory 240756 kb
Host smart-0617d86c-4660-4c57-a7db-19aac714169f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318687015 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.318687015
Directory /workspace/7.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.2621288887
Short name T1249
Test name
Test status
Simulation time 41914110 ps
CPU time 1.43 seconds
Started Mar 21 02:33:21 PM PDT 24
Finished Mar 21 02:33:23 PM PDT 24
Peak memory 229552 kb
Host smart-d9291e39-bf69-4b51-9e36-570566f7e090
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621288887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.2621288887
Directory /workspace/7.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.4085108053
Short name T1241
Test name
Test status
Simulation time 112130267 ps
CPU time 3.06 seconds
Started Mar 21 02:33:24 PM PDT 24
Finished Mar 21 02:33:27 PM PDT 24
Peak memory 238640 kb
Host smart-8257a78c-9688-4b48-8071-242bd09713c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085108053 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_c
trl_same_csr_outstanding.4085108053
Directory /workspace/7.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.3382226853
Short name T1297
Test name
Test status
Simulation time 98376737 ps
CPU time 3.53 seconds
Started Mar 21 02:32:59 PM PDT 24
Finished Mar 21 02:33:03 PM PDT 24
Peak memory 245396 kb
Host smart-b70464d3-73f4-4eed-96fa-98265e5cfb45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382226853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.3382226853
Directory /workspace/7.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.1040362127
Short name T286
Test name
Test status
Simulation time 9819823288 ps
CPU time 11.94 seconds
Started Mar 21 02:33:02 PM PDT 24
Finished Mar 21 02:33:14 PM PDT 24
Peak memory 243644 kb
Host smart-a2379c38-b482-4dfd-ad87-2d848f945af7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040362127 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_in
tg_err.1040362127
Directory /workspace/7.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.334382147
Short name T1317
Test name
Test status
Simulation time 213637833 ps
CPU time 3.7 seconds
Started Mar 21 02:33:12 PM PDT 24
Finished Mar 21 02:33:16 PM PDT 24
Peak memory 246812 kb
Host smart-145c99b7-719c-437e-bb49-7795651c1ad2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334382147 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.otp_ctrl_csr_mem_rw_with_rand_reset.334382147
Directory /workspace/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.4253249336
Short name T313
Test name
Test status
Simulation time 51319870 ps
CPU time 1.51 seconds
Started Mar 21 02:33:25 PM PDT 24
Finished Mar 21 02:33:26 PM PDT 24
Peak memory 238608 kb
Host smart-79eca3d8-c18f-4d2c-9963-d07926450782
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253249336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.4253249336
Directory /workspace/8.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.206222126
Short name T1285
Test name
Test status
Simulation time 48970112 ps
CPU time 1.49 seconds
Started Mar 21 02:33:13 PM PDT 24
Finished Mar 21 02:33:16 PM PDT 24
Peak memory 230436 kb
Host smart-59901499-3a07-4a54-be74-369ea0c9d68f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206222126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.206222126
Directory /workspace/8.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.2372065784
Short name T284
Test name
Test status
Simulation time 141500831 ps
CPU time 3.85 seconds
Started Mar 21 02:33:25 PM PDT 24
Finished Mar 21 02:33:29 PM PDT 24
Peak memory 241604 kb
Host smart-356221ca-c1b6-4640-8560-14c1facc6b98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372065784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_c
trl_same_csr_outstanding.2372065784
Directory /workspace/8.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.3682605689
Short name T1234
Test name
Test status
Simulation time 121740679 ps
CPU time 5.51 seconds
Started Mar 21 02:33:12 PM PDT 24
Finished Mar 21 02:33:17 PM PDT 24
Peak memory 245728 kb
Host smart-6120abbb-2d7f-4c5c-8463-1c35a923eff2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682605689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.3682605689
Directory /workspace/8.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.1063760562
Short name T280
Test name
Test status
Simulation time 2447177854 ps
CPU time 21.2 seconds
Started Mar 21 02:33:22 PM PDT 24
Finished Mar 21 02:33:43 PM PDT 24
Peak memory 243988 kb
Host smart-751cf3e3-6657-4f50-8907-17ff6388d565
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063760562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_in
tg_err.1063760562
Directory /workspace/8.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.2729067040
Short name T1305
Test name
Test status
Simulation time 105830386 ps
CPU time 3.1 seconds
Started Mar 21 02:33:23 PM PDT 24
Finished Mar 21 02:33:26 PM PDT 24
Peak memory 246896 kb
Host smart-0d938b7a-61b6-4881-97a8-930ccbb71e3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729067040 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.otp_ctrl_csr_mem_rw_with_rand_reset.2729067040
Directory /workspace/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.1895925996
Short name T1314
Test name
Test status
Simulation time 88138611 ps
CPU time 2 seconds
Started Mar 21 02:33:12 PM PDT 24
Finished Mar 21 02:33:14 PM PDT 24
Peak memory 240748 kb
Host smart-c5312fdf-1c28-4382-b39e-7358b54405b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895925996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.1895925996
Directory /workspace/9.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.4186882044
Short name T1286
Test name
Test status
Simulation time 569364347 ps
CPU time 2.07 seconds
Started Mar 21 02:33:23 PM PDT 24
Finished Mar 21 02:33:26 PM PDT 24
Peak memory 229592 kb
Host smart-4d08e433-6ad7-4b19-9a45-d4c0993f859f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186882044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.4186882044
Directory /workspace/9.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.830552574
Short name T335
Test name
Test status
Simulation time 86688956 ps
CPU time 2.87 seconds
Started Mar 21 02:33:12 PM PDT 24
Finished Mar 21 02:33:15 PM PDT 24
Peak memory 238628 kb
Host smart-37689980-b5a4-4a0e-97f0-6c0bcd51dd9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830552574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ct
rl_same_csr_outstanding.830552574
Directory /workspace/9.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.1688763849
Short name T1274
Test name
Test status
Simulation time 397836886 ps
CPU time 6.62 seconds
Started Mar 21 02:33:15 PM PDT 24
Finished Mar 21 02:33:21 PM PDT 24
Peak memory 246560 kb
Host smart-37523e8c-688d-440c-845c-f93afd477ec9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688763849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.1688763849
Directory /workspace/9.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.1255327600
Short name T369
Test name
Test status
Simulation time 19807946912 ps
CPU time 31.85 seconds
Started Mar 21 02:33:13 PM PDT 24
Finished Mar 21 02:33:46 PM PDT 24
Peak memory 244236 kb
Host smart-c557a79f-1908-4a4b-82db-8af85975a15f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255327600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_in
tg_err.1255327600
Directory /workspace/9.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.otp_ctrl_background_chks.1867586156
Short name T839
Test name
Test status
Simulation time 359405152 ps
CPU time 13.32 seconds
Started Mar 21 03:27:02 PM PDT 24
Finished Mar 21 03:27:15 PM PDT 24
Peak memory 241624 kb
Host smart-34c985dd-f22f-4702-afe4-575ae86a21c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867586156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.1867586156
Directory /workspace/0.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/0.otp_ctrl_check_fail.2208593614
Short name T1042
Test name
Test status
Simulation time 6007012096 ps
CPU time 46.55 seconds
Started Mar 21 03:26:54 PM PDT 24
Finished Mar 21 03:27:41 PM PDT 24
Peak memory 241916 kb
Host smart-dd6b61ef-d349-4361-958b-85fb7e6004ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208593614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.2208593614
Directory /workspace/0.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_errs.1531871737
Short name T246
Test name
Test status
Simulation time 3545025881 ps
CPU time 29.66 seconds
Started Mar 21 03:27:04 PM PDT 24
Finished Mar 21 03:27:34 PM PDT 24
Peak memory 243516 kb
Host smart-59be37ce-628a-4d41-9792-589dd3e526d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531871737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.1531871737
Directory /workspace/0.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_lock.3224537668
Short name T1087
Test name
Test status
Simulation time 9533588557 ps
CPU time 26.13 seconds
Started Mar 21 03:26:56 PM PDT 24
Finished Mar 21 03:27:23 PM PDT 24
Peak memory 242220 kb
Host smart-23febc4b-55f4-43b1-ad92-fbaeb2cc0f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224537668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.3224537668
Directory /workspace/0.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/0.otp_ctrl_low_freq_read.2982202630
Short name T415
Test name
Test status
Simulation time 5880117146 ps
CPU time 13.52 seconds
Started Mar 21 03:26:54 PM PDT 24
Finished Mar 21 03:27:07 PM PDT 24
Peak memory 240968 kb
Host smart-ffb704a2-ed7a-430c-83cb-d5f691222a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982202630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.2982202630
Directory /workspace/0.otp_ctrl_low_freq_read/latest

Test location /workspace/coverage/default/0.otp_ctrl_macro_errs.1406382154
Short name T181
Test name
Test status
Simulation time 889403635 ps
CPU time 15.47 seconds
Started Mar 21 03:26:57 PM PDT 24
Finished Mar 21 03:27:12 PM PDT 24
Peak memory 241764 kb
Host smart-87b1b198-b97f-4d43-8a37-74ac4a7b2576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406382154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.1406382154
Directory /workspace/0.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_key_req.1480493835
Short name T974
Test name
Test status
Simulation time 1185194145 ps
CPU time 25.43 seconds
Started Mar 21 03:27:02 PM PDT 24
Finished Mar 21 03:27:27 PM PDT 24
Peak memory 241408 kb
Host smart-157048a1-c515-43f6-8d4a-cc40a9cf4e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480493835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.1480493835
Directory /workspace/0.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_esc.4078114002
Short name T1123
Test name
Test status
Simulation time 3412573410 ps
CPU time 9.62 seconds
Started Mar 21 03:26:59 PM PDT 24
Finished Mar 21 03:27:09 PM PDT 24
Peak memory 241452 kb
Host smart-323b2539-f1bf-426d-99e4-c31c5c66dae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078114002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.4078114002
Directory /workspace/0.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_req.3211912044
Short name T431
Test name
Test status
Simulation time 525021956 ps
CPU time 13.42 seconds
Started Mar 21 03:26:57 PM PDT 24
Finished Mar 21 03:27:10 PM PDT 24
Peak memory 241212 kb
Host smart-57054b92-ede0-45ed-99bf-314791e01351
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3211912044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.3211912044
Directory /workspace/0.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_partition_walk.1301864263
Short name T421
Test name
Test status
Simulation time 5098715650 ps
CPU time 24.33 seconds
Started Mar 21 03:27:00 PM PDT 24
Finished Mar 21 03:27:24 PM PDT 24
Peak memory 240892 kb
Host smart-2ba7faf8-9af2-4d0e-b8c7-5495c1a21e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301864263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.1301864263
Directory /workspace/0.otp_ctrl_partition_walk/latest

Test location /workspace/coverage/default/0.otp_ctrl_regwen.2750805145
Short name T1154
Test name
Test status
Simulation time 292477744 ps
CPU time 10.03 seconds
Started Mar 21 03:26:58 PM PDT 24
Finished Mar 21 03:27:08 PM PDT 24
Peak memory 241348 kb
Host smart-d53a8a01-ea2e-46ce-b323-9acd75fd0f2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2750805145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.2750805145
Directory /workspace/0.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/0.otp_ctrl_sec_cm.3616310956
Short name T25
Test name
Test status
Simulation time 10550006745 ps
CPU time 190.43 seconds
Started Mar 21 03:26:59 PM PDT 24
Finished Mar 21 03:30:10 PM PDT 24
Peak memory 266088 kb
Host smart-5ac2be13-f1f1-49d4-8639-a0e42d5a4cbb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616310956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.3616310956
Directory /workspace/0.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.otp_ctrl_smoke.3408618985
Short name T970
Test name
Test status
Simulation time 256865215 ps
CPU time 7.47 seconds
Started Mar 21 03:27:00 PM PDT 24
Finished Mar 21 03:27:08 PM PDT 24
Peak memory 241612 kb
Host smart-4307e187-18e8-4db4-bb18-c01ff4dc5dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408618985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.3408618985
Directory /workspace/0.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all_with_rand_reset.3449075030
Short name T141
Test name
Test status
Simulation time 69638531111 ps
CPU time 1811.99 seconds
Started Mar 21 03:26:58 PM PDT 24
Finished Mar 21 03:57:11 PM PDT 24
Peak memory 284028 kb
Host smart-b743544b-f9ed-42a2-a3b9-60e1efc65cff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449075030 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all_with_rand_reset.3449075030
Directory /workspace/0.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.otp_ctrl_test_access.2175153583
Short name T291
Test name
Test status
Simulation time 3582724856 ps
CPU time 35.29 seconds
Started Mar 21 03:26:55 PM PDT 24
Finished Mar 21 03:27:30 PM PDT 24
Peak memory 241916 kb
Host smart-caedb5f7-a95e-4479-99be-16f0a94cbe88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175153583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.2175153583
Directory /workspace/0.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/0.otp_ctrl_wake_up.1802492764
Short name T479
Test name
Test status
Simulation time 199236405 ps
CPU time 1.88 seconds
Started Mar 21 03:27:01 PM PDT 24
Finished Mar 21 03:27:03 PM PDT 24
Peak memory 239940 kb
Host smart-bd9a9ef8-1569-497c-9fa3-3b4806d7dab9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1802492764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.1802492764
Directory /workspace/0.otp_ctrl_wake_up/latest

Test location /workspace/coverage/default/1.otp_ctrl_alert_test.2179980304
Short name T550
Test name
Test status
Simulation time 1031133310 ps
CPU time 2.4 seconds
Started Mar 21 03:26:56 PM PDT 24
Finished Mar 21 03:26:59 PM PDT 24
Peak memory 240148 kb
Host smart-7034b3bb-e107-4429-ab2a-ee75f017845e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179980304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.2179980304
Directory /workspace/1.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.otp_ctrl_background_chks.2907191731
Short name T862
Test name
Test status
Simulation time 17078178580 ps
CPU time 29.43 seconds
Started Mar 21 03:27:03 PM PDT 24
Finished Mar 21 03:27:33 PM PDT 24
Peak memory 242356 kb
Host smart-d823388f-c445-4ae8-ae13-e9fb0e104c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907191731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.2907191731
Directory /workspace/1.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/1.otp_ctrl_check_fail.1886447760
Short name T70
Test name
Test status
Simulation time 1036572796 ps
CPU time 10.74 seconds
Started Mar 21 03:27:04 PM PDT 24
Finished Mar 21 03:27:15 PM PDT 24
Peak memory 241892 kb
Host smart-5a8e4283-00c1-4769-a1c8-8251f6e12c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886447760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.1886447760
Directory /workspace/1.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_errs.3722985755
Short name T1127
Test name
Test status
Simulation time 663792795 ps
CPU time 18.42 seconds
Started Mar 21 03:26:59 PM PDT 24
Finished Mar 21 03:27:19 PM PDT 24
Peak memory 241276 kb
Host smart-0dd48a91-f8b7-4d49-aa0e-b46e0ce52474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722985755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.3722985755
Directory /workspace/1.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_lock.456479664
Short name T543
Test name
Test status
Simulation time 1838581261 ps
CPU time 37.78 seconds
Started Mar 21 03:27:00 PM PDT 24
Finished Mar 21 03:27:38 PM PDT 24
Peak memory 242404 kb
Host smart-85d0b7eb-b26d-4471-b151-aeeea353d9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456479664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.456479664
Directory /workspace/1.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/1.otp_ctrl_init_fail.2776807328
Short name T613
Test name
Test status
Simulation time 270839243 ps
CPU time 5.65 seconds
Started Mar 21 03:27:02 PM PDT 24
Finished Mar 21 03:27:08 PM PDT 24
Peak memory 241352 kb
Host smart-d3edfa55-fb57-4d3f-be87-2e64f0139336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776807328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.2776807328
Directory /workspace/1.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_macro_errs.1519594444
Short name T218
Test name
Test status
Simulation time 32331655990 ps
CPU time 301.18 seconds
Started Mar 21 03:26:56 PM PDT 24
Finished Mar 21 03:31:57 PM PDT 24
Peak memory 256692 kb
Host smart-b4e97869-3f8c-49f9-ade4-b2d9dc5ef234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519594444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.1519594444
Directory /workspace/1.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_key_req.2782914948
Short name T209
Test name
Test status
Simulation time 3495715927 ps
CPU time 61.05 seconds
Started Mar 21 03:27:02 PM PDT 24
Finished Mar 21 03:28:03 PM PDT 24
Peak memory 241764 kb
Host smart-553cead6-338e-467d-985d-853096334ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782914948 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.2782914948
Directory /workspace/1.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_esc.1550944048
Short name T154
Test name
Test status
Simulation time 292914068 ps
CPU time 5 seconds
Started Mar 21 03:26:59 PM PDT 24
Finished Mar 21 03:27:04 PM PDT 24
Peak memory 241676 kb
Host smart-274f0688-9834-4dd8-96c3-ea33f50047b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550944048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.1550944048
Directory /workspace/1.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_req.1186112760
Short name T102
Test name
Test status
Simulation time 1146228785 ps
CPU time 19.58 seconds
Started Mar 21 03:27:00 PM PDT 24
Finished Mar 21 03:27:20 PM PDT 24
Peak memory 241256 kb
Host smart-a112a9b9-ff51-4226-a1de-f0a841ff5c67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1186112760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.1186112760
Directory /workspace/1.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_sec_cm.406626222
Short name T27
Test name
Test status
Simulation time 12975978512 ps
CPU time 230.71 seconds
Started Mar 21 03:26:58 PM PDT 24
Finished Mar 21 03:30:49 PM PDT 24
Peak memory 274560 kb
Host smart-a7e742c4-4d8b-4210-ab51-1a8f160cceba
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406626222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.406626222
Directory /workspace/1.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.otp_ctrl_smoke.1631623754
Short name T1008
Test name
Test status
Simulation time 305186205 ps
CPU time 7.11 seconds
Started Mar 21 03:26:58 PM PDT 24
Finished Mar 21 03:27:05 PM PDT 24
Peak memory 241588 kb
Host smart-f091a674-77a8-4619-bf7a-64fb40631785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631623754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.1631623754
Directory /workspace/1.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all.3531412055
Short name T634
Test name
Test status
Simulation time 29485821451 ps
CPU time 117.28 seconds
Started Mar 21 03:27:01 PM PDT 24
Finished Mar 21 03:28:59 PM PDT 24
Peak memory 245704 kb
Host smart-2edb2224-6ae8-4111-ade5-625955d88498
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531412055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all.
3531412055
Directory /workspace/1.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.otp_ctrl_test_access.3089200182
Short name T1112
Test name
Test status
Simulation time 526183907 ps
CPU time 19.91 seconds
Started Mar 21 03:26:56 PM PDT 24
Finished Mar 21 03:27:16 PM PDT 24
Peak memory 242292 kb
Host smart-cf05fc80-94e8-4fc3-af66-facb75be1dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089200182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.3089200182
Directory /workspace/1.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/10.otp_ctrl_alert_test.4175856577
Short name T290
Test name
Test status
Simulation time 137568467 ps
CPU time 1.97 seconds
Started Mar 21 03:27:23 PM PDT 24
Finished Mar 21 03:27:25 PM PDT 24
Peak memory 240204 kb
Host smart-4268a3ef-93cd-4e15-a841-7af1c27ac63a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175856577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.4175856577
Directory /workspace/10.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.otp_ctrl_check_fail.1730471466
Short name T1149
Test name
Test status
Simulation time 457914707 ps
CPU time 16.38 seconds
Started Mar 21 03:27:29 PM PDT 24
Finished Mar 21 03:27:46 PM PDT 24
Peak memory 242204 kb
Host smart-3966e02a-1f83-4cb4-9034-9179e5710008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730471466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.1730471466
Directory /workspace/10.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_errs.1437263600
Short name T808
Test name
Test status
Simulation time 2580795393 ps
CPU time 26.43 seconds
Started Mar 21 03:27:26 PM PDT 24
Finished Mar 21 03:27:52 PM PDT 24
Peak memory 241400 kb
Host smart-6761b7f0-637e-4323-b950-a8d7691ff332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437263600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.1437263600
Directory /workspace/10.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_lock.2344144373
Short name T1036
Test name
Test status
Simulation time 18188711504 ps
CPU time 34.02 seconds
Started Mar 21 03:27:24 PM PDT 24
Finished Mar 21 03:27:58 PM PDT 24
Peak memory 241592 kb
Host smart-27cddb52-aabe-48b4-8c3c-7cbd10242fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344144373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.2344144373
Directory /workspace/10.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/10.otp_ctrl_init_fail.4235089798
Short name T1023
Test name
Test status
Simulation time 514922181 ps
CPU time 4.06 seconds
Started Mar 21 03:27:29 PM PDT 24
Finished Mar 21 03:27:33 PM PDT 24
Peak memory 240876 kb
Host smart-81e6cb4e-2bd5-4167-b093-cc4b14bbc510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235089798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.4235089798
Directory /workspace/10.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_macro_errs.3424760163
Short name T491
Test name
Test status
Simulation time 553916979 ps
CPU time 15.02 seconds
Started Mar 21 03:27:31 PM PDT 24
Finished Mar 21 03:27:46 PM PDT 24
Peak memory 244512 kb
Host smart-15792440-20f6-4148-9701-8457836eaa78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424760163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.3424760163
Directory /workspace/10.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_key_req.135201458
Short name T250
Test name
Test status
Simulation time 7301491619 ps
CPU time 20.66 seconds
Started Mar 21 03:27:23 PM PDT 24
Finished Mar 21 03:27:44 PM PDT 24
Peak memory 248368 kb
Host smart-1dda11dc-8661-414a-84a4-dd823af8190a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135201458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.135201458
Directory /workspace/10.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_esc.1806549608
Short name T603
Test name
Test status
Simulation time 114471978 ps
CPU time 4.51 seconds
Started Mar 21 03:27:31 PM PDT 24
Finished Mar 21 03:27:35 PM PDT 24
Peak memory 241164 kb
Host smart-5014cf1e-93fe-4107-80bb-83d3495b2487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806549608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.1806549608
Directory /workspace/10.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_req.3537364542
Short name T978
Test name
Test status
Simulation time 502366947 ps
CPU time 5.07 seconds
Started Mar 21 03:27:26 PM PDT 24
Finished Mar 21 03:27:31 PM PDT 24
Peak memory 241136 kb
Host smart-818b8626-dbe6-49b0-91db-df5a05a2f218
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3537364542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.3537364542
Directory /workspace/10.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_regwen.2303029574
Short name T1188
Test name
Test status
Simulation time 387563987 ps
CPU time 10.63 seconds
Started Mar 21 03:27:33 PM PDT 24
Finished Mar 21 03:27:44 PM PDT 24
Peak memory 241636 kb
Host smart-3dd453e6-ffe9-4fec-ad29-7bd88ce902f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2303029574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.2303029574
Directory /workspace/10.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/10.otp_ctrl_smoke.282857002
Short name T757
Test name
Test status
Simulation time 755440776 ps
CPU time 9.57 seconds
Started Mar 21 03:27:31 PM PDT 24
Finished Mar 21 03:27:41 PM PDT 24
Peak memory 241184 kb
Host smart-a7faa275-d6c0-487e-817f-36b3e13519a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282857002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.282857002
Directory /workspace/10.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all.4278219254
Short name T362
Test name
Test status
Simulation time 8399426755 ps
CPU time 167.36 seconds
Started Mar 21 03:27:25 PM PDT 24
Finished Mar 21 03:30:12 PM PDT 24
Peak memory 256556 kb
Host smart-39970a61-a1e8-4fb7-961e-bdb47c89ebec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278219254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all
.4278219254
Directory /workspace/10.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all_with_rand_reset.3749514780
Short name T541
Test name
Test status
Simulation time 29712490332 ps
CPU time 538.68 seconds
Started Mar 21 03:27:24 PM PDT 24
Finished Mar 21 03:36:23 PM PDT 24
Peak memory 256696 kb
Host smart-9287ace2-1511-40fa-8db0-817b65d48fa3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749514780 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all_with_rand_reset.3749514780
Directory /workspace/10.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.otp_ctrl_test_access.825264517
Short name T1078
Test name
Test status
Simulation time 1621605517 ps
CPU time 31.22 seconds
Started Mar 21 03:27:27 PM PDT 24
Finished Mar 21 03:27:58 PM PDT 24
Peak memory 242200 kb
Host smart-a0da7dc3-429e-48da-9cae-f37339672175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825264517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.825264517
Directory /workspace/10.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/100.otp_ctrl_parallel_lc_esc.796203184
Short name T720
Test name
Test status
Simulation time 281906267 ps
CPU time 7.71 seconds
Started Mar 21 03:29:58 PM PDT 24
Finished Mar 21 03:30:06 PM PDT 24
Peak memory 241396 kb
Host smart-878bb7ef-32b8-4459-af00-ddba97923456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796203184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.796203184
Directory /workspace/100.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/101.otp_ctrl_init_fail.3478176966
Short name T1198
Test name
Test status
Simulation time 113521243 ps
CPU time 3.37 seconds
Started Mar 21 03:29:59 PM PDT 24
Finished Mar 21 03:30:03 PM PDT 24
Peak memory 241668 kb
Host smart-3b172fd1-5edf-4a23-9c8c-e5ef0ead0d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478176966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.3478176966
Directory /workspace/101.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/101.otp_ctrl_parallel_lc_esc.3782809875
Short name T152
Test name
Test status
Simulation time 377933937 ps
CPU time 10.27 seconds
Started Mar 21 03:30:12 PM PDT 24
Finished Mar 21 03:30:23 PM PDT 24
Peak memory 241312 kb
Host smart-6ca14cef-510e-4a2b-bbee-b249fdf0cd1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782809875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.3782809875
Directory /workspace/101.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/102.otp_ctrl_init_fail.3951195521
Short name T326
Test name
Test status
Simulation time 467469017 ps
CPU time 4.1 seconds
Started Mar 21 03:30:04 PM PDT 24
Finished Mar 21 03:30:09 PM PDT 24
Peak memory 241284 kb
Host smart-8495f474-677a-409f-a3c9-468eeb957b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951195521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.3951195521
Directory /workspace/102.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/102.otp_ctrl_parallel_lc_esc.1477733295
Short name T936
Test name
Test status
Simulation time 1151811994 ps
CPU time 3.68 seconds
Started Mar 21 03:30:00 PM PDT 24
Finished Mar 21 03:30:04 PM PDT 24
Peak memory 241140 kb
Host smart-e75bb069-a043-4e9e-8f41-90a2cfb4e933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477733295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.1477733295
Directory /workspace/102.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/103.otp_ctrl_init_fail.2571714820
Short name T990
Test name
Test status
Simulation time 301720835 ps
CPU time 4.25 seconds
Started Mar 21 03:30:07 PM PDT 24
Finished Mar 21 03:30:12 PM PDT 24
Peak memory 241668 kb
Host smart-7932932f-a741-4115-a0db-7461f3516a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571714820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.2571714820
Directory /workspace/103.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/103.otp_ctrl_parallel_lc_esc.1825548767
Short name T820
Test name
Test status
Simulation time 770728059 ps
CPU time 10.57 seconds
Started Mar 21 03:30:02 PM PDT 24
Finished Mar 21 03:30:13 PM PDT 24
Peak memory 241208 kb
Host smart-df1b62dc-fcae-4e7f-b822-07d80e704a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825548767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.1825548767
Directory /workspace/103.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/104.otp_ctrl_init_fail.3703306153
Short name T949
Test name
Test status
Simulation time 332269671 ps
CPU time 5.23 seconds
Started Mar 21 03:30:12 PM PDT 24
Finished Mar 21 03:30:17 PM PDT 24
Peak memory 241396 kb
Host smart-87ae6acd-a173-41fb-b801-92bf7d3e8296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703306153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.3703306153
Directory /workspace/104.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/105.otp_ctrl_init_fail.1734524218
Short name T1179
Test name
Test status
Simulation time 2225267264 ps
CPU time 7 seconds
Started Mar 21 03:30:08 PM PDT 24
Finished Mar 21 03:30:16 PM PDT 24
Peak memory 241844 kb
Host smart-33e7d334-455b-4fa7-bf28-a33ae2b6f855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734524218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.1734524218
Directory /workspace/105.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/105.otp_ctrl_parallel_lc_esc.1448360750
Short name T731
Test name
Test status
Simulation time 327434905 ps
CPU time 3.82 seconds
Started Mar 21 03:30:00 PM PDT 24
Finished Mar 21 03:30:04 PM PDT 24
Peak memory 241456 kb
Host smart-ae6d8926-a389-4a2d-981c-69febf4e7beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448360750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.1448360750
Directory /workspace/105.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/106.otp_ctrl_init_fail.2045021570
Short name T965
Test name
Test status
Simulation time 436881728 ps
CPU time 3.75 seconds
Started Mar 21 03:30:12 PM PDT 24
Finished Mar 21 03:30:16 PM PDT 24
Peak memory 241468 kb
Host smart-54627c8c-fdd7-4df4-b7aa-06361b550def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045021570 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.2045021570
Directory /workspace/106.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/106.otp_ctrl_parallel_lc_esc.989206123
Short name T355
Test name
Test status
Simulation time 1516847701 ps
CPU time 6.48 seconds
Started Mar 21 03:30:12 PM PDT 24
Finished Mar 21 03:30:19 PM PDT 24
Peak memory 241636 kb
Host smart-698c3543-f24d-4aa9-ac68-8fcc1787254d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989206123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.989206123
Directory /workspace/106.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/107.otp_ctrl_init_fail.265291812
Short name T1132
Test name
Test status
Simulation time 342237719 ps
CPU time 4.99 seconds
Started Mar 21 03:30:04 PM PDT 24
Finished Mar 21 03:30:10 PM PDT 24
Peak memory 241152 kb
Host smart-5b7a6ced-1576-47c6-8bc9-0db75743c1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265291812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.265291812
Directory /workspace/107.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/107.otp_ctrl_parallel_lc_esc.4038687166
Short name T358
Test name
Test status
Simulation time 93099745 ps
CPU time 3.41 seconds
Started Mar 21 03:30:09 PM PDT 24
Finished Mar 21 03:30:13 PM PDT 24
Peak memory 241268 kb
Host smart-37299afc-a85c-48f8-a2cc-7fea41655902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038687166 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.4038687166
Directory /workspace/107.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/108.otp_ctrl_init_fail.3407344933
Short name T78
Test name
Test status
Simulation time 538586196 ps
CPU time 3.81 seconds
Started Mar 21 03:30:02 PM PDT 24
Finished Mar 21 03:30:06 PM PDT 24
Peak memory 241452 kb
Host smart-7f8ea9e7-a601-41d9-a31d-2c5552053a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407344933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.3407344933
Directory /workspace/108.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/108.otp_ctrl_parallel_lc_esc.3670967571
Short name T719
Test name
Test status
Simulation time 599464104 ps
CPU time 5.18 seconds
Started Mar 21 03:30:12 PM PDT 24
Finished Mar 21 03:30:17 PM PDT 24
Peak memory 241288 kb
Host smart-f4d6bd73-4052-47c5-9d0d-b1bb3802723e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670967571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.3670967571
Directory /workspace/108.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/109.otp_ctrl_init_fail.1799878136
Short name T909
Test name
Test status
Simulation time 330751884 ps
CPU time 4.4 seconds
Started Mar 21 03:30:08 PM PDT 24
Finished Mar 21 03:30:13 PM PDT 24
Peak memory 241268 kb
Host smart-b5f256ec-f4fd-4552-8d99-e584679d394b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799878136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.1799878136
Directory /workspace/109.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/109.otp_ctrl_parallel_lc_esc.2940007239
Short name T267
Test name
Test status
Simulation time 192156934 ps
CPU time 4.18 seconds
Started Mar 21 03:30:06 PM PDT 24
Finished Mar 21 03:30:11 PM PDT 24
Peak memory 241200 kb
Host smart-b671c4e6-1918-465d-a16a-8651b4f27c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940007239 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.2940007239
Directory /workspace/109.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_alert_test.357009792
Short name T1126
Test name
Test status
Simulation time 85479321 ps
CPU time 2.29 seconds
Started Mar 21 03:27:26 PM PDT 24
Finished Mar 21 03:27:28 PM PDT 24
Peak memory 240104 kb
Host smart-d0c91bb9-633a-425d-8b9e-85102ac32822
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357009792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.357009792
Directory /workspace/11.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.otp_ctrl_check_fail.2745139403
Short name T651
Test name
Test status
Simulation time 1208964598 ps
CPU time 15.38 seconds
Started Mar 21 03:27:26 PM PDT 24
Finished Mar 21 03:27:41 PM PDT 24
Peak memory 248220 kb
Host smart-82af42be-96ab-420a-bba0-244a47e934d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745139403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.2745139403
Directory /workspace/11.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_errs.1620409062
Short name T951
Test name
Test status
Simulation time 1614133113 ps
CPU time 28.75 seconds
Started Mar 21 03:27:24 PM PDT 24
Finished Mar 21 03:27:53 PM PDT 24
Peak memory 241696 kb
Host smart-71e9b00a-8405-44fe-b5c3-be85a3807737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620409062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.1620409062
Directory /workspace/11.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_lock.3745821694
Short name T624
Test name
Test status
Simulation time 1336838876 ps
CPU time 25.15 seconds
Started Mar 21 03:27:25 PM PDT 24
Finished Mar 21 03:27:50 PM PDT 24
Peak memory 241748 kb
Host smart-4ba82d56-38fe-48f3-b3d2-911abc0cd5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745821694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.3745821694
Directory /workspace/11.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/11.otp_ctrl_init_fail.3671355861
Short name T712
Test name
Test status
Simulation time 117804022 ps
CPU time 4.39 seconds
Started Mar 21 03:27:23 PM PDT 24
Finished Mar 21 03:27:28 PM PDT 24
Peak memory 241324 kb
Host smart-4cbb7afb-19ed-44e8-b8fd-cc5adc3243f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671355861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.3671355861
Directory /workspace/11.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_macro_errs.525389207
Short name T544
Test name
Test status
Simulation time 23065957140 ps
CPU time 51.92 seconds
Started Mar 21 03:27:26 PM PDT 24
Finished Mar 21 03:28:18 PM PDT 24
Peak memory 256952 kb
Host smart-afe07e99-a9ef-4a23-8338-5d3b461c4293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525389207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.525389207
Directory /workspace/11.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_key_req.105810546
Short name T1040
Test name
Test status
Simulation time 592039239 ps
CPU time 12.55 seconds
Started Mar 21 03:27:26 PM PDT 24
Finished Mar 21 03:27:38 PM PDT 24
Peak memory 241424 kb
Host smart-7ded05a5-619b-4c97-9ccf-528a8338d458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105810546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.105810546
Directory /workspace/11.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_esc.697941759
Short name T535
Test name
Test status
Simulation time 151080937 ps
CPU time 4.45 seconds
Started Mar 21 03:27:30 PM PDT 24
Finished Mar 21 03:27:35 PM PDT 24
Peak memory 241328 kb
Host smart-b205f2dc-b030-4ebb-9c45-1ddad8336b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697941759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.697941759
Directory /workspace/11.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_req.901479921
Short name T427
Test name
Test status
Simulation time 605484439 ps
CPU time 5.8 seconds
Started Mar 21 03:27:31 PM PDT 24
Finished Mar 21 03:27:37 PM PDT 24
Peak memory 241240 kb
Host smart-5ed51e82-61b5-45cc-b325-bc1e32721853
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=901479921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.901479921
Directory /workspace/11.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_regwen.2481781705
Short name T806
Test name
Test status
Simulation time 183262463 ps
CPU time 4.81 seconds
Started Mar 21 03:27:24 PM PDT 24
Finished Mar 21 03:27:29 PM PDT 24
Peak memory 241432 kb
Host smart-15decd8a-5ab7-41ea-966a-3bd91e3a3bbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2481781705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.2481781705
Directory /workspace/11.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/11.otp_ctrl_smoke.3853747197
Short name T439
Test name
Test status
Simulation time 1635132747 ps
CPU time 9.06 seconds
Started Mar 21 03:27:24 PM PDT 24
Finished Mar 21 03:27:33 PM PDT 24
Peak memory 241372 kb
Host smart-a4d228fd-9741-4f75-baa9-062da08b0108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853747197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.3853747197
Directory /workspace/11.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all.3377550072
Short name T672
Test name
Test status
Simulation time 26955518735 ps
CPU time 233.25 seconds
Started Mar 21 03:27:29 PM PDT 24
Finished Mar 21 03:31:22 PM PDT 24
Peak memory 256992 kb
Host smart-7d4e71c5-8a9e-48c5-80f0-ea11a7dd532d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377550072 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all
.3377550072
Directory /workspace/11.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all_with_rand_reset.567903342
Short name T653
Test name
Test status
Simulation time 108102742419 ps
CPU time 1274.56 seconds
Started Mar 21 03:27:35 PM PDT 24
Finished Mar 21 03:48:50 PM PDT 24
Peak memory 385596 kb
Host smart-1e54c00b-3820-4dd6-83ee-b9a110b06975
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567903342 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all_with_rand_reset.567903342
Directory /workspace/11.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.otp_ctrl_test_access.611382046
Short name T612
Test name
Test status
Simulation time 1659771805 ps
CPU time 11.96 seconds
Started Mar 21 03:27:34 PM PDT 24
Finished Mar 21 03:27:46 PM PDT 24
Peak memory 241360 kb
Host smart-ac9eed4e-4c38-4cf5-a15b-fdbf9934e7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611382046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.611382046
Directory /workspace/11.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/110.otp_ctrl_init_fail.892491816
Short name T656
Test name
Test status
Simulation time 129338447 ps
CPU time 3.69 seconds
Started Mar 21 03:30:06 PM PDT 24
Finished Mar 21 03:30:10 PM PDT 24
Peak memory 241376 kb
Host smart-3a7e0bca-12d5-449b-b474-a9ede025b9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892491816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.892491816
Directory /workspace/110.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/110.otp_ctrl_parallel_lc_esc.182631710
Short name T1140
Test name
Test status
Simulation time 96711877 ps
CPU time 3.45 seconds
Started Mar 21 03:30:09 PM PDT 24
Finished Mar 21 03:30:13 PM PDT 24
Peak memory 241436 kb
Host smart-4c93851d-9998-4986-ab49-d10a2da467c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182631710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.182631710
Directory /workspace/110.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/111.otp_ctrl_init_fail.2260033826
Short name T241
Test name
Test status
Simulation time 497357335 ps
CPU time 4.58 seconds
Started Mar 21 03:30:10 PM PDT 24
Finished Mar 21 03:30:15 PM PDT 24
Peak memory 241704 kb
Host smart-a797fa9e-2394-4798-bee0-daeddf50c801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260033826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.2260033826
Directory /workspace/111.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/111.otp_ctrl_parallel_lc_esc.692389497
Short name T1128
Test name
Test status
Simulation time 159305347 ps
CPU time 4.44 seconds
Started Mar 21 03:30:10 PM PDT 24
Finished Mar 21 03:30:15 PM PDT 24
Peak memory 241692 kb
Host smart-3ad752c5-e59c-43c7-9e21-c29cbf6aeb93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692389497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.692389497
Directory /workspace/111.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/112.otp_ctrl_init_fail.417117362
Short name T802
Test name
Test status
Simulation time 121898995 ps
CPU time 4.98 seconds
Started Mar 21 03:30:08 PM PDT 24
Finished Mar 21 03:30:14 PM PDT 24
Peak memory 241752 kb
Host smart-d6bcbf61-389e-4e7b-8281-67fdf960592d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417117362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.417117362
Directory /workspace/112.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/112.otp_ctrl_parallel_lc_esc.2397382552
Short name T189
Test name
Test status
Simulation time 109282260 ps
CPU time 4.07 seconds
Started Mar 21 03:30:06 PM PDT 24
Finished Mar 21 03:30:11 PM PDT 24
Peak memory 241320 kb
Host smart-7402ce4d-b219-4377-8d10-32380b24b831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397382552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.2397382552
Directory /workspace/112.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/113.otp_ctrl_init_fail.3336112186
Short name T913
Test name
Test status
Simulation time 137034576 ps
CPU time 3.37 seconds
Started Mar 21 03:30:02 PM PDT 24
Finished Mar 21 03:30:06 PM PDT 24
Peak memory 241472 kb
Host smart-39d13c67-8c62-46d6-8742-de5ffec3b619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336112186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.3336112186
Directory /workspace/113.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/113.otp_ctrl_parallel_lc_esc.1650432335
Short name T520
Test name
Test status
Simulation time 11259661971 ps
CPU time 37.37 seconds
Started Mar 21 03:30:07 PM PDT 24
Finished Mar 21 03:30:45 PM PDT 24
Peak memory 241432 kb
Host smart-8be914d7-3d53-4de2-8b47-2572f5dbe025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650432335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.1650432335
Directory /workspace/113.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/114.otp_ctrl_parallel_lc_esc.3014147703
Short name T1065
Test name
Test status
Simulation time 876221807 ps
CPU time 14.4 seconds
Started Mar 21 03:30:06 PM PDT 24
Finished Mar 21 03:30:21 PM PDT 24
Peak memory 241392 kb
Host smart-25ba7c34-4654-4c44-aa22-12973498ce3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014147703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.3014147703
Directory /workspace/114.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/115.otp_ctrl_init_fail.2493895824
Short name T859
Test name
Test status
Simulation time 168377031 ps
CPU time 4.71 seconds
Started Mar 21 03:30:03 PM PDT 24
Finished Mar 21 03:30:08 PM PDT 24
Peak memory 241600 kb
Host smart-cf9e1243-31cf-4c45-a069-9e82b05dc927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493895824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.2493895824
Directory /workspace/115.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/115.otp_ctrl_parallel_lc_esc.3457197652
Short name T538
Test name
Test status
Simulation time 1090781626 ps
CPU time 24.67 seconds
Started Mar 21 03:30:04 PM PDT 24
Finished Mar 21 03:30:30 PM PDT 24
Peak memory 241336 kb
Host smart-ad3fe0e7-bdab-4301-805d-f22433612ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457197652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.3457197652
Directory /workspace/115.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/116.otp_ctrl_init_fail.2658707979
Short name T1062
Test name
Test status
Simulation time 352910272 ps
CPU time 4.39 seconds
Started Mar 21 03:30:06 PM PDT 24
Finished Mar 21 03:30:12 PM PDT 24
Peak memory 241676 kb
Host smart-1e8d8f6d-72ea-4194-9af8-1f923a55c4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658707979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.2658707979
Directory /workspace/116.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/116.otp_ctrl_parallel_lc_esc.428289302
Short name T755
Test name
Test status
Simulation time 148731709 ps
CPU time 5.67 seconds
Started Mar 21 03:30:16 PM PDT 24
Finished Mar 21 03:30:22 PM PDT 24
Peak memory 241164 kb
Host smart-bf54d123-a604-412d-834e-677a477748ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428289302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.428289302
Directory /workspace/116.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/117.otp_ctrl_init_fail.3827694337
Short name T558
Test name
Test status
Simulation time 244064789 ps
CPU time 4.73 seconds
Started Mar 21 03:30:12 PM PDT 24
Finished Mar 21 03:30:17 PM PDT 24
Peak memory 241316 kb
Host smart-ca5d30ff-00f6-46c8-bc2e-e66f28bee94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827694337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.3827694337
Directory /workspace/117.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/117.otp_ctrl_parallel_lc_esc.208181296
Short name T1098
Test name
Test status
Simulation time 262514941 ps
CPU time 4.8 seconds
Started Mar 21 03:30:16 PM PDT 24
Finished Mar 21 03:30:22 PM PDT 24
Peak memory 241188 kb
Host smart-922bef53-d6ac-441d-9085-e9275e4837bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208181296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.208181296
Directory /workspace/117.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/118.otp_ctrl_parallel_lc_esc.2681328619
Short name T677
Test name
Test status
Simulation time 292100148 ps
CPU time 8.92 seconds
Started Mar 21 03:30:19 PM PDT 24
Finished Mar 21 03:30:29 PM PDT 24
Peak memory 241728 kb
Host smart-a629a2ee-1151-4c47-8c80-c82bc0eb11f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681328619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.2681328619
Directory /workspace/118.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/119.otp_ctrl_init_fail.2861025543
Short name T589
Test name
Test status
Simulation time 2230060836 ps
CPU time 5.77 seconds
Started Mar 21 03:30:12 PM PDT 24
Finished Mar 21 03:30:18 PM PDT 24
Peak memory 241840 kb
Host smart-67beaeae-9e8c-45be-ace9-826dfec51069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861025543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.2861025543
Directory /workspace/119.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/119.otp_ctrl_parallel_lc_esc.227287111
Short name T159
Test name
Test status
Simulation time 1396495147 ps
CPU time 11.21 seconds
Started Mar 21 03:30:12 PM PDT 24
Finished Mar 21 03:30:24 PM PDT 24
Peak memory 241692 kb
Host smart-80851a0b-64bb-429b-83ce-17d182e3a8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227287111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.227287111
Directory /workspace/119.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_alert_test.122556401
Short name T721
Test name
Test status
Simulation time 77166427 ps
CPU time 2.18 seconds
Started Mar 21 03:27:30 PM PDT 24
Finished Mar 21 03:27:33 PM PDT 24
Peak memory 239868 kb
Host smart-5cbe1161-c681-4980-8037-0ad853afe8a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122556401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.122556401
Directory /workspace/12.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_errs.4211877185
Short name T817
Test name
Test status
Simulation time 5001930597 ps
CPU time 34.92 seconds
Started Mar 21 03:27:24 PM PDT 24
Finished Mar 21 03:27:59 PM PDT 24
Peak memory 247940 kb
Host smart-900aa65e-f129-48e7-a3c2-4e25766dfdfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211877185 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.4211877185
Directory /workspace/12.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_lock.3086580081
Short name T1174
Test name
Test status
Simulation time 10531260154 ps
CPU time 20.03 seconds
Started Mar 21 03:27:28 PM PDT 24
Finished Mar 21 03:27:49 PM PDT 24
Peak memory 242032 kb
Host smart-e9481d3a-ce06-4dd6-8449-f7b47234bb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086580081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.3086580081
Directory /workspace/12.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/12.otp_ctrl_init_fail.3879575211
Short name T1052
Test name
Test status
Simulation time 162984935 ps
CPU time 4.44 seconds
Started Mar 21 03:27:35 PM PDT 24
Finished Mar 21 03:27:40 PM PDT 24
Peak memory 241356 kb
Host smart-f0d60183-2ce1-4b01-a68d-683a480577eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879575211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.3879575211
Directory /workspace/12.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_macro_errs.1644301356
Short name T819
Test name
Test status
Simulation time 4077533668 ps
CPU time 35.89 seconds
Started Mar 21 03:27:26 PM PDT 24
Finished Mar 21 03:28:02 PM PDT 24
Peak memory 245940 kb
Host smart-d3b16d24-8591-4f37-9d90-f70d05cbdc02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644301356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.1644301356
Directory /workspace/12.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_key_req.3395398420
Short name T1139
Test name
Test status
Simulation time 1057376955 ps
CPU time 15.08 seconds
Started Mar 21 03:27:34 PM PDT 24
Finished Mar 21 03:27:49 PM PDT 24
Peak memory 241692 kb
Host smart-682392c1-5a11-42cc-89bc-65600414f29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395398420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.3395398420
Directory /workspace/12.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_req.606829335
Short name T916
Test name
Test status
Simulation time 6669187874 ps
CPU time 23.08 seconds
Started Mar 21 03:27:30 PM PDT 24
Finished Mar 21 03:27:54 PM PDT 24
Peak memory 241244 kb
Host smart-db7f5420-f554-4915-8b97-f63a05c0c91d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=606829335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.606829335
Directory /workspace/12.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_regwen.1564803008
Short name T1129
Test name
Test status
Simulation time 700216424 ps
CPU time 7.56 seconds
Started Mar 21 03:27:26 PM PDT 24
Finished Mar 21 03:27:34 PM PDT 24
Peak memory 241352 kb
Host smart-3f2cfa89-55ab-4660-beac-5141a366c868
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1564803008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.1564803008
Directory /workspace/12.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/12.otp_ctrl_smoke.2801200643
Short name T743
Test name
Test status
Simulation time 3586404642 ps
CPU time 10.23 seconds
Started Mar 21 03:27:26 PM PDT 24
Finished Mar 21 03:27:36 PM PDT 24
Peak memory 241468 kb
Host smart-070e80a5-0617-4e12-b73c-e3aa420be8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801200643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.2801200643
Directory /workspace/12.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all.627059258
Short name T1094
Test name
Test status
Simulation time 4459157858 ps
CPU time 88.51 seconds
Started Mar 21 03:27:36 PM PDT 24
Finished Mar 21 03:29:04 PM PDT 24
Peak memory 246828 kb
Host smart-17f26a33-f71b-4525-af63-e6c7cc86a084
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627059258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all.
627059258
Directory /workspace/12.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all_with_rand_reset.140417085
Short name T835
Test name
Test status
Simulation time 66531543928 ps
CPU time 626.76 seconds
Started Mar 21 03:27:28 PM PDT 24
Finished Mar 21 03:37:55 PM PDT 24
Peak memory 271152 kb
Host smart-c93d384b-ad07-4359-ba42-2e4cc16ae0ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140417085 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all_with_rand_reset.140417085
Directory /workspace/12.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.otp_ctrl_test_access.1222197933
Short name T950
Test name
Test status
Simulation time 775270690 ps
CPU time 12.36 seconds
Started Mar 21 03:27:24 PM PDT 24
Finished Mar 21 03:27:37 PM PDT 24
Peak memory 241356 kb
Host smart-43936f7a-36ff-4b94-984b-f4a02f97a6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222197933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.1222197933
Directory /workspace/12.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/121.otp_ctrl_init_fail.3743124935
Short name T83
Test name
Test status
Simulation time 239449323 ps
CPU time 3.56 seconds
Started Mar 21 03:30:10 PM PDT 24
Finished Mar 21 03:30:14 PM PDT 24
Peak memory 241368 kb
Host smart-c8435a84-2707-4359-82e8-4f5099cc9ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743124935 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.3743124935
Directory /workspace/121.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/121.otp_ctrl_parallel_lc_esc.3865629402
Short name T579
Test name
Test status
Simulation time 473266422 ps
CPU time 7.06 seconds
Started Mar 21 03:30:13 PM PDT 24
Finished Mar 21 03:30:20 PM PDT 24
Peak memory 241216 kb
Host smart-7469fe7e-7209-4325-b442-9e358eafdcc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865629402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.3865629402
Directory /workspace/121.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/122.otp_ctrl_init_fail.141310534
Short name T1025
Test name
Test status
Simulation time 108341298 ps
CPU time 3.77 seconds
Started Mar 21 03:30:14 PM PDT 24
Finished Mar 21 03:30:18 PM PDT 24
Peak memory 241668 kb
Host smart-403e8c2a-96aa-44a6-a44d-4204ab57e392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141310534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.141310534
Directory /workspace/122.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/122.otp_ctrl_parallel_lc_esc.3524463574
Short name T1137
Test name
Test status
Simulation time 200593464 ps
CPU time 4.21 seconds
Started Mar 21 03:30:10 PM PDT 24
Finished Mar 21 03:30:15 PM PDT 24
Peak memory 241276 kb
Host smart-136813d7-3178-4dd7-b3eb-8af61e5ddd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524463574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.3524463574
Directory /workspace/122.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/123.otp_ctrl_parallel_lc_esc.3091459281
Short name T943
Test name
Test status
Simulation time 3298509143 ps
CPU time 11.17 seconds
Started Mar 21 03:30:17 PM PDT 24
Finished Mar 21 03:30:29 PM PDT 24
Peak memory 241864 kb
Host smart-89a65ff5-bf9d-496f-b1d2-42378a5c9a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091459281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.3091459281
Directory /workspace/123.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/124.otp_ctrl_parallel_lc_esc.620470201
Short name T211
Test name
Test status
Simulation time 274250664 ps
CPU time 8.3 seconds
Started Mar 21 03:30:14 PM PDT 24
Finished Mar 21 03:30:23 PM PDT 24
Peak memory 241328 kb
Host smart-c3875acf-4d46-485a-875b-ca03df1477d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620470201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.620470201
Directory /workspace/124.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/125.otp_ctrl_init_fail.2524788711
Short name T1001
Test name
Test status
Simulation time 99806144 ps
CPU time 3.9 seconds
Started Mar 21 03:30:17 PM PDT 24
Finished Mar 21 03:30:21 PM PDT 24
Peak memory 241696 kb
Host smart-63cb0b49-fba5-4d83-8199-bf02c76a73ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524788711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.2524788711
Directory /workspace/125.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/126.otp_ctrl_init_fail.2654328647
Short name T1164
Test name
Test status
Simulation time 125070709 ps
CPU time 3.76 seconds
Started Mar 21 03:30:12 PM PDT 24
Finished Mar 21 03:30:15 PM PDT 24
Peak memory 241464 kb
Host smart-4564512d-384b-465b-a796-47b870f0d73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654328647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.2654328647
Directory /workspace/126.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/126.otp_ctrl_parallel_lc_esc.3063542271
Short name T849
Test name
Test status
Simulation time 277061123 ps
CPU time 4.41 seconds
Started Mar 21 03:30:19 PM PDT 24
Finished Mar 21 03:30:24 PM PDT 24
Peak memory 241316 kb
Host smart-7417d1da-a78d-4fb0-9b24-2769e46720b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063542271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.3063542271
Directory /workspace/126.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/127.otp_ctrl_init_fail.2477829925
Short name T449
Test name
Test status
Simulation time 248087701 ps
CPU time 3.54 seconds
Started Mar 21 03:30:15 PM PDT 24
Finished Mar 21 03:30:18 PM PDT 24
Peak memory 241664 kb
Host smart-d90db31e-7d1f-4914-9638-e5481e172944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477829925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.2477829925
Directory /workspace/127.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/127.otp_ctrl_parallel_lc_esc.2195803720
Short name T865
Test name
Test status
Simulation time 247639454 ps
CPU time 6.93 seconds
Started Mar 21 03:30:13 PM PDT 24
Finished Mar 21 03:30:20 PM PDT 24
Peak memory 241204 kb
Host smart-ae355fe7-b1be-41cd-9c48-eb299dc9edba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195803720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.2195803720
Directory /workspace/127.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/128.otp_ctrl_parallel_lc_esc.3509076470
Short name T161
Test name
Test status
Simulation time 285289192 ps
CPU time 3.9 seconds
Started Mar 21 03:30:11 PM PDT 24
Finished Mar 21 03:30:16 PM PDT 24
Peak memory 241540 kb
Host smart-efb7ce85-d93e-43df-a1c8-4bebe1cf86b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509076470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.3509076470
Directory /workspace/128.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/129.otp_ctrl_init_fail.2475642846
Short name T59
Test name
Test status
Simulation time 252499068 ps
CPU time 4.47 seconds
Started Mar 21 03:30:14 PM PDT 24
Finished Mar 21 03:30:18 PM PDT 24
Peak memory 241348 kb
Host smart-52c3070f-d50b-4eaa-9b29-9140b47f43dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475642846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.2475642846
Directory /workspace/129.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/129.otp_ctrl_parallel_lc_esc.1475831312
Short name T443
Test name
Test status
Simulation time 423269180 ps
CPU time 9.82 seconds
Started Mar 21 03:30:13 PM PDT 24
Finished Mar 21 03:30:22 PM PDT 24
Peak memory 241328 kb
Host smart-b56961d3-841e-4926-ab07-9daf83ee50c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475831312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.1475831312
Directory /workspace/129.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_alert_test.4047000409
Short name T1049
Test name
Test status
Simulation time 46941056 ps
CPU time 1.69 seconds
Started Mar 21 03:27:43 PM PDT 24
Finished Mar 21 03:27:44 PM PDT 24
Peak memory 240196 kb
Host smart-d1674425-d1b2-48a8-9cd8-10fd69b8b624
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047000409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.4047000409
Directory /workspace/13.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.otp_ctrl_check_fail.1918970318
Short name T111
Test name
Test status
Simulation time 2174399556 ps
CPU time 26.1 seconds
Started Mar 21 03:27:42 PM PDT 24
Finished Mar 21 03:28:08 PM PDT 24
Peak memory 243524 kb
Host smart-4c56659f-b911-4765-adfa-1c93d13bbc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918970318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.1918970318
Directory /workspace/13.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_errs.382198729
Short name T1161
Test name
Test status
Simulation time 4798143618 ps
CPU time 22.69 seconds
Started Mar 21 03:27:40 PM PDT 24
Finished Mar 21 03:28:03 PM PDT 24
Peak memory 241644 kb
Host smart-f2149d58-0e1c-467c-aa0b-e5deae4e9285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382198729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.382198729
Directory /workspace/13.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_lock.3286156712
Short name T505
Test name
Test status
Simulation time 130913715 ps
CPU time 5.12 seconds
Started Mar 21 03:27:28 PM PDT 24
Finished Mar 21 03:27:34 PM PDT 24
Peak memory 241488 kb
Host smart-b2390fbd-4553-4df2-a7c7-dd2d01807d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286156712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.3286156712
Directory /workspace/13.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/13.otp_ctrl_macro_errs.2652845201
Short name T305
Test name
Test status
Simulation time 2273171599 ps
CPU time 23.92 seconds
Started Mar 21 03:27:43 PM PDT 24
Finished Mar 21 03:28:07 PM PDT 24
Peak memory 246948 kb
Host smart-f2c053ce-ba62-4ac0-9eca-885be58ad2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652845201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.2652845201
Directory /workspace/13.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_key_req.4203446645
Short name T412
Test name
Test status
Simulation time 247813215 ps
CPU time 7.07 seconds
Started Mar 21 03:27:44 PM PDT 24
Finished Mar 21 03:27:51 PM PDT 24
Peak memory 241272 kb
Host smart-3ec4fc99-15f8-41e2-9aae-566ec8e20bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203446645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.4203446645
Directory /workspace/13.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_esc.955988668
Short name T499
Test name
Test status
Simulation time 914643663 ps
CPU time 7.35 seconds
Started Mar 21 03:27:25 PM PDT 24
Finished Mar 21 03:27:33 PM PDT 24
Peak memory 241396 kb
Host smart-30c46332-b7b9-4dcb-a3db-ea2f8d7eee1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955988668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.955988668
Directory /workspace/13.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_req.1652104800
Short name T496
Test name
Test status
Simulation time 4951253871 ps
CPU time 13.02 seconds
Started Mar 21 03:27:23 PM PDT 24
Finished Mar 21 03:27:37 PM PDT 24
Peak memory 241312 kb
Host smart-f55ede02-b414-409e-a171-e63dc04f7cc3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1652104800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.1652104800
Directory /workspace/13.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_regwen.1590179077
Short name T754
Test name
Test status
Simulation time 656985798 ps
CPU time 6.75 seconds
Started Mar 21 03:27:41 PM PDT 24
Finished Mar 21 03:27:48 PM PDT 24
Peak memory 241680 kb
Host smart-3f4d34f4-3913-4c2a-9b63-feb3b08455e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1590179077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.1590179077
Directory /workspace/13.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/13.otp_ctrl_smoke.4127298364
Short name T423
Test name
Test status
Simulation time 770388390 ps
CPU time 10.94 seconds
Started Mar 21 03:27:26 PM PDT 24
Finished Mar 21 03:27:38 PM PDT 24
Peak memory 241620 kb
Host smart-e1c610a0-0186-4b6b-bb2f-3c71cfbd602b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127298364 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.4127298364
Directory /workspace/13.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/13.otp_ctrl_test_access.2733539579
Short name T184
Test name
Test status
Simulation time 33591383669 ps
CPU time 69.03 seconds
Started Mar 21 03:27:42 PM PDT 24
Finished Mar 21 03:28:51 PM PDT 24
Peak memory 248288 kb
Host smart-f97d8217-fe2a-411a-ab56-8da606434b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733539579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.2733539579
Directory /workspace/13.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/130.otp_ctrl_init_fail.537744050
Short name T527
Test name
Test status
Simulation time 262007123 ps
CPU time 4.08 seconds
Started Mar 21 03:30:10 PM PDT 24
Finished Mar 21 03:30:15 PM PDT 24
Peak memory 241408 kb
Host smart-49075196-9ea3-4ef0-a1d5-62dcafa2ebab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537744050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.537744050
Directory /workspace/130.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/130.otp_ctrl_parallel_lc_esc.996562932
Short name T946
Test name
Test status
Simulation time 1216705793 ps
CPU time 11.13 seconds
Started Mar 21 03:30:14 PM PDT 24
Finished Mar 21 03:30:25 PM PDT 24
Peak memory 241684 kb
Host smart-89b06885-0270-479d-93ec-39578b746df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996562932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.996562932
Directory /workspace/130.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/131.otp_ctrl_init_fail.427891497
Short name T201
Test name
Test status
Simulation time 1683354976 ps
CPU time 5.62 seconds
Started Mar 21 03:30:15 PM PDT 24
Finished Mar 21 03:30:20 PM PDT 24
Peak memory 241568 kb
Host smart-8922fcc1-539b-4a2f-b969-cde47b271fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427891497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.427891497
Directory /workspace/131.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/131.otp_ctrl_parallel_lc_esc.771442246
Short name T811
Test name
Test status
Simulation time 145975564 ps
CPU time 5.67 seconds
Started Mar 21 03:30:08 PM PDT 24
Finished Mar 21 03:30:14 PM PDT 24
Peak memory 241080 kb
Host smart-3e2ef765-4dad-4815-b962-18a79b1b4e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771442246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.771442246
Directory /workspace/131.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/132.otp_ctrl_init_fail.2711083013
Short name T1046
Test name
Test status
Simulation time 547075109 ps
CPU time 4.01 seconds
Started Mar 21 03:30:11 PM PDT 24
Finished Mar 21 03:30:15 PM PDT 24
Peak memory 241396 kb
Host smart-83d5847f-5c0f-4ca1-b166-e95989b0c71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711083013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.2711083013
Directory /workspace/132.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/132.otp_ctrl_parallel_lc_esc.2710417164
Short name T1192
Test name
Test status
Simulation time 449945095 ps
CPU time 6.48 seconds
Started Mar 21 03:30:16 PM PDT 24
Finished Mar 21 03:30:23 PM PDT 24
Peak memory 241668 kb
Host smart-0e6bd7ba-5082-4110-bfa3-996b605a4565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710417164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.2710417164
Directory /workspace/132.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/133.otp_ctrl_parallel_lc_esc.2670314912
Short name T504
Test name
Test status
Simulation time 518477739 ps
CPU time 3.72 seconds
Started Mar 21 03:30:13 PM PDT 24
Finished Mar 21 03:30:17 PM PDT 24
Peak memory 241792 kb
Host smart-c405d4c5-44c1-4943-8d9b-900154d35f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670314912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.2670314912
Directory /workspace/133.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/134.otp_ctrl_init_fail.3272469544
Short name T1041
Test name
Test status
Simulation time 502942044 ps
CPU time 4 seconds
Started Mar 21 03:30:14 PM PDT 24
Finished Mar 21 03:30:18 PM PDT 24
Peak memory 241688 kb
Host smart-26f06e77-e475-47dd-8449-f53ed5a84091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272469544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.3272469544
Directory /workspace/134.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/134.otp_ctrl_parallel_lc_esc.2502454735
Short name T645
Test name
Test status
Simulation time 112632713 ps
CPU time 3.78 seconds
Started Mar 21 03:30:19 PM PDT 24
Finished Mar 21 03:30:23 PM PDT 24
Peak memory 241084 kb
Host smart-c0c611da-684c-4521-942b-7e9d367b543f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502454735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.2502454735
Directory /workspace/134.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/135.otp_ctrl_init_fail.3247097526
Short name T1141
Test name
Test status
Simulation time 544017901 ps
CPU time 4.05 seconds
Started Mar 21 03:30:09 PM PDT 24
Finished Mar 21 03:30:13 PM PDT 24
Peak memory 241648 kb
Host smart-d3cbef7d-1278-4a1e-86b8-fa12c48db09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247097526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.3247097526
Directory /workspace/135.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/135.otp_ctrl_parallel_lc_esc.4042064594
Short name T442
Test name
Test status
Simulation time 1117765822 ps
CPU time 10.02 seconds
Started Mar 21 03:30:13 PM PDT 24
Finished Mar 21 03:30:23 PM PDT 24
Peak memory 241348 kb
Host smart-8d8b91bc-7411-42b0-bfac-ad3782abff4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042064594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.4042064594
Directory /workspace/135.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/136.otp_ctrl_init_fail.3676005547
Short name T762
Test name
Test status
Simulation time 136988763 ps
CPU time 4.13 seconds
Started Mar 21 03:30:19 PM PDT 24
Finished Mar 21 03:30:23 PM PDT 24
Peak memory 241368 kb
Host smart-30e37a0c-7643-48c5-82cf-e2dc6c711257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676005547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.3676005547
Directory /workspace/136.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/136.otp_ctrl_parallel_lc_esc.750027319
Short name T261
Test name
Test status
Simulation time 107551962 ps
CPU time 4.32 seconds
Started Mar 21 03:30:12 PM PDT 24
Finished Mar 21 03:30:17 PM PDT 24
Peak memory 241148 kb
Host smart-753cc8a4-66b0-46d4-8287-f90eda91ecca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750027319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.750027319
Directory /workspace/136.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/137.otp_ctrl_init_fail.3146535728
Short name T833
Test name
Test status
Simulation time 1590056460 ps
CPU time 5.12 seconds
Started Mar 21 03:30:12 PM PDT 24
Finished Mar 21 03:30:17 PM PDT 24
Peak memory 241848 kb
Host smart-0e3c4cdf-b895-44fe-a7da-cf676550836e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146535728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.3146535728
Directory /workspace/137.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/137.otp_ctrl_parallel_lc_esc.3318115512
Short name T899
Test name
Test status
Simulation time 1325573815 ps
CPU time 10.54 seconds
Started Mar 21 03:30:13 PM PDT 24
Finished Mar 21 03:30:24 PM PDT 24
Peak memory 241392 kb
Host smart-8e766d0a-9604-4b7d-9113-7c14e04e8384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318115512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.3318115512
Directory /workspace/137.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/138.otp_ctrl_init_fail.3246639132
Short name T200
Test name
Test status
Simulation time 1551131666 ps
CPU time 5.66 seconds
Started Mar 21 03:30:11 PM PDT 24
Finished Mar 21 03:30:17 PM PDT 24
Peak memory 241304 kb
Host smart-3a09ba2b-7dcb-4eb8-a535-c7d5703dd5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246639132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.3246639132
Directory /workspace/138.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/138.otp_ctrl_parallel_lc_esc.1731049160
Short name T668
Test name
Test status
Simulation time 338038736 ps
CPU time 9.69 seconds
Started Mar 21 03:30:11 PM PDT 24
Finished Mar 21 03:30:20 PM PDT 24
Peak memory 241208 kb
Host smart-767d45f0-a5aa-4415-9fe3-b4eb45f96de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731049160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.1731049160
Directory /workspace/138.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/139.otp_ctrl_init_fail.1777319524
Short name T646
Test name
Test status
Simulation time 275782344 ps
CPU time 4.4 seconds
Started Mar 21 03:30:17 PM PDT 24
Finished Mar 21 03:30:22 PM PDT 24
Peak memory 241432 kb
Host smart-7463e821-ae68-43da-a80d-e3eaf1e06da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777319524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.1777319524
Directory /workspace/139.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/139.otp_ctrl_parallel_lc_esc.4216667742
Short name T807
Test name
Test status
Simulation time 691932517 ps
CPU time 9.4 seconds
Started Mar 21 03:30:18 PM PDT 24
Finished Mar 21 03:30:27 PM PDT 24
Peak memory 241744 kb
Host smart-661a579a-2b38-4348-920e-fe304cde163e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216667742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.4216667742
Directory /workspace/139.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_alert_test.3520817138
Short name T477
Test name
Test status
Simulation time 87434338 ps
CPU time 2.39 seconds
Started Mar 21 03:27:44 PM PDT 24
Finished Mar 21 03:27:46 PM PDT 24
Peak memory 239844 kb
Host smart-b4297e72-e706-49be-a52f-42d09a2a8285
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520817138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.3520817138
Directory /workspace/14.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.otp_ctrl_check_fail.2573542846
Short name T654
Test name
Test status
Simulation time 1957199935 ps
CPU time 16.31 seconds
Started Mar 21 03:27:46 PM PDT 24
Finished Mar 21 03:28:03 PM PDT 24
Peak memory 248292 kb
Host smart-09804ede-447f-4fdd-a955-cea005047c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573542846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.2573542846
Directory /workspace/14.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_errs.308167814
Short name T364
Test name
Test status
Simulation time 2320186606 ps
CPU time 34.86 seconds
Started Mar 21 03:27:41 PM PDT 24
Finished Mar 21 03:28:16 PM PDT 24
Peak memory 246568 kb
Host smart-13b9a0ff-8fbf-4acc-ad67-21ddc604edd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308167814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.308167814
Directory /workspace/14.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_lock.2753415608
Short name T733
Test name
Test status
Simulation time 1066675222 ps
CPU time 17.54 seconds
Started Mar 21 03:27:48 PM PDT 24
Finished Mar 21 03:28:06 PM PDT 24
Peak memory 241524 kb
Host smart-3d9484cb-1ac6-44d0-980a-43cf75815bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753415608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.2753415608
Directory /workspace/14.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/14.otp_ctrl_init_fail.104335817
Short name T494
Test name
Test status
Simulation time 129828627 ps
CPU time 4.28 seconds
Started Mar 21 03:27:43 PM PDT 24
Finished Mar 21 03:27:47 PM PDT 24
Peak memory 241672 kb
Host smart-7cbab95a-26d0-4aca-8887-04e8b2cb220a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104335817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.104335817
Directory /workspace/14.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_macro_errs.1174248452
Short name T1145
Test name
Test status
Simulation time 2086605128 ps
CPU time 4.8 seconds
Started Mar 21 03:27:45 PM PDT 24
Finished Mar 21 03:27:50 PM PDT 24
Peak memory 241268 kb
Host smart-bad6c4ab-7e02-4f84-aa63-ee3788969a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174248452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_macro_errs.1174248452
Directory /workspace/14.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_key_req.880542331
Short name T254
Test name
Test status
Simulation time 701369343 ps
CPU time 30 seconds
Started Mar 21 03:27:46 PM PDT 24
Finished Mar 21 03:28:16 PM PDT 24
Peak memory 248168 kb
Host smart-96840d57-fd6c-443b-ae42-32e495a7cdac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880542331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.880542331
Directory /workspace/14.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_esc.82196026
Short name T810
Test name
Test status
Simulation time 192446350 ps
CPU time 8.11 seconds
Started Mar 21 03:27:45 PM PDT 24
Finished Mar 21 03:27:53 PM PDT 24
Peak memory 241284 kb
Host smart-65e330c4-5a29-4fe1-8425-1fddcf25d20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82196026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.82196026
Directory /workspace/14.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_req.1009170356
Short name T1177
Test name
Test status
Simulation time 546088035 ps
CPU time 9.7 seconds
Started Mar 21 03:27:43 PM PDT 24
Finished Mar 21 03:27:52 PM PDT 24
Peak memory 241640 kb
Host smart-5e79d28e-fa4f-4317-b60a-d20ef8043c71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1009170356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.1009170356
Directory /workspace/14.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_regwen.2257397729
Short name T1027
Test name
Test status
Simulation time 478927841 ps
CPU time 6.51 seconds
Started Mar 21 03:27:44 PM PDT 24
Finished Mar 21 03:27:50 PM PDT 24
Peak memory 241392 kb
Host smart-53f4a27c-3e47-4986-a328-43481a8433a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2257397729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.2257397729
Directory /workspace/14.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/14.otp_ctrl_smoke.2056730473
Short name T850
Test name
Test status
Simulation time 689070707 ps
CPU time 9.14 seconds
Started Mar 21 03:27:35 PM PDT 24
Finished Mar 21 03:27:44 PM PDT 24
Peak memory 241356 kb
Host smart-4abdfa1c-1b13-4f45-b03c-8ebcd9848817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056730473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.2056730473
Directory /workspace/14.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all.2520909772
Short name T812
Test name
Test status
Simulation time 77724218411 ps
CPU time 189.15 seconds
Started Mar 21 03:27:42 PM PDT 24
Finished Mar 21 03:30:52 PM PDT 24
Peak memory 257344 kb
Host smart-b129c6df-92e3-425d-a8f1-bfd1ab93d4fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520909772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all
.2520909772
Directory /workspace/14.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all_with_rand_reset.4230222273
Short name T742
Test name
Test status
Simulation time 58525668618 ps
CPU time 1737.55 seconds
Started Mar 21 03:27:43 PM PDT 24
Finished Mar 21 03:56:41 PM PDT 24
Peak memory 264812 kb
Host smart-688b80ed-fde7-4bd2-b641-924c51405ef9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230222273 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all_with_rand_reset.4230222273
Directory /workspace/14.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.otp_ctrl_test_access.2909586814
Short name T840
Test name
Test status
Simulation time 1985383912 ps
CPU time 19.04 seconds
Started Mar 21 03:27:42 PM PDT 24
Finished Mar 21 03:28:01 PM PDT 24
Peak memory 241812 kb
Host smart-b5b6537c-3ecf-42fe-8bcf-26e5bdd53331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909586814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.2909586814
Directory /workspace/14.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/140.otp_ctrl_init_fail.1468299075
Short name T204
Test name
Test status
Simulation time 2118305864 ps
CPU time 3.79 seconds
Started Mar 21 03:30:19 PM PDT 24
Finished Mar 21 03:30:23 PM PDT 24
Peak memory 241300 kb
Host smart-3a41035f-39c7-4bba-a1aa-d3ef421c6c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468299075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.1468299075
Directory /workspace/140.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/140.otp_ctrl_parallel_lc_esc.2585240433
Short name T1106
Test name
Test status
Simulation time 3485746332 ps
CPU time 11.14 seconds
Started Mar 21 03:30:14 PM PDT 24
Finished Mar 21 03:30:26 PM PDT 24
Peak memory 241396 kb
Host smart-8e928db8-156b-402f-a8ec-9bf909581667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585240433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.2585240433
Directory /workspace/140.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/141.otp_ctrl_init_fail.4122386793
Short name T12
Test name
Test status
Simulation time 237316874 ps
CPU time 5.41 seconds
Started Mar 21 03:30:20 PM PDT 24
Finished Mar 21 03:30:25 PM PDT 24
Peak memory 241360 kb
Host smart-730c69e3-629e-443b-9b44-b44d87aa77ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122386793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.4122386793
Directory /workspace/141.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/142.otp_ctrl_init_fail.3425576330
Short name T1031
Test name
Test status
Simulation time 142032001 ps
CPU time 3.99 seconds
Started Mar 21 03:30:20 PM PDT 24
Finished Mar 21 03:30:24 PM PDT 24
Peak memory 241224 kb
Host smart-55926886-72bc-4c10-890c-82bd31dd4dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425576330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.3425576330
Directory /workspace/142.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/142.otp_ctrl_parallel_lc_esc.1156579884
Short name T1054
Test name
Test status
Simulation time 154056168 ps
CPU time 3.4 seconds
Started Mar 21 03:30:15 PM PDT 24
Finished Mar 21 03:30:18 PM PDT 24
Peak memory 241568 kb
Host smart-1931dea7-4cd6-4fab-9f29-03e31fa33b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156579884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.1156579884
Directory /workspace/142.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/143.otp_ctrl_init_fail.2766842159
Short name T836
Test name
Test status
Simulation time 2558206667 ps
CPU time 7.8 seconds
Started Mar 21 03:30:21 PM PDT 24
Finished Mar 21 03:30:29 PM PDT 24
Peak memory 241340 kb
Host smart-d94ca128-9100-49e7-9816-7316bda66f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766842159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.2766842159
Directory /workspace/143.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/143.otp_ctrl_parallel_lc_esc.1658885187
Short name T960
Test name
Test status
Simulation time 278768782 ps
CPU time 4.56 seconds
Started Mar 21 03:30:15 PM PDT 24
Finished Mar 21 03:30:19 PM PDT 24
Peak memory 241260 kb
Host smart-682060b6-66f3-4e96-bd97-41f0ca2aaaaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658885187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.1658885187
Directory /workspace/143.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/144.otp_ctrl_init_fail.1720517014
Short name T764
Test name
Test status
Simulation time 371341792 ps
CPU time 4.36 seconds
Started Mar 21 03:30:21 PM PDT 24
Finished Mar 21 03:30:26 PM PDT 24
Peak memory 241280 kb
Host smart-d9e4cb4b-f785-4560-8ffc-b3ed3b21adca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720517014 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.1720517014
Directory /workspace/144.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/144.otp_ctrl_parallel_lc_esc.2197409945
Short name T790
Test name
Test status
Simulation time 889928810 ps
CPU time 12.91 seconds
Started Mar 21 03:30:16 PM PDT 24
Finished Mar 21 03:30:29 PM PDT 24
Peak memory 241696 kb
Host smart-c777e373-70f7-4d7a-a6f7-7b82f5f901f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197409945 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.2197409945
Directory /workspace/144.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/145.otp_ctrl_init_fail.2687252788
Short name T693
Test name
Test status
Simulation time 146519910 ps
CPU time 3.49 seconds
Started Mar 21 03:30:15 PM PDT 24
Finished Mar 21 03:30:18 PM PDT 24
Peak memory 241368 kb
Host smart-3435ef78-fa66-4e7b-8dad-0ea718799505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687252788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.2687252788
Directory /workspace/145.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/145.otp_ctrl_parallel_lc_esc.819205483
Short name T274
Test name
Test status
Simulation time 374245391 ps
CPU time 10.18 seconds
Started Mar 21 03:30:20 PM PDT 24
Finished Mar 21 03:30:31 PM PDT 24
Peak memory 241124 kb
Host smart-b8c83720-e092-4afd-ad1d-eb804e2eae1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819205483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.819205483
Directory /workspace/145.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/146.otp_ctrl_init_fail.3278380970
Short name T861
Test name
Test status
Simulation time 109855612 ps
CPU time 4.21 seconds
Started Mar 21 03:30:20 PM PDT 24
Finished Mar 21 03:30:25 PM PDT 24
Peak memory 241512 kb
Host smart-aab53583-6e87-4e96-911c-31b5f048f4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278380970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.3278380970
Directory /workspace/146.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/146.otp_ctrl_parallel_lc_esc.3410745456
Short name T627
Test name
Test status
Simulation time 115099034 ps
CPU time 3.94 seconds
Started Mar 21 03:30:22 PM PDT 24
Finished Mar 21 03:30:26 PM PDT 24
Peak memory 241088 kb
Host smart-f3c0dcad-8551-4e94-b819-a186eab9e4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410745456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.3410745456
Directory /workspace/146.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/147.otp_ctrl_init_fail.1025541222
Short name T1015
Test name
Test status
Simulation time 249990244 ps
CPU time 3.86 seconds
Started Mar 21 03:30:21 PM PDT 24
Finished Mar 21 03:30:25 PM PDT 24
Peak memory 241644 kb
Host smart-130e224f-46d7-4bbc-b322-7b5e59466326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025541222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.1025541222
Directory /workspace/147.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/148.otp_ctrl_parallel_lc_esc.42389098
Short name T622
Test name
Test status
Simulation time 128916559 ps
CPU time 5.55 seconds
Started Mar 21 03:30:16 PM PDT 24
Finished Mar 21 03:30:22 PM PDT 24
Peak memory 241680 kb
Host smart-7f7c7a8b-28d5-46dc-815a-bc9302bb4ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42389098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.42389098
Directory /workspace/148.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/149.otp_ctrl_init_fail.3041622380
Short name T1104
Test name
Test status
Simulation time 103710133 ps
CPU time 4.07 seconds
Started Mar 21 03:30:15 PM PDT 24
Finished Mar 21 03:30:20 PM PDT 24
Peak memory 241332 kb
Host smart-c6ab5a55-ecaa-409d-8675-2f3f90d2754b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041622380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.3041622380
Directory /workspace/149.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/149.otp_ctrl_parallel_lc_esc.25697517
Short name T1155
Test name
Test status
Simulation time 4287952380 ps
CPU time 8.37 seconds
Started Mar 21 03:30:15 PM PDT 24
Finished Mar 21 03:30:24 PM PDT 24
Peak memory 241308 kb
Host smart-027bc6be-6e4a-45af-b3a8-b26421be00e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25697517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.25697517
Directory /workspace/149.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_alert_test.1482216717
Short name T1185
Test name
Test status
Simulation time 72147472 ps
CPU time 1.84 seconds
Started Mar 21 03:27:42 PM PDT 24
Finished Mar 21 03:27:44 PM PDT 24
Peak memory 239836 kb
Host smart-945628a7-e863-4ad3-b662-bde4990a0270
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482216717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.1482216717
Directory /workspace/15.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.otp_ctrl_check_fail.2489051738
Short name T798
Test name
Test status
Simulation time 7646571292 ps
CPU time 26.71 seconds
Started Mar 21 03:27:42 PM PDT 24
Finished Mar 21 03:28:09 PM PDT 24
Peak memory 242116 kb
Host smart-837d3f5f-7e38-4671-8716-72711c21d1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489051738 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.2489051738
Directory /workspace/15.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_errs.1573202152
Short name T483
Test name
Test status
Simulation time 24611418180 ps
CPU time 68.38 seconds
Started Mar 21 03:27:46 PM PDT 24
Finished Mar 21 03:28:55 PM PDT 24
Peak memory 256692 kb
Host smart-b7c0f60f-204e-4dae-b1b8-306e23c2cfd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573202152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.1573202152
Directory /workspace/15.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_lock.1131336292
Short name T131
Test name
Test status
Simulation time 336971742 ps
CPU time 7.93 seconds
Started Mar 21 03:27:46 PM PDT 24
Finished Mar 21 03:27:54 PM PDT 24
Peak memory 241344 kb
Host smart-5d557c6b-48c0-415f-8fd0-649328156270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131336292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.1131336292
Directory /workspace/15.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/15.otp_ctrl_init_fail.3874738416
Short name T963
Test name
Test status
Simulation time 442340563 ps
CPU time 3.54 seconds
Started Mar 21 03:27:41 PM PDT 24
Finished Mar 21 03:27:44 PM PDT 24
Peak memory 241676 kb
Host smart-6d407b79-ed54-412c-8ec1-48cd94bea323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874738416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.3874738416
Directory /workspace/15.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_macro_errs.3206692550
Short name T367
Test name
Test status
Simulation time 6025705400 ps
CPU time 34.61 seconds
Started Mar 21 03:27:41 PM PDT 24
Finished Mar 21 03:28:16 PM PDT 24
Peak memory 245768 kb
Host smart-99757273-51d8-4c2f-97d9-5cdfbf81bd53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206692550 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.3206692550
Directory /workspace/15.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_key_req.3837361521
Short name T956
Test name
Test status
Simulation time 19460124065 ps
CPU time 56.39 seconds
Started Mar 21 03:27:42 PM PDT 24
Finished Mar 21 03:28:38 PM PDT 24
Peak memory 242832 kb
Host smart-90526197-8bd0-4cf8-ae0a-d5b6fec139e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837361521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.3837361521
Directory /workspace/15.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_esc.3556317303
Short name T148
Test name
Test status
Simulation time 1882780607 ps
CPU time 3.88 seconds
Started Mar 21 03:27:45 PM PDT 24
Finished Mar 21 03:27:49 PM PDT 24
Peak memory 241392 kb
Host smart-541b9da8-59e4-41fd-b273-f5eda1cc9884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556317303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.3556317303
Directory /workspace/15.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_req.4150558542
Short name T827
Test name
Test status
Simulation time 11263953995 ps
CPU time 24.38 seconds
Started Mar 21 03:27:43 PM PDT 24
Finished Mar 21 03:28:08 PM PDT 24
Peak memory 241324 kb
Host smart-f53abf0a-b0af-4356-82b4-a667299c6821
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4150558542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.4150558542
Directory /workspace/15.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_smoke.246599137
Short name T741
Test name
Test status
Simulation time 1330844419 ps
CPU time 9.21 seconds
Started Mar 21 03:27:41 PM PDT 24
Finished Mar 21 03:27:51 PM PDT 24
Peak memory 241336 kb
Host smart-bf308a3a-acb6-466a-95b1-e3ae71c7098f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246599137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.246599137
Directory /workspace/15.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/15.otp_ctrl_stress_all_with_rand_reset.314733709
Short name T528
Test name
Test status
Simulation time 24482187117 ps
CPU time 329.52 seconds
Started Mar 21 03:27:44 PM PDT 24
Finished Mar 21 03:33:14 PM PDT 24
Peak memory 314048 kb
Host smart-abaced3e-cf49-4944-bdf9-bc5163d8ca1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314733709 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all_with_rand_reset.314733709
Directory /workspace/15.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.otp_ctrl_test_access.714249869
Short name T183
Test name
Test status
Simulation time 4820627370 ps
CPU time 9.16 seconds
Started Mar 21 03:27:43 PM PDT 24
Finished Mar 21 03:27:52 PM PDT 24
Peak memory 248308 kb
Host smart-3ac8d3b0-a454-4726-82a5-ce29d38ab613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714249869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.714249869
Directory /workspace/15.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/150.otp_ctrl_init_fail.1252342673
Short name T1136
Test name
Test status
Simulation time 127080389 ps
CPU time 4.53 seconds
Started Mar 21 03:30:16 PM PDT 24
Finished Mar 21 03:30:21 PM PDT 24
Peak memory 241432 kb
Host smart-66a9ca0c-5cf8-43cb-ad80-f0f88f1f0ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252342673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.1252342673
Directory /workspace/150.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/150.otp_ctrl_parallel_lc_esc.307957006
Short name T354
Test name
Test status
Simulation time 148133377 ps
CPU time 3.97 seconds
Started Mar 21 03:30:16 PM PDT 24
Finished Mar 21 03:30:20 PM PDT 24
Peak memory 241664 kb
Host smart-a2139991-0434-412c-8f36-e6bd25677ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307957006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.307957006
Directory /workspace/150.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/151.otp_ctrl_parallel_lc_esc.4121185314
Short name T259
Test name
Test status
Simulation time 224429350 ps
CPU time 9.67 seconds
Started Mar 21 03:30:13 PM PDT 24
Finished Mar 21 03:30:22 PM PDT 24
Peak memory 241280 kb
Host smart-1f57f100-97db-4d9b-815c-1f230a3049e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121185314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.4121185314
Directory /workspace/151.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/152.otp_ctrl_init_fail.886599304
Short name T182
Test name
Test status
Simulation time 295484365 ps
CPU time 4.05 seconds
Started Mar 21 03:30:13 PM PDT 24
Finished Mar 21 03:30:17 PM PDT 24
Peak memory 241712 kb
Host smart-ebcfabc5-708c-44dd-9bdf-c23719e18700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886599304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.886599304
Directory /workspace/152.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/152.otp_ctrl_parallel_lc_esc.2373606226
Short name T600
Test name
Test status
Simulation time 200415889 ps
CPU time 4.17 seconds
Started Mar 21 03:30:15 PM PDT 24
Finished Mar 21 03:30:19 PM PDT 24
Peak memory 241220 kb
Host smart-b4d87ff9-0a52-4eea-9e42-a7d2ae5487e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373606226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.2373606226
Directory /workspace/152.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/153.otp_ctrl_init_fail.63304976
Short name T991
Test name
Test status
Simulation time 513021434 ps
CPU time 4.98 seconds
Started Mar 21 03:30:15 PM PDT 24
Finished Mar 21 03:30:20 PM PDT 24
Peak memory 241372 kb
Host smart-7b0757f0-d656-4f1c-b31f-a6e9eb4fd6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63304976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.63304976
Directory /workspace/153.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/154.otp_ctrl_init_fail.2772778580
Short name T67
Test name
Test status
Simulation time 586448035 ps
CPU time 6.33 seconds
Started Mar 21 03:30:29 PM PDT 24
Finished Mar 21 03:30:36 PM PDT 24
Peak memory 241468 kb
Host smart-c53a6509-7663-491d-86e3-f2d964e87c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772778580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.2772778580
Directory /workspace/154.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/154.otp_ctrl_parallel_lc_esc.2223651753
Short name T727
Test name
Test status
Simulation time 192312131 ps
CPU time 9.09 seconds
Started Mar 21 03:30:31 PM PDT 24
Finished Mar 21 03:30:40 PM PDT 24
Peak memory 241308 kb
Host smart-a8919ed9-43ae-4762-ac28-5a0759b8e2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223651753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.2223651753
Directory /workspace/154.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/155.otp_ctrl_init_fail.2415563725
Short name T779
Test name
Test status
Simulation time 162349041 ps
CPU time 4.43 seconds
Started Mar 21 03:30:26 PM PDT 24
Finished Mar 21 03:30:31 PM PDT 24
Peak memory 241648 kb
Host smart-5068def8-7670-4adb-94a0-c71385bacdb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415563725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.2415563725
Directory /workspace/155.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/155.otp_ctrl_parallel_lc_esc.908949524
Short name T1190
Test name
Test status
Simulation time 3443948059 ps
CPU time 16.27 seconds
Started Mar 21 03:30:31 PM PDT 24
Finished Mar 21 03:30:48 PM PDT 24
Peak memory 241448 kb
Host smart-8500b2d0-2f49-492c-8af8-287370564e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908949524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.908949524
Directory /workspace/155.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/156.otp_ctrl_init_fail.772259233
Short name T122
Test name
Test status
Simulation time 109159031 ps
CPU time 4.16 seconds
Started Mar 21 03:30:28 PM PDT 24
Finished Mar 21 03:30:32 PM PDT 24
Peak memory 241312 kb
Host smart-af3bad5b-fcc5-4bd6-b0cb-7af233866ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772259233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.772259233
Directory /workspace/156.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/156.otp_ctrl_parallel_lc_esc.2609175050
Short name T1048
Test name
Test status
Simulation time 724572541 ps
CPU time 12.51 seconds
Started Mar 21 03:30:31 PM PDT 24
Finished Mar 21 03:30:43 PM PDT 24
Peak memory 241160 kb
Host smart-aa3d2e1e-034e-4be4-b029-6b1203f1ff0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609175050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.2609175050
Directory /workspace/156.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/157.otp_ctrl_parallel_lc_esc.169941003
Short name T930
Test name
Test status
Simulation time 131410451 ps
CPU time 5.42 seconds
Started Mar 21 03:30:28 PM PDT 24
Finished Mar 21 03:30:33 PM PDT 24
Peak memory 241644 kb
Host smart-1a6b4a89-45fa-4330-bbb8-84b1c33fd18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169941003 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.169941003
Directory /workspace/157.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/158.otp_ctrl_init_fail.1369506264
Short name T942
Test name
Test status
Simulation time 268657380 ps
CPU time 4.59 seconds
Started Mar 21 03:30:27 PM PDT 24
Finished Mar 21 03:30:32 PM PDT 24
Peak memory 241400 kb
Host smart-034eeadc-441c-4e86-bf06-5122c7d4706b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369506264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.1369506264
Directory /workspace/158.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/158.otp_ctrl_parallel_lc_esc.2209987261
Short name T1064
Test name
Test status
Simulation time 1097519297 ps
CPU time 9.29 seconds
Started Mar 21 03:30:29 PM PDT 24
Finished Mar 21 03:30:39 PM PDT 24
Peak memory 241084 kb
Host smart-fc1fbac5-81b1-4da2-95a1-a6525414647d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209987261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.2209987261
Directory /workspace/158.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/159.otp_ctrl_init_fail.3532712065
Short name T1074
Test name
Test status
Simulation time 296369254 ps
CPU time 4.5 seconds
Started Mar 21 03:30:27 PM PDT 24
Finished Mar 21 03:30:32 PM PDT 24
Peak memory 241316 kb
Host smart-ad99a9f0-e122-406f-9b32-ad135c94f910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532712065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.3532712065
Directory /workspace/159.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/159.otp_ctrl_parallel_lc_esc.4178874580
Short name T593
Test name
Test status
Simulation time 862957545 ps
CPU time 13.72 seconds
Started Mar 21 03:30:32 PM PDT 24
Finished Mar 21 03:30:45 PM PDT 24
Peak memory 241280 kb
Host smart-d8e68ad1-bc3e-4a8b-803e-29cfe8b3a554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178874580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.4178874580
Directory /workspace/159.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_alert_test.2283491737
Short name T1134
Test name
Test status
Simulation time 73219425 ps
CPU time 2.19 seconds
Started Mar 21 03:27:43 PM PDT 24
Finished Mar 21 03:27:45 PM PDT 24
Peak memory 239856 kb
Host smart-64501d69-886c-4be4-9a55-22e8609b5a20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283491737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.2283491737
Directory /workspace/16.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.otp_ctrl_check_fail.4228800255
Short name T65
Test name
Test status
Simulation time 10332783532 ps
CPU time 25.08 seconds
Started Mar 21 03:27:43 PM PDT 24
Finished Mar 21 03:28:09 PM PDT 24
Peak memory 243068 kb
Host smart-61b196dc-5e0d-47a1-aadd-12f627f8801b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228800255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.4228800255
Directory /workspace/16.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_errs.3188986590
Short name T365
Test name
Test status
Simulation time 204043421 ps
CPU time 9.36 seconds
Started Mar 21 03:27:43 PM PDT 24
Finished Mar 21 03:27:53 PM PDT 24
Peak memory 241160 kb
Host smart-eda6b755-8b2a-4e86-9253-d16a4f560f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188986590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.3188986590
Directory /workspace/16.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_lock.2641957865
Short name T1081
Test name
Test status
Simulation time 901419859 ps
CPU time 22.71 seconds
Started Mar 21 03:27:43 PM PDT 24
Finished Mar 21 03:28:06 PM PDT 24
Peak memory 241232 kb
Host smart-6d0a5b51-81b5-47b7-b46d-ee2c66796d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641957865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.2641957865
Directory /workspace/16.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/16.otp_ctrl_macro_errs.193440468
Short name T238
Test name
Test status
Simulation time 1132633592 ps
CPU time 8.41 seconds
Started Mar 21 03:27:45 PM PDT 24
Finished Mar 21 03:27:53 PM PDT 24
Peak memory 242932 kb
Host smart-e29627ad-065a-4046-9414-8d99393c18ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193440468 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.193440468
Directory /workspace/16.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_key_req.1920952733
Short name T945
Test name
Test status
Simulation time 784908852 ps
CPU time 12.17 seconds
Started Mar 21 03:27:43 PM PDT 24
Finished Mar 21 03:27:56 PM PDT 24
Peak memory 241840 kb
Host smart-ef4b7dd5-512d-46bd-87f4-3e514174394f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920952733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.1920952733
Directory /workspace/16.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_esc.4072031552
Short name T969
Test name
Test status
Simulation time 775409943 ps
CPU time 8.3 seconds
Started Mar 21 03:27:45 PM PDT 24
Finished Mar 21 03:27:53 PM PDT 24
Peak memory 241620 kb
Host smart-59576e79-a8d2-4e6a-ab30-bb4a8e6dd486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072031552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.4072031552
Directory /workspace/16.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_req.2276076460
Short name T610
Test name
Test status
Simulation time 11610162755 ps
CPU time 28.55 seconds
Started Mar 21 03:27:49 PM PDT 24
Finished Mar 21 03:28:17 PM PDT 24
Peak memory 241140 kb
Host smart-392e0c4c-8ff0-4095-b9f3-a694d147e13a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2276076460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_req.2276076460
Directory /workspace/16.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_regwen.2851819324
Short name T380
Test name
Test status
Simulation time 1056513142 ps
CPU time 10.07 seconds
Started Mar 21 03:27:44 PM PDT 24
Finished Mar 21 03:27:55 PM PDT 24
Peak memory 241608 kb
Host smart-ff03adc6-27be-44fa-9455-ea640056a35b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2851819324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.2851819324
Directory /workspace/16.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/16.otp_ctrl_smoke.208046186
Short name T353
Test name
Test status
Simulation time 2515153265 ps
CPU time 6.48 seconds
Started Mar 21 03:27:42 PM PDT 24
Finished Mar 21 03:27:49 PM PDT 24
Peak memory 241824 kb
Host smart-d5e3f244-0cae-4b60-9aaa-2c50fe2bc1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208046186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_smoke.208046186
Directory /workspace/16.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all.4090818073
Short name T97
Test name
Test status
Simulation time 1997695542 ps
CPU time 38.78 seconds
Started Mar 21 03:27:45 PM PDT 24
Finished Mar 21 03:28:24 PM PDT 24
Peak memory 241272 kb
Host smart-ef2dd25a-72ff-4470-93ef-37bace54338a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090818073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all
.4090818073
Directory /workspace/16.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all_with_rand_reset.2769032384
Short name T361
Test name
Test status
Simulation time 125716772698 ps
CPU time 3183.11 seconds
Started Mar 21 03:27:45 PM PDT 24
Finished Mar 21 04:20:49 PM PDT 24
Peak memory 322156 kb
Host smart-e46e8af5-31bd-4de9-b051-22b92d22212c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769032384 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all_with_rand_reset.2769032384
Directory /workspace/16.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.otp_ctrl_test_access.347348544
Short name T908
Test name
Test status
Simulation time 579132147 ps
CPU time 11 seconds
Started Mar 21 03:27:43 PM PDT 24
Finished Mar 21 03:27:54 PM PDT 24
Peak memory 241424 kb
Host smart-7fe1fab6-108e-41e4-9068-47ae1d7b3883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347348544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.347348544
Directory /workspace/16.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/160.otp_ctrl_init_fail.2005067975
Short name T620
Test name
Test status
Simulation time 2158392599 ps
CPU time 5.44 seconds
Started Mar 21 03:30:29 PM PDT 24
Finished Mar 21 03:30:34 PM PDT 24
Peak memory 241608 kb
Host smart-679dbdc9-1087-48a6-a611-d65df7cccc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005067975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.2005067975
Directory /workspace/160.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/160.otp_ctrl_parallel_lc_esc.2202329526
Short name T529
Test name
Test status
Simulation time 229406843 ps
CPU time 12.27 seconds
Started Mar 21 03:30:28 PM PDT 24
Finished Mar 21 03:30:40 PM PDT 24
Peak memory 241232 kb
Host smart-e6a436e0-93a5-4bed-bdc9-759c17ffa824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202329526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.2202329526
Directory /workspace/160.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/161.otp_ctrl_init_fail.901301604
Short name T1
Test name
Test status
Simulation time 139116088 ps
CPU time 4.23 seconds
Started Mar 21 03:30:31 PM PDT 24
Finished Mar 21 03:30:35 PM PDT 24
Peak memory 241612 kb
Host smart-c5701e59-538a-48f8-bbc4-ee531e5c4f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901301604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.901301604
Directory /workspace/161.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/161.otp_ctrl_parallel_lc_esc.3843237774
Short name T545
Test name
Test status
Simulation time 2934058288 ps
CPU time 20.77 seconds
Started Mar 21 03:30:32 PM PDT 24
Finished Mar 21 03:30:53 PM PDT 24
Peak memory 241480 kb
Host smart-3f6c7a5e-f3cb-4132-8088-04f0f27e1c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843237774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.3843237774
Directory /workspace/161.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/162.otp_ctrl_init_fail.964322312
Short name T563
Test name
Test status
Simulation time 186464674 ps
CPU time 3.95 seconds
Started Mar 21 03:30:29 PM PDT 24
Finished Mar 21 03:30:33 PM PDT 24
Peak memory 241700 kb
Host smart-9adebf24-8c5c-49a4-8ba9-759a44ef501e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964322312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.964322312
Directory /workspace/162.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/162.otp_ctrl_parallel_lc_esc.4042695165
Short name T474
Test name
Test status
Simulation time 1004396723 ps
CPU time 15.76 seconds
Started Mar 21 03:30:31 PM PDT 24
Finished Mar 21 03:30:47 PM PDT 24
Peak memory 241332 kb
Host smart-1fae7ee5-e735-4420-a7a1-374daa01c2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042695165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.4042695165
Directory /workspace/162.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/163.otp_ctrl_init_fail.2066402874
Short name T486
Test name
Test status
Simulation time 569973446 ps
CPU time 4.82 seconds
Started Mar 21 03:30:28 PM PDT 24
Finished Mar 21 03:30:33 PM PDT 24
Peak memory 241284 kb
Host smart-b0e79016-ba0b-4c38-a03c-70ce86f87891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066402874 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.2066402874
Directory /workspace/163.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/163.otp_ctrl_parallel_lc_esc.821524117
Short name T655
Test name
Test status
Simulation time 336381635 ps
CPU time 10.33 seconds
Started Mar 21 03:30:29 PM PDT 24
Finished Mar 21 03:30:39 PM PDT 24
Peak memory 241376 kb
Host smart-d7fc3b47-052d-48d6-bde3-6277d29d378d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821524117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.821524117
Directory /workspace/163.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/164.otp_ctrl_init_fail.3305686981
Short name T1114
Test name
Test status
Simulation time 184829658 ps
CPU time 3.94 seconds
Started Mar 21 03:30:28 PM PDT 24
Finished Mar 21 03:30:32 PM PDT 24
Peak memory 241440 kb
Host smart-ced5e232-3d2d-451b-b156-21a356accbb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305686981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.3305686981
Directory /workspace/164.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/164.otp_ctrl_parallel_lc_esc.1202521073
Short name T517
Test name
Test status
Simulation time 9455867828 ps
CPU time 36.95 seconds
Started Mar 21 03:30:29 PM PDT 24
Finished Mar 21 03:31:06 PM PDT 24
Peak memory 241524 kb
Host smart-f8b99baa-a6d3-4c4f-a5ed-8de42be6d4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202521073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.1202521073
Directory /workspace/164.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/165.otp_ctrl_init_fail.690040094
Short name T516
Test name
Test status
Simulation time 172420349 ps
CPU time 4.33 seconds
Started Mar 21 03:30:30 PM PDT 24
Finished Mar 21 03:30:34 PM PDT 24
Peak memory 241432 kb
Host smart-4944078a-279b-40ff-b32e-dfd7fe3308b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690040094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.690040094
Directory /workspace/165.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/165.otp_ctrl_parallel_lc_esc.2216171735
Short name T145
Test name
Test status
Simulation time 1756886270 ps
CPU time 7.04 seconds
Started Mar 21 03:30:31 PM PDT 24
Finished Mar 21 03:30:38 PM PDT 24
Peak memory 241144 kb
Host smart-4398efbb-5bf2-47de-9f99-c4f55cbe2b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216171735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.2216171735
Directory /workspace/165.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/166.otp_ctrl_init_fail.332321868
Short name T175
Test name
Test status
Simulation time 191495975 ps
CPU time 4.37 seconds
Started Mar 21 03:30:32 PM PDT 24
Finished Mar 21 03:30:36 PM PDT 24
Peak memory 241352 kb
Host smart-f1e02a30-1346-4e22-8eaa-95036970e2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332321868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.332321868
Directory /workspace/166.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/166.otp_ctrl_parallel_lc_esc.3336552615
Short name T150
Test name
Test status
Simulation time 225444397 ps
CPU time 7.05 seconds
Started Mar 21 03:30:28 PM PDT 24
Finished Mar 21 03:30:35 PM PDT 24
Peak memory 241408 kb
Host smart-190cdf06-01ea-4076-aeb0-fc81a9d00e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336552615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.3336552615
Directory /workspace/166.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/167.otp_ctrl_init_fail.3159784356
Short name T198
Test name
Test status
Simulation time 272776359 ps
CPU time 4.19 seconds
Started Mar 21 03:30:30 PM PDT 24
Finished Mar 21 03:30:34 PM PDT 24
Peak memory 241420 kb
Host smart-d684a0d8-8548-444e-8444-4b8ef792c4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159784356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.3159784356
Directory /workspace/167.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/168.otp_ctrl_init_fail.1351000214
Short name T1022
Test name
Test status
Simulation time 155358069 ps
CPU time 4.01 seconds
Started Mar 21 03:30:28 PM PDT 24
Finished Mar 21 03:30:32 PM PDT 24
Peak memory 241408 kb
Host smart-01217f30-9337-4aa5-af28-2281f2e381e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351000214 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.1351000214
Directory /workspace/168.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/168.otp_ctrl_parallel_lc_esc.2398151238
Short name T692
Test name
Test status
Simulation time 703655002 ps
CPU time 9.37 seconds
Started Mar 21 03:30:28 PM PDT 24
Finished Mar 21 03:30:38 PM PDT 24
Peak memory 241740 kb
Host smart-9610eefa-bbf2-48a7-935e-ca88510e29f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398151238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.2398151238
Directory /workspace/168.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/169.otp_ctrl_parallel_lc_esc.1962695636
Short name T264
Test name
Test status
Simulation time 1048230286 ps
CPU time 26.45 seconds
Started Mar 21 03:30:29 PM PDT 24
Finished Mar 21 03:30:56 PM PDT 24
Peak memory 241624 kb
Host smart-03213771-1ac2-4ccb-8edd-1eef08df9f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962695636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.1962695636
Directory /workspace/169.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_alert_test.4113255639
Short name T906
Test name
Test status
Simulation time 50516004 ps
CPU time 1.81 seconds
Started Mar 21 03:27:45 PM PDT 24
Finished Mar 21 03:27:47 PM PDT 24
Peak memory 239884 kb
Host smart-e772e026-5fa3-40f3-94d8-1d19ef576476
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113255639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.4113255639
Directory /workspace/17.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.otp_ctrl_check_fail.3441112408
Short name T116
Test name
Test status
Simulation time 9673558841 ps
CPU time 27.03 seconds
Started Mar 21 03:27:45 PM PDT 24
Finished Mar 21 03:28:12 PM PDT 24
Peak memory 243316 kb
Host smart-54a34219-11de-4eca-9a57-6e92e1a36f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441112408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.3441112408
Directory /workspace/17.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_errs.601545914
Short name T1148
Test name
Test status
Simulation time 5939796289 ps
CPU time 16.21 seconds
Started Mar 21 03:27:46 PM PDT 24
Finished Mar 21 03:28:02 PM PDT 24
Peak memory 241780 kb
Host smart-d2121314-af43-4716-8321-1a05ddbf7b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601545914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.601545914
Directory /workspace/17.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_lock.1252481528
Short name T481
Test name
Test status
Simulation time 2168991492 ps
CPU time 22.74 seconds
Started Mar 21 03:27:44 PM PDT 24
Finished Mar 21 03:28:07 PM PDT 24
Peak memory 241680 kb
Host smart-215f7cc4-7d78-4fa6-a12f-061436f6d276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252481528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.1252481528
Directory /workspace/17.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/17.otp_ctrl_init_fail.2271518185
Short name T1138
Test name
Test status
Simulation time 1734425458 ps
CPU time 5.05 seconds
Started Mar 21 03:27:44 PM PDT 24
Finished Mar 21 03:27:49 PM PDT 24
Peak memory 241668 kb
Host smart-8c9b744a-828f-4e0f-ba55-b803e171ca9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271518185 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.2271518185
Directory /workspace/17.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_macro_errs.2204739170
Short name T323
Test name
Test status
Simulation time 669523138 ps
CPU time 18.64 seconds
Started Mar 21 03:27:43 PM PDT 24
Finished Mar 21 03:28:01 PM PDT 24
Peak memory 248276 kb
Host smart-b901a729-7914-4c1e-ad93-09001548480f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204739170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.2204739170
Directory /workspace/17.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_key_req.2076739801
Short name T1158
Test name
Test status
Simulation time 429097778 ps
CPU time 16.94 seconds
Started Mar 21 03:27:44 PM PDT 24
Finished Mar 21 03:28:01 PM PDT 24
Peak memory 248188 kb
Host smart-ebcf7be5-a6ff-4e0a-8e2b-b7f8add21f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076739801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.2076739801
Directory /workspace/17.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_esc.693836581
Short name T537
Test name
Test status
Simulation time 672017279 ps
CPU time 6.99 seconds
Started Mar 21 03:27:43 PM PDT 24
Finished Mar 21 03:27:50 PM PDT 24
Peak memory 241616 kb
Host smart-4d196775-bc74-46ca-beec-75069721c64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693836581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.693836581
Directory /workspace/17.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_regwen.3263410086
Short name T273
Test name
Test status
Simulation time 3791267446 ps
CPU time 11.71 seconds
Started Mar 21 03:27:44 PM PDT 24
Finished Mar 21 03:27:56 PM PDT 24
Peak memory 241536 kb
Host smart-e877de4a-e49f-45f9-b222-c618128b0437
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3263410086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.3263410086
Directory /workspace/17.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/17.otp_ctrl_smoke.2452949334
Short name T1122
Test name
Test status
Simulation time 955441772 ps
CPU time 7.46 seconds
Started Mar 21 03:27:45 PM PDT 24
Finished Mar 21 03:27:53 PM PDT 24
Peak memory 241344 kb
Host smart-b95952eb-1952-4075-af14-b23ec16782c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452949334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.2452949334
Directory /workspace/17.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all.2343455349
Short name T952
Test name
Test status
Simulation time 3899115683 ps
CPU time 13.61 seconds
Started Mar 21 03:27:43 PM PDT 24
Finished Mar 21 03:27:57 PM PDT 24
Peak memory 241268 kb
Host smart-6052f601-1af9-449c-bd05-7bf919425ce7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343455349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all
.2343455349
Directory /workspace/17.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all_with_rand_reset.207796934
Short name T619
Test name
Test status
Simulation time 26947565512 ps
CPU time 471.49 seconds
Started Mar 21 03:27:47 PM PDT 24
Finished Mar 21 03:35:39 PM PDT 24
Peak memory 276144 kb
Host smart-16526404-c76c-4819-a175-ced9653a9987
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207796934 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all_with_rand_reset.207796934
Directory /workspace/17.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.otp_ctrl_test_access.1007442304
Short name T977
Test name
Test status
Simulation time 1226196696 ps
CPU time 23.62 seconds
Started Mar 21 03:27:43 PM PDT 24
Finished Mar 21 03:28:07 PM PDT 24
Peak memory 241616 kb
Host smart-b84885c5-12ae-4cee-88b1-7be37bc4cbab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007442304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.1007442304
Directory /workspace/17.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/170.otp_ctrl_init_fail.3117259785
Short name T1193
Test name
Test status
Simulation time 123093128 ps
CPU time 3.98 seconds
Started Mar 21 03:30:30 PM PDT 24
Finished Mar 21 03:30:35 PM PDT 24
Peak memory 241452 kb
Host smart-298d519d-6487-4bf7-ab55-53e59ce2dded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117259785 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.3117259785
Directory /workspace/170.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/170.otp_ctrl_parallel_lc_esc.1090774715
Short name T234
Test name
Test status
Simulation time 730180082 ps
CPU time 6.21 seconds
Started Mar 21 03:30:29 PM PDT 24
Finished Mar 21 03:30:35 PM PDT 24
Peak memory 241396 kb
Host smart-f3d1acfd-24b0-4e8f-980e-ebc97e629fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090774715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.1090774715
Directory /workspace/170.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/171.otp_ctrl_init_fail.554015210
Short name T57
Test name
Test status
Simulation time 2137920987 ps
CPU time 5.12 seconds
Started Mar 21 03:30:29 PM PDT 24
Finished Mar 21 03:30:34 PM PDT 24
Peak memory 241420 kb
Host smart-f473d8db-b6ac-4d83-ba86-0084b9818478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554015210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.554015210
Directory /workspace/171.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/171.otp_ctrl_parallel_lc_esc.3728887603
Short name T466
Test name
Test status
Simulation time 433527955 ps
CPU time 6.46 seconds
Started Mar 21 03:30:32 PM PDT 24
Finished Mar 21 03:30:38 PM PDT 24
Peak memory 241760 kb
Host smart-833dcf14-536c-434a-a02e-cada206dae5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728887603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.3728887603
Directory /workspace/171.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/172.otp_ctrl_init_fail.3195985083
Short name T138
Test name
Test status
Simulation time 186047258 ps
CPU time 4.66 seconds
Started Mar 21 03:30:29 PM PDT 24
Finished Mar 21 03:30:34 PM PDT 24
Peak memory 241420 kb
Host smart-fff491ef-2c5e-488f-9f20-d45fc16e85c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195985083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.3195985083
Directory /workspace/172.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/172.otp_ctrl_parallel_lc_esc.2868453212
Short name T935
Test name
Test status
Simulation time 759626361 ps
CPU time 15.45 seconds
Started Mar 21 03:30:30 PM PDT 24
Finished Mar 21 03:30:46 PM PDT 24
Peak memory 241208 kb
Host smart-eb15c704-123b-49e1-9b30-bd3416d0e799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868453212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.2868453212
Directory /workspace/172.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/173.otp_ctrl_init_fail.4270009235
Short name T509
Test name
Test status
Simulation time 155748094 ps
CPU time 4.33 seconds
Started Mar 21 03:30:29 PM PDT 24
Finished Mar 21 03:30:34 PM PDT 24
Peak memory 241428 kb
Host smart-8d9273f6-a633-4a47-ae64-fe88d059f976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270009235 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.4270009235
Directory /workspace/173.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/173.otp_ctrl_parallel_lc_esc.2430900296
Short name T716
Test name
Test status
Simulation time 1149680063 ps
CPU time 18.14 seconds
Started Mar 21 03:30:32 PM PDT 24
Finished Mar 21 03:30:50 PM PDT 24
Peak memory 241684 kb
Host smart-593b9fad-1103-429a-bf05-10c9347ed8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430900296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.2430900296
Directory /workspace/173.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/174.otp_ctrl_init_fail.144386623
Short name T852
Test name
Test status
Simulation time 197418098 ps
CPU time 4.27 seconds
Started Mar 21 03:30:47 PM PDT 24
Finished Mar 21 03:30:51 PM PDT 24
Peak memory 241400 kb
Host smart-0448fc64-ec7e-4de3-a7fe-90e449141114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144386623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.144386623
Directory /workspace/174.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/174.otp_ctrl_parallel_lc_esc.3791843739
Short name T1125
Test name
Test status
Simulation time 7724255275 ps
CPU time 14.06 seconds
Started Mar 21 03:30:46 PM PDT 24
Finished Mar 21 03:31:00 PM PDT 24
Peak memory 241908 kb
Host smart-a44425c2-2734-4c33-8f02-28a4647b3266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791843739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.3791843739
Directory /workspace/174.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/175.otp_ctrl_init_fail.762290781
Short name T706
Test name
Test status
Simulation time 164968104 ps
CPU time 4.28 seconds
Started Mar 21 03:30:48 PM PDT 24
Finished Mar 21 03:30:53 PM PDT 24
Peak memory 241424 kb
Host smart-087b6efe-7e50-48a7-b032-4fd352cc70ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762290781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.762290781
Directory /workspace/175.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/175.otp_ctrl_parallel_lc_esc.4201343367
Short name T786
Test name
Test status
Simulation time 8519635722 ps
CPU time 14.69 seconds
Started Mar 21 03:30:45 PM PDT 24
Finished Mar 21 03:31:00 PM PDT 24
Peak memory 241768 kb
Host smart-0cd5c7b6-8e99-48da-85c5-86eca625d0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201343367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.4201343367
Directory /workspace/175.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/176.otp_ctrl_init_fail.2505979318
Short name T752
Test name
Test status
Simulation time 141973113 ps
CPU time 4.2 seconds
Started Mar 21 03:30:45 PM PDT 24
Finished Mar 21 03:30:49 PM PDT 24
Peak memory 241608 kb
Host smart-d8d81f2a-99a6-48d4-88c2-c13f855c8865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505979318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.2505979318
Directory /workspace/176.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/176.otp_ctrl_parallel_lc_esc.2386956490
Short name T711
Test name
Test status
Simulation time 2905848996 ps
CPU time 22.04 seconds
Started Mar 21 03:30:46 PM PDT 24
Finished Mar 21 03:31:08 PM PDT 24
Peak memory 241536 kb
Host smart-9ede1f04-7bfb-4f15-9a10-c1cb8d5cafe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386956490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.2386956490
Directory /workspace/176.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/177.otp_ctrl_init_fail.4063165029
Short name T883
Test name
Test status
Simulation time 201438606 ps
CPU time 4.42 seconds
Started Mar 21 03:30:48 PM PDT 24
Finished Mar 21 03:30:52 PM PDT 24
Peak memory 241428 kb
Host smart-2b8aace7-08c2-4a3d-bffe-18d23ea400e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063165029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.4063165029
Directory /workspace/177.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/177.otp_ctrl_parallel_lc_esc.394777814
Short name T1100
Test name
Test status
Simulation time 565392248 ps
CPU time 14.44 seconds
Started Mar 21 03:30:48 PM PDT 24
Finished Mar 21 03:31:02 PM PDT 24
Peak memory 241688 kb
Host smart-90b7d848-c780-4536-a925-eff07f3c5f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394777814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.394777814
Directory /workspace/177.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/178.otp_ctrl_init_fail.3210890863
Short name T521
Test name
Test status
Simulation time 582776454 ps
CPU time 4.99 seconds
Started Mar 21 03:30:50 PM PDT 24
Finished Mar 21 03:30:55 PM PDT 24
Peak memory 241308 kb
Host smart-9376433f-3a19-4c34-b247-3cae6ae8e739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210890863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.3210890863
Directory /workspace/178.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/178.otp_ctrl_parallel_lc_esc.375508827
Short name T165
Test name
Test status
Simulation time 2417245740 ps
CPU time 17.88 seconds
Started Mar 21 03:30:44 PM PDT 24
Finished Mar 21 03:31:02 PM PDT 24
Peak memory 241400 kb
Host smart-8a4cfee6-3e4d-4bef-b081-8e463a580ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375508827 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.375508827
Directory /workspace/178.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/179.otp_ctrl_init_fail.16269747
Short name T805
Test name
Test status
Simulation time 1535155231 ps
CPU time 4.63 seconds
Started Mar 21 03:30:48 PM PDT 24
Finished Mar 21 03:30:52 PM PDT 24
Peak memory 241728 kb
Host smart-f52020f8-710d-4e7a-aeea-c52da77d0b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16269747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.16269747
Directory /workspace/179.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/179.otp_ctrl_parallel_lc_esc.1083414897
Short name T1102
Test name
Test status
Simulation time 535104797 ps
CPU time 17.18 seconds
Started Mar 21 03:30:48 PM PDT 24
Finished Mar 21 03:31:05 PM PDT 24
Peak memory 241396 kb
Host smart-cea673b3-b665-45fd-8038-6a53dc5c697d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083414897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.1083414897
Directory /workspace/179.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_alert_test.576338199
Short name T666
Test name
Test status
Simulation time 166746349 ps
CPU time 2.22 seconds
Started Mar 21 03:27:47 PM PDT 24
Finished Mar 21 03:27:49 PM PDT 24
Peak memory 240212 kb
Host smart-2be1d7d7-bc6d-4eb1-8d4e-1461c06d0a7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576338199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.576338199
Directory /workspace/18.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.otp_ctrl_check_fail.183677281
Short name T617
Test name
Test status
Simulation time 882576017 ps
CPU time 13.25 seconds
Started Mar 21 03:27:44 PM PDT 24
Finished Mar 21 03:27:58 PM PDT 24
Peak memory 241308 kb
Host smart-45ffcc17-0174-46b7-a11b-e262cf9881e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183677281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.183677281
Directory /workspace/18.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_errs.3792119815
Short name T1029
Test name
Test status
Simulation time 2911364062 ps
CPU time 25.62 seconds
Started Mar 21 03:27:45 PM PDT 24
Finished Mar 21 03:28:11 PM PDT 24
Peak memory 242064 kb
Host smart-7ff2fb1a-6768-499a-bf91-c6ebefc72a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792119815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.3792119815
Directory /workspace/18.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_lock.4055789506
Short name T745
Test name
Test status
Simulation time 294325493 ps
CPU time 6.98 seconds
Started Mar 21 03:27:44 PM PDT 24
Finished Mar 21 03:27:51 PM PDT 24
Peak memory 241752 kb
Host smart-ce79bdab-58f2-4b01-9bcf-5191fdb8b8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055789506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.4055789506
Directory /workspace/18.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/18.otp_ctrl_init_fail.268515571
Short name T911
Test name
Test status
Simulation time 272680621 ps
CPU time 3.99 seconds
Started Mar 21 03:27:43 PM PDT 24
Finished Mar 21 03:27:47 PM PDT 24
Peak memory 241368 kb
Host smart-58aae993-484b-44a2-b0d3-ec25a3108b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268515571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.268515571
Directory /workspace/18.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_key_req.2834266462
Short name T792
Test name
Test status
Simulation time 10881470315 ps
CPU time 27.92 seconds
Started Mar 21 03:27:45 PM PDT 24
Finished Mar 21 03:28:13 PM PDT 24
Peak memory 242092 kb
Host smart-eaa220c0-756a-4d1e-9f95-62f21fe21f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834266462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.2834266462
Directory /workspace/18.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_esc.852350988
Short name T1168
Test name
Test status
Simulation time 633864634 ps
CPU time 4.72 seconds
Started Mar 21 03:27:44 PM PDT 24
Finished Mar 21 03:27:48 PM PDT 24
Peak memory 241536 kb
Host smart-dcbc81b3-603f-42ef-84ca-30f03f5832c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852350988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.852350988
Directory /workspace/18.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_req.1691135298
Short name T132
Test name
Test status
Simulation time 602071438 ps
CPU time 8.52 seconds
Started Mar 21 03:27:46 PM PDT 24
Finished Mar 21 03:27:55 PM PDT 24
Peak memory 241176 kb
Host smart-b89c40cf-1e9d-4ccf-b047-0f19d33f1b0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1691135298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.1691135298
Directory /workspace/18.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_regwen.239043161
Short name T931
Test name
Test status
Simulation time 3721194872 ps
CPU time 7.92 seconds
Started Mar 21 03:27:44 PM PDT 24
Finished Mar 21 03:27:52 PM PDT 24
Peak memory 241796 kb
Host smart-5dc936fa-5cc8-476c-a858-d1889ec1ddee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=239043161 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.239043161
Directory /workspace/18.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/18.otp_ctrl_smoke.4216423458
Short name T1093
Test name
Test status
Simulation time 4714984897 ps
CPU time 12.46 seconds
Started Mar 21 03:27:44 PM PDT 24
Finished Mar 21 03:27:57 PM PDT 24
Peak memory 241464 kb
Host smart-c48a876c-08e7-47d4-a54c-17c101a0ca84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216423458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.4216423458
Directory /workspace/18.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all.1079168891
Short name T413
Test name
Test status
Simulation time 29064712406 ps
CPU time 419.97 seconds
Started Mar 21 03:27:45 PM PDT 24
Finished Mar 21 03:34:45 PM PDT 24
Peak memory 264660 kb
Host smart-81246f2f-e74a-448e-b163-5b60c599059d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079168891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all
.1079168891
Directory /workspace/18.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all_with_rand_reset.653041925
Short name T268
Test name
Test status
Simulation time 147359874710 ps
CPU time 705.38 seconds
Started Mar 21 03:27:45 PM PDT 24
Finished Mar 21 03:39:31 PM PDT 24
Peak memory 264140 kb
Host smart-010f4dcd-312b-486f-bd12-8be92af71997
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653041925 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all_with_rand_reset.653041925
Directory /workspace/18.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.otp_ctrl_test_access.1128414585
Short name T680
Test name
Test status
Simulation time 1476975376 ps
CPU time 12.83 seconds
Started Mar 21 03:27:42 PM PDT 24
Finished Mar 21 03:27:55 PM PDT 24
Peak memory 241356 kb
Host smart-1873df3a-1cb3-4e42-b5c4-1d593acbb421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128414585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.1128414585
Directory /workspace/18.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/180.otp_ctrl_init_fail.1971898085
Short name T981
Test name
Test status
Simulation time 126173693 ps
CPU time 5.19 seconds
Started Mar 21 03:30:37 PM PDT 24
Finished Mar 21 03:30:42 PM PDT 24
Peak memory 241672 kb
Host smart-11fe2fa1-33c7-4883-9a10-a483e9bad3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971898085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.1971898085
Directory /workspace/180.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/180.otp_ctrl_parallel_lc_esc.2713782154
Short name T356
Test name
Test status
Simulation time 725766839 ps
CPU time 11.28 seconds
Started Mar 21 03:30:47 PM PDT 24
Finished Mar 21 03:30:58 PM PDT 24
Peak memory 241740 kb
Host smart-02f99fd2-6af5-46e7-a7a4-60b48a0389bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713782154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.2713782154
Directory /workspace/180.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/181.otp_ctrl_init_fail.3348711870
Short name T514
Test name
Test status
Simulation time 162131604 ps
CPU time 3.85 seconds
Started Mar 21 03:30:47 PM PDT 24
Finished Mar 21 03:30:51 PM PDT 24
Peak memory 241676 kb
Host smart-fed91623-dc41-4ca9-89ae-7665092ff896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348711870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.3348711870
Directory /workspace/181.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/181.otp_ctrl_parallel_lc_esc.1757760559
Short name T359
Test name
Test status
Simulation time 295076397 ps
CPU time 5.32 seconds
Started Mar 21 03:30:48 PM PDT 24
Finished Mar 21 03:30:53 PM PDT 24
Peak memory 241104 kb
Host smart-bc33a6bc-b901-4589-89db-86cd427a71ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757760559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.1757760559
Directory /workspace/181.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/182.otp_ctrl_parallel_lc_esc.4264920656
Short name T1109
Test name
Test status
Simulation time 876518255 ps
CPU time 22.99 seconds
Started Mar 21 03:30:45 PM PDT 24
Finished Mar 21 03:31:08 PM PDT 24
Peak memory 241400 kb
Host smart-104497cb-6a2e-4759-9ad0-8efcdff40fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264920656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.4264920656
Directory /workspace/182.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/183.otp_ctrl_init_fail.2587168652
Short name T889
Test name
Test status
Simulation time 1563754357 ps
CPU time 4.65 seconds
Started Mar 21 03:30:48 PM PDT 24
Finished Mar 21 03:30:53 PM PDT 24
Peak memory 241576 kb
Host smart-8d55eb19-c348-46a3-b400-698fa9a980ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587168652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.2587168652
Directory /workspace/183.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/183.otp_ctrl_parallel_lc_esc.888365137
Short name T513
Test name
Test status
Simulation time 424402793 ps
CPU time 5.86 seconds
Started Mar 21 03:30:47 PM PDT 24
Finished Mar 21 03:30:53 PM PDT 24
Peak memory 241180 kb
Host smart-d9b23015-0e8b-4bed-99cc-d282b4d5532c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888365137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.888365137
Directory /workspace/183.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/184.otp_ctrl_init_fail.1542256924
Short name T95
Test name
Test status
Simulation time 2093955230 ps
CPU time 5.87 seconds
Started Mar 21 03:30:48 PM PDT 24
Finished Mar 21 03:30:54 PM PDT 24
Peak memory 241400 kb
Host smart-223dcb9b-ed56-4165-94e3-10115ee5b7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542256924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.1542256924
Directory /workspace/184.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/184.otp_ctrl_parallel_lc_esc.3016055920
Short name T430
Test name
Test status
Simulation time 297141489 ps
CPU time 5.38 seconds
Started Mar 21 03:30:50 PM PDT 24
Finished Mar 21 03:30:56 PM PDT 24
Peak memory 241140 kb
Host smart-4fea428d-80b8-4adc-a5ab-10796300d24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016055920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.3016055920
Directory /workspace/184.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/185.otp_ctrl_init_fail.951398491
Short name T475
Test name
Test status
Simulation time 154690814 ps
CPU time 4.51 seconds
Started Mar 21 03:30:48 PM PDT 24
Finished Mar 21 03:30:53 PM PDT 24
Peak memory 241376 kb
Host smart-dd69cfaf-ada4-4c5f-b8a8-538f6211bb6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951398491 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.951398491
Directory /workspace/185.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/185.otp_ctrl_parallel_lc_esc.4221671447
Short name T831
Test name
Test status
Simulation time 1155623622 ps
CPU time 13.92 seconds
Started Mar 21 03:30:49 PM PDT 24
Finished Mar 21 03:31:03 PM PDT 24
Peak memory 241356 kb
Host smart-0ed646b2-1bcc-445b-9e2c-5b0806163028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221671447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.4221671447
Directory /workspace/185.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/186.otp_ctrl_init_fail.2944791415
Short name T1152
Test name
Test status
Simulation time 441141073 ps
CPU time 5.11 seconds
Started Mar 21 03:30:47 PM PDT 24
Finished Mar 21 03:30:52 PM PDT 24
Peak memory 241728 kb
Host smart-a884513a-27ff-41ea-8cc0-efa7558f4376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944791415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.2944791415
Directory /workspace/186.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/186.otp_ctrl_parallel_lc_esc.3963752145
Short name T799
Test name
Test status
Simulation time 440638588 ps
CPU time 3.15 seconds
Started Mar 21 03:30:47 PM PDT 24
Finished Mar 21 03:30:51 PM PDT 24
Peak memory 241580 kb
Host smart-aeb9c163-3ea7-4c55-8f8e-a3f310f3ff0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963752145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.3963752145
Directory /workspace/186.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/187.otp_ctrl_init_fail.217701294
Short name T1083
Test name
Test status
Simulation time 154582727 ps
CPU time 4.58 seconds
Started Mar 21 03:30:48 PM PDT 24
Finished Mar 21 03:30:53 PM PDT 24
Peak memory 241408 kb
Host smart-ea336385-e395-4330-a54f-c40bf0fc3385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217701294 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.217701294
Directory /workspace/187.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/187.otp_ctrl_parallel_lc_esc.4277275141
Short name T586
Test name
Test status
Simulation time 13864137373 ps
CPU time 28.77 seconds
Started Mar 21 03:30:47 PM PDT 24
Finished Mar 21 03:31:16 PM PDT 24
Peak memory 241500 kb
Host smart-d90bbbc7-43fd-44f7-a931-35e31bb0b6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277275141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.4277275141
Directory /workspace/187.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/188.otp_ctrl_init_fail.468761764
Short name T845
Test name
Test status
Simulation time 1773073861 ps
CPU time 6.34 seconds
Started Mar 21 03:31:09 PM PDT 24
Finished Mar 21 03:31:16 PM PDT 24
Peak memory 241376 kb
Host smart-e123d242-40be-45bd-b828-31d50466d05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468761764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.468761764
Directory /workspace/188.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/188.otp_ctrl_parallel_lc_esc.2249640138
Short name T345
Test name
Test status
Simulation time 396430256 ps
CPU time 8.05 seconds
Started Mar 21 03:30:49 PM PDT 24
Finished Mar 21 03:30:57 PM PDT 24
Peak memory 241148 kb
Host smart-1aef9d8f-6c32-49a4-8b71-682572a8023d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249640138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.2249640138
Directory /workspace/188.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/189.otp_ctrl_init_fail.884925268
Short name T203
Test name
Test status
Simulation time 482352909 ps
CPU time 3.51 seconds
Started Mar 21 03:30:49 PM PDT 24
Finished Mar 21 03:30:52 PM PDT 24
Peak memory 241800 kb
Host smart-b203d64e-de32-41e7-ae74-a8c386860a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884925268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.884925268
Directory /workspace/189.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/189.otp_ctrl_parallel_lc_esc.248489388
Short name T1178
Test name
Test status
Simulation time 321774990 ps
CPU time 7.52 seconds
Started Mar 21 03:30:47 PM PDT 24
Finished Mar 21 03:30:55 PM PDT 24
Peak memory 241660 kb
Host smart-30128cd4-aba5-442c-800e-94e2050ffbd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248489388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.248489388
Directory /workspace/189.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_alert_test.3128484016
Short name T735
Test name
Test status
Simulation time 120032561 ps
CPU time 2.11 seconds
Started Mar 21 03:28:01 PM PDT 24
Finished Mar 21 03:28:04 PM PDT 24
Peak memory 240032 kb
Host smart-74ded08f-3520-42e1-bbb2-2cd1ea9b2adb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128484016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.3128484016
Directory /workspace/19.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.otp_ctrl_check_fail.1806202318
Short name T934
Test name
Test status
Simulation time 5557094198 ps
CPU time 10.46 seconds
Started Mar 21 03:27:49 PM PDT 24
Finished Mar 21 03:28:00 PM PDT 24
Peak memory 242048 kb
Host smart-300bae62-7207-4ef4-862c-4e007e676bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806202318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.1806202318
Directory /workspace/19.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_errs.2082120972
Short name T441
Test name
Test status
Simulation time 16641605390 ps
CPU time 44.48 seconds
Started Mar 21 03:27:45 PM PDT 24
Finished Mar 21 03:28:29 PM PDT 24
Peak memory 247164 kb
Host smart-c0c76a9d-2309-4bda-b345-601d89195353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082120972 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.2082120972
Directory /workspace/19.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_lock.2078147706
Short name T404
Test name
Test status
Simulation time 1058894048 ps
CPU time 20.01 seconds
Started Mar 21 03:27:49 PM PDT 24
Finished Mar 21 03:28:09 PM PDT 24
Peak memory 241608 kb
Host smart-38157343-3091-4e63-bc0d-6f4c4829d788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078147706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.2078147706
Directory /workspace/19.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/19.otp_ctrl_init_fail.1970347943
Short name T107
Test name
Test status
Simulation time 2342391195 ps
CPU time 6.02 seconds
Started Mar 21 03:27:45 PM PDT 24
Finished Mar 21 03:27:51 PM PDT 24
Peak memory 241792 kb
Host smart-9b79cd3a-8de3-4af8-acd8-7fb7173a4c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970347943 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.1970347943
Directory /workspace/19.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_macro_errs.2045268026
Short name T789
Test name
Test status
Simulation time 11054704318 ps
CPU time 20.38 seconds
Started Mar 21 03:27:47 PM PDT 24
Finished Mar 21 03:28:07 PM PDT 24
Peak memory 248340 kb
Host smart-6601f2cd-790f-4cb0-8f02-007d97ead65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045268026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.2045268026
Directory /workspace/19.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_key_req.2790761956
Short name T547
Test name
Test status
Simulation time 1173892842 ps
CPU time 25.23 seconds
Started Mar 21 03:27:59 PM PDT 24
Finished Mar 21 03:28:25 PM PDT 24
Peak memory 241760 kb
Host smart-53fc8edd-ac3f-4072-acf4-9378442251a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790761956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_key_req.2790761956
Directory /workspace/19.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_esc.988743272
Short name T134
Test name
Test status
Simulation time 2013904999 ps
CPU time 8.4 seconds
Started Mar 21 03:27:46 PM PDT 24
Finished Mar 21 03:27:55 PM PDT 24
Peak memory 241232 kb
Host smart-f62c4f5e-dd5b-45b6-b703-9aa5be7ede22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988743272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.988743272
Directory /workspace/19.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_req.4037668709
Short name T1005
Test name
Test status
Simulation time 953169254 ps
CPU time 16.39 seconds
Started Mar 21 03:27:46 PM PDT 24
Finished Mar 21 03:28:03 PM PDT 24
Peak memory 241240 kb
Host smart-b15e10af-ad23-451e-9f50-be661414d68d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4037668709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_req.4037668709
Directory /workspace/19.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_regwen.260994063
Short name T384
Test name
Test status
Simulation time 239376973 ps
CPU time 7.26 seconds
Started Mar 21 03:27:58 PM PDT 24
Finished Mar 21 03:28:06 PM PDT 24
Peak memory 241372 kb
Host smart-85cd22e5-53a8-461b-a42a-6506ac793115
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=260994063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.260994063
Directory /workspace/19.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/19.otp_ctrl_smoke.3625757234
Short name T759
Test name
Test status
Simulation time 3477512902 ps
CPU time 8.3 seconds
Started Mar 21 03:27:47 PM PDT 24
Finished Mar 21 03:27:56 PM PDT 24
Peak memory 241300 kb
Host smart-4aeaaab1-2823-4fd1-bada-f1bd000b4c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625757234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.3625757234
Directory /workspace/19.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all.502946063
Short name T1095
Test name
Test status
Simulation time 5214399063 ps
CPU time 117.86 seconds
Started Mar 21 03:27:56 PM PDT 24
Finished Mar 21 03:29:55 PM PDT 24
Peak memory 251784 kb
Host smart-6a7a8911-dbf2-44e2-acd7-8796603cb129
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502946063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all.
502946063
Directory /workspace/19.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.otp_ctrl_test_access.3507130629
Short name T511
Test name
Test status
Simulation time 2422902204 ps
CPU time 32.77 seconds
Started Mar 21 03:27:56 PM PDT 24
Finished Mar 21 03:28:29 PM PDT 24
Peak memory 241532 kb
Host smart-52de7cf2-52df-45dc-9140-35219764837a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507130629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.3507130629
Directory /workspace/19.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/190.otp_ctrl_init_fail.1607250429
Short name T565
Test name
Test status
Simulation time 128617966 ps
CPU time 4.83 seconds
Started Mar 21 03:30:49 PM PDT 24
Finished Mar 21 03:30:54 PM PDT 24
Peak memory 241324 kb
Host smart-b7e6823f-9539-4f22-9d6d-bfa50b25b937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607250429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.1607250429
Directory /workspace/190.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/190.otp_ctrl_parallel_lc_esc.436611126
Short name T649
Test name
Test status
Simulation time 364810473 ps
CPU time 3.96 seconds
Started Mar 21 03:30:49 PM PDT 24
Finished Mar 21 03:30:53 PM PDT 24
Peak memory 241120 kb
Host smart-cdc7dd1a-f0a8-4204-a19a-08e06daffe09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436611126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.436611126
Directory /workspace/190.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/191.otp_ctrl_init_fail.1366093156
Short name T1066
Test name
Test status
Simulation time 140289429 ps
CPU time 4.33 seconds
Started Mar 21 03:30:48 PM PDT 24
Finished Mar 21 03:30:52 PM PDT 24
Peak memory 241388 kb
Host smart-d5af76d4-915c-4b3a-834f-edef621a2a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366093156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.1366093156
Directory /workspace/191.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/191.otp_ctrl_parallel_lc_esc.2006575893
Short name T157
Test name
Test status
Simulation time 285319064 ps
CPU time 7.03 seconds
Started Mar 21 03:30:49 PM PDT 24
Finished Mar 21 03:30:56 PM PDT 24
Peak memory 241688 kb
Host smart-4132008d-8ba6-4453-8231-154783661970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006575893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.2006575893
Directory /workspace/191.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/192.otp_ctrl_init_fail.3559332762
Short name T992
Test name
Test status
Simulation time 283942300 ps
CPU time 4.06 seconds
Started Mar 21 03:30:50 PM PDT 24
Finished Mar 21 03:30:54 PM PDT 24
Peak memory 241728 kb
Host smart-12f0ec02-aab2-410d-ae00-a60051d7a159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559332762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.3559332762
Directory /workspace/192.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/192.otp_ctrl_parallel_lc_esc.4128472684
Short name T262
Test name
Test status
Simulation time 2783524891 ps
CPU time 7.25 seconds
Started Mar 21 03:30:54 PM PDT 24
Finished Mar 21 03:31:01 PM PDT 24
Peak memory 241764 kb
Host smart-5b74c8d9-0287-4f3f-9767-b5e2a8560511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128472684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.4128472684
Directory /workspace/192.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/193.otp_ctrl_init_fail.4249883349
Short name T777
Test name
Test status
Simulation time 275444674 ps
CPU time 3.69 seconds
Started Mar 21 03:30:49 PM PDT 24
Finished Mar 21 03:30:53 PM PDT 24
Peak memory 241364 kb
Host smart-fb40076f-653b-4569-b288-8201a0a080ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249883349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.4249883349
Directory /workspace/193.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/194.otp_ctrl_init_fail.1066595716
Short name T109
Test name
Test status
Simulation time 259066555 ps
CPU time 4.11 seconds
Started Mar 21 03:30:54 PM PDT 24
Finished Mar 21 03:30:58 PM PDT 24
Peak memory 241000 kb
Host smart-4e05d2c4-fd5c-4354-81e1-4734d47cb573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066595716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.1066595716
Directory /workspace/194.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/194.otp_ctrl_parallel_lc_esc.3765188331
Short name T766
Test name
Test status
Simulation time 549949367 ps
CPU time 7.56 seconds
Started Mar 21 03:30:54 PM PDT 24
Finished Mar 21 03:31:02 PM PDT 24
Peak memory 241068 kb
Host smart-e6ef8c19-57d0-4292-867a-1a6a84cd63bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765188331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.3765188331
Directory /workspace/194.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/195.otp_ctrl_init_fail.1150745698
Short name T971
Test name
Test status
Simulation time 287344024 ps
CPU time 4.31 seconds
Started Mar 21 03:30:48 PM PDT 24
Finished Mar 21 03:30:52 PM PDT 24
Peak memory 241700 kb
Host smart-fd81f986-e970-4890-928f-51130c732961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150745698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.1150745698
Directory /workspace/195.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/195.otp_ctrl_parallel_lc_esc.2320867734
Short name T1146
Test name
Test status
Simulation time 907245787 ps
CPU time 19.04 seconds
Started Mar 21 03:30:48 PM PDT 24
Finished Mar 21 03:31:08 PM PDT 24
Peak memory 241656 kb
Host smart-585393f6-a9de-4250-9d1c-831584fb1df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320867734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.2320867734
Directory /workspace/195.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/196.otp_ctrl_init_fail.1362348350
Short name T588
Test name
Test status
Simulation time 1919968293 ps
CPU time 6.31 seconds
Started Mar 21 03:30:49 PM PDT 24
Finished Mar 21 03:30:55 PM PDT 24
Peak memory 241640 kb
Host smart-5620896d-ddda-4f1e-9966-65c34130c76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362348350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.1362348350
Directory /workspace/196.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/196.otp_ctrl_parallel_lc_esc.3836942391
Short name T800
Test name
Test status
Simulation time 349689755 ps
CPU time 17.86 seconds
Started Mar 21 03:30:54 PM PDT 24
Finished Mar 21 03:31:12 PM PDT 24
Peak memory 241152 kb
Host smart-c0c9208b-e0eb-40d2-9e86-1be9156ac079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836942391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.3836942391
Directory /workspace/196.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/197.otp_ctrl_init_fail.2147900619
Short name T1097
Test name
Test status
Simulation time 236857396 ps
CPU time 4.14 seconds
Started Mar 21 03:30:50 PM PDT 24
Finished Mar 21 03:30:54 PM PDT 24
Peak memory 241596 kb
Host smart-0eefeb57-e077-4390-8bcd-d60f7546cbe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147900619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.2147900619
Directory /workspace/197.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/197.otp_ctrl_parallel_lc_esc.1983453285
Short name T1003
Test name
Test status
Simulation time 190857533 ps
CPU time 5.36 seconds
Started Mar 21 03:30:51 PM PDT 24
Finished Mar 21 03:30:56 PM PDT 24
Peak memory 241620 kb
Host smart-eb43e16e-58fc-4fa0-a4e9-b6a992992811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983453285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.1983453285
Directory /workspace/197.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/198.otp_ctrl_init_fail.1127544676
Short name T37
Test name
Test status
Simulation time 146008518 ps
CPU time 4.24 seconds
Started Mar 21 03:30:50 PM PDT 24
Finished Mar 21 03:30:54 PM PDT 24
Peak memory 241312 kb
Host smart-ea90d155-25d1-41e8-a2c4-3f1548e30225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127544676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.1127544676
Directory /workspace/198.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/198.otp_ctrl_parallel_lc_esc.2145012041
Short name T847
Test name
Test status
Simulation time 355521753 ps
CPU time 8.43 seconds
Started Mar 21 03:30:49 PM PDT 24
Finished Mar 21 03:30:58 PM PDT 24
Peak memory 241296 kb
Host smart-45909c56-f620-436d-90cc-e8eaf90deee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145012041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.2145012041
Directory /workspace/198.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/199.otp_ctrl_init_fail.2079096793
Short name T821
Test name
Test status
Simulation time 135214760 ps
CPU time 5.02 seconds
Started Mar 21 03:30:45 PM PDT 24
Finished Mar 21 03:30:50 PM PDT 24
Peak memory 241372 kb
Host smart-c6b6684d-fdfb-4522-bf15-fe23f9b59900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079096793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.2079096793
Directory /workspace/199.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/199.otp_ctrl_parallel_lc_esc.2280353691
Short name T596
Test name
Test status
Simulation time 476610641 ps
CPU time 5.5 seconds
Started Mar 21 03:30:46 PM PDT 24
Finished Mar 21 03:30:52 PM PDT 24
Peak memory 241096 kb
Host smart-cbeecf87-9b9d-4eb5-a0a3-277935a8fea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280353691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.2280353691
Directory /workspace/199.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_alert_test.1037725155
Short name T429
Test name
Test status
Simulation time 55784115 ps
CPU time 1.85 seconds
Started Mar 21 03:26:59 PM PDT 24
Finished Mar 21 03:27:01 PM PDT 24
Peak memory 239932 kb
Host smart-83ddf92d-24dc-4e52-bffc-96b8f8acbc55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037725155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.1037725155
Directory /workspace/2.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.otp_ctrl_background_chks.4106530343
Short name T124
Test name
Test status
Simulation time 602846601 ps
CPU time 8.87 seconds
Started Mar 21 03:27:03 PM PDT 24
Finished Mar 21 03:27:12 PM PDT 24
Peak memory 241408 kb
Host smart-82409171-e7bd-4ece-bb5a-9613b29cc7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106530343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.4106530343
Directory /workspace/2.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/2.otp_ctrl_check_fail.3105537892
Short name T55
Test name
Test status
Simulation time 1382894504 ps
CPU time 32.38 seconds
Started Mar 21 03:27:02 PM PDT 24
Finished Mar 21 03:27:35 PM PDT 24
Peak memory 243272 kb
Host smart-635a6ee6-d129-4146-85a4-3da1dcaba8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105537892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.3105537892
Directory /workspace/2.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_errs.1455451570
Short name T639
Test name
Test status
Simulation time 2515056961 ps
CPU time 10.82 seconds
Started Mar 21 03:27:02 PM PDT 24
Finished Mar 21 03:27:13 PM PDT 24
Peak memory 241484 kb
Host smart-ab324304-96c3-46ec-9470-4ff9d39f4a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455451570 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.1455451570
Directory /workspace/2.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_lock.875641693
Short name T633
Test name
Test status
Simulation time 1059310971 ps
CPU time 31.35 seconds
Started Mar 21 03:27:03 PM PDT 24
Finished Mar 21 03:27:34 PM PDT 24
Peak memory 242240 kb
Host smart-44a1d9cf-e1c3-46eb-8546-c11835de99ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875641693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.875641693
Directory /workspace/2.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/2.otp_ctrl_init_fail.2043672029
Short name T924
Test name
Test status
Simulation time 535365449 ps
CPU time 4.53 seconds
Started Mar 21 03:27:04 PM PDT 24
Finished Mar 21 03:27:09 PM PDT 24
Peak memory 241584 kb
Host smart-f46466d2-2d0b-4644-a26c-fcf86041dbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043672029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.2043672029
Directory /workspace/2.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_macro_errs.1745576595
Short name T578
Test name
Test status
Simulation time 1097115367 ps
CPU time 12.43 seconds
Started Mar 21 03:26:57 PM PDT 24
Finished Mar 21 03:27:10 PM PDT 24
Peak memory 241916 kb
Host smart-05f890b0-7707-483d-8eb6-0cabad4e2d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745576595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.1745576595
Directory /workspace/2.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_key_req.3578164562
Short name T471
Test name
Test status
Simulation time 295801053 ps
CPU time 4.54 seconds
Started Mar 21 03:27:04 PM PDT 24
Finished Mar 21 03:27:08 PM PDT 24
Peak memory 241268 kb
Host smart-da296797-6519-4510-bd9b-1f839512a00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578164562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.3578164562
Directory /workspace/2.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_esc.1328083751
Short name T1157
Test name
Test status
Simulation time 1002130214 ps
CPU time 8.92 seconds
Started Mar 21 03:27:04 PM PDT 24
Finished Mar 21 03:27:13 PM PDT 24
Peak memory 241336 kb
Host smart-4d9b75ee-d258-49ed-a013-ebf51dc542df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328083751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.1328083751
Directory /workspace/2.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_req.168212282
Short name T395
Test name
Test status
Simulation time 404933061 ps
CPU time 11.49 seconds
Started Mar 21 03:27:03 PM PDT 24
Finished Mar 21 03:27:15 PM PDT 24
Peak memory 241188 kb
Host smart-ca221153-19f2-49b9-972b-a24c71b3cde0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=168212282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.168212282
Directory /workspace/2.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_regwen.1866860369
Short name T275
Test name
Test status
Simulation time 369568196 ps
CPU time 10.03 seconds
Started Mar 21 03:27:03 PM PDT 24
Finished Mar 21 03:27:13 PM PDT 24
Peak memory 241692 kb
Host smart-e897ca4f-d1de-432a-82b2-19cf0d1c029d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1866860369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.1866860369
Directory /workspace/2.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/2.otp_ctrl_smoke.248822087
Short name T732
Test name
Test status
Simulation time 838779812 ps
CPU time 12.85 seconds
Started Mar 21 03:27:02 PM PDT 24
Finished Mar 21 03:27:15 PM PDT 24
Peak memory 241292 kb
Host smart-e3482481-aab0-450a-a84e-016e3a1537e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248822087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.248822087
Directory /workspace/2.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all.4247171396
Short name T409
Test name
Test status
Simulation time 39231251927 ps
CPU time 90.56 seconds
Started Mar 21 03:27:01 PM PDT 24
Finished Mar 21 03:28:32 PM PDT 24
Peak memory 245844 kb
Host smart-e3092d0a-8f0a-46f8-9900-eac7eaf8e541
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247171396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all.
4247171396
Directory /workspace/2.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all_with_rand_reset.3086035775
Short name T803
Test name
Test status
Simulation time 80471367253 ps
CPU time 693.56 seconds
Started Mar 21 03:27:01 PM PDT 24
Finished Mar 21 03:38:35 PM PDT 24
Peak memory 344264 kb
Host smart-1be766de-e98e-4091-aa12-3b92850064ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086035775 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all_with_rand_reset.3086035775
Directory /workspace/2.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.otp_ctrl_test_access.3655555407
Short name T905
Test name
Test status
Simulation time 1794042007 ps
CPU time 15.5 seconds
Started Mar 21 03:27:02 PM PDT 24
Finished Mar 21 03:27:18 PM PDT 24
Peak memory 241556 kb
Host smart-417cc6f8-fbfc-4b57-a906-c4f5cf388ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655555407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.3655555407
Directory /workspace/2.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/20.otp_ctrl_alert_test.3923565637
Short name T1024
Test name
Test status
Simulation time 231746823 ps
CPU time 2.23 seconds
Started Mar 21 03:27:53 PM PDT 24
Finished Mar 21 03:27:55 PM PDT 24
Peak memory 240008 kb
Host smart-6b19192d-dd86-4f6d-9f26-fd6b8fe9193d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923565637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.3923565637
Directory /workspace/20.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_errs.327119034
Short name T912
Test name
Test status
Simulation time 754800863 ps
CPU time 24.6 seconds
Started Mar 21 03:27:59 PM PDT 24
Finished Mar 21 03:28:24 PM PDT 24
Peak memory 241408 kb
Host smart-191ecaa6-bf97-451f-860c-7d8b6b0ddd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327119034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.327119034
Directory /workspace/20.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_lock.3879427302
Short name T98
Test name
Test status
Simulation time 2648558476 ps
CPU time 22.04 seconds
Started Mar 21 03:27:57 PM PDT 24
Finished Mar 21 03:28:20 PM PDT 24
Peak memory 241800 kb
Host smart-6bee592c-09bd-4d83-a40d-188c960a7346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879427302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.3879427302
Directory /workspace/20.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/20.otp_ctrl_init_fail.286783296
Short name T47
Test name
Test status
Simulation time 1657070903 ps
CPU time 6.17 seconds
Started Mar 21 03:28:01 PM PDT 24
Finished Mar 21 03:28:08 PM PDT 24
Peak memory 241220 kb
Host smart-c9336362-5d28-462f-aa3b-524235e962e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286783296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.286783296
Directory /workspace/20.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_macro_errs.1135390608
Short name T828
Test name
Test status
Simulation time 816181138 ps
CPU time 10.28 seconds
Started Mar 21 03:27:57 PM PDT 24
Finished Mar 21 03:28:07 PM PDT 24
Peak memory 242860 kb
Host smart-71bbf633-26f3-4397-90d0-cb0875fef8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135390608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_macro_errs.1135390608
Directory /workspace/20.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_key_req.654043302
Short name T256
Test name
Test status
Simulation time 388068012 ps
CPU time 6.61 seconds
Started Mar 21 03:27:56 PM PDT 24
Finished Mar 21 03:28:03 PM PDT 24
Peak memory 241328 kb
Host smart-8aa4207f-0858-49a3-8251-fe4637e3c57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654043302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.654043302
Directory /workspace/20.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_esc.3580907262
Short name T892
Test name
Test status
Simulation time 2188424844 ps
CPU time 7.05 seconds
Started Mar 21 03:27:55 PM PDT 24
Finished Mar 21 03:28:03 PM PDT 24
Peak memory 241516 kb
Host smart-d04f30fd-b4e1-473f-b963-d2af0c389184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580907262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.3580907262
Directory /workspace/20.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_req.3621012902
Short name T1080
Test name
Test status
Simulation time 764188861 ps
CPU time 18.92 seconds
Started Mar 21 03:27:56 PM PDT 24
Finished Mar 21 03:28:15 PM PDT 24
Peak memory 241272 kb
Host smart-bd3861d1-941e-4516-bf0f-523d8bc82059
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3621012902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.3621012902
Directory /workspace/20.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_regwen.3524608943
Short name T737
Test name
Test status
Simulation time 811704506 ps
CPU time 8.04 seconds
Started Mar 21 03:27:57 PM PDT 24
Finished Mar 21 03:28:06 PM PDT 24
Peak memory 241472 kb
Host smart-aed4adb0-e88a-41dd-9b84-8a403d741697
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3524608943 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.3524608943
Directory /workspace/20.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/20.otp_ctrl_smoke.46385704
Short name T465
Test name
Test status
Simulation time 811921761 ps
CPU time 6.49 seconds
Started Mar 21 03:27:54 PM PDT 24
Finished Mar 21 03:28:01 PM PDT 24
Peak memory 241368 kb
Host smart-cd3373fe-71c0-46ac-817d-7ac27d8f2835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46385704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.46385704
Directory /workspace/20.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all_with_rand_reset.151356595
Short name T1162
Test name
Test status
Simulation time 2483106237328 ps
CPU time 5778.78 seconds
Started Mar 21 03:27:55 PM PDT 24
Finished Mar 21 05:04:15 PM PDT 24
Peak memory 336420 kb
Host smart-dc22dcbc-0a90-4476-8c98-c6ff63868653
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151356595 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all_with_rand_reset.151356595
Directory /workspace/20.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.otp_ctrl_test_access.3898127424
Short name T392
Test name
Test status
Simulation time 5617011857 ps
CPU time 15 seconds
Started Mar 21 03:27:58 PM PDT 24
Finished Mar 21 03:28:13 PM PDT 24
Peak memory 242108 kb
Host smart-ccd02872-aced-4300-a517-8bd646b86ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898127424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.3898127424
Directory /workspace/20.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/200.otp_ctrl_init_fail.3097600942
Short name T233
Test name
Test status
Simulation time 2512937059 ps
CPU time 5.52 seconds
Started Mar 21 03:30:45 PM PDT 24
Finished Mar 21 03:30:50 PM PDT 24
Peak memory 241924 kb
Host smart-becdea01-d419-4470-b594-b835b306c04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097600942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.3097600942
Directory /workspace/200.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/201.otp_ctrl_init_fail.970142512
Short name T809
Test name
Test status
Simulation time 162032418 ps
CPU time 3.87 seconds
Started Mar 21 03:30:45 PM PDT 24
Finished Mar 21 03:30:49 PM PDT 24
Peak memory 241300 kb
Host smart-45edb98d-d272-4b37-91fa-214e672a0b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970142512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.970142512
Directory /workspace/201.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/203.otp_ctrl_init_fail.3053326449
Short name T826
Test name
Test status
Simulation time 99628677 ps
CPU time 4.21 seconds
Started Mar 21 03:30:47 PM PDT 24
Finished Mar 21 03:30:51 PM PDT 24
Peak memory 241264 kb
Host smart-edcfe202-93e1-49f7-9c3f-b3f539bec38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053326449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.3053326449
Directory /workspace/203.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/204.otp_ctrl_init_fail.1275605372
Short name T594
Test name
Test status
Simulation time 116918725 ps
CPU time 4.57 seconds
Started Mar 21 03:30:44 PM PDT 24
Finished Mar 21 03:30:49 PM PDT 24
Peak memory 241376 kb
Host smart-f003964f-39f6-4efe-9576-895508761d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275605372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.1275605372
Directory /workspace/204.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/205.otp_ctrl_init_fail.1703008121
Short name T498
Test name
Test status
Simulation time 2283658681 ps
CPU time 4.31 seconds
Started Mar 21 03:30:44 PM PDT 24
Finished Mar 21 03:30:49 PM PDT 24
Peak memory 241772 kb
Host smart-cf7df870-a353-4b3a-90be-9116a8953622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703008121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.1703008121
Directory /workspace/205.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/206.otp_ctrl_init_fail.4124645915
Short name T91
Test name
Test status
Simulation time 2285992651 ps
CPU time 5.5 seconds
Started Mar 21 03:30:45 PM PDT 24
Finished Mar 21 03:30:51 PM PDT 24
Peak memory 241548 kb
Host smart-5ea672f4-d41b-4a18-aa3b-ef2722f5cfed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124645915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.4124645915
Directory /workspace/206.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/207.otp_ctrl_init_fail.3969007394
Short name T112
Test name
Test status
Simulation time 98125255 ps
CPU time 3.7 seconds
Started Mar 21 03:30:46 PM PDT 24
Finished Mar 21 03:30:50 PM PDT 24
Peak memory 241452 kb
Host smart-79104f47-c9d3-4ddc-9e04-5e5a9b6b5ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969007394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.3969007394
Directory /workspace/207.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/208.otp_ctrl_init_fail.3715460769
Short name T1017
Test name
Test status
Simulation time 2102316312 ps
CPU time 4.59 seconds
Started Mar 21 03:30:48 PM PDT 24
Finished Mar 21 03:30:53 PM PDT 24
Peak memory 241420 kb
Host smart-c3c277d7-5158-43d5-aeaa-fe10621f5abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715460769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.3715460769
Directory /workspace/208.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/209.otp_ctrl_init_fail.1474071133
Short name T561
Test name
Test status
Simulation time 434130939 ps
CPU time 3.86 seconds
Started Mar 21 03:30:49 PM PDT 24
Finished Mar 21 03:30:53 PM PDT 24
Peak memory 241668 kb
Host smart-3627b1bc-235f-4cff-afae-d59d85dab7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474071133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.1474071133
Directory /workspace/209.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_alert_test.1777048746
Short name T1107
Test name
Test status
Simulation time 89705828 ps
CPU time 1.88 seconds
Started Mar 21 03:27:57 PM PDT 24
Finished Mar 21 03:27:59 PM PDT 24
Peak memory 239900 kb
Host smart-6340bb6d-37f5-4f7f-8138-f355a380d9fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777048746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.1777048746
Directory /workspace/21.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.otp_ctrl_check_fail.2145451819
Short name T62
Test name
Test status
Simulation time 867842159 ps
CPU time 10.45 seconds
Started Mar 21 03:27:56 PM PDT 24
Finished Mar 21 03:28:07 PM PDT 24
Peak memory 241504 kb
Host smart-8a121485-40f0-471d-8c16-b115effb778f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145451819 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.2145451819
Directory /workspace/21.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_errs.3630476227
Short name T983
Test name
Test status
Simulation time 2009724010 ps
CPU time 40.07 seconds
Started Mar 21 03:27:56 PM PDT 24
Finished Mar 21 03:28:36 PM PDT 24
Peak memory 245968 kb
Host smart-ea332080-7319-49a7-9f68-a25124226114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630476227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.3630476227
Directory /workspace/21.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_lock.1474107610
Short name T572
Test name
Test status
Simulation time 1015691540 ps
CPU time 21.57 seconds
Started Mar 21 03:27:59 PM PDT 24
Finished Mar 21 03:28:21 PM PDT 24
Peak memory 241432 kb
Host smart-79cd1f38-7433-4ae6-b876-27a22bd8e4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474107610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.1474107610
Directory /workspace/21.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/21.otp_ctrl_init_fail.1881922995
Short name T460
Test name
Test status
Simulation time 220975962 ps
CPU time 4.55 seconds
Started Mar 21 03:27:57 PM PDT 24
Finished Mar 21 03:28:01 PM PDT 24
Peak memory 241612 kb
Host smart-d577e929-f7bd-4aaf-9131-57f5f4bb3ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881922995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.1881922995
Directory /workspace/21.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_macro_errs.2730673371
Short name T188
Test name
Test status
Simulation time 11578289624 ps
CPU time 38.87 seconds
Started Mar 21 03:27:59 PM PDT 24
Finished Mar 21 03:28:38 PM PDT 24
Peak memory 245768 kb
Host smart-81b3bdb1-5887-47b1-b64d-35a7a4d687f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730673371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_macro_errs.2730673371
Directory /workspace/21.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_key_req.566061041
Short name T438
Test name
Test status
Simulation time 263763760 ps
CPU time 9.99 seconds
Started Mar 21 03:27:57 PM PDT 24
Finished Mar 21 03:28:07 PM PDT 24
Peak memory 241548 kb
Host smart-41c48516-18dc-4f37-aed2-3e5738de88b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566061041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.566061041
Directory /workspace/21.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_esc.433541797
Short name T533
Test name
Test status
Simulation time 250754552 ps
CPU time 6.13 seconds
Started Mar 21 03:28:00 PM PDT 24
Finished Mar 21 03:28:06 PM PDT 24
Peak memory 241144 kb
Host smart-ea9bc0ea-3cb8-47be-96be-9d1e185c3510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433541797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.433541797
Directory /workspace/21.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_req.1037831537
Short name T484
Test name
Test status
Simulation time 1482938839 ps
CPU time 23.47 seconds
Started Mar 21 03:27:58 PM PDT 24
Finished Mar 21 03:28:23 PM PDT 24
Peak memory 241164 kb
Host smart-0375db9c-a840-4987-85fc-351ae96309fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1037831537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_req.1037831537
Directory /workspace/21.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_regwen.418928152
Short name T1143
Test name
Test status
Simulation time 403107606 ps
CPU time 4.21 seconds
Started Mar 21 03:27:57 PM PDT 24
Finished Mar 21 03:28:02 PM PDT 24
Peak memory 241260 kb
Host smart-d54799a4-4c5e-46b5-b5ff-4ff7764cbe2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=418928152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.418928152
Directory /workspace/21.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/21.otp_ctrl_smoke.3584739278
Short name T495
Test name
Test status
Simulation time 949551677 ps
CPU time 12.24 seconds
Started Mar 21 03:27:57 PM PDT 24
Finished Mar 21 03:28:10 PM PDT 24
Peak memory 241308 kb
Host smart-590d322c-027e-4c66-b5c6-e456b19699ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584739278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.3584739278
Directory /workspace/21.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all.3180914558
Short name T1142
Test name
Test status
Simulation time 60396290742 ps
CPU time 196.66 seconds
Started Mar 21 03:27:59 PM PDT 24
Finished Mar 21 03:31:16 PM PDT 24
Peak memory 248448 kb
Host smart-69f63930-2d51-4053-b80a-2e65e1e008c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180914558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all
.3180914558
Directory /workspace/21.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all_with_rand_reset.3763192857
Short name T253
Test name
Test status
Simulation time 134463721779 ps
CPU time 1167.7 seconds
Started Mar 21 03:27:58 PM PDT 24
Finished Mar 21 03:47:27 PM PDT 24
Peak memory 284652 kb
Host smart-808c7e43-30a2-40bc-9e11-e9c28a33a19a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763192857 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all_with_rand_reset.3763192857
Directory /workspace/21.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.otp_ctrl_test_access.1090397712
Short name T19
Test name
Test status
Simulation time 1618850100 ps
CPU time 15 seconds
Started Mar 21 03:27:57 PM PDT 24
Finished Mar 21 03:28:13 PM PDT 24
Peak memory 241240 kb
Host smart-eaebf26c-edb2-4b29-aad3-927b17b310a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090397712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.1090397712
Directory /workspace/21.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/210.otp_ctrl_init_fail.3667166179
Short name T1117
Test name
Test status
Simulation time 526936190 ps
CPU time 4.79 seconds
Started Mar 21 03:30:48 PM PDT 24
Finished Mar 21 03:30:53 PM PDT 24
Peak memory 241284 kb
Host smart-8eea14d9-2fb4-4e50-832a-35fafd935e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667166179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.3667166179
Directory /workspace/210.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/211.otp_ctrl_init_fail.4182390865
Short name T462
Test name
Test status
Simulation time 219540359 ps
CPU time 4.75 seconds
Started Mar 21 03:30:48 PM PDT 24
Finished Mar 21 03:30:52 PM PDT 24
Peak memory 241088 kb
Host smart-d2e4631e-b7f5-4fc7-aaca-c4a3f0aaff11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182390865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.4182390865
Directory /workspace/211.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/212.otp_ctrl_init_fail.1766179838
Short name T590
Test name
Test status
Simulation time 2041093516 ps
CPU time 6.25 seconds
Started Mar 21 03:30:47 PM PDT 24
Finished Mar 21 03:30:54 PM PDT 24
Peak memory 241696 kb
Host smart-a436175c-c009-4299-a955-de5cdfa0ed0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766179838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.1766179838
Directory /workspace/212.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/213.otp_ctrl_init_fail.1977785393
Short name T944
Test name
Test status
Simulation time 134191583 ps
CPU time 3.83 seconds
Started Mar 21 03:30:47 PM PDT 24
Finished Mar 21 03:30:51 PM PDT 24
Peak memory 241696 kb
Host smart-90902adb-0390-487b-a276-e86e18d52a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977785393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.1977785393
Directory /workspace/213.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/214.otp_ctrl_init_fail.1645071950
Short name T910
Test name
Test status
Simulation time 126738055 ps
CPU time 4.37 seconds
Started Mar 21 03:30:48 PM PDT 24
Finished Mar 21 03:30:53 PM PDT 24
Peak memory 241372 kb
Host smart-03b78ee8-9e33-4efb-b533-21ceffd7252b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645071950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.1645071950
Directory /workspace/214.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/215.otp_ctrl_init_fail.1242553698
Short name T1163
Test name
Test status
Simulation time 148231090 ps
CPU time 3.86 seconds
Started Mar 21 03:30:46 PM PDT 24
Finished Mar 21 03:30:50 PM PDT 24
Peak memory 241328 kb
Host smart-30bb4850-b8cf-4685-963b-9512125f668d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242553698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.1242553698
Directory /workspace/215.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/216.otp_ctrl_init_fail.3781065097
Short name T997
Test name
Test status
Simulation time 100799477 ps
CPU time 3.94 seconds
Started Mar 21 03:31:08 PM PDT 24
Finished Mar 21 03:31:12 PM PDT 24
Peak memory 241360 kb
Host smart-5e70c321-39ba-4bfe-b929-f87e5bfb9be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781065097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.3781065097
Directory /workspace/216.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/217.otp_ctrl_init_fail.2726157190
Short name T698
Test name
Test status
Simulation time 253034802 ps
CPU time 3.73 seconds
Started Mar 21 03:31:07 PM PDT 24
Finished Mar 21 03:31:11 PM PDT 24
Peak memory 241500 kb
Host smart-d2fb5689-11de-450e-bb37-a61c11f85a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726157190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.2726157190
Directory /workspace/217.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/218.otp_ctrl_init_fail.258096000
Short name T866
Test name
Test status
Simulation time 2340371258 ps
CPU time 5.49 seconds
Started Mar 21 03:31:07 PM PDT 24
Finished Mar 21 03:31:13 PM PDT 24
Peak memory 241772 kb
Host smart-aa732036-8a01-4bbe-a41a-6f537dafc219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258096000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.258096000
Directory /workspace/218.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/219.otp_ctrl_init_fail.970858242
Short name T953
Test name
Test status
Simulation time 468776520 ps
CPU time 5.13 seconds
Started Mar 21 03:31:09 PM PDT 24
Finished Mar 21 03:31:14 PM PDT 24
Peak memory 241652 kb
Host smart-d159df2f-0a52-43d0-95f8-ac1c888e35e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970858242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.970858242
Directory /workspace/219.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_alert_test.3781455768
Short name T1058
Test name
Test status
Simulation time 59467907 ps
CPU time 1.86 seconds
Started Mar 21 03:28:02 PM PDT 24
Finished Mar 21 03:28:04 PM PDT 24
Peak memory 239916 kb
Host smart-8e9f5af8-bf71-4e16-a8bc-d3196554a51f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781455768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.3781455768
Directory /workspace/22.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_errs.2715841597
Short name T1063
Test name
Test status
Simulation time 1087428766 ps
CPU time 25.74 seconds
Started Mar 21 03:27:56 PM PDT 24
Finished Mar 21 03:28:22 PM PDT 24
Peak memory 241304 kb
Host smart-bdc53cbd-efb5-4e63-9d02-3840ff3d764b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715841597 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.2715841597
Directory /workspace/22.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_lock.360849692
Short name T322
Test name
Test status
Simulation time 215078115 ps
CPU time 8.28 seconds
Started Mar 21 03:28:00 PM PDT 24
Finished Mar 21 03:28:08 PM PDT 24
Peak memory 241592 kb
Host smart-b85737da-e3ba-4825-8f29-e427db274bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360849692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.360849692
Directory /workspace/22.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/22.otp_ctrl_init_fail.654747599
Short name T652
Test name
Test status
Simulation time 283153373 ps
CPU time 4.7 seconds
Started Mar 21 03:27:56 PM PDT 24
Finished Mar 21 03:28:01 PM PDT 24
Peak memory 241472 kb
Host smart-8cb05239-568e-4d68-862c-bcec545b10f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654747599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.654747599
Directory /workspace/22.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_macro_errs.1220758400
Short name T648
Test name
Test status
Simulation time 13031911075 ps
CPU time 25.17 seconds
Started Mar 21 03:27:55 PM PDT 24
Finished Mar 21 03:28:21 PM PDT 24
Peak memory 248076 kb
Host smart-ed924e58-fe22-40a2-b4c3-c7654167670c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220758400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_macro_errs.1220758400
Directory /workspace/22.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_key_req.3188581585
Short name T914
Test name
Test status
Simulation time 554952627 ps
CPU time 24.26 seconds
Started Mar 21 03:27:59 PM PDT 24
Finished Mar 21 03:28:24 PM PDT 24
Peak memory 241216 kb
Host smart-db99484e-44f9-47fc-bafb-be783745e139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188581585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.3188581585
Directory /workspace/22.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_esc.1493155157
Short name T678
Test name
Test status
Simulation time 702200736 ps
CPU time 16.32 seconds
Started Mar 21 03:27:59 PM PDT 24
Finished Mar 21 03:28:16 PM PDT 24
Peak memory 241800 kb
Host smart-e91adfee-a1f9-4654-a809-81ddc3b92f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493155157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.1493155157
Directory /workspace/22.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_req.239050342
Short name T419
Test name
Test status
Simulation time 3242677492 ps
CPU time 8.32 seconds
Started Mar 21 03:27:56 PM PDT 24
Finished Mar 21 03:28:05 PM PDT 24
Peak memory 241336 kb
Host smart-f574d9d9-d38b-4cc7-b9d4-0a4f339e6bfa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=239050342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_req.239050342
Directory /workspace/22.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_regwen.4127185928
Short name T629
Test name
Test status
Simulation time 1061240198 ps
CPU time 8.25 seconds
Started Mar 21 03:28:00 PM PDT 24
Finished Mar 21 03:28:09 PM PDT 24
Peak memory 241616 kb
Host smart-34127605-e623-4f84-9c7f-a521ae8f1788
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4127185928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.4127185928
Directory /workspace/22.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/22.otp_ctrl_smoke.696487037
Short name T1039
Test name
Test status
Simulation time 220712373 ps
CPU time 3.75 seconds
Started Mar 21 03:27:56 PM PDT 24
Finished Mar 21 03:28:00 PM PDT 24
Peak memory 241368 kb
Host smart-c9fcea60-0d7f-44fe-9dbf-80abd382972d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696487037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.696487037
Directory /workspace/22.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all.213958975
Short name T411
Test name
Test status
Simulation time 46353217469 ps
CPU time 194.05 seconds
Started Mar 21 03:28:00 PM PDT 24
Finished Mar 21 03:31:14 PM PDT 24
Peak memory 257552 kb
Host smart-379ff532-ab6e-4396-b809-ceaad1048583
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213958975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all.
213958975
Directory /workspace/22.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all_with_rand_reset.75017787
Short name T1032
Test name
Test status
Simulation time 261139553404 ps
CPU time 2315.52 seconds
Started Mar 21 03:27:54 PM PDT 24
Finished Mar 21 04:06:30 PM PDT 24
Peak memory 599488 kb
Host smart-89e6fe16-69be-4555-9d76-42f9d8627154
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75017787 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all_with_rand_reset.75017787
Directory /workspace/22.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.otp_ctrl_test_access.2284251197
Short name T854
Test name
Test status
Simulation time 723656072 ps
CPU time 13.82 seconds
Started Mar 21 03:28:06 PM PDT 24
Finished Mar 21 03:28:20 PM PDT 24
Peak memory 241620 kb
Host smart-782d76a1-c90e-45bc-a617-73f69061db8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284251197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.2284251197
Directory /workspace/22.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/220.otp_ctrl_init_fail.2793499121
Short name T575
Test name
Test status
Simulation time 213139378 ps
CPU time 3.86 seconds
Started Mar 21 03:31:07 PM PDT 24
Finished Mar 21 03:31:11 PM PDT 24
Peak memory 241320 kb
Host smart-ce3b9b21-6174-414a-ab21-0fda1909472b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793499121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.2793499121
Directory /workspace/220.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/221.otp_ctrl_init_fail.3456070604
Short name T878
Test name
Test status
Simulation time 99891031 ps
CPU time 4.54 seconds
Started Mar 21 03:31:13 PM PDT 24
Finished Mar 21 03:31:18 PM PDT 24
Peak memory 241392 kb
Host smart-10a3147a-bb5c-4c6a-a1df-850b9dc4f6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456070604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.3456070604
Directory /workspace/221.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/222.otp_ctrl_init_fail.4118250065
Short name T1151
Test name
Test status
Simulation time 2019076640 ps
CPU time 3.73 seconds
Started Mar 21 03:31:08 PM PDT 24
Finished Mar 21 03:31:12 PM PDT 24
Peak memory 241416 kb
Host smart-02ba0051-9acd-4cbe-8615-b8f8b336c239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118250065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.4118250065
Directory /workspace/222.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/223.otp_ctrl_init_fail.278513895
Short name T838
Test name
Test status
Simulation time 234490028 ps
CPU time 3.34 seconds
Started Mar 21 03:31:07 PM PDT 24
Finished Mar 21 03:31:11 PM PDT 24
Peak memory 241400 kb
Host smart-e1e90ae5-1ff0-47f5-b59e-b43c4ed29831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278513895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.278513895
Directory /workspace/223.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/224.otp_ctrl_init_fail.1895451578
Short name T1131
Test name
Test status
Simulation time 166776946 ps
CPU time 4.69 seconds
Started Mar 21 03:31:09 PM PDT 24
Finished Mar 21 03:31:15 PM PDT 24
Peak memory 241424 kb
Host smart-62e11862-6403-4baf-a1ac-57f6a4b745b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895451578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.1895451578
Directory /workspace/224.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/226.otp_ctrl_init_fail.818762555
Short name T38
Test name
Test status
Simulation time 436906175 ps
CPU time 4.76 seconds
Started Mar 21 03:31:09 PM PDT 24
Finished Mar 21 03:31:15 PM PDT 24
Peak memory 241220 kb
Host smart-d1ef162d-6bbc-4bbb-a04d-625538357ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818762555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.818762555
Directory /workspace/226.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/227.otp_ctrl_init_fail.3479382978
Short name T125
Test name
Test status
Simulation time 159000454 ps
CPU time 3.86 seconds
Started Mar 21 03:31:09 PM PDT 24
Finished Mar 21 03:31:14 PM PDT 24
Peak memory 241420 kb
Host smart-e7895f33-e9e1-497c-94f4-928718fb8a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479382978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.3479382978
Directory /workspace/227.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/228.otp_ctrl_init_fail.183059602
Short name T574
Test name
Test status
Simulation time 396010855 ps
CPU time 3.63 seconds
Started Mar 21 03:31:08 PM PDT 24
Finished Mar 21 03:31:11 PM PDT 24
Peak memory 241604 kb
Host smart-5d934ea2-9947-49c2-a3cf-7ffb9aae2d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183059602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.183059602
Directory /workspace/228.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/229.otp_ctrl_init_fail.918476995
Short name T954
Test name
Test status
Simulation time 506227168 ps
CPU time 4.48 seconds
Started Mar 21 03:31:09 PM PDT 24
Finished Mar 21 03:31:14 PM PDT 24
Peak memory 241412 kb
Host smart-f6dd266c-4e67-455c-8916-9eace7cfc718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918476995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.918476995
Directory /workspace/229.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_alert_test.3470816511
Short name T843
Test name
Test status
Simulation time 285070547 ps
CPU time 2.42 seconds
Started Mar 21 03:28:00 PM PDT 24
Finished Mar 21 03:28:03 PM PDT 24
Peak memory 240068 kb
Host smart-7e0f9466-ac4e-433a-81c7-6c81dd637f67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470816511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.3470816511
Directory /workspace/23.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.otp_ctrl_check_fail.3100229830
Short name T1034
Test name
Test status
Simulation time 3774041436 ps
CPU time 28.04 seconds
Started Mar 21 03:27:58 PM PDT 24
Finished Mar 21 03:28:27 PM PDT 24
Peak memory 248356 kb
Host smart-411ebbad-5f2f-44aa-9d2c-ec3a01d809c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100229830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.3100229830
Directory /workspace/23.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_errs.2100901322
Short name T1147
Test name
Test status
Simulation time 1711200700 ps
CPU time 40.42 seconds
Started Mar 21 03:27:58 PM PDT 24
Finished Mar 21 03:28:40 PM PDT 24
Peak memory 248524 kb
Host smart-c13ee735-cda9-4371-b051-26dc94ca9eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100901322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.2100901322
Directory /workspace/23.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_lock.1614438038
Short name T526
Test name
Test status
Simulation time 999049947 ps
CPU time 34.5 seconds
Started Mar 21 03:27:57 PM PDT 24
Finished Mar 21 03:28:32 PM PDT 24
Peak memory 241808 kb
Host smart-e821e18d-0174-481f-b883-f738b0b7ddc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614438038 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.1614438038
Directory /workspace/23.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/23.otp_ctrl_init_fail.147185239
Short name T287
Test name
Test status
Simulation time 162307208 ps
CPU time 3.76 seconds
Started Mar 21 03:28:00 PM PDT 24
Finished Mar 21 03:28:04 PM PDT 24
Peak memory 241408 kb
Host smart-5798289b-c423-4f07-a891-a84906c05902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147185239 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.147185239
Directory /workspace/23.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_macro_errs.2290652442
Short name T602
Test name
Test status
Simulation time 3417877319 ps
CPU time 26.09 seconds
Started Mar 21 03:28:03 PM PDT 24
Finished Mar 21 03:28:30 PM PDT 24
Peak memory 248348 kb
Host smart-c6baef39-300b-4a9f-9a9e-e05858874f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290652442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.2290652442
Directory /workspace/23.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_key_req.1777816759
Short name T106
Test name
Test status
Simulation time 10376654295 ps
CPU time 36.72 seconds
Started Mar 21 03:28:01 PM PDT 24
Finished Mar 21 03:28:38 PM PDT 24
Peak memory 241980 kb
Host smart-8f36b5c8-f251-4b79-8ca8-d134e78e9bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777816759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.1777816759
Directory /workspace/23.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_esc.2176793556
Short name T793
Test name
Test status
Simulation time 1747797084 ps
CPU time 23.07 seconds
Started Mar 21 03:27:58 PM PDT 24
Finished Mar 21 03:28:21 PM PDT 24
Peak memory 241340 kb
Host smart-20b467bd-825c-4785-9133-757419314f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176793556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.2176793556
Directory /workspace/23.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_req.2421610152
Short name T679
Test name
Test status
Simulation time 1129844397 ps
CPU time 16.35 seconds
Started Mar 21 03:28:04 PM PDT 24
Finished Mar 21 03:28:21 PM PDT 24
Peak memory 241132 kb
Host smart-40dd8c93-2c2c-435a-aede-9241547d01b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2421610152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.2421610152
Directory /workspace/23.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_regwen.979891363
Short name T694
Test name
Test status
Simulation time 446998589 ps
CPU time 4.63 seconds
Started Mar 21 03:27:56 PM PDT 24
Finished Mar 21 03:28:01 PM PDT 24
Peak memory 241184 kb
Host smart-cd7185a3-4083-4929-96de-896353eccd8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=979891363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.979891363
Directory /workspace/23.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/23.otp_ctrl_smoke.154461261
Short name T642
Test name
Test status
Simulation time 820697977 ps
CPU time 11.53 seconds
Started Mar 21 03:27:59 PM PDT 24
Finished Mar 21 03:28:11 PM PDT 24
Peak memory 241552 kb
Host smart-4f86f8e6-e966-45e1-a18f-14ccfd100442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154461261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.154461261
Directory /workspace/23.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all_with_rand_reset.734653686
Short name T346
Test name
Test status
Simulation time 404472844125 ps
CPU time 1064.31 seconds
Started Mar 21 03:27:57 PM PDT 24
Finished Mar 21 03:45:42 PM PDT 24
Peak memory 350252 kb
Host smart-e1bc16c5-b14a-4e18-8e30-d4a98f133c31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734653686 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all_with_rand_reset.734653686
Directory /workspace/23.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.otp_ctrl_test_access.4017850285
Short name T224
Test name
Test status
Simulation time 2361198596 ps
CPU time 28.17 seconds
Started Mar 21 03:27:57 PM PDT 24
Finished Mar 21 03:28:26 PM PDT 24
Peak memory 241828 kb
Host smart-3e5a42e6-fd39-4dd6-89ee-87ae65dc21d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017850285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_test_access.4017850285
Directory /workspace/23.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/230.otp_ctrl_init_fail.2584548747
Short name T473
Test name
Test status
Simulation time 1570008119 ps
CPU time 3.54 seconds
Started Mar 21 03:31:08 PM PDT 24
Finished Mar 21 03:31:11 PM PDT 24
Peak memory 241432 kb
Host smart-660f05f2-6eca-48da-b527-8e400cdb40d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584548747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.2584548747
Directory /workspace/230.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/231.otp_ctrl_init_fail.916620593
Short name T69
Test name
Test status
Simulation time 161967757 ps
CPU time 5.24 seconds
Started Mar 21 03:31:08 PM PDT 24
Finished Mar 21 03:31:13 PM PDT 24
Peak memory 241388 kb
Host smart-8179beb7-5359-40dd-88c0-eab8e2984e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916620593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.916620593
Directory /workspace/231.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/232.otp_ctrl_init_fail.1295299092
Short name T11
Test name
Test status
Simulation time 257473333 ps
CPU time 3.77 seconds
Started Mar 21 03:31:08 PM PDT 24
Finished Mar 21 03:31:12 PM PDT 24
Peak memory 241664 kb
Host smart-317e71e5-71b4-4026-b015-ab924166a77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295299092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.1295299092
Directory /workspace/232.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/233.otp_ctrl_init_fail.2503440490
Short name T623
Test name
Test status
Simulation time 148308943 ps
CPU time 3.26 seconds
Started Mar 21 03:31:08 PM PDT 24
Finished Mar 21 03:31:12 PM PDT 24
Peak memory 241360 kb
Host smart-b72852f3-a06e-4fc0-b247-f95b8004cde3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503440490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.2503440490
Directory /workspace/233.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/235.otp_ctrl_init_fail.56603209
Short name T996
Test name
Test status
Simulation time 145272374 ps
CPU time 3.87 seconds
Started Mar 21 03:31:07 PM PDT 24
Finished Mar 21 03:31:11 PM PDT 24
Peak memory 241772 kb
Host smart-737ce77b-8375-477c-9b3c-e8916bf279ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56603209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.56603209
Directory /workspace/235.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/236.otp_ctrl_init_fail.2707727105
Short name T939
Test name
Test status
Simulation time 205143012 ps
CPU time 4.4 seconds
Started Mar 21 03:31:08 PM PDT 24
Finished Mar 21 03:31:13 PM PDT 24
Peak memory 241484 kb
Host smart-26c8f4dd-f62a-4274-a610-74fb68e73b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707727105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.2707727105
Directory /workspace/236.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/237.otp_ctrl_init_fail.1372014414
Short name T765
Test name
Test status
Simulation time 149310716 ps
CPU time 4.78 seconds
Started Mar 21 03:31:08 PM PDT 24
Finished Mar 21 03:31:13 PM PDT 24
Peak memory 241308 kb
Host smart-603feadd-ca9b-47bc-8331-b562e8d3de64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372014414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.1372014414
Directory /workspace/237.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/238.otp_ctrl_init_fail.4221964168
Short name T643
Test name
Test status
Simulation time 306279514 ps
CPU time 3.87 seconds
Started Mar 21 03:31:08 PM PDT 24
Finished Mar 21 03:31:12 PM PDT 24
Peak memory 241716 kb
Host smart-20111d52-8eb8-4714-9ec9-86996af7973a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221964168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.4221964168
Directory /workspace/238.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/239.otp_ctrl_init_fail.810807624
Short name T856
Test name
Test status
Simulation time 191441860 ps
CPU time 4.17 seconds
Started Mar 21 03:31:08 PM PDT 24
Finished Mar 21 03:31:13 PM PDT 24
Peak memory 241560 kb
Host smart-76d53ef2-83ab-4b72-bf4d-d57945c17959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810807624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.810807624
Directory /workspace/239.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_alert_test.3538911320
Short name T904
Test name
Test status
Simulation time 267991597 ps
CPU time 1.98 seconds
Started Mar 21 03:28:08 PM PDT 24
Finished Mar 21 03:28:10 PM PDT 24
Peak memory 240052 kb
Host smart-2fe9cdd5-1bd0-490f-af8d-10a1030cd692
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538911320 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.3538911320
Directory /workspace/24.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.otp_ctrl_check_fail.3043280238
Short name T446
Test name
Test status
Simulation time 2789658849 ps
CPU time 35.97 seconds
Started Mar 21 03:28:08 PM PDT 24
Finished Mar 21 03:28:45 PM PDT 24
Peak memory 241804 kb
Host smart-651ffff1-2d37-4ab0-81cc-af96e7f9dbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043280238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.3043280238
Directory /workspace/24.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_errs.1717196073
Short name T587
Test name
Test status
Simulation time 596614141 ps
CPU time 18.24 seconds
Started Mar 21 03:28:08 PM PDT 24
Finished Mar 21 03:28:27 PM PDT 24
Peak memory 241216 kb
Host smart-9c33e3a6-8b0f-44aa-a124-34f2f2189f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717196073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.1717196073
Directory /workspace/24.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_lock.2206840017
Short name T685
Test name
Test status
Simulation time 1076934290 ps
CPU time 22.33 seconds
Started Mar 21 03:28:08 PM PDT 24
Finished Mar 21 03:28:30 PM PDT 24
Peak memory 241432 kb
Host smart-9584ce46-1379-4a00-8c36-3d5bde90884f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206840017 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.2206840017
Directory /workspace/24.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/24.otp_ctrl_init_fail.2347082911
Short name T681
Test name
Test status
Simulation time 175757340 ps
CPU time 3.73 seconds
Started Mar 21 03:28:08 PM PDT 24
Finished Mar 21 03:28:12 PM PDT 24
Peak memory 241476 kb
Host smart-739ba268-aa4b-4148-b202-d6ccb832dcff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347082911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.2347082911
Directory /workspace/24.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_macro_errs.115653438
Short name T1124
Test name
Test status
Simulation time 2285274473 ps
CPU time 25.28 seconds
Started Mar 21 03:28:15 PM PDT 24
Finished Mar 21 03:28:41 PM PDT 24
Peak memory 242232 kb
Host smart-5dc4b92c-97fc-4864-acf4-4c2e93ad4901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115653438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.115653438
Directory /workspace/24.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_key_req.1249684625
Short name T747
Test name
Test status
Simulation time 4331851274 ps
CPU time 12.65 seconds
Started Mar 21 03:28:10 PM PDT 24
Finished Mar 21 03:28:23 PM PDT 24
Peak memory 241452 kb
Host smart-b18d832e-f227-47d2-848f-4ca33450b468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249684625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.1249684625
Directory /workspace/24.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_esc.915541183
Short name T604
Test name
Test status
Simulation time 233305717 ps
CPU time 5.27 seconds
Started Mar 21 03:28:15 PM PDT 24
Finished Mar 21 03:28:21 PM PDT 24
Peak memory 241300 kb
Host smart-4d98e65b-17f0-472d-a442-9bc243d9e1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915541183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.915541183
Directory /workspace/24.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_req.2456911089
Short name T968
Test name
Test status
Simulation time 759965041 ps
CPU time 11.62 seconds
Started Mar 21 03:28:10 PM PDT 24
Finished Mar 21 03:28:22 PM PDT 24
Peak memory 241228 kb
Host smart-b645414f-b30a-4f3e-a161-4c362ffa28b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2456911089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.2456911089
Directory /workspace/24.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_regwen.2295785220
Short name T512
Test name
Test status
Simulation time 732108527 ps
CPU time 5.69 seconds
Started Mar 21 03:28:12 PM PDT 24
Finished Mar 21 03:28:17 PM PDT 24
Peak memory 241428 kb
Host smart-e23f5255-ca4d-43db-89b7-49e5abcf5da1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2295785220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.2295785220
Directory /workspace/24.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/24.otp_ctrl_smoke.708048359
Short name T581
Test name
Test status
Simulation time 1616054078 ps
CPU time 5.52 seconds
Started Mar 21 03:28:08 PM PDT 24
Finished Mar 21 03:28:13 PM PDT 24
Peak memory 241628 kb
Host smart-258c9215-1316-475d-9b19-0c0afa6dca9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708048359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.708048359
Directory /workspace/24.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all_with_rand_reset.4171344268
Short name T608
Test name
Test status
Simulation time 95764078137 ps
CPU time 552.03 seconds
Started Mar 21 03:28:10 PM PDT 24
Finished Mar 21 03:37:23 PM PDT 24
Peak memory 306932 kb
Host smart-ae6abcd3-aec5-441b-8f14-84dfe5e5c4d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171344268 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all_with_rand_reset.4171344268
Directory /workspace/24.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.otp_ctrl_test_access.1557287172
Short name T823
Test name
Test status
Simulation time 12436914264 ps
CPU time 35.88 seconds
Started Mar 21 03:28:15 PM PDT 24
Finished Mar 21 03:28:52 PM PDT 24
Peak memory 242924 kb
Host smart-c2af3229-173d-4fd4-b0eb-eeac442ad8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557287172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_test_access.1557287172
Directory /workspace/24.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/240.otp_ctrl_init_fail.189507852
Short name T647
Test name
Test status
Simulation time 631540598 ps
CPU time 4.17 seconds
Started Mar 21 03:31:08 PM PDT 24
Finished Mar 21 03:31:12 PM PDT 24
Peak memory 241720 kb
Host smart-e95a7856-f1f9-4f0b-9ad8-9a6aef4fe64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189507852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.189507852
Directory /workspace/240.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/241.otp_ctrl_init_fail.1921139027
Short name T605
Test name
Test status
Simulation time 315493562 ps
CPU time 4.45 seconds
Started Mar 21 03:31:09 PM PDT 24
Finished Mar 21 03:31:13 PM PDT 24
Peak memory 241368 kb
Host smart-d5a9599a-22d8-4851-9243-4c57d9dda633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921139027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.1921139027
Directory /workspace/241.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/242.otp_ctrl_init_fail.3282157137
Short name T657
Test name
Test status
Simulation time 165114491 ps
CPU time 4.22 seconds
Started Mar 21 03:31:04 PM PDT 24
Finished Mar 21 03:31:08 PM PDT 24
Peak memory 241428 kb
Host smart-db043b0e-f27c-475b-8c21-7a8651b70def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282157137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.3282157137
Directory /workspace/242.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/243.otp_ctrl_init_fail.3925629281
Short name T761
Test name
Test status
Simulation time 636661695 ps
CPU time 4.81 seconds
Started Mar 21 03:31:08 PM PDT 24
Finished Mar 21 03:31:14 PM PDT 24
Peak memory 241648 kb
Host smart-63be5ca9-e8fd-4547-8701-880e6abad336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925629281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.3925629281
Directory /workspace/243.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/244.otp_ctrl_init_fail.1083377762
Short name T447
Test name
Test status
Simulation time 95873199 ps
CPU time 3.66 seconds
Started Mar 21 03:31:09 PM PDT 24
Finished Mar 21 03:31:13 PM PDT 24
Peak memory 241252 kb
Host smart-fb6dad13-f0c6-4994-adc3-8a649cfcb7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083377762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.1083377762
Directory /workspace/244.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/245.otp_ctrl_init_fail.3709543398
Short name T232
Test name
Test status
Simulation time 442916209 ps
CPU time 4.07 seconds
Started Mar 21 03:31:06 PM PDT 24
Finished Mar 21 03:31:10 PM PDT 24
Peak memory 241536 kb
Host smart-f1546e58-6049-4602-b945-6d5abb4ce084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709543398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.3709543398
Directory /workspace/245.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/246.otp_ctrl_init_fail.1988336091
Short name T726
Test name
Test status
Simulation time 129929346 ps
CPU time 3.65 seconds
Started Mar 21 03:31:02 PM PDT 24
Finished Mar 21 03:31:06 PM PDT 24
Peak memory 241424 kb
Host smart-cc1cb5b1-7c04-4498-8278-7fe2146fab0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988336091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.1988336091
Directory /workspace/246.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/247.otp_ctrl_init_fail.4247215507
Short name T595
Test name
Test status
Simulation time 235036020 ps
CPU time 4.84 seconds
Started Mar 21 03:31:05 PM PDT 24
Finished Mar 21 03:31:10 PM PDT 24
Peak memory 241336 kb
Host smart-b42be4a1-d2cb-4b6f-ac4c-fd9e0d26faa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247215507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.4247215507
Directory /workspace/247.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/248.otp_ctrl_init_fail.338797227
Short name T193
Test name
Test status
Simulation time 278240300 ps
CPU time 4.49 seconds
Started Mar 21 03:31:13 PM PDT 24
Finished Mar 21 03:31:18 PM PDT 24
Peak memory 241620 kb
Host smart-9640c5c6-1dbc-4e79-afa9-e4a59e9743b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338797227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.338797227
Directory /workspace/248.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/249.otp_ctrl_init_fail.3988758055
Short name T893
Test name
Test status
Simulation time 399870985 ps
CPU time 4.46 seconds
Started Mar 21 03:31:05 PM PDT 24
Finished Mar 21 03:31:10 PM PDT 24
Peak memory 241388 kb
Host smart-1c1c5928-3022-4148-93b6-4dc6b7dc47df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988758055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.3988758055
Directory /workspace/249.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_alert_test.3040730180
Short name T1105
Test name
Test status
Simulation time 106463373 ps
CPU time 2.23 seconds
Started Mar 21 03:28:10 PM PDT 24
Finished Mar 21 03:28:12 PM PDT 24
Peak memory 239936 kb
Host smart-ca2aa6a5-3923-4710-8032-674c161fe11f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040730180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.3040730180
Directory /workspace/25.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.otp_ctrl_check_fail.2540598952
Short name T73
Test name
Test status
Simulation time 11197810948 ps
CPU time 35.43 seconds
Started Mar 21 03:28:11 PM PDT 24
Finished Mar 21 03:28:46 PM PDT 24
Peak memory 243620 kb
Host smart-e463c04a-6f9b-4f39-814e-bb2f611a8765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540598952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.2540598952
Directory /workspace/25.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_errs.2661723515
Short name T797
Test name
Test status
Simulation time 268584627 ps
CPU time 12.8 seconds
Started Mar 21 03:28:10 PM PDT 24
Finished Mar 21 03:28:23 PM PDT 24
Peak memory 241208 kb
Host smart-49fc4fc8-49a8-41e3-b462-abc53ff827b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661723515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_errs.2661723515
Directory /workspace/25.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_lock.131070299
Short name T631
Test name
Test status
Simulation time 949335861 ps
CPU time 10.35 seconds
Started Mar 21 03:28:09 PM PDT 24
Finished Mar 21 03:28:20 PM PDT 24
Peak memory 241696 kb
Host smart-f58a2a77-cf36-4617-955d-fa949ba4c5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131070299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.131070299
Directory /workspace/25.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/25.otp_ctrl_init_fail.1042630728
Short name T173
Test name
Test status
Simulation time 2157111757 ps
CPU time 7.11 seconds
Started Mar 21 03:28:10 PM PDT 24
Finished Mar 21 03:28:18 PM PDT 24
Peak memory 241496 kb
Host smart-f905274b-7945-4978-b3a5-9a5800c470da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042630728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.1042630728
Directory /workspace/25.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_macro_errs.4055059587
Short name T592
Test name
Test status
Simulation time 539003072 ps
CPU time 9.03 seconds
Started Mar 21 03:28:09 PM PDT 24
Finished Mar 21 03:28:19 PM PDT 24
Peak memory 241652 kb
Host smart-a6b3e014-25e6-4bcf-a8d9-af541f3d6afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055059587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.4055059587
Directory /workspace/25.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_key_req.1855080532
Short name T328
Test name
Test status
Simulation time 1976823461 ps
CPU time 15.91 seconds
Started Mar 21 03:28:10 PM PDT 24
Finished Mar 21 03:28:26 PM PDT 24
Peak memory 241852 kb
Host smart-5f8d98af-9e07-49b0-91ef-ef3d25012ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855080532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_key_req.1855080532
Directory /workspace/25.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_esc.2432327480
Short name T713
Test name
Test status
Simulation time 1142970381 ps
CPU time 15.79 seconds
Started Mar 21 03:28:09 PM PDT 24
Finished Mar 21 03:28:25 PM PDT 24
Peak memory 241340 kb
Host smart-1b156487-13ce-42a2-b628-20ed5300b081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432327480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.2432327480
Directory /workspace/25.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_req.3851210141
Short name T31
Test name
Test status
Simulation time 301049680 ps
CPU time 11.27 seconds
Started Mar 21 03:28:09 PM PDT 24
Finished Mar 21 03:28:21 PM PDT 24
Peak memory 248108 kb
Host smart-31204bc8-7de6-4310-a8db-732ecf45a261
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3851210141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_req.3851210141
Directory /workspace/25.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_smoke.4229794776
Short name T1159
Test name
Test status
Simulation time 2035994921 ps
CPU time 5.83 seconds
Started Mar 21 03:28:13 PM PDT 24
Finished Mar 21 03:28:19 PM PDT 24
Peak memory 241684 kb
Host smart-8da80d1b-9ca2-4d05-bda4-b8f7a92f136c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229794776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.4229794776
Directory /workspace/25.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all.2776918920
Short name T895
Test name
Test status
Simulation time 5864649878 ps
CPU time 105.93 seconds
Started Mar 21 03:28:09 PM PDT 24
Finished Mar 21 03:29:55 PM PDT 24
Peak memory 248344 kb
Host smart-3ade4a88-2c37-4619-8e38-5cfd1cfcaf13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776918920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all
.2776918920
Directory /workspace/25.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.otp_ctrl_test_access.2168067156
Short name T662
Test name
Test status
Simulation time 5673183613 ps
CPU time 32.87 seconds
Started Mar 21 03:28:12 PM PDT 24
Finished Mar 21 03:28:46 PM PDT 24
Peak memory 243272 kb
Host smart-774c20e0-53d3-4e71-a0f7-1acbc4027fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168067156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.2168067156
Directory /workspace/25.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/250.otp_ctrl_init_fail.761278718
Short name T708
Test name
Test status
Simulation time 144083824 ps
CPU time 3.99 seconds
Started Mar 21 03:31:06 PM PDT 24
Finished Mar 21 03:31:10 PM PDT 24
Peak memory 241612 kb
Host smart-0486e4d9-c864-4312-bdd1-39ed78df9e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761278718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.761278718
Directory /workspace/250.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/251.otp_ctrl_init_fail.3717977075
Short name T1013
Test name
Test status
Simulation time 141990625 ps
CPU time 4.07 seconds
Started Mar 21 03:31:04 PM PDT 24
Finished Mar 21 03:31:08 PM PDT 24
Peak memory 241428 kb
Host smart-2b0587f9-e0c5-49af-94a9-55074f245108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717977075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.3717977075
Directory /workspace/251.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/252.otp_ctrl_init_fail.3827535738
Short name T695
Test name
Test status
Simulation time 161706563 ps
CPU time 4.18 seconds
Started Mar 21 03:31:08 PM PDT 24
Finished Mar 21 03:31:12 PM PDT 24
Peak memory 241712 kb
Host smart-99847179-74d6-4f61-a05f-7c09d5bf344c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827535738 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.3827535738
Directory /workspace/252.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/253.otp_ctrl_init_fail.2785197924
Short name T785
Test name
Test status
Simulation time 1754556252 ps
CPU time 5.47 seconds
Started Mar 21 03:31:04 PM PDT 24
Finished Mar 21 03:31:10 PM PDT 24
Peak memory 241452 kb
Host smart-ab898725-b7cc-4c16-bf35-b376df181cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785197924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.2785197924
Directory /workspace/253.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/254.otp_ctrl_init_fail.3281759032
Short name T1184
Test name
Test status
Simulation time 217123473 ps
CPU time 5.11 seconds
Started Mar 21 03:31:07 PM PDT 24
Finished Mar 21 03:31:13 PM PDT 24
Peak memory 241436 kb
Host smart-8ac61bf9-d1bd-4949-922c-ddc2da7d2269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281759032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.3281759032
Directory /workspace/254.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/257.otp_ctrl_init_fail.2491326227
Short name T728
Test name
Test status
Simulation time 243526794 ps
CPU time 4.28 seconds
Started Mar 21 03:31:04 PM PDT 24
Finished Mar 21 03:31:08 PM PDT 24
Peak memory 241332 kb
Host smart-ae159551-de82-4e27-86c8-a2f76910aa49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491326227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.2491326227
Directory /workspace/257.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/258.otp_ctrl_init_fail.3520765299
Short name T1091
Test name
Test status
Simulation time 2214656248 ps
CPU time 4.88 seconds
Started Mar 21 03:31:06 PM PDT 24
Finished Mar 21 03:31:12 PM PDT 24
Peak memory 241856 kb
Host smart-3a48ca04-514f-484f-80e9-b2107f4a4a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520765299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.3520765299
Directory /workspace/258.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/259.otp_ctrl_init_fail.850670024
Short name T425
Test name
Test status
Simulation time 633686983 ps
CPU time 4.39 seconds
Started Mar 21 03:31:07 PM PDT 24
Finished Mar 21 03:31:12 PM PDT 24
Peak memory 241408 kb
Host smart-1256bae6-2890-4819-bfbb-52d655d3afc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850670024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.850670024
Directory /workspace/259.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_alert_test.4110607390
Short name T190
Test name
Test status
Simulation time 186336224 ps
CPU time 2.77 seconds
Started Mar 21 03:28:09 PM PDT 24
Finished Mar 21 03:28:13 PM PDT 24
Peak memory 239920 kb
Host smart-c177b353-7060-4300-a26d-9de10abcd317
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110607390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.4110607390
Directory /workspace/26.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.otp_ctrl_check_fail.1764874183
Short name T665
Test name
Test status
Simulation time 2678782845 ps
CPU time 17.21 seconds
Started Mar 21 03:28:14 PM PDT 24
Finished Mar 21 03:28:31 PM PDT 24
Peak memory 248244 kb
Host smart-8a1150f4-ea09-435e-a37b-786ba3512c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764874183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.1764874183
Directory /workspace/26.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_errs.3245733058
Short name T445
Test name
Test status
Simulation time 673497246 ps
CPU time 21.91 seconds
Started Mar 21 03:28:17 PM PDT 24
Finished Mar 21 03:28:39 PM PDT 24
Peak memory 241472 kb
Host smart-107a239c-3063-4c47-8912-57a3cd53d576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245733058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.3245733058
Directory /workspace/26.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_lock.3969399707
Short name T1072
Test name
Test status
Simulation time 1120243007 ps
CPU time 14.5 seconds
Started Mar 21 03:28:13 PM PDT 24
Finished Mar 21 03:28:27 PM PDT 24
Peak memory 241760 kb
Host smart-18e39a34-3224-46dc-8b2d-97e02c829ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969399707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.3969399707
Directory /workspace/26.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/26.otp_ctrl_init_fail.1176482694
Short name T536
Test name
Test status
Simulation time 1628319281 ps
CPU time 5.58 seconds
Started Mar 21 03:28:17 PM PDT 24
Finished Mar 21 03:28:23 PM PDT 24
Peak memory 241380 kb
Host smart-8f622c9c-c480-4d61-8cbf-a77bdbc036cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176482694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.1176482694
Directory /workspace/26.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_key_req.2388301382
Short name T103
Test name
Test status
Simulation time 798553983 ps
CPU time 31.4 seconds
Started Mar 21 03:28:14 PM PDT 24
Finished Mar 21 03:28:45 PM PDT 24
Peak memory 248140 kb
Host smart-22813c16-cffc-41fd-9094-4ef52cd641b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388301382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.2388301382
Directory /workspace/26.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_esc.3316208937
Short name T288
Test name
Test status
Simulation time 319238407 ps
CPU time 6.17 seconds
Started Mar 21 03:28:15 PM PDT 24
Finished Mar 21 03:28:22 PM PDT 24
Peak memory 241220 kb
Host smart-5043bce7-02d5-4d07-a758-d89233bfcc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316208937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.3316208937
Directory /workspace/26.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_req.3462888907
Short name T32
Test name
Test status
Simulation time 2356588903 ps
CPU time 15.9 seconds
Started Mar 21 03:28:18 PM PDT 24
Finished Mar 21 03:28:34 PM PDT 24
Peak memory 241252 kb
Host smart-beddf42f-b214-479b-8838-8de9f54a104a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3462888907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.3462888907
Directory /workspace/26.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_regwen.1311695975
Short name T1016
Test name
Test status
Simulation time 497296585 ps
CPU time 7.19 seconds
Started Mar 21 03:28:18 PM PDT 24
Finished Mar 21 03:28:25 PM PDT 24
Peak memory 241420 kb
Host smart-045108ad-53d5-4b79-bbdf-5d29c66a40e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1311695975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.1311695975
Directory /workspace/26.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/26.otp_ctrl_smoke.1009298157
Short name T701
Test name
Test status
Simulation time 11273579695 ps
CPU time 10.97 seconds
Started Mar 21 03:28:13 PM PDT 24
Finished Mar 21 03:28:24 PM PDT 24
Peak memory 241420 kb
Host smart-9cf64943-0d05-4f46-b578-b98d05dcd808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009298157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.1009298157
Directory /workspace/26.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all.3947837314
Short name T780
Test name
Test status
Simulation time 315816521 ps
CPU time 9.63 seconds
Started Mar 21 03:28:18 PM PDT 24
Finished Mar 21 03:28:28 PM PDT 24
Peak memory 241348 kb
Host smart-62c83aab-03a7-4416-a212-70b8f00ab941
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947837314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all
.3947837314
Directory /workspace/26.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all_with_rand_reset.2202399338
Short name T923
Test name
Test status
Simulation time 731464490655 ps
CPU time 1501.5 seconds
Started Mar 21 03:28:10 PM PDT 24
Finished Mar 21 03:53:12 PM PDT 24
Peak memory 428132 kb
Host smart-a17eef40-d9f2-4422-9f6b-cc8b42a31905
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202399338 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all_with_rand_reset.2202399338
Directory /workspace/26.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.otp_ctrl_test_access.3743011018
Short name T964
Test name
Test status
Simulation time 976185670 ps
CPU time 11.51 seconds
Started Mar 21 03:28:18 PM PDT 24
Finished Mar 21 03:28:29 PM PDT 24
Peak memory 241608 kb
Host smart-c178233b-538b-4bf4-ab9e-ee80cfc154db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743011018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.3743011018
Directory /workspace/26.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/260.otp_ctrl_init_fail.2649973751
Short name T197
Test name
Test status
Simulation time 111948051 ps
CPU time 4.1 seconds
Started Mar 21 03:31:11 PM PDT 24
Finished Mar 21 03:31:15 PM PDT 24
Peak memory 241268 kb
Host smart-b292090e-70f1-40f8-b02b-fcd7f1e34f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649973751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.2649973751
Directory /workspace/260.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/261.otp_ctrl_init_fail.1324821633
Short name T882
Test name
Test status
Simulation time 163525489 ps
CPU time 3.62 seconds
Started Mar 21 03:31:09 PM PDT 24
Finished Mar 21 03:31:13 PM PDT 24
Peak memory 241432 kb
Host smart-a8d8ace8-53f3-4813-8cea-b44be3f5b773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324821633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.1324821633
Directory /workspace/261.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/262.otp_ctrl_init_fail.570483537
Short name T464
Test name
Test status
Simulation time 2406920857 ps
CPU time 4.41 seconds
Started Mar 21 03:31:06 PM PDT 24
Finished Mar 21 03:31:10 PM PDT 24
Peak memory 241792 kb
Host smart-c8c29547-8936-48af-9f5d-c6cfee344229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570483537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.570483537
Directory /workspace/262.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/263.otp_ctrl_init_fail.3324942925
Short name T1194
Test name
Test status
Simulation time 1717823803 ps
CPU time 4.84 seconds
Started Mar 21 03:31:05 PM PDT 24
Finished Mar 21 03:31:11 PM PDT 24
Peak memory 241392 kb
Host smart-8e006031-5a74-483f-8e49-c9b5a7f1edf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324942925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.3324942925
Directory /workspace/263.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/264.otp_ctrl_init_fail.114423497
Short name T933
Test name
Test status
Simulation time 141758838 ps
CPU time 3.12 seconds
Started Mar 21 03:31:15 PM PDT 24
Finished Mar 21 03:31:18 PM PDT 24
Peak memory 241268 kb
Host smart-b199f3e8-d1e9-46e3-b827-4c6d37af55d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114423497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.114423497
Directory /workspace/264.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/265.otp_ctrl_init_fail.1889278921
Short name T976
Test name
Test status
Simulation time 412658455 ps
CPU time 4.33 seconds
Started Mar 21 03:31:08 PM PDT 24
Finished Mar 21 03:31:12 PM PDT 24
Peak memory 241352 kb
Host smart-e1937d89-5b27-4ff6-813d-133322d9b5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889278921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.1889278921
Directory /workspace/265.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/266.otp_ctrl_init_fail.1277453939
Short name T691
Test name
Test status
Simulation time 460858942 ps
CPU time 4.43 seconds
Started Mar 21 03:31:07 PM PDT 24
Finished Mar 21 03:31:12 PM PDT 24
Peak memory 241424 kb
Host smart-86905f79-0c73-471f-be8e-18a00cd560be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277453939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.1277453939
Directory /workspace/266.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/267.otp_ctrl_init_fail.1365723446
Short name T243
Test name
Test status
Simulation time 375582334 ps
CPU time 3.71 seconds
Started Mar 21 03:31:06 PM PDT 24
Finished Mar 21 03:31:10 PM PDT 24
Peak memory 241668 kb
Host smart-828590bd-b3d6-4399-a995-7fe9a2c5efca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365723446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.1365723446
Directory /workspace/267.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/268.otp_ctrl_init_fail.2352412386
Short name T753
Test name
Test status
Simulation time 235314604 ps
CPU time 4.27 seconds
Started Mar 21 03:31:08 PM PDT 24
Finished Mar 21 03:31:13 PM PDT 24
Peak memory 241420 kb
Host smart-104e7820-dae3-41f9-b0c1-f941d383ab4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352412386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.2352412386
Directory /workspace/268.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/269.otp_ctrl_init_fail.1545567969
Short name T1050
Test name
Test status
Simulation time 2151419200 ps
CPU time 5.64 seconds
Started Mar 21 03:31:09 PM PDT 24
Finished Mar 21 03:31:14 PM PDT 24
Peak memory 241424 kb
Host smart-9e4b4c16-e440-421b-8de1-ec4c5ec633dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545567969 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.1545567969
Directory /workspace/269.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_alert_test.1963624285
Short name T1118
Test name
Test status
Simulation time 76018939 ps
CPU time 1.9 seconds
Started Mar 21 03:28:11 PM PDT 24
Finished Mar 21 03:28:13 PM PDT 24
Peak memory 240096 kb
Host smart-ddc994f7-7f55-4737-88cf-c598ace955a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963624285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.1963624285
Directory /workspace/27.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.otp_ctrl_check_fail.1782585009
Short name T35
Test name
Test status
Simulation time 5981718854 ps
CPU time 47.44 seconds
Started Mar 21 03:28:11 PM PDT 24
Finished Mar 21 03:28:59 PM PDT 24
Peak memory 245928 kb
Host smart-d2fc2225-e789-4b95-9a15-6601b003bc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782585009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.1782585009
Directory /workspace/27.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_errs.2708426721
Short name T363
Test name
Test status
Simulation time 526889959 ps
CPU time 14.24 seconds
Started Mar 21 03:28:09 PM PDT 24
Finished Mar 21 03:28:23 PM PDT 24
Peak memory 241532 kb
Host smart-54ad4d60-7951-4762-86ff-f8b0ee393624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708426721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_errs.2708426721
Directory /workspace/27.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_lock.3667041358
Short name T985
Test name
Test status
Simulation time 2738193172 ps
CPU time 9.17 seconds
Started Mar 21 03:28:10 PM PDT 24
Finished Mar 21 03:28:19 PM PDT 24
Peak memory 241728 kb
Host smart-b771c569-d733-4888-8845-7d9865d5a50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667041358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.3667041358
Directory /workspace/27.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/27.otp_ctrl_init_fail.597344657
Short name T644
Test name
Test status
Simulation time 137344320 ps
CPU time 4.07 seconds
Started Mar 21 03:28:08 PM PDT 24
Finished Mar 21 03:28:12 PM PDT 24
Peak memory 241716 kb
Host smart-6876d1dc-453d-48c4-a0ee-7bb303544031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597344657 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.597344657
Directory /workspace/27.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_key_req.1346580705
Short name T867
Test name
Test status
Simulation time 8517019647 ps
CPU time 34.02 seconds
Started Mar 21 03:28:10 PM PDT 24
Finished Mar 21 03:28:44 PM PDT 24
Peak memory 242892 kb
Host smart-28f5304b-7b5a-4ace-bc70-1f5e1043a737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346580705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.1346580705
Directory /workspace/27.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_esc.3821084914
Short name T941
Test name
Test status
Simulation time 282613215 ps
CPU time 12.93 seconds
Started Mar 21 03:28:10 PM PDT 24
Finished Mar 21 03:28:23 PM PDT 24
Peak memory 241268 kb
Host smart-c1ecc28f-e9dc-4473-a8b0-76f60820a100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821084914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.3821084914
Directory /workspace/27.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_req.542196036
Short name T744
Test name
Test status
Simulation time 1150159040 ps
CPU time 9.51 seconds
Started Mar 21 03:28:12 PM PDT 24
Finished Mar 21 03:28:22 PM PDT 24
Peak memory 241132 kb
Host smart-ce82cc14-d97b-47d2-8e57-19ef4d94b10b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=542196036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.542196036
Directory /workspace/27.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_smoke.1159407453
Short name T995
Test name
Test status
Simulation time 2248454773 ps
CPU time 7.77 seconds
Started Mar 21 03:28:07 PM PDT 24
Finished Mar 21 03:28:16 PM PDT 24
Peak memory 241740 kb
Host smart-733ffb13-90a4-41d2-ba02-ef7c80b44567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159407453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_smoke.1159407453
Directory /workspace/27.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all.3416505413
Short name T1028
Test name
Test status
Simulation time 36905646182 ps
CPU time 144.93 seconds
Started Mar 21 03:28:10 PM PDT 24
Finished Mar 21 03:30:35 PM PDT 24
Peak memory 256624 kb
Host smart-92e2647f-0313-4869-9af3-e640cfc43d74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416505413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all
.3416505413
Directory /workspace/27.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all_with_rand_reset.884312003
Short name T813
Test name
Test status
Simulation time 724799123790 ps
CPU time 2004.98 seconds
Started Mar 21 03:28:09 PM PDT 24
Finished Mar 21 04:01:35 PM PDT 24
Peak memory 418660 kb
Host smart-20f5aa2c-bd98-45ec-895f-5bebcf61073b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884312003 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all_with_rand_reset.884312003
Directory /workspace/27.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.otp_ctrl_test_access.562222913
Short name T270
Test name
Test status
Simulation time 303849144 ps
CPU time 12.97 seconds
Started Mar 21 03:28:13 PM PDT 24
Finished Mar 21 03:28:26 PM PDT 24
Peak memory 241212 kb
Host smart-22c6587a-a8e9-4ae4-82d3-fde86bee3199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562222913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_test_access.562222913
Directory /workspace/27.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/270.otp_ctrl_init_fail.1639616504
Short name T444
Test name
Test status
Simulation time 157734866 ps
CPU time 3.98 seconds
Started Mar 21 03:31:04 PM PDT 24
Finished Mar 21 03:31:08 PM PDT 24
Peak memory 241376 kb
Host smart-cb7bfb07-3225-4f35-827e-6431dc661fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639616504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.1639616504
Directory /workspace/270.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/272.otp_ctrl_init_fail.292529409
Short name T46
Test name
Test status
Simulation time 2708849104 ps
CPU time 6.73 seconds
Started Mar 21 03:31:03 PM PDT 24
Finished Mar 21 03:31:10 PM PDT 24
Peak memory 241548 kb
Host smart-fa65249c-41f5-4184-8ef8-e461f7c9f5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292529409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.292529409
Directory /workspace/272.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/273.otp_ctrl_init_fail.634418908
Short name T675
Test name
Test status
Simulation time 323158815 ps
CPU time 4.64 seconds
Started Mar 21 03:31:02 PM PDT 24
Finished Mar 21 03:31:07 PM PDT 24
Peak memory 241412 kb
Host smart-e53ad5c3-bc89-4f00-be50-4b6bd882a4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634418908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.634418908
Directory /workspace/273.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/274.otp_ctrl_init_fail.1664564361
Short name T436
Test name
Test status
Simulation time 151409432 ps
CPU time 4.64 seconds
Started Mar 21 03:31:03 PM PDT 24
Finished Mar 21 03:31:07 PM PDT 24
Peak memory 241400 kb
Host smart-08f40ff0-2f3b-46fc-9bc4-a51f3e188140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664564361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.1664564361
Directory /workspace/274.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/275.otp_ctrl_init_fail.4270160271
Short name T196
Test name
Test status
Simulation time 120044781 ps
CPU time 3.51 seconds
Started Mar 21 03:31:06 PM PDT 24
Finished Mar 21 03:31:10 PM PDT 24
Peak memory 241392 kb
Host smart-6ecaa438-a8c8-46db-b74d-71661a69e53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270160271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.4270160271
Directory /workspace/275.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/276.otp_ctrl_init_fail.917265147
Short name T795
Test name
Test status
Simulation time 248606101 ps
CPU time 4.51 seconds
Started Mar 21 03:31:03 PM PDT 24
Finished Mar 21 03:31:08 PM PDT 24
Peak memory 241228 kb
Host smart-cbcd0713-fc5b-40fd-aaa4-e385c6ab93b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917265147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.917265147
Directory /workspace/276.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/277.otp_ctrl_init_fail.3079423292
Short name T614
Test name
Test status
Simulation time 87066167 ps
CPU time 3.17 seconds
Started Mar 21 03:31:06 PM PDT 24
Finished Mar 21 03:31:10 PM PDT 24
Peak memory 241596 kb
Host smart-4073029c-61ca-4e25-89c1-1c9ce40ad92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079423292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.3079423292
Directory /workspace/277.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/279.otp_ctrl_init_fail.224665929
Short name T873
Test name
Test status
Simulation time 252987066 ps
CPU time 5.11 seconds
Started Mar 21 03:31:06 PM PDT 24
Finished Mar 21 03:31:11 PM PDT 24
Peak memory 241540 kb
Host smart-d492bc24-737a-4ff2-8dab-e1e3c0ac9cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224665929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.224665929
Directory /workspace/279.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_alert_test.896451976
Short name T959
Test name
Test status
Simulation time 53621367 ps
CPU time 1.78 seconds
Started Mar 21 03:28:24 PM PDT 24
Finished Mar 21 03:28:26 PM PDT 24
Peak memory 239808 kb
Host smart-5d0cca96-5bac-4b01-8a11-859775760863
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896451976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.896451976
Directory /workspace/28.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_lock.2502210463
Short name T396
Test name
Test status
Simulation time 869792431 ps
CPU time 30.79 seconds
Started Mar 21 03:28:13 PM PDT 24
Finished Mar 21 03:28:44 PM PDT 24
Peak memory 242072 kb
Host smart-eb067182-1864-41c1-bee1-492e81279d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502210463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.2502210463
Directory /workspace/28.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/28.otp_ctrl_init_fail.3472691459
Short name T857
Test name
Test status
Simulation time 550658934 ps
CPU time 4.72 seconds
Started Mar 21 03:28:09 PM PDT 24
Finished Mar 21 03:28:14 PM PDT 24
Peak memory 241404 kb
Host smart-4d26a904-a277-43c0-a9f1-413244985457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472691459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.3472691459
Directory /workspace/28.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_macro_errs.631523436
Short name T1002
Test name
Test status
Simulation time 4286603183 ps
CPU time 9.91 seconds
Started Mar 21 03:28:10 PM PDT 24
Finished Mar 21 03:28:20 PM PDT 24
Peak memory 243956 kb
Host smart-ee91b50e-9a0c-4887-a190-0a521f9892f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631523436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.631523436
Directory /workspace/28.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_key_req.3511014545
Short name T402
Test name
Test status
Simulation time 4718064079 ps
CPU time 36.76 seconds
Started Mar 21 03:28:06 PM PDT 24
Finished Mar 21 03:28:44 PM PDT 24
Peak memory 241460 kb
Host smart-d3cccb18-8ad3-4be5-875a-330628a87d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511014545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.3511014545
Directory /workspace/28.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_esc.958480364
Short name T357
Test name
Test status
Simulation time 218103278 ps
CPU time 3.7 seconds
Started Mar 21 03:28:10 PM PDT 24
Finished Mar 21 03:28:14 PM PDT 24
Peak memory 241316 kb
Host smart-d82644d1-7da8-4773-8c34-adce9855a201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958480364 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.958480364
Directory /workspace/28.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_req.3282386701
Short name T900
Test name
Test status
Simulation time 784660283 ps
CPU time 7.24 seconds
Started Mar 21 03:28:08 PM PDT 24
Finished Mar 21 03:28:15 PM PDT 24
Peak memory 241172 kb
Host smart-15fcf4cb-c5d7-4f37-a7be-09b243dc719b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3282386701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.3282386701
Directory /workspace/28.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_regwen.2144702620
Short name T381
Test name
Test status
Simulation time 293917928 ps
CPU time 8.73 seconds
Started Mar 21 03:28:08 PM PDT 24
Finished Mar 21 03:28:18 PM PDT 24
Peak memory 241700 kb
Host smart-44cb6cb8-4873-429a-93d9-edc15a8a8b44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2144702620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.2144702620
Directory /workspace/28.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/28.otp_ctrl_smoke.1336798118
Short name T100
Test name
Test status
Simulation time 149316438 ps
CPU time 3.92 seconds
Started Mar 21 03:28:13 PM PDT 24
Finished Mar 21 03:28:17 PM PDT 24
Peak memory 241352 kb
Host smart-888b3f63-dcb2-456a-afaf-e5ffbe00cb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336798118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.1336798118
Directory /workspace/28.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all_with_rand_reset.2594628981
Short name T700
Test name
Test status
Simulation time 168903996923 ps
CPU time 1470.3 seconds
Started Mar 21 03:28:21 PM PDT 24
Finished Mar 21 03:52:52 PM PDT 24
Peak memory 350180 kb
Host smart-72b5988b-b16b-488d-8961-d9eb62ae7e60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594628981 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all_with_rand_reset.2594628981
Directory /workspace/28.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.otp_ctrl_test_access.1420517056
Short name T567
Test name
Test status
Simulation time 749989245 ps
CPU time 18.84 seconds
Started Mar 21 03:28:13 PM PDT 24
Finished Mar 21 03:28:32 PM PDT 24
Peak memory 241516 kb
Host smart-ccdb17cb-53ab-41b2-b11f-9f9efd97dcfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420517056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_test_access.1420517056
Directory /workspace/28.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/280.otp_ctrl_init_fail.482479239
Short name T717
Test name
Test status
Simulation time 181193182 ps
CPU time 4.44 seconds
Started Mar 21 03:31:04 PM PDT 24
Finished Mar 21 03:31:09 PM PDT 24
Peak memory 241260 kb
Host smart-dcebcdc5-6c35-4684-bb2f-fbd1656c661e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482479239 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.482479239
Directory /workspace/280.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/281.otp_ctrl_init_fail.988628547
Short name T240
Test name
Test status
Simulation time 424628321 ps
CPU time 4.85 seconds
Started Mar 21 03:31:04 PM PDT 24
Finished Mar 21 03:31:09 PM PDT 24
Peak memory 241428 kb
Host smart-f7d07b85-b0ed-4fab-b035-867f4be5b687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988628547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.988628547
Directory /workspace/281.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/282.otp_ctrl_init_fail.559330002
Short name T493
Test name
Test status
Simulation time 225827416 ps
CPU time 3.69 seconds
Started Mar 21 03:31:04 PM PDT 24
Finished Mar 21 03:31:07 PM PDT 24
Peak memory 241388 kb
Host smart-8957170d-e85d-475f-9b13-e0de70c78829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559330002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.559330002
Directory /workspace/282.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/283.otp_ctrl_init_fail.3906159878
Short name T684
Test name
Test status
Simulation time 430329006 ps
CPU time 3.8 seconds
Started Mar 21 03:31:04 PM PDT 24
Finished Mar 21 03:31:08 PM PDT 24
Peak memory 241320 kb
Host smart-1b4edca2-b8a6-4fa8-be0b-69ab345d2dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906159878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.3906159878
Directory /workspace/283.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/284.otp_ctrl_init_fail.257345870
Short name T763
Test name
Test status
Simulation time 196629419 ps
CPU time 3.75 seconds
Started Mar 21 03:31:06 PM PDT 24
Finished Mar 21 03:31:10 PM PDT 24
Peak memory 241420 kb
Host smart-37064746-4e61-4593-bafb-b6caff595ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257345870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.257345870
Directory /workspace/284.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/285.otp_ctrl_init_fail.2630560713
Short name T458
Test name
Test status
Simulation time 383930159 ps
CPU time 4.27 seconds
Started Mar 21 03:31:05 PM PDT 24
Finished Mar 21 03:31:09 PM PDT 24
Peak memory 241332 kb
Host smart-56989063-31b5-4394-a467-a3dd71be324e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630560713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.2630560713
Directory /workspace/285.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/286.otp_ctrl_init_fail.1760853612
Short name T60
Test name
Test status
Simulation time 239681886 ps
CPU time 3.81 seconds
Started Mar 21 03:31:06 PM PDT 24
Finished Mar 21 03:31:10 PM PDT 24
Peak memory 241348 kb
Host smart-1d9fac39-4960-4fd9-8e0e-2902e745f6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760853612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.1760853612
Directory /workspace/286.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/287.otp_ctrl_init_fail.2352063660
Short name T202
Test name
Test status
Simulation time 591357542 ps
CPU time 4.92 seconds
Started Mar 21 03:31:04 PM PDT 24
Finished Mar 21 03:31:09 PM PDT 24
Peak memory 241432 kb
Host smart-179fe69a-aed5-488e-9fe6-d2cb5a1f712e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352063660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.2352063660
Directory /workspace/287.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/288.otp_ctrl_init_fail.2159252709
Short name T133
Test name
Test status
Simulation time 418276680 ps
CPU time 3.81 seconds
Started Mar 21 03:31:13 PM PDT 24
Finished Mar 21 03:31:17 PM PDT 24
Peak memory 241364 kb
Host smart-0be7297f-740f-4f3b-b668-96239fa875dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159252709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.2159252709
Directory /workspace/288.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/289.otp_ctrl_init_fail.3620519400
Short name T179
Test name
Test status
Simulation time 1906641969 ps
CPU time 3.66 seconds
Started Mar 21 03:31:06 PM PDT 24
Finished Mar 21 03:31:10 PM PDT 24
Peak memory 241680 kb
Host smart-2864fdcd-3105-48b0-925d-71e4483a8979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620519400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.3620519400
Directory /workspace/289.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_alert_test.3391917798
Short name T10
Test name
Test status
Simulation time 185214271 ps
CPU time 1.68 seconds
Started Mar 21 03:28:25 PM PDT 24
Finished Mar 21 03:28:27 PM PDT 24
Peak memory 239904 kb
Host smart-52b70a36-deb1-4378-b5d7-46fb30671774
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391917798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.3391917798
Directory /workspace/29.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.otp_ctrl_check_fail.326635548
Short name T393
Test name
Test status
Simulation time 22185437032 ps
CPU time 31.76 seconds
Started Mar 21 03:28:20 PM PDT 24
Finished Mar 21 03:28:53 PM PDT 24
Peak memory 241644 kb
Host smart-bdb06e9d-fb07-40df-8d42-c51395f91b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326635548 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.326635548
Directory /workspace/29.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_errs.572741621
Short name T128
Test name
Test status
Simulation time 2947618729 ps
CPU time 30.75 seconds
Started Mar 21 03:28:21 PM PDT 24
Finished Mar 21 03:28:53 PM PDT 24
Peak memory 242580 kb
Host smart-d74f1df9-57d7-46d3-b37b-c9854f96fcb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572741621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.572741621
Directory /workspace/29.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_lock.526830298
Short name T118
Test name
Test status
Simulation time 627364265 ps
CPU time 20.21 seconds
Started Mar 21 03:28:21 PM PDT 24
Finished Mar 21 03:28:42 PM PDT 24
Peak memory 241280 kb
Host smart-e9197d69-9cd8-40c9-ab33-d110b1b6bded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526830298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.526830298
Directory /workspace/29.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/29.otp_ctrl_init_fail.153852704
Short name T880
Test name
Test status
Simulation time 636729244 ps
CPU time 4.07 seconds
Started Mar 21 03:28:21 PM PDT 24
Finished Mar 21 03:28:26 PM PDT 24
Peak memory 241340 kb
Host smart-6c06df9c-1586-48c8-9824-81dd3b98ef38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153852704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.153852704
Directory /workspace/29.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_macro_errs.1776873814
Short name T1004
Test name
Test status
Simulation time 220149973 ps
CPU time 4.14 seconds
Started Mar 21 03:28:21 PM PDT 24
Finished Mar 21 03:28:26 PM PDT 24
Peak memory 241376 kb
Host smart-73a3fae2-31a3-4041-abf6-a2cd15f8797b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776873814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.1776873814
Directory /workspace/29.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_key_req.4284755177
Short name T637
Test name
Test status
Simulation time 671704595 ps
CPU time 25.24 seconds
Started Mar 21 03:28:25 PM PDT 24
Finished Mar 21 03:28:50 PM PDT 24
Peak memory 241348 kb
Host smart-040ff026-59bd-4066-9f3f-9d146fbe3295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284755177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.4284755177
Directory /workspace/29.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_esc.430626758
Short name T756
Test name
Test status
Simulation time 370236032 ps
CPU time 11.49 seconds
Started Mar 21 03:28:24 PM PDT 24
Finished Mar 21 03:28:36 PM PDT 24
Peak memory 241600 kb
Host smart-ebd065f6-e1e2-499d-9f32-222885687ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430626758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.430626758
Directory /workspace/29.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/29.otp_ctrl_regwen.1626494830
Short name T984
Test name
Test status
Simulation time 1057145449 ps
CPU time 10.47 seconds
Started Mar 21 03:28:21 PM PDT 24
Finished Mar 21 03:28:32 PM PDT 24
Peak memory 241396 kb
Host smart-64f9f481-258c-4593-8cf7-18f5745123e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1626494830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.1626494830
Directory /workspace/29.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/29.otp_ctrl_smoke.810371471
Short name T226
Test name
Test status
Simulation time 241712101 ps
CPU time 5.42 seconds
Started Mar 21 03:28:19 PM PDT 24
Finished Mar 21 03:28:25 PM PDT 24
Peak memory 241244 kb
Host smart-614730c3-41e8-4c58-a962-004be9f74809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810371471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.810371471
Directory /workspace/29.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/29.otp_ctrl_test_access.236714496
Short name T676
Test name
Test status
Simulation time 1225754127 ps
CPU time 19.76 seconds
Started Mar 21 03:28:24 PM PDT 24
Finished Mar 21 03:28:45 PM PDT 24
Peak memory 241364 kb
Host smart-29d4be23-c24f-42fa-a9ab-7ccfe44cfce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236714496 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.236714496
Directory /workspace/29.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/290.otp_ctrl_init_fail.3731319656
Short name T748
Test name
Test status
Simulation time 142631721 ps
CPU time 3.88 seconds
Started Mar 21 03:31:06 PM PDT 24
Finished Mar 21 03:31:11 PM PDT 24
Peak memory 241440 kb
Host smart-d00b4acc-9945-41e4-a230-b5fda16be98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731319656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.3731319656
Directory /workspace/290.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/291.otp_ctrl_init_fail.477413995
Short name T841
Test name
Test status
Simulation time 1959841521 ps
CPU time 7.1 seconds
Started Mar 21 03:31:06 PM PDT 24
Finished Mar 21 03:31:14 PM PDT 24
Peak memory 241428 kb
Host smart-eadce8d2-0554-4214-995e-c6cf986748f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477413995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.477413995
Directory /workspace/291.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/292.otp_ctrl_init_fail.3571321344
Short name T1175
Test name
Test status
Simulation time 178504745 ps
CPU time 5.46 seconds
Started Mar 21 03:31:10 PM PDT 24
Finished Mar 21 03:31:15 PM PDT 24
Peak memory 241296 kb
Host smart-5824a506-14ff-4f3f-b000-ac1881e8f79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571321344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.3571321344
Directory /workspace/292.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/293.otp_ctrl_init_fail.1827737866
Short name T48
Test name
Test status
Simulation time 198996148 ps
CPU time 5.13 seconds
Started Mar 21 03:31:05 PM PDT 24
Finished Mar 21 03:31:11 PM PDT 24
Peak memory 241312 kb
Host smart-b7528d9c-b6ad-45f3-83f8-5410c6cb64c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827737866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.1827737866
Directory /workspace/293.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/295.otp_ctrl_init_fail.1862069634
Short name T546
Test name
Test status
Simulation time 560602920 ps
CPU time 3.83 seconds
Started Mar 21 03:31:18 PM PDT 24
Finished Mar 21 03:31:23 PM PDT 24
Peak memory 241368 kb
Host smart-27bb7ff6-d1cd-4109-b183-36d3de8bf47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862069634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.1862069634
Directory /workspace/295.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/296.otp_ctrl_init_fail.1748633505
Short name T230
Test name
Test status
Simulation time 152747275 ps
CPU time 3.68 seconds
Started Mar 21 03:31:18 PM PDT 24
Finished Mar 21 03:31:22 PM PDT 24
Peak memory 241428 kb
Host smart-3eedba9c-6cf2-4843-a28b-2b070a1a33cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748633505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.1748633505
Directory /workspace/296.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/297.otp_ctrl_init_fail.3613043308
Short name T628
Test name
Test status
Simulation time 586551951 ps
CPU time 5.21 seconds
Started Mar 21 03:31:18 PM PDT 24
Finished Mar 21 03:31:23 PM PDT 24
Peak memory 241356 kb
Host smart-6d6e0500-96f2-4826-ba68-c4f244b25554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613043308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.3613043308
Directory /workspace/297.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/298.otp_ctrl_init_fail.4283719060
Short name T1189
Test name
Test status
Simulation time 144081089 ps
CPU time 4.21 seconds
Started Mar 21 03:31:14 PM PDT 24
Finished Mar 21 03:31:18 PM PDT 24
Peak memory 241772 kb
Host smart-06e77a64-0e13-4783-a77a-a5069d439ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283719060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.4283719060
Directory /workspace/298.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/299.otp_ctrl_init_fail.1311280065
Short name T689
Test name
Test status
Simulation time 2039605683 ps
CPU time 4.27 seconds
Started Mar 21 03:31:16 PM PDT 24
Finished Mar 21 03:31:21 PM PDT 24
Peak memory 241672 kb
Host smart-0c309de3-c289-4824-8a57-c2e5137648a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311280065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.1311280065
Directory /workspace/299.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_alert_test.4105089226
Short name T822
Test name
Test status
Simulation time 86009070 ps
CPU time 1.67 seconds
Started Mar 21 03:27:05 PM PDT 24
Finished Mar 21 03:27:06 PM PDT 24
Peak memory 240072 kb
Host smart-17d3b3ce-f648-4b72-b43a-abe8c49b80df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105089226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.4105089226
Directory /workspace/3.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.otp_ctrl_background_chks.215891387
Short name T502
Test name
Test status
Simulation time 637907443 ps
CPU time 21.86 seconds
Started Mar 21 03:27:04 PM PDT 24
Finished Mar 21 03:27:27 PM PDT 24
Peak memory 241452 kb
Host smart-b8a54cef-b5b6-428d-bfae-210ebb9c805e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215891387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.215891387
Directory /workspace/3.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/3.otp_ctrl_check_fail.1282666170
Short name T66
Test name
Test status
Simulation time 1775689273 ps
CPU time 18.33 seconds
Started Mar 21 03:27:02 PM PDT 24
Finished Mar 21 03:27:21 PM PDT 24
Peak memory 241760 kb
Host smart-349e014e-0982-4621-8244-6ee4e52add12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282666170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.1282666170
Directory /workspace/3.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_errs.3914225572
Short name T7
Test name
Test status
Simulation time 6267916047 ps
CPU time 33.29 seconds
Started Mar 21 03:27:03 PM PDT 24
Finished Mar 21 03:27:36 PM PDT 24
Peak memory 241976 kb
Host smart-74926b54-4e8b-4ee2-a9d9-4cedb8dc17a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914225572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.3914225572
Directory /workspace/3.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_lock.4255042010
Short name T351
Test name
Test status
Simulation time 12425304152 ps
CPU time 33.32 seconds
Started Mar 21 03:27:04 PM PDT 24
Finished Mar 21 03:27:38 PM PDT 24
Peak memory 242524 kb
Host smart-9ccbbdc8-8a6c-4fa5-b88a-6f04c225dd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255042010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.4255042010
Directory /workspace/3.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/3.otp_ctrl_init_fail.2480130598
Short name T542
Test name
Test status
Simulation time 139854990 ps
CPU time 3.9 seconds
Started Mar 21 03:27:03 PM PDT 24
Finished Mar 21 03:27:07 PM PDT 24
Peak memory 241792 kb
Host smart-299f3002-b44b-46a3-bdb8-546798c01add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480130598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.2480130598
Directory /workspace/3.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_macro_errs.1372004579
Short name T368
Test name
Test status
Simulation time 1175568529 ps
CPU time 17.69 seconds
Started Mar 21 03:26:57 PM PDT 24
Finished Mar 21 03:27:15 PM PDT 24
Peak memory 241604 kb
Host smart-beca89ce-75ab-4c28-bfda-2d8ef5d20f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372004579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.1372004579
Directory /workspace/3.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_key_req.446067465
Short name T921
Test name
Test status
Simulation time 426002945 ps
CPU time 9.68 seconds
Started Mar 21 03:26:57 PM PDT 24
Finished Mar 21 03:27:07 PM PDT 24
Peak memory 241208 kb
Host smart-090e3f84-932e-4ea8-8531-d65027dbc981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446067465 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.446067465
Directory /workspace/3.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_esc.3350052388
Short name T896
Test name
Test status
Simulation time 339255288 ps
CPU time 6.3 seconds
Started Mar 21 03:27:04 PM PDT 24
Finished Mar 21 03:27:10 PM PDT 24
Peak memory 241308 kb
Host smart-209b54a5-4ed4-4417-8526-aebc6fbff4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350052388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.3350052388
Directory /workspace/3.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_req.1289374188
Short name T500
Test name
Test status
Simulation time 518728869 ps
CPU time 8.13 seconds
Started Mar 21 03:27:02 PM PDT 24
Finished Mar 21 03:27:10 PM PDT 24
Peak memory 241636 kb
Host smart-a5e5f060-d40b-49e5-92c6-fe1874a0cdf4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1289374188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.1289374188
Directory /workspace/3.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_regwen.1695978162
Short name T778
Test name
Test status
Simulation time 382608451 ps
CPU time 4.32 seconds
Started Mar 21 03:27:03 PM PDT 24
Finished Mar 21 03:27:07 PM PDT 24
Peak memory 241220 kb
Host smart-e6212952-eba9-41a9-ba4f-58be9aad1833
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1695978162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.1695978162
Directory /workspace/3.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/3.otp_ctrl_sec_cm.3446697075
Short name T248
Test name
Test status
Simulation time 21366118883 ps
CPU time 213.9 seconds
Started Mar 21 03:27:04 PM PDT 24
Finished Mar 21 03:30:39 PM PDT 24
Peak memory 273956 kb
Host smart-90727670-908d-4841-8f57-651a91494dc2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446697075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.3446697075
Directory /workspace/3.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.otp_ctrl_smoke.3717999122
Short name T476
Test name
Test status
Simulation time 3200278486 ps
CPU time 10.14 seconds
Started Mar 21 03:26:57 PM PDT 24
Finished Mar 21 03:27:07 PM PDT 24
Peak memory 241428 kb
Host smart-4ab5877b-cbf6-46f0-8e58-5ee50d7ae25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717999122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.3717999122
Directory /workspace/3.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all_with_rand_reset.175021636
Short name T140
Test name
Test status
Simulation time 18911522050 ps
CPU time 585.01 seconds
Started Mar 21 03:26:58 PM PDT 24
Finished Mar 21 03:36:43 PM PDT 24
Peak memory 264816 kb
Host smart-efdf3217-1a07-4fb5-85ef-78b0418817fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175021636 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all_with_rand_reset.175021636
Directory /workspace/3.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.otp_ctrl_test_access.3832770434
Short name T418
Test name
Test status
Simulation time 142980491 ps
CPU time 4.52 seconds
Started Mar 21 03:27:04 PM PDT 24
Finished Mar 21 03:27:08 PM PDT 24
Peak memory 241220 kb
Host smart-8aa6ad67-9b42-484a-a2c7-59302b14f378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832770434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.3832770434
Directory /workspace/3.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/30.otp_ctrl_alert_test.306031893
Short name T433
Test name
Test status
Simulation time 117361827 ps
CPU time 2.18 seconds
Started Mar 21 03:28:23 PM PDT 24
Finished Mar 21 03:28:25 PM PDT 24
Peak memory 240144 kb
Host smart-580a8f38-12c3-42ac-a3d7-cedee4a47cae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306031893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.306031893
Directory /workspace/30.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.otp_ctrl_check_fail.431184623
Short name T962
Test name
Test status
Simulation time 910168007 ps
CPU time 7.88 seconds
Started Mar 21 03:28:21 PM PDT 24
Finished Mar 21 03:28:30 PM PDT 24
Peak memory 241640 kb
Host smart-6d44fe42-d653-4e45-a26a-a36cec2670b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431184623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.431184623
Directory /workspace/30.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_errs.868754000
Short name T472
Test name
Test status
Simulation time 1874860935 ps
CPU time 28.26 seconds
Started Mar 21 03:28:22 PM PDT 24
Finished Mar 21 03:28:51 PM PDT 24
Peak memory 241840 kb
Host smart-503fb6c1-1881-4821-896c-741c54c91d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868754000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.868754000
Directory /workspace/30.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_lock.3372997543
Short name T391
Test name
Test status
Simulation time 2790197389 ps
CPU time 33.46 seconds
Started Mar 21 03:28:22 PM PDT 24
Finished Mar 21 03:28:56 PM PDT 24
Peak memory 241500 kb
Host smart-be341ef5-7a3a-46b6-a2f1-a99932c40dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372997543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.3372997543
Directory /workspace/30.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/30.otp_ctrl_init_fail.1927890066
Short name T129
Test name
Test status
Simulation time 762795518 ps
CPU time 5.18 seconds
Started Mar 21 03:28:27 PM PDT 24
Finished Mar 21 03:28:32 PM PDT 24
Peak memory 241376 kb
Host smart-d3821a83-9b92-4f6a-819a-cece9d4189b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927890066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.1927890066
Directory /workspace/30.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_macro_errs.4050485511
Short name T1099
Test name
Test status
Simulation time 932529579 ps
CPU time 22.41 seconds
Started Mar 21 03:28:22 PM PDT 24
Finished Mar 21 03:28:45 PM PDT 24
Peak memory 244400 kb
Host smart-733e60be-7cf4-4c3b-8c86-91513f282ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050485511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.4050485511
Directory /workspace/30.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_key_req.189873883
Short name T452
Test name
Test status
Simulation time 15193849569 ps
CPU time 37.28 seconds
Started Mar 21 03:28:24 PM PDT 24
Finished Mar 21 03:29:01 PM PDT 24
Peak memory 242492 kb
Host smart-07e5eb39-b698-497f-a78f-fc560c65fc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189873883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.189873883
Directory /workspace/30.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_esc.3409345917
Short name T928
Test name
Test status
Simulation time 105013499 ps
CPU time 3.54 seconds
Started Mar 21 03:28:24 PM PDT 24
Finished Mar 21 03:28:28 PM PDT 24
Peak memory 241192 kb
Host smart-4d13fc14-ff0e-49f1-99d9-4bc282d34d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409345917 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.3409345917
Directory /workspace/30.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_req.3112061962
Short name T804
Test name
Test status
Simulation time 1398032397 ps
CPU time 16.88 seconds
Started Mar 21 03:28:25 PM PDT 24
Finished Mar 21 03:28:42 PM PDT 24
Peak memory 248040 kb
Host smart-08eb5ec2-cb09-4cfb-9cff-98c1606b9a61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3112061962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_req.3112061962
Directory /workspace/30.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_regwen.3697257893
Short name T1073
Test name
Test status
Simulation time 2900098264 ps
CPU time 6.36 seconds
Started Mar 21 03:28:22 PM PDT 24
Finished Mar 21 03:28:29 PM PDT 24
Peak memory 241480 kb
Host smart-a52a984d-9675-422f-abe1-77b370fd0413
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3697257893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.3697257893
Directory /workspace/30.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/30.otp_ctrl_smoke.3889552861
Short name T776
Test name
Test status
Simulation time 510768119 ps
CPU time 4.9 seconds
Started Mar 21 03:28:21 PM PDT 24
Finished Mar 21 03:28:26 PM PDT 24
Peak memory 241208 kb
Host smart-ac0eec5b-4302-421a-80e6-08e6e9b6cee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889552861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.3889552861
Directory /workspace/30.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all.854848592
Short name T130
Test name
Test status
Simulation time 9928561797 ps
CPU time 46.68 seconds
Started Mar 21 03:28:22 PM PDT 24
Finished Mar 21 03:29:09 PM PDT 24
Peak memory 243568 kb
Host smart-e9a23ed7-8759-4274-869e-9be82689f27d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854848592 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all.
854848592
Directory /workspace/30.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all_with_rand_reset.2831536088
Short name T348
Test name
Test status
Simulation time 1278119819770 ps
CPU time 2059.44 seconds
Started Mar 21 03:28:24 PM PDT 24
Finished Mar 21 04:02:44 PM PDT 24
Peak memory 704632 kb
Host smart-7e1b06aa-4485-4dfe-9358-e73024e538a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831536088 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all_with_rand_reset.2831536088
Directory /workspace/30.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.otp_ctrl_test_access.3861848735
Short name T1096
Test name
Test status
Simulation time 394925355 ps
CPU time 8.09 seconds
Started Mar 21 03:28:26 PM PDT 24
Finished Mar 21 03:28:35 PM PDT 24
Peak memory 241300 kb
Host smart-260bba71-69d7-4539-ba8f-2c86b84f5952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861848735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.3861848735
Directory /workspace/30.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/31.otp_ctrl_alert_test.3232207711
Short name T440
Test name
Test status
Simulation time 270346539 ps
CPU time 2.13 seconds
Started Mar 21 03:28:20 PM PDT 24
Finished Mar 21 03:28:22 PM PDT 24
Peak memory 240008 kb
Host smart-97fc53f5-d91c-4147-8617-f846ae415645
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232207711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.3232207711
Directory /workspace/31.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.otp_ctrl_check_fail.2477628525
Short name T1115
Test name
Test status
Simulation time 17668687993 ps
CPU time 47.35 seconds
Started Mar 21 03:28:25 PM PDT 24
Finished Mar 21 03:29:13 PM PDT 24
Peak memory 244296 kb
Host smart-e9475821-bb83-4441-9266-bcd12a5476cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477628525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.2477628525
Directory /workspace/31.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_errs.4204262089
Short name T522
Test name
Test status
Simulation time 1059819436 ps
CPU time 22.81 seconds
Started Mar 21 03:28:23 PM PDT 24
Finished Mar 21 03:28:46 PM PDT 24
Peak memory 241180 kb
Host smart-06ec0c5a-14cd-49b6-a36d-0d958ba41852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204262089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_errs.4204262089
Directory /workspace/31.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_lock.800771016
Short name T534
Test name
Test status
Simulation time 1656293647 ps
CPU time 33.14 seconds
Started Mar 21 03:28:21 PM PDT 24
Finished Mar 21 03:28:55 PM PDT 24
Peak memory 241520 kb
Host smart-3aa8cd4e-64fb-4e45-912c-1880ea7561d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800771016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.800771016
Directory /workspace/31.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/31.otp_ctrl_init_fail.802333234
Short name T890
Test name
Test status
Simulation time 144732761 ps
CPU time 4.12 seconds
Started Mar 21 03:28:24 PM PDT 24
Finished Mar 21 03:28:28 PM PDT 24
Peak memory 241156 kb
Host smart-2298d407-9e8e-4e57-a785-de80c4bb2fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802333234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.802333234
Directory /workspace/31.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_macro_errs.4109755653
Short name T221
Test name
Test status
Simulation time 1193138370 ps
CPU time 17.7 seconds
Started Mar 21 03:28:25 PM PDT 24
Finished Mar 21 03:28:43 PM PDT 24
Peak memory 246660 kb
Host smart-76b7b927-dee0-4027-bc53-de94eaab04c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109755653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.4109755653
Directory /workspace/31.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_key_req.4035078974
Short name T864
Test name
Test status
Simulation time 3010709362 ps
CPU time 6.62 seconds
Started Mar 21 03:28:22 PM PDT 24
Finished Mar 21 03:28:29 PM PDT 24
Peak memory 241836 kb
Host smart-e394c78e-76ef-40fd-9010-68a0a47075db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035078974 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.4035078974
Directory /workspace/31.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_esc.1787099287
Short name T925
Test name
Test status
Simulation time 2516943929 ps
CPU time 20.28 seconds
Started Mar 21 03:28:26 PM PDT 24
Finished Mar 21 03:28:46 PM PDT 24
Peak memory 241308 kb
Host smart-fa5b3b82-5d36-4e6f-8f5d-92c7b624323b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787099287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.1787099287
Directory /workspace/31.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_req.1357115335
Short name T714
Test name
Test status
Simulation time 9903968325 ps
CPU time 32.41 seconds
Started Mar 21 03:28:22 PM PDT 24
Finished Mar 21 03:28:55 PM PDT 24
Peak memory 241392 kb
Host smart-d86dd87a-a74a-43ed-9b47-deb2b443fdcf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1357115335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_req.1357115335
Directory /workspace/31.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_regwen.2697215864
Short name T570
Test name
Test status
Simulation time 271649556 ps
CPU time 7.39 seconds
Started Mar 21 03:28:19 PM PDT 24
Finished Mar 21 03:28:27 PM PDT 24
Peak memory 241424 kb
Host smart-ecac65b2-d635-4cdd-be3b-52b0079836c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2697215864 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.2697215864
Directory /workspace/31.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/31.otp_ctrl_smoke.2008522729
Short name T13
Test name
Test status
Simulation time 358154955 ps
CPU time 7.42 seconds
Started Mar 21 03:28:25 PM PDT 24
Finished Mar 21 03:28:33 PM PDT 24
Peak memory 241340 kb
Host smart-a431dd9b-f070-48b1-9941-c34d0cc72611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008522729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.2008522729
Directory /workspace/31.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all_with_rand_reset.3083536401
Short name T1035
Test name
Test status
Simulation time 57510341576 ps
CPU time 1274.08 seconds
Started Mar 21 03:28:25 PM PDT 24
Finished Mar 21 03:49:40 PM PDT 24
Peak memory 252696 kb
Host smart-a084161f-c211-447c-a5cf-950c189a1f38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083536401 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all_with_rand_reset.3083536401
Directory /workspace/31.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.otp_ctrl_test_access.2493280545
Short name T1057
Test name
Test status
Simulation time 119550010 ps
CPU time 3.07 seconds
Started Mar 21 03:28:22 PM PDT 24
Finished Mar 21 03:28:25 PM PDT 24
Peak memory 241664 kb
Host smart-2322835c-9cc9-47d3-9fae-ca2f846bbdf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493280545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.2493280545
Directory /workspace/31.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/32.otp_ctrl_alert_test.3046802773
Short name T488
Test name
Test status
Simulation time 69509035 ps
CPU time 1.84 seconds
Started Mar 21 03:28:22 PM PDT 24
Finished Mar 21 03:28:24 PM PDT 24
Peak memory 239848 kb
Host smart-12fba710-65fd-4d28-ab8b-8e52b5ba063f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046802773 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.3046802773
Directory /workspace/32.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.otp_ctrl_check_fail.2573596963
Short name T86
Test name
Test status
Simulation time 1491377081 ps
CPU time 26.71 seconds
Started Mar 21 03:28:21 PM PDT 24
Finished Mar 21 03:28:48 PM PDT 24
Peak memory 248260 kb
Host smart-1387b9c3-800f-49e4-9ef6-6d4d75c06efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573596963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.2573596963
Directory /workspace/32.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_errs.1044576568
Short name T582
Test name
Test status
Simulation time 3367338273 ps
CPU time 13.79 seconds
Started Mar 21 03:28:24 PM PDT 24
Finished Mar 21 03:28:38 PM PDT 24
Peak memory 241484 kb
Host smart-b0441cda-b0c2-4f48-b56f-fbc0cebb25a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044576568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.1044576568
Directory /workspace/32.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_lock.2171543024
Short name T468
Test name
Test status
Simulation time 4669208559 ps
CPU time 32.81 seconds
Started Mar 21 03:28:25 PM PDT 24
Finished Mar 21 03:28:59 PM PDT 24
Peak memory 241808 kb
Host smart-c7be1d1d-7fbe-4ba3-8d13-c5c89d43bd70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171543024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.2171543024
Directory /workspace/32.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/32.otp_ctrl_init_fail.2369044461
Short name T1169
Test name
Test status
Simulation time 278285540 ps
CPU time 4.26 seconds
Started Mar 21 03:28:27 PM PDT 24
Finished Mar 21 03:28:31 PM PDT 24
Peak memory 241368 kb
Host smart-a0316f49-c8b7-48ea-a6e6-ddf9d774f340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369044461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.2369044461
Directory /workspace/32.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_macro_errs.4237943977
Short name T1019
Test name
Test status
Simulation time 3947584805 ps
CPU time 25.39 seconds
Started Mar 21 03:28:27 PM PDT 24
Finished Mar 21 03:28:53 PM PDT 24
Peak memory 246300 kb
Host smart-a1f08bd4-ecbc-4f22-98cb-57a21756cf30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237943977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_macro_errs.4237943977
Directory /workspace/32.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_key_req.103193457
Short name T269
Test name
Test status
Simulation time 4028331743 ps
CPU time 8.68 seconds
Started Mar 21 03:28:20 PM PDT 24
Finished Mar 21 03:28:30 PM PDT 24
Peak memory 241456 kb
Host smart-57bce2b9-0438-4a03-9d5e-ac603ebd342b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103193457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.103193457
Directory /workspace/32.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_esc.3418577534
Short name T163
Test name
Test status
Simulation time 8041608732 ps
CPU time 18.92 seconds
Started Mar 21 03:28:24 PM PDT 24
Finished Mar 21 03:28:44 PM PDT 24
Peak memory 241240 kb
Host smart-4c10468d-4459-43c3-900b-4ada1c8bb339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418577534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.3418577534
Directory /workspace/32.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_req.1819975428
Short name T408
Test name
Test status
Simulation time 9728651466 ps
CPU time 27.67 seconds
Started Mar 21 03:28:26 PM PDT 24
Finished Mar 21 03:28:54 PM PDT 24
Peak memory 241392 kb
Host smart-7f61550f-ca70-4c28-8ca1-2e7c766f20b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1819975428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.1819975428
Directory /workspace/32.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_regwen.2194545224
Short name T842
Test name
Test status
Simulation time 195851294 ps
CPU time 3.66 seconds
Started Mar 21 03:28:20 PM PDT 24
Finished Mar 21 03:28:24 PM PDT 24
Peak memory 241180 kb
Host smart-7ff9e21f-0fdb-4025-91c3-2682ff81d958
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2194545224 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.2194545224
Directory /workspace/32.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/32.otp_ctrl_smoke.3471119001
Short name T872
Test name
Test status
Simulation time 695408372 ps
CPU time 5.52 seconds
Started Mar 21 03:28:23 PM PDT 24
Finished Mar 21 03:28:29 PM PDT 24
Peak memory 241620 kb
Host smart-3d34a579-052b-43ac-8c59-20680bc33255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471119001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.3471119001
Directory /workspace/32.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all.178846250
Short name T948
Test name
Test status
Simulation time 2827866535 ps
CPU time 103.13 seconds
Started Mar 21 03:28:21 PM PDT 24
Finished Mar 21 03:30:04 PM PDT 24
Peak memory 246124 kb
Host smart-f8d89898-d61e-44c0-810f-359c0c4cf5e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178846250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all.
178846250
Directory /workspace/32.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all_with_rand_reset.3276864432
Short name T626
Test name
Test status
Simulation time 60947412000 ps
CPU time 673.8 seconds
Started Mar 21 03:28:20 PM PDT 24
Finished Mar 21 03:39:35 PM PDT 24
Peak memory 257124 kb
Host smart-7c4649ea-3b23-4465-bbae-b9bfb81a2240
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276864432 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all_with_rand_reset.3276864432
Directory /workspace/32.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.otp_ctrl_test_access.1613745418
Short name T406
Test name
Test status
Simulation time 1334104183 ps
CPU time 10.67 seconds
Started Mar 21 03:28:22 PM PDT 24
Finished Mar 21 03:28:33 PM PDT 24
Peak memory 241756 kb
Host smart-24c0ab59-db0f-47b5-87c3-fdd4299eefbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613745418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.1613745418
Directory /workspace/32.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/33.otp_ctrl_alert_test.4132338439
Short name T671
Test name
Test status
Simulation time 296702799 ps
CPU time 1.86 seconds
Started Mar 21 03:28:34 PM PDT 24
Finished Mar 21 03:28:36 PM PDT 24
Peak memory 239960 kb
Host smart-7bf7fdd3-ab2c-4a15-8aeb-23b32c4db0c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132338439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.4132338439
Directory /workspace/33.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.otp_ctrl_check_fail.45495694
Short name T34
Test name
Test status
Simulation time 3190334728 ps
CPU time 25.3 seconds
Started Mar 21 03:28:35 PM PDT 24
Finished Mar 21 03:29:01 PM PDT 24
Peak memory 241812 kb
Host smart-44610717-2990-451b-8451-270897cdef34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45495694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.45495694
Directory /workspace/33.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_errs.699498735
Short name T455
Test name
Test status
Simulation time 317195333 ps
CPU time 8.13 seconds
Started Mar 21 03:28:35 PM PDT 24
Finished Mar 21 03:28:44 PM PDT 24
Peak memory 241384 kb
Host smart-31037a44-c012-48d2-b28c-7f9bff803deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699498735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.699498735
Directory /workspace/33.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_lock.3218779398
Short name T562
Test name
Test status
Simulation time 1227619327 ps
CPU time 10.74 seconds
Started Mar 21 03:28:22 PM PDT 24
Finished Mar 21 03:28:33 PM PDT 24
Peak memory 241704 kb
Host smart-42430d0d-f47e-4eab-97a3-251fe811998b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218779398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_lock.3218779398
Directory /workspace/33.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/33.otp_ctrl_init_fail.2995199125
Short name T548
Test name
Test status
Simulation time 2162396332 ps
CPU time 6.4 seconds
Started Mar 21 03:28:26 PM PDT 24
Finished Mar 21 03:28:32 PM PDT 24
Peak memory 241752 kb
Host smart-45cb0906-dd4a-4459-bb87-ff777c966b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995199125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.2995199125
Directory /workspace/33.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_macro_errs.1622639479
Short name T166
Test name
Test status
Simulation time 485812089 ps
CPU time 8.98 seconds
Started Mar 21 03:28:35 PM PDT 24
Finished Mar 21 03:28:44 PM PDT 24
Peak memory 241996 kb
Host smart-5b2635dd-c56f-472c-beaf-da59ecc7bf6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622639479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.1622639479
Directory /workspace/33.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_key_req.2061822717
Short name T17
Test name
Test status
Simulation time 9167773069 ps
CPU time 20.84 seconds
Started Mar 21 03:28:37 PM PDT 24
Finished Mar 21 03:28:58 PM PDT 24
Peak memory 242732 kb
Host smart-c01b1290-a84d-4da6-a7ea-73c69b646bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061822717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_key_req.2061822717
Directory /workspace/33.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_esc.2390806185
Short name T967
Test name
Test status
Simulation time 256004505 ps
CPU time 3.84 seconds
Started Mar 21 03:28:21 PM PDT 24
Finished Mar 21 03:28:26 PM PDT 24
Peak memory 241232 kb
Host smart-33f15647-d8da-47a6-994e-9f207d7040e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390806185 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.2390806185
Directory /workspace/33.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_req.3801153077
Short name T450
Test name
Test status
Simulation time 576075052 ps
CPU time 12.11 seconds
Started Mar 21 03:28:20 PM PDT 24
Finished Mar 21 03:28:32 PM PDT 24
Peak memory 241132 kb
Host smart-177406b6-6e5d-4741-a88e-88ab20a4f587
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3801153077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_req.3801153077
Directory /workspace/33.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_regwen.1470722123
Short name T379
Test name
Test status
Simulation time 197586721 ps
CPU time 6.81 seconds
Started Mar 21 03:28:33 PM PDT 24
Finished Mar 21 03:28:40 PM PDT 24
Peak memory 241340 kb
Host smart-65ac641a-a4da-48db-a75d-0d50fe97013c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1470722123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.1470722123
Directory /workspace/33.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/33.otp_ctrl_smoke.2899141961
Short name T485
Test name
Test status
Simulation time 632955642 ps
CPU time 14.02 seconds
Started Mar 21 03:28:23 PM PDT 24
Finished Mar 21 03:28:38 PM PDT 24
Peak memory 241368 kb
Host smart-8467dd55-4fad-42a1-83c4-bc0db3f8c24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899141961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.2899141961
Directory /workspace/33.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all.2748192664
Short name T72
Test name
Test status
Simulation time 26074014288 ps
CPU time 273.96 seconds
Started Mar 21 03:28:36 PM PDT 24
Finished Mar 21 03:33:10 PM PDT 24
Peak memory 249340 kb
Host smart-6e5c41e2-455f-41ae-a9c0-78e99a48d366
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748192664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all
.2748192664
Directory /workspace/33.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all_with_rand_reset.1477674869
Short name T306
Test name
Test status
Simulation time 88362151815 ps
CPU time 1535.52 seconds
Started Mar 21 03:28:33 PM PDT 24
Finished Mar 21 03:54:09 PM PDT 24
Peak memory 266012 kb
Host smart-e4f0ee63-5ded-425f-bca6-08e97fc0cf6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477674869 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all_with_rand_reset.1477674869
Directory /workspace/33.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.otp_ctrl_alert_test.2284946588
Short name T1070
Test name
Test status
Simulation time 71474050 ps
CPU time 2 seconds
Started Mar 21 03:28:37 PM PDT 24
Finished Mar 21 03:28:39 PM PDT 24
Peak memory 239916 kb
Host smart-737e7baf-81b3-48f2-a8dd-4fb61484b096
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284946588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.2284946588
Directory /workspace/34.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_errs.128261003
Short name T1033
Test name
Test status
Simulation time 2047586641 ps
CPU time 34.53 seconds
Started Mar 21 03:28:33 PM PDT 24
Finished Mar 21 03:29:08 PM PDT 24
Peak memory 243692 kb
Host smart-6370dd86-c459-4403-80de-c37429270a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128261003 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.128261003
Directory /workspace/34.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_lock.1885793155
Short name T758
Test name
Test status
Simulation time 1049453821 ps
CPU time 14.09 seconds
Started Mar 21 03:28:32 PM PDT 24
Finished Mar 21 03:28:47 PM PDT 24
Peak memory 241708 kb
Host smart-fa9c0ccd-be54-4e77-a3d3-d16b5fe2de35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885793155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_lock.1885793155
Directory /workspace/34.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/34.otp_ctrl_init_fail.2883441148
Short name T703
Test name
Test status
Simulation time 1822595363 ps
CPU time 7 seconds
Started Mar 21 03:28:32 PM PDT 24
Finished Mar 21 03:28:40 PM PDT 24
Peak memory 241836 kb
Host smart-3e239ac1-8cea-461d-9cc7-578d95c800f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883441148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.2883441148
Directory /workspace/34.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_macro_errs.2041145717
Short name T870
Test name
Test status
Simulation time 924046132 ps
CPU time 26.63 seconds
Started Mar 21 03:28:34 PM PDT 24
Finished Mar 21 03:29:01 PM PDT 24
Peak memory 241808 kb
Host smart-9b2857b6-507d-4acb-8c01-372cbae1bf78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041145717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.2041145717
Directory /workspace/34.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_key_req.4071432705
Short name T729
Test name
Test status
Simulation time 10612128331 ps
CPU time 36.18 seconds
Started Mar 21 03:28:32 PM PDT 24
Finished Mar 21 03:29:09 PM PDT 24
Peak memory 242452 kb
Host smart-4a098fc2-b30b-4465-800c-d446fcfc91db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071432705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.4071432705
Directory /workspace/34.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_esc.2240226333
Short name T540
Test name
Test status
Simulation time 700883076 ps
CPU time 17.98 seconds
Started Mar 21 03:28:35 PM PDT 24
Finished Mar 21 03:28:53 PM PDT 24
Peak memory 241356 kb
Host smart-d65cf38d-a51a-4d0a-84bf-4c4b8d586222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240226333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.2240226333
Directory /workspace/34.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_req.676598116
Short name T206
Test name
Test status
Simulation time 6352592101 ps
CPU time 15.88 seconds
Started Mar 21 03:28:38 PM PDT 24
Finished Mar 21 03:28:54 PM PDT 24
Peak memory 241348 kb
Host smart-3c6bf79a-ffb5-4bc5-a178-1071f6eddbfd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=676598116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.676598116
Directory /workspace/34.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_regwen.3353710275
Short name T855
Test name
Test status
Simulation time 246588199 ps
CPU time 6.29 seconds
Started Mar 21 03:28:36 PM PDT 24
Finished Mar 21 03:28:43 PM PDT 24
Peak memory 241168 kb
Host smart-60ade1bf-7180-4483-b943-3272ea79f6c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3353710275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.3353710275
Directory /workspace/34.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/34.otp_ctrl_smoke.2861272426
Short name T881
Test name
Test status
Simulation time 438720037 ps
CPU time 7.24 seconds
Started Mar 21 03:28:37 PM PDT 24
Finished Mar 21 03:28:44 PM PDT 24
Peak memory 241724 kb
Host smart-355d3317-bd5d-491c-b346-d9bc859e358e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861272426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_smoke.2861272426
Directory /workspace/34.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all.1573901477
Short name T1171
Test name
Test status
Simulation time 21454008894 ps
CPU time 112.46 seconds
Started Mar 21 03:28:38 PM PDT 24
Finished Mar 21 03:30:31 PM PDT 24
Peak memory 245284 kb
Host smart-5a414226-3104-488d-928d-780f8abe9e95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573901477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all
.1573901477
Directory /workspace/34.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.otp_ctrl_test_access.392018822
Short name T227
Test name
Test status
Simulation time 384339367 ps
CPU time 7.99 seconds
Started Mar 21 03:28:37 PM PDT 24
Finished Mar 21 03:28:45 PM PDT 24
Peak memory 241232 kb
Host smart-a75c56fa-12ef-477c-a592-1be8b736fd7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392018822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_test_access.392018822
Directory /workspace/34.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/35.otp_ctrl_alert_test.3494524946
Short name T1026
Test name
Test status
Simulation time 190188787 ps
CPU time 1.68 seconds
Started Mar 21 03:28:35 PM PDT 24
Finished Mar 21 03:28:37 PM PDT 24
Peak memory 239872 kb
Host smart-00b49253-9e10-480b-a276-088d3ad33a9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494524946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.3494524946
Directory /workspace/35.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.otp_ctrl_check_fail.1051353814
Short name T660
Test name
Test status
Simulation time 1587701189 ps
CPU time 11.02 seconds
Started Mar 21 03:28:33 PM PDT 24
Finished Mar 21 03:28:44 PM PDT 24
Peak memory 241896 kb
Host smart-0a4ba3aa-4087-4d2e-af64-736513e03358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051353814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.1051353814
Directory /workspace/35.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_errs.3742498645
Short name T705
Test name
Test status
Simulation time 1906390971 ps
CPU time 33.19 seconds
Started Mar 21 03:28:35 PM PDT 24
Finished Mar 21 03:29:09 PM PDT 24
Peak memory 243180 kb
Host smart-1c9e387e-78c1-4778-8f31-deb4defbc1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742498645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_errs.3742498645
Directory /workspace/35.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_lock.3104495942
Short name T1170
Test name
Test status
Simulation time 3715943612 ps
CPU time 38.9 seconds
Started Mar 21 03:28:34 PM PDT 24
Finished Mar 21 03:29:13 PM PDT 24
Peak memory 241348 kb
Host smart-8e62c957-791f-42eb-929c-370881e35773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104495942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_lock.3104495942
Directory /workspace/35.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/35.otp_ctrl_init_fail.2821500016
Short name T986
Test name
Test status
Simulation time 92894088 ps
CPU time 3.44 seconds
Started Mar 21 03:28:37 PM PDT 24
Finished Mar 21 03:28:41 PM PDT 24
Peak memory 241640 kb
Host smart-c57ce46f-3ba3-4483-9987-cbb4b4260a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821500016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.2821500016
Directory /workspace/35.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_macro_errs.2022179613
Short name T920
Test name
Test status
Simulation time 827571562 ps
CPU time 11.52 seconds
Started Mar 21 03:28:35 PM PDT 24
Finished Mar 21 03:28:47 PM PDT 24
Peak memory 244536 kb
Host smart-28049dd8-8435-4b28-8115-c3788ca32e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022179613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.2022179613
Directory /workspace/35.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_key_req.2533195038
Short name T399
Test name
Test status
Simulation time 661799132 ps
CPU time 28.05 seconds
Started Mar 21 03:28:38 PM PDT 24
Finished Mar 21 03:29:06 PM PDT 24
Peak memory 241804 kb
Host smart-d23e4208-2202-43d4-8185-4a922e831eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533195038 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.2533195038
Directory /workspace/35.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_esc.2382657032
Short name T607
Test name
Test status
Simulation time 148895659 ps
CPU time 4.37 seconds
Started Mar 21 03:28:35 PM PDT 24
Finished Mar 21 03:28:40 PM PDT 24
Peak memory 241700 kb
Host smart-2246afb7-3f57-4490-9a63-133e70e41956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382657032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.2382657032
Directory /workspace/35.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_req.3478125311
Short name T1068
Test name
Test status
Simulation time 977353431 ps
CPU time 16.85 seconds
Started Mar 21 03:28:36 PM PDT 24
Finished Mar 21 03:28:53 PM PDT 24
Peak memory 241236 kb
Host smart-ad4111ff-235d-4fa6-a3aa-d2d2e652b767
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3478125311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.3478125311
Directory /workspace/35.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_regwen.2344889866
Short name T975
Test name
Test status
Simulation time 1088487142 ps
CPU time 9.96 seconds
Started Mar 21 03:28:35 PM PDT 24
Finished Mar 21 03:28:46 PM PDT 24
Peak memory 241444 kb
Host smart-602b62ed-a1ab-4ecc-abd2-61d19a112f24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2344889866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.2344889866
Directory /workspace/35.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/35.otp_ctrl_smoke.1656265126
Short name T801
Test name
Test status
Simulation time 228938704 ps
CPU time 9.47 seconds
Started Mar 21 03:28:36 PM PDT 24
Finished Mar 21 03:28:46 PM PDT 24
Peak memory 241200 kb
Host smart-3036997c-1b52-4f17-a1d4-cbee09b412ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656265126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.1656265126
Directory /workspace/35.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/35.otp_ctrl_stress_all.477479269
Short name T497
Test name
Test status
Simulation time 23797211575 ps
CPU time 168.06 seconds
Started Mar 21 03:28:34 PM PDT 24
Finished Mar 21 03:31:23 PM PDT 24
Peak memory 262332 kb
Host smart-21fc1a49-2529-47c3-8438-2e635acd7e0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477479269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all.
477479269
Directory /workspace/35.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.otp_ctrl_stress_all_with_rand_reset.1445074463
Short name T555
Test name
Test status
Simulation time 17310631973 ps
CPU time 428.79 seconds
Started Mar 21 03:28:36 PM PDT 24
Finished Mar 21 03:35:45 PM PDT 24
Peak memory 264432 kb
Host smart-758fab2d-3e4e-4a6c-b7e9-061d10a070a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445074463 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all_with_rand_reset.1445074463
Directory /workspace/35.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.otp_ctrl_test_access.219001530
Short name T518
Test name
Test status
Simulation time 204170693 ps
CPU time 5.1 seconds
Started Mar 21 03:28:34 PM PDT 24
Finished Mar 21 03:28:40 PM PDT 24
Peak memory 241088 kb
Host smart-0d107b54-3d17-451f-a848-fc4f153936b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219001530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_test_access.219001530
Directory /workspace/35.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/36.otp_ctrl_alert_test.2307649669
Short name T825
Test name
Test status
Simulation time 204014884 ps
CPU time 2.07 seconds
Started Mar 21 03:28:35 PM PDT 24
Finished Mar 21 03:28:37 PM PDT 24
Peak memory 239852 kb
Host smart-f7068360-b2ba-4fef-b3eb-45292dd74ce1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307649669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.2307649669
Directory /workspace/36.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.otp_ctrl_check_fail.1067158535
Short name T115
Test name
Test status
Simulation time 982220551 ps
CPU time 22.88 seconds
Started Mar 21 03:28:36 PM PDT 24
Finished Mar 21 03:28:59 PM PDT 24
Peak memory 241320 kb
Host smart-1f4f6c32-2e43-4de8-b7c7-f347c3b003b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067158535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.1067158535
Directory /workspace/36.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_errs.2662466752
Short name T360
Test name
Test status
Simulation time 693334931 ps
CPU time 10.24 seconds
Started Mar 21 03:28:37 PM PDT 24
Finished Mar 21 03:28:47 PM PDT 24
Peak memory 241180 kb
Host smart-ec6f5021-2d10-41d1-a76c-ba2628cbae42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662466752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.2662466752
Directory /workspace/36.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_lock.1186952222
Short name T641
Test name
Test status
Simulation time 3332735672 ps
CPU time 14.92 seconds
Started Mar 21 03:28:37 PM PDT 24
Finished Mar 21 03:28:52 PM PDT 24
Peak memory 241376 kb
Host smart-06f4ab84-9f5d-4705-9c53-1a3b59080a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186952222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_lock.1186952222
Directory /workspace/36.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/36.otp_ctrl_init_fail.954921986
Short name T760
Test name
Test status
Simulation time 480520076 ps
CPU time 4.57 seconds
Started Mar 21 03:28:34 PM PDT 24
Finished Mar 21 03:28:38 PM PDT 24
Peak memory 241376 kb
Host smart-ffade214-9caf-4fcc-a195-235b52d93336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954921986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.954921986
Directory /workspace/36.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_macro_errs.2477289279
Short name T1110
Test name
Test status
Simulation time 13611442804 ps
CPU time 37.78 seconds
Started Mar 21 03:28:35 PM PDT 24
Finished Mar 21 03:29:13 PM PDT 24
Peak memory 247452 kb
Host smart-aba3b64e-1635-495f-b640-9929dcab40d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477289279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.2477289279
Directory /workspace/36.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_key_req.3908135379
Short name T110
Test name
Test status
Simulation time 454007571 ps
CPU time 10.8 seconds
Started Mar 21 03:28:36 PM PDT 24
Finished Mar 21 03:28:47 PM PDT 24
Peak memory 241452 kb
Host smart-54151780-f6b2-4273-9580-2bc38ddd6447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908135379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.3908135379
Directory /workspace/36.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_esc.521093653
Short name T709
Test name
Test status
Simulation time 242164855 ps
CPU time 5.25 seconds
Started Mar 21 03:28:35 PM PDT 24
Finished Mar 21 03:28:41 PM PDT 24
Peak memory 240968 kb
Host smart-0050b6d6-6ea5-4a19-85bb-30020cb214f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521093653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.521093653
Directory /workspace/36.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_req.609168495
Short name T101
Test name
Test status
Simulation time 11052287761 ps
CPU time 30.54 seconds
Started Mar 21 03:28:34 PM PDT 24
Finished Mar 21 03:29:05 PM PDT 24
Peak memory 241760 kb
Host smart-199ee724-c931-4726-a034-69184e15f839
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=609168495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.609168495
Directory /workspace/36.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_regwen.707555964
Short name T1060
Test name
Test status
Simulation time 205330220 ps
CPU time 7.13 seconds
Started Mar 21 03:28:33 PM PDT 24
Finished Mar 21 03:28:41 PM PDT 24
Peak memory 241676 kb
Host smart-ac625162-1966-47e7-bd86-3bfd4cb5f227
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=707555964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.707555964
Directory /workspace/36.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/36.otp_ctrl_smoke.3426344041
Short name T414
Test name
Test status
Simulation time 1490707633 ps
CPU time 15.25 seconds
Started Mar 21 03:28:35 PM PDT 24
Finished Mar 21 03:28:51 PM PDT 24
Peak memory 241324 kb
Host smart-e3b24515-cbf1-43ad-9328-62b4dca80cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426344041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.3426344041
Directory /workspace/36.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all.2214450480
Short name T723
Test name
Test status
Simulation time 18284632111 ps
CPU time 223.47 seconds
Started Mar 21 03:28:32 PM PDT 24
Finished Mar 21 03:32:16 PM PDT 24
Peak memory 264820 kb
Host smart-0fa3e7f4-8548-404d-b93e-6a67633491a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214450480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all
.2214450480
Directory /workspace/36.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all_with_rand_reset.1489501763
Short name T687
Test name
Test status
Simulation time 305901063153 ps
CPU time 589.71 seconds
Started Mar 21 03:28:34 PM PDT 24
Finished Mar 21 03:38:24 PM PDT 24
Peak memory 295016 kb
Host smart-bb473df5-618e-4512-8042-69877a16f13c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489501763 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all_with_rand_reset.1489501763
Directory /workspace/36.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.otp_ctrl_test_access.2509728610
Short name T696
Test name
Test status
Simulation time 3445616977 ps
CPU time 36.3 seconds
Started Mar 21 03:28:34 PM PDT 24
Finished Mar 21 03:29:11 PM PDT 24
Peak memory 241820 kb
Host smart-a0cb8f18-c105-4b87-a1b8-9584c934e191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509728610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.2509728610
Directory /workspace/36.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/37.otp_ctrl_alert_test.781128788
Short name T848
Test name
Test status
Simulation time 205413078 ps
CPU time 1.78 seconds
Started Mar 21 03:28:49 PM PDT 24
Finished Mar 21 03:28:50 PM PDT 24
Peak memory 239832 kb
Host smart-60756d3b-663f-4d8b-8a44-991253c65375
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781128788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.781128788
Directory /workspace/37.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_errs.3954295394
Short name T749
Test name
Test status
Simulation time 8950275867 ps
CPU time 26.53 seconds
Started Mar 21 03:28:35 PM PDT 24
Finished Mar 21 03:29:02 PM PDT 24
Peak memory 241904 kb
Host smart-a6404a6d-3e69-45d9-ba2d-9aaa54ab49e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954295394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.3954295394
Directory /workspace/37.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_lock.562608808
Short name T394
Test name
Test status
Simulation time 2025573242 ps
CPU time 20.23 seconds
Started Mar 21 03:28:40 PM PDT 24
Finished Mar 21 03:29:00 PM PDT 24
Peak memory 241688 kb
Host smart-ec12570d-3d9f-478a-9d81-63cbc935e0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562608808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.562608808
Directory /workspace/37.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/37.otp_ctrl_init_fail.105832114
Short name T174
Test name
Test status
Simulation time 160433582 ps
CPU time 4.24 seconds
Started Mar 21 03:28:35 PM PDT 24
Finished Mar 21 03:28:40 PM PDT 24
Peak memory 241404 kb
Host smart-234237bd-9db0-4dc1-bbe6-e5af598835ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105832114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.105832114
Directory /workspace/37.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_macro_errs.4287317678
Short name T524
Test name
Test status
Simulation time 12485702090 ps
CPU time 29.91 seconds
Started Mar 21 03:28:49 PM PDT 24
Finished Mar 21 03:29:19 PM PDT 24
Peak memory 244060 kb
Host smart-1b40b71d-9391-46bd-8777-c5465045270b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287317678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.4287317678
Directory /workspace/37.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_key_req.555761707
Short name T398
Test name
Test status
Simulation time 358413000 ps
CPU time 13.46 seconds
Started Mar 21 03:28:48 PM PDT 24
Finished Mar 21 03:29:02 PM PDT 24
Peak memory 248144 kb
Host smart-36931afd-f379-4f5f-a9a5-2e2d0e16f209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555761707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_key_req.555761707
Directory /workspace/37.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_esc.263322307
Short name T1053
Test name
Test status
Simulation time 542729765 ps
CPU time 5.52 seconds
Started Mar 21 03:28:35 PM PDT 24
Finished Mar 21 03:28:41 PM PDT 24
Peak memory 241520 kb
Host smart-6b83996b-3151-4cf9-a510-d2acc04570de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263322307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.263322307
Directory /workspace/37.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_req.345237903
Short name T1150
Test name
Test status
Simulation time 2282070620 ps
CPU time 22.1 seconds
Started Mar 21 03:28:35 PM PDT 24
Finished Mar 21 03:28:57 PM PDT 24
Peak memory 241776 kb
Host smart-8dbca02b-e916-49d6-9d75-3d5c6e696c5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=345237903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.345237903
Directory /workspace/37.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_regwen.477149695
Short name T1079
Test name
Test status
Simulation time 231443885 ps
CPU time 7.32 seconds
Started Mar 21 03:28:49 PM PDT 24
Finished Mar 21 03:28:56 PM PDT 24
Peak memory 241648 kb
Host smart-e913cbf1-a9dd-4086-965b-91b34c2e4782
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=477149695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.477149695
Directory /workspace/37.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/37.otp_ctrl_smoke.1180096219
Short name T489
Test name
Test status
Simulation time 399106723 ps
CPU time 8.24 seconds
Started Mar 21 03:28:35 PM PDT 24
Finished Mar 21 03:28:44 PM PDT 24
Peak memory 241316 kb
Host smart-a0d32958-0dc4-462a-86ac-007cd1c6e17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180096219 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_smoke.1180096219
Directory /workspace/37.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all.2610022993
Short name T1167
Test name
Test status
Simulation time 17943575997 ps
CPU time 129.81 seconds
Started Mar 21 03:28:51 PM PDT 24
Finished Mar 21 03:31:01 PM PDT 24
Peak memory 248436 kb
Host smart-af261737-d37b-4d97-b840-a5d7165deb54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610022993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all
.2610022993
Directory /workspace/37.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all_with_rand_reset.208037231
Short name T577
Test name
Test status
Simulation time 439939286951 ps
CPU time 1523.1 seconds
Started Mar 21 03:28:51 PM PDT 24
Finished Mar 21 03:54:15 PM PDT 24
Peak memory 346592 kb
Host smart-c94955a6-c088-428d-931b-dabfa251fadb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208037231 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all_with_rand_reset.208037231
Directory /workspace/37.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.otp_ctrl_test_access.2413915823
Short name T993
Test name
Test status
Simulation time 4120426853 ps
CPU time 30.48 seconds
Started Mar 21 03:28:47 PM PDT 24
Finished Mar 21 03:29:18 PM PDT 24
Peak memory 241484 kb
Host smart-8a3bb25d-930e-4535-ba5f-f1784af734e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413915823 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.2413915823
Directory /workspace/37.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/38.otp_ctrl_alert_test.932179536
Short name T508
Test name
Test status
Simulation time 140267197 ps
CPU time 1.98 seconds
Started Mar 21 03:28:50 PM PDT 24
Finished Mar 21 03:28:52 PM PDT 24
Peak memory 239892 kb
Host smart-b802d56f-ee86-40ed-bb31-e777238f4366
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932179536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.932179536
Directory /workspace/38.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.otp_ctrl_check_fail.3640058517
Short name T482
Test name
Test status
Simulation time 288012422 ps
CPU time 4.39 seconds
Started Mar 21 03:28:50 PM PDT 24
Finished Mar 21 03:28:54 PM PDT 24
Peak memory 241300 kb
Host smart-21790ec3-da80-4ceb-ab15-2e87ed0f796d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640058517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.3640058517
Directory /workspace/38.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_errs.1716526485
Short name T170
Test name
Test status
Simulation time 1872730625 ps
CPU time 46.62 seconds
Started Mar 21 03:28:50 PM PDT 24
Finished Mar 21 03:29:36 PM PDT 24
Peak memory 249112 kb
Host smart-c6aa039a-116a-424d-bc4a-5022c5c803ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716526485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_errs.1716526485
Directory /workspace/38.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_lock.3492720979
Short name T501
Test name
Test status
Simulation time 1591092391 ps
CPU time 22.11 seconds
Started Mar 21 03:28:48 PM PDT 24
Finished Mar 21 03:29:10 PM PDT 24
Peak memory 241408 kb
Host smart-95724f4d-115f-4348-b195-a300f421e81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492720979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_lock.3492720979
Directory /workspace/38.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/38.otp_ctrl_macro_errs.3572078978
Short name T553
Test name
Test status
Simulation time 3341838107 ps
CPU time 31.51 seconds
Started Mar 21 03:28:51 PM PDT 24
Finished Mar 21 03:29:23 PM PDT 24
Peak memory 247004 kb
Host smart-af275db5-6226-49b4-b8c0-bd1b6b6ef14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572078978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.3572078978
Directory /workspace/38.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_key_req.3563971433
Short name T523
Test name
Test status
Simulation time 558938124 ps
CPU time 5.32 seconds
Started Mar 21 03:28:48 PM PDT 24
Finished Mar 21 03:28:54 PM PDT 24
Peak memory 241632 kb
Host smart-c13373f8-a9ed-469d-a4d7-c0aecbce0d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563971433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_key_req.3563971433
Directory /workspace/38.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_esc.72090793
Short name T16
Test name
Test status
Simulation time 299267509 ps
CPU time 3.97 seconds
Started Mar 21 03:28:47 PM PDT 24
Finished Mar 21 03:28:51 PM PDT 24
Peak memory 241208 kb
Host smart-4ed8be74-5d80-4aa6-ad97-28f77426a475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72090793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.72090793
Directory /workspace/38.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_req.1512829050
Short name T469
Test name
Test status
Simulation time 10839469542 ps
CPU time 25.57 seconds
Started Mar 21 03:28:48 PM PDT 24
Finished Mar 21 03:29:14 PM PDT 24
Peak memory 241356 kb
Host smart-4fe16989-f1ea-4018-98a9-2578e5ddba08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1512829050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.1512829050
Directory /workspace/38.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_regwen.1433357630
Short name T980
Test name
Test status
Simulation time 3081429936 ps
CPU time 7.59 seconds
Started Mar 21 03:28:50 PM PDT 24
Finished Mar 21 03:28:58 PM PDT 24
Peak memory 241528 kb
Host smart-3e2fa622-07b8-4529-ba6b-72b2b723450b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1433357630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.1433357630
Directory /workspace/38.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/38.otp_ctrl_smoke.41462848
Short name T324
Test name
Test status
Simulation time 1031391979 ps
CPU time 9.4 seconds
Started Mar 21 03:28:50 PM PDT 24
Finished Mar 21 03:28:59 PM PDT 24
Peak memory 248156 kb
Host smart-e2930907-b4a6-42dd-ba79-5e090fda3a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41462848 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.41462848
Directory /workspace/38.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all.588601905
Short name T688
Test name
Test status
Simulation time 8430588384 ps
CPU time 28.53 seconds
Started Mar 21 03:28:47 PM PDT 24
Finished Mar 21 03:29:15 PM PDT 24
Peak memory 241536 kb
Host smart-ff1ffcc9-5d33-4abf-a5ac-e85a760d044d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588601905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all.
588601905
Directory /workspace/38.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.otp_ctrl_test_access.1277671388
Short name T1135
Test name
Test status
Simulation time 414684353 ps
CPU time 5.24 seconds
Started Mar 21 03:28:51 PM PDT 24
Finished Mar 21 03:28:57 PM PDT 24
Peak memory 241592 kb
Host smart-ddb7fd23-de76-4708-8694-3554a45cbdd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277671388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.1277671388
Directory /workspace/38.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/39.otp_ctrl_alert_test.106635853
Short name T715
Test name
Test status
Simulation time 212043298 ps
CPU time 3.05 seconds
Started Mar 21 03:28:49 PM PDT 24
Finished Mar 21 03:28:53 PM PDT 24
Peak memory 239856 kb
Host smart-2817a98f-86b1-4682-8bb3-b3c0d62a9118
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106635853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.106635853
Directory /workspace/39.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.otp_ctrl_check_fail.2644260368
Short name T49
Test name
Test status
Simulation time 3202140289 ps
CPU time 41.84 seconds
Started Mar 21 03:28:49 PM PDT 24
Finished Mar 21 03:29:31 PM PDT 24
Peak memory 242000 kb
Host smart-3299c714-1e53-4844-99e5-72dfa38a9b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644260368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.2644260368
Directory /workspace/39.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_errs.954900406
Short name T580
Test name
Test status
Simulation time 884964839 ps
CPU time 25.61 seconds
Started Mar 21 03:28:49 PM PDT 24
Finished Mar 21 03:29:15 PM PDT 24
Peak memory 241464 kb
Host smart-bdad2cdd-8235-461e-837a-5c75178a664d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954900406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.954900406
Directory /workspace/39.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_lock.19054627
Short name T1037
Test name
Test status
Simulation time 4820592405 ps
CPU time 16.01 seconds
Started Mar 21 03:28:49 PM PDT 24
Finished Mar 21 03:29:05 PM PDT 24
Peak memory 242264 kb
Host smart-a357de68-1603-41eb-84b4-9bf6baafa941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19054627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.19054627
Directory /workspace/39.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/39.otp_ctrl_init_fail.4120455679
Short name T816
Test name
Test status
Simulation time 542252168 ps
CPU time 4.18 seconds
Started Mar 21 03:28:52 PM PDT 24
Finished Mar 21 03:28:57 PM PDT 24
Peak memory 241400 kb
Host smart-76ef3344-5a23-40b1-8c2d-ad135a416d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120455679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.4120455679
Directory /workspace/39.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_macro_errs.2418666250
Short name T661
Test name
Test status
Simulation time 262086637 ps
CPU time 3.8 seconds
Started Mar 21 03:28:50 PM PDT 24
Finished Mar 21 03:28:54 PM PDT 24
Peak memory 241692 kb
Host smart-916a3ea2-fbc9-4554-ab60-1771fc86aa1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418666250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_macro_errs.2418666250
Directory /workspace/39.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_esc.704360228
Short name T989
Test name
Test status
Simulation time 116703821 ps
CPU time 4.81 seconds
Started Mar 21 03:28:48 PM PDT 24
Finished Mar 21 03:28:53 PM PDT 24
Peak memory 241064 kb
Host smart-7c93cc8f-5e87-4ac4-a800-3df80e024d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704360228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.704360228
Directory /workspace/39.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_req.4172039130
Short name T569
Test name
Test status
Simulation time 483170155 ps
CPU time 3.98 seconds
Started Mar 21 03:28:49 PM PDT 24
Finished Mar 21 03:28:53 PM PDT 24
Peak memory 241120 kb
Host smart-65d88520-5fce-4c35-87bc-c12ff86d23d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4172039130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.4172039130
Directory /workspace/39.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_regwen.2919463276
Short name T99
Test name
Test status
Simulation time 258912307 ps
CPU time 9.69 seconds
Started Mar 21 03:28:51 PM PDT 24
Finished Mar 21 03:29:01 PM PDT 24
Peak memory 241476 kb
Host smart-34b4290d-59ac-42d1-aaa1-fc68ec8540f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2919463276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.2919463276
Directory /workspace/39.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/39.otp_ctrl_smoke.1092382013
Short name T877
Test name
Test status
Simulation time 79799543 ps
CPU time 2.81 seconds
Started Mar 21 03:28:49 PM PDT 24
Finished Mar 21 03:28:52 PM PDT 24
Peak memory 247412 kb
Host smart-ecd7da02-3d70-4461-9596-ea177538fd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092382013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.1092382013
Directory /workspace/39.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all.3130723439
Short name T1176
Test name
Test status
Simulation time 3820319309 ps
CPU time 89.42 seconds
Started Mar 21 03:28:50 PM PDT 24
Finished Mar 21 03:30:19 PM PDT 24
Peak memory 260504 kb
Host smart-1edabc11-fb4c-4a46-994d-a84ec36a9a4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130723439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all
.3130723439
Directory /workspace/39.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all_with_rand_reset.2507940814
Short name T615
Test name
Test status
Simulation time 180533761552 ps
CPU time 1545.12 seconds
Started Mar 21 03:28:50 PM PDT 24
Finished Mar 21 03:54:35 PM PDT 24
Peak memory 273000 kb
Host smart-ec694747-4ff3-4ac3-a69d-234886cc3a07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507940814 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all_with_rand_reset.2507940814
Directory /workspace/39.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.otp_ctrl_test_access.896308841
Short name T638
Test name
Test status
Simulation time 6145590785 ps
CPU time 28.94 seconds
Started Mar 21 03:28:51 PM PDT 24
Finished Mar 21 03:29:20 PM PDT 24
Peak memory 242388 kb
Host smart-4bf80187-e228-4256-8d11-eff01f0f75ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896308841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.896308841
Directory /workspace/39.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/4.otp_ctrl_alert_test.2482559272
Short name T349
Test name
Test status
Simulation time 142211199 ps
CPU time 1.8 seconds
Started Mar 21 03:27:09 PM PDT 24
Finished Mar 21 03:27:11 PM PDT 24
Peak memory 239892 kb
Host smart-deaf0e1c-5feb-437e-82f8-e2cc48c1c63f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482559272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.2482559272
Directory /workspace/4.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.otp_ctrl_background_chks.1488492399
Short name T93
Test name
Test status
Simulation time 4929001615 ps
CPU time 17.15 seconds
Started Mar 21 03:27:10 PM PDT 24
Finished Mar 21 03:27:27 PM PDT 24
Peak memory 241752 kb
Host smart-92731a36-5927-473e-a332-a8c8b31d991f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488492399 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.1488492399
Directory /workspace/4.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/4.otp_ctrl_check_fail.2958995073
Short name T552
Test name
Test status
Simulation time 572378958 ps
CPU time 10.99 seconds
Started Mar 21 03:27:27 PM PDT 24
Finished Mar 21 03:27:39 PM PDT 24
Peak memory 248236 kb
Host smart-81b68bcb-ae2f-4ace-bfb8-0673d7e94569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958995073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.2958995073
Directory /workspace/4.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_errs.344897385
Short name T724
Test name
Test status
Simulation time 498602845 ps
CPU time 15.55 seconds
Started Mar 21 03:27:13 PM PDT 24
Finished Mar 21 03:27:29 PM PDT 24
Peak memory 241616 kb
Host smart-4163317c-a058-4e7b-b529-52da65ed2e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344897385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.344897385
Directory /workspace/4.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_lock.3108048041
Short name T767
Test name
Test status
Simulation time 2593227089 ps
CPU time 16.74 seconds
Started Mar 21 03:27:17 PM PDT 24
Finished Mar 21 03:27:34 PM PDT 24
Peak memory 241520 kb
Host smart-e863847b-f32c-4719-a103-ce9b5e0e6711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108048041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.3108048041
Directory /workspace/4.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/4.otp_ctrl_init_fail.3483912811
Short name T180
Test name
Test status
Simulation time 91677685 ps
CPU time 4.09 seconds
Started Mar 21 03:27:16 PM PDT 24
Finished Mar 21 03:27:21 PM PDT 24
Peak memory 241420 kb
Host smart-8e57722a-d122-459b-b4b9-c52757aa78d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483912811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.3483912811
Directory /workspace/4.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_key_req.3073834760
Short name T1180
Test name
Test status
Simulation time 180533400 ps
CPU time 3.75 seconds
Started Mar 21 03:27:12 PM PDT 24
Finished Mar 21 03:27:16 PM PDT 24
Peak memory 241688 kb
Host smart-7876b86b-73cc-4873-b940-e58fd1f0302f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073834760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.3073834760
Directory /workspace/4.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_esc.3823520801
Short name T1197
Test name
Test status
Simulation time 910969910 ps
CPU time 13.12 seconds
Started Mar 21 03:27:10 PM PDT 24
Finished Mar 21 03:27:23 PM PDT 24
Peak memory 241784 kb
Host smart-34a22edc-294a-4952-9d39-5e7b854256e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823520801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.3823520801
Directory /workspace/4.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_req.1341287150
Short name T532
Test name
Test status
Simulation time 11283654345 ps
CPU time 28.25 seconds
Started Mar 21 03:27:16 PM PDT 24
Finished Mar 21 03:27:44 PM PDT 24
Peak memory 241336 kb
Host smart-643317b8-ddcd-4cc3-874f-0a57c1f84723
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1341287150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.1341287150
Directory /workspace/4.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_regwen.3231309858
Short name T301
Test name
Test status
Simulation time 1764378324 ps
CPU time 6.14 seconds
Started Mar 21 03:27:11 PM PDT 24
Finished Mar 21 03:27:17 PM PDT 24
Peak memory 241188 kb
Host smart-ed614a8b-e0df-4a9f-9ce3-7ff323540cea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3231309858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.3231309858
Directory /workspace/4.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/4.otp_ctrl_sec_cm.3080608493
Short name T249
Test name
Test status
Simulation time 9935904982 ps
CPU time 177.24 seconds
Started Mar 21 03:27:12 PM PDT 24
Finished Mar 21 03:30:09 PM PDT 24
Peak memory 270140 kb
Host smart-4bd0ee6c-382a-44d9-b358-02582e512bd0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080608493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.3080608493
Directory /workspace/4.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.otp_ctrl_smoke.3721204352
Short name T932
Test name
Test status
Simulation time 1394022159 ps
CPU time 12.2 seconds
Started Mar 21 03:27:11 PM PDT 24
Finished Mar 21 03:27:23 PM PDT 24
Peak memory 241320 kb
Host smart-f0d5b2cf-e2e2-44fa-a303-ca332e9130ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721204352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.3721204352
Directory /workspace/4.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/4.otp_ctrl_test_access.1470065006
Short name T435
Test name
Test status
Simulation time 285976598 ps
CPU time 9.44 seconds
Started Mar 21 03:27:11 PM PDT 24
Finished Mar 21 03:27:21 PM PDT 24
Peak memory 241548 kb
Host smart-432b39e0-689d-494c-8af4-ffa12f4aabb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470065006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.1470065006
Directory /workspace/4.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/40.otp_ctrl_alert_test.3782550462
Short name T289
Test name
Test status
Simulation time 879872964 ps
CPU time 3.54 seconds
Started Mar 21 03:28:46 PM PDT 24
Finished Mar 21 03:28:50 PM PDT 24
Peak memory 239924 kb
Host smart-ef86c7f4-f37b-4559-933f-8fc6ac19ed2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782550462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.3782550462
Directory /workspace/40.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.otp_ctrl_check_fail.3959969777
Short name T176
Test name
Test status
Simulation time 783973020 ps
CPU time 14.64 seconds
Started Mar 21 03:28:49 PM PDT 24
Finished Mar 21 03:29:03 PM PDT 24
Peak memory 241848 kb
Host smart-8e56c079-ed06-49a0-9487-d5aeb39380dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959969777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.3959969777
Directory /workspace/40.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_errs.3327083886
Short name T1196
Test name
Test status
Simulation time 1510829720 ps
CPU time 33.3 seconds
Started Mar 21 03:28:47 PM PDT 24
Finished Mar 21 03:29:20 PM PDT 24
Peak memory 244716 kb
Host smart-d852f2cb-258e-40d1-af55-4418a728c0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327083886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_errs.3327083886
Directory /workspace/40.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_lock.1311298644
Short name T403
Test name
Test status
Simulation time 756650993 ps
CPU time 16.64 seconds
Started Mar 21 03:28:47 PM PDT 24
Finished Mar 21 03:29:04 PM PDT 24
Peak memory 241780 kb
Host smart-8d010e96-d19a-4654-a003-128c14188104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311298644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.1311298644
Directory /workspace/40.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/40.otp_ctrl_init_fail.3454756916
Short name T137
Test name
Test status
Simulation time 202971032 ps
CPU time 4.59 seconds
Started Mar 21 03:28:51 PM PDT 24
Finished Mar 21 03:28:56 PM PDT 24
Peak memory 241684 kb
Host smart-9a9aa702-7c31-42ad-a43b-ccc71b22df3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454756916 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.3454756916
Directory /workspace/40.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_macro_errs.3369922091
Short name T530
Test name
Test status
Simulation time 7798100916 ps
CPU time 48.61 seconds
Started Mar 21 03:28:48 PM PDT 24
Finished Mar 21 03:29:37 PM PDT 24
Peak memory 249156 kb
Host smart-4b08d421-498e-4f87-b1b3-68f4c1f502a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369922091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.3369922091
Directory /workspace/40.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_key_req.3768312693
Short name T94
Test name
Test status
Simulation time 4005404318 ps
CPU time 30.61 seconds
Started Mar 21 03:28:47 PM PDT 24
Finished Mar 21 03:29:18 PM PDT 24
Peak memory 241624 kb
Host smart-80f24a99-26db-430f-a395-f3d53b8879dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768312693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_key_req.3768312693
Directory /workspace/40.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_esc.1020565760
Short name T212
Test name
Test status
Simulation time 158316936 ps
CPU time 7.75 seconds
Started Mar 21 03:28:49 PM PDT 24
Finished Mar 21 03:28:56 PM PDT 24
Peak memory 241264 kb
Host smart-bcdb1aec-ffea-46fd-9a44-d8182c4241b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020565760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.1020565760
Directory /workspace/40.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_req.1968421888
Short name T707
Test name
Test status
Simulation time 638241822 ps
CPU time 11.88 seconds
Started Mar 21 03:28:49 PM PDT 24
Finished Mar 21 03:29:01 PM PDT 24
Peak memory 241176 kb
Host smart-aa3609c9-d693-4ada-a61c-e4d0d26a9f71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1968421888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.1968421888
Directory /workspace/40.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_regwen.2042624925
Short name T378
Test name
Test status
Simulation time 435200031 ps
CPU time 6.98 seconds
Started Mar 21 03:28:51 PM PDT 24
Finished Mar 21 03:28:58 PM PDT 24
Peak memory 241096 kb
Host smart-3565ecd5-390d-462d-84d2-2e0f8ae6c5d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2042624925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.2042624925
Directory /workspace/40.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/40.otp_ctrl_smoke.1886091360
Short name T1113
Test name
Test status
Simulation time 878495602 ps
CPU time 9.11 seconds
Started Mar 21 03:28:49 PM PDT 24
Finished Mar 21 03:28:58 PM PDT 24
Peak memory 241564 kb
Host smart-9e152f48-ace6-48e5-be49-15c17b01a9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886091360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_smoke.1886091360
Directory /workspace/40.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all_with_rand_reset.1205609558
Short name T341
Test name
Test status
Simulation time 56454237356 ps
CPU time 721.65 seconds
Started Mar 21 03:28:49 PM PDT 24
Finished Mar 21 03:40:51 PM PDT 24
Peak memory 313592 kb
Host smart-8996fbaf-867f-4315-ac80-efb6c0fef8fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205609558 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all_with_rand_reset.1205609558
Directory /workspace/40.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.otp_ctrl_test_access.1245463259
Short name T782
Test name
Test status
Simulation time 4070086237 ps
CPU time 27.47 seconds
Started Mar 21 03:28:48 PM PDT 24
Finished Mar 21 03:29:16 PM PDT 24
Peak memory 242188 kb
Host smart-151b1c3f-30eb-49f3-af62-d2c836999626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245463259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.1245463259
Directory /workspace/40.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/41.otp_ctrl_alert_test.1093353394
Short name T832
Test name
Test status
Simulation time 275749455 ps
CPU time 2.24 seconds
Started Mar 21 03:29:01 PM PDT 24
Finished Mar 21 03:29:03 PM PDT 24
Peak memory 239876 kb
Host smart-722e8f7d-3bb5-4ce7-9b44-73f21718b909
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093353394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.1093353394
Directory /workspace/41.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_errs.618816124
Short name T327
Test name
Test status
Simulation time 13473483241 ps
CPU time 24.61 seconds
Started Mar 21 03:28:48 PM PDT 24
Finished Mar 21 03:29:13 PM PDT 24
Peak memory 241656 kb
Host smart-43e00f8f-8927-48d1-83df-f52251d9344d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618816124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_errs.618816124
Directory /workspace/41.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_lock.2840753879
Short name T788
Test name
Test status
Simulation time 6456866008 ps
CPU time 12.43 seconds
Started Mar 21 03:28:50 PM PDT 24
Finished Mar 21 03:29:02 PM PDT 24
Peak memory 242412 kb
Host smart-bd06d6f0-4fb7-4db9-a2f6-a97966e74239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840753879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.2840753879
Directory /workspace/41.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/41.otp_ctrl_init_fail.743599268
Short name T1021
Test name
Test status
Simulation time 212631095 ps
CPU time 3.42 seconds
Started Mar 21 03:28:48 PM PDT 24
Finished Mar 21 03:28:52 PM PDT 24
Peak memory 241420 kb
Host smart-3aa208c4-6028-4c7f-bc1e-292ea52621f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743599268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.743599268
Directory /workspace/41.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_macro_errs.2711232558
Short name T625
Test name
Test status
Simulation time 3651283855 ps
CPU time 29.81 seconds
Started Mar 21 03:28:48 PM PDT 24
Finished Mar 21 03:29:18 PM PDT 24
Peak memory 244556 kb
Host smart-108203f0-a7a0-463b-a012-4ab6fb9af7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711232558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.2711232558
Directory /workspace/41.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_key_req.1820641561
Short name T551
Test name
Test status
Simulation time 16485358965 ps
CPU time 34.89 seconds
Started Mar 21 03:28:51 PM PDT 24
Finished Mar 21 03:29:27 PM PDT 24
Peak memory 242988 kb
Host smart-97d7077a-9b1c-47d3-ba3a-49f6cfec08e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820641561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_key_req.1820641561
Directory /workspace/41.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_esc.2889894951
Short name T844
Test name
Test status
Simulation time 344238218 ps
CPU time 4.09 seconds
Started Mar 21 03:28:48 PM PDT 24
Finished Mar 21 03:28:52 PM PDT 24
Peak memory 241460 kb
Host smart-2a440469-52fa-4e64-aba5-f7ba455b2dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889894951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.2889894951
Directory /workspace/41.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_req.1493147084
Short name T616
Test name
Test status
Simulation time 1023721518 ps
CPU time 13.52 seconds
Started Mar 21 03:28:48 PM PDT 24
Finished Mar 21 03:29:02 PM PDT 24
Peak memory 248092 kb
Host smart-5a333d4d-040d-4375-8fb4-140d35d5bbff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1493147084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.1493147084
Directory /workspace/41.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_regwen.3782555546
Short name T383
Test name
Test status
Simulation time 3610167457 ps
CPU time 8.63 seconds
Started Mar 21 03:29:03 PM PDT 24
Finished Mar 21 03:29:11 PM PDT 24
Peak memory 241956 kb
Host smart-75ecfb15-d1d9-425b-883b-ded625237161
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3782555546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.3782555546
Directory /workspace/41.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/41.otp_ctrl_smoke.2310927876
Short name T420
Test name
Test status
Simulation time 545165439 ps
CPU time 3.94 seconds
Started Mar 21 03:28:48 PM PDT 24
Finished Mar 21 03:28:52 PM PDT 24
Peak memory 248140 kb
Host smart-e7e6d2df-6458-42a8-a64c-aebbfac7923d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310927876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.2310927876
Directory /workspace/41.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/41.otp_ctrl_stress_all.3139535179
Short name T658
Test name
Test status
Simulation time 16460326767 ps
CPU time 256.61 seconds
Started Mar 21 03:29:03 PM PDT 24
Finished Mar 21 03:33:20 PM PDT 24
Peak memory 264008 kb
Host smart-89e4b603-bff0-4c28-839a-0e37863d4181
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139535179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all
.3139535179
Directory /workspace/41.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.otp_ctrl_stress_all_with_rand_reset.3971545962
Short name T699
Test name
Test status
Simulation time 94819739932 ps
CPU time 2456.13 seconds
Started Mar 21 03:29:05 PM PDT 24
Finished Mar 21 04:10:01 PM PDT 24
Peak memory 396760 kb
Host smart-963c2ae0-8a50-4697-82f7-5f831836f8a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971545962 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all_with_rand_reset.3971545962
Directory /workspace/41.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.otp_ctrl_test_access.716571062
Short name T104
Test name
Test status
Simulation time 1013431168 ps
CPU time 35.57 seconds
Started Mar 21 03:29:08 PM PDT 24
Finished Mar 21 03:29:43 PM PDT 24
Peak memory 241568 kb
Host smart-0ff23225-7938-4c3e-bbfb-d47535411f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716571062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.716571062
Directory /workspace/41.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/42.otp_ctrl_alert_test.1324307907
Short name T531
Test name
Test status
Simulation time 93386425 ps
CPU time 2.45 seconds
Started Mar 21 03:29:04 PM PDT 24
Finished Mar 21 03:29:06 PM PDT 24
Peak memory 240096 kb
Host smart-241738a5-9fc5-4edf-bde2-9009e7a256e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324307907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.1324307907
Directory /workspace/42.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.otp_ctrl_check_fail.1139372889
Short name T82
Test name
Test status
Simulation time 11615315293 ps
CPU time 17.84 seconds
Started Mar 21 03:29:01 PM PDT 24
Finished Mar 21 03:29:18 PM PDT 24
Peak memory 244552 kb
Host smart-7fd16af1-aaab-4c17-bc1c-c88e6ea7a2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139372889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.1139372889
Directory /workspace/42.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_errs.838693475
Short name T1101
Test name
Test status
Simulation time 2370226114 ps
CPU time 32.66 seconds
Started Mar 21 03:29:01 PM PDT 24
Finished Mar 21 03:29:33 PM PDT 24
Peak memory 244524 kb
Host smart-651586dd-7f52-451d-9a7c-f21942cecffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838693475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_errs.838693475
Directory /workspace/42.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_lock.3469542797
Short name T1166
Test name
Test status
Simulation time 1582351943 ps
CPU time 17.4 seconds
Started Mar 21 03:29:07 PM PDT 24
Finished Mar 21 03:29:25 PM PDT 24
Peak memory 241716 kb
Host smart-378c0e88-ade1-47ce-b694-1f25b8bfd0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469542797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.3469542797
Directory /workspace/42.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/42.otp_ctrl_init_fail.1998815280
Short name T199
Test name
Test status
Simulation time 417329715 ps
CPU time 4.5 seconds
Started Mar 21 03:29:07 PM PDT 24
Finished Mar 21 03:29:12 PM PDT 24
Peak memory 241352 kb
Host smart-fc7091b7-c595-467c-98f0-386248362db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998815280 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.1998815280
Directory /workspace/42.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_macro_errs.219893966
Short name T168
Test name
Test status
Simulation time 15321267909 ps
CPU time 36.88 seconds
Started Mar 21 03:29:04 PM PDT 24
Finished Mar 21 03:29:41 PM PDT 24
Peak memory 246564 kb
Host smart-ad53c760-c514-4646-a056-908710593eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219893966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_macro_errs.219893966
Directory /workspace/42.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_key_req.3823301872
Short name T229
Test name
Test status
Simulation time 1104135222 ps
CPU time 31.49 seconds
Started Mar 21 03:29:03 PM PDT 24
Finished Mar 21 03:29:35 PM PDT 24
Peak memory 248244 kb
Host smart-2ecacfbf-4183-4386-9b12-b98c824c2906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823301872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.3823301872
Directory /workspace/42.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_esc.668069324
Short name T630
Test name
Test status
Simulation time 515021923 ps
CPU time 14.45 seconds
Started Mar 21 03:29:02 PM PDT 24
Finished Mar 21 03:29:17 PM PDT 24
Peak memory 241272 kb
Host smart-b75472f4-2e69-4c73-b6e3-d9c0cc750dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668069324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.668069324
Directory /workspace/42.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_req.1509265107
Short name T400
Test name
Test status
Simulation time 1023090612 ps
CPU time 16.82 seconds
Started Mar 21 03:29:02 PM PDT 24
Finished Mar 21 03:29:19 PM PDT 24
Peak memory 241188 kb
Host smart-b91fc59c-c768-46a8-8572-aa3120e588e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1509265107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.1509265107
Directory /workspace/42.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_regwen.4096578334
Short name T879
Test name
Test status
Simulation time 432702412 ps
CPU time 5.49 seconds
Started Mar 21 03:29:02 PM PDT 24
Finished Mar 21 03:29:07 PM PDT 24
Peak memory 247840 kb
Host smart-bf77c9e7-60b6-4828-91b2-dc3be8799e6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4096578334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.4096578334
Directory /workspace/42.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/42.otp_ctrl_smoke.781585201
Short name T1108
Test name
Test status
Simulation time 665896868 ps
CPU time 8.06 seconds
Started Mar 21 03:29:07 PM PDT 24
Finished Mar 21 03:29:15 PM PDT 24
Peak memory 241112 kb
Host smart-4367e623-f81c-4166-94f2-a86ba9b4c71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781585201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_smoke.781585201
Directory /workspace/42.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all.98358335
Short name T397
Test name
Test status
Simulation time 29192171968 ps
CPU time 235.73 seconds
Started Mar 21 03:29:03 PM PDT 24
Finished Mar 21 03:32:58 PM PDT 24
Peak memory 269884 kb
Host smart-349b784c-25ca-45db-bbc6-8b8e3dac93e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98358335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all.98358335
Directory /workspace/42.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.otp_ctrl_test_access.1812549644
Short name T459
Test name
Test status
Simulation time 694623428 ps
CPU time 11.13 seconds
Started Mar 21 03:29:05 PM PDT 24
Finished Mar 21 03:29:16 PM PDT 24
Peak memory 241276 kb
Host smart-0d6b02bc-0b08-41ea-b93a-c9479c9a6402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812549644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.1812549644
Directory /workspace/42.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/43.otp_ctrl_alert_test.2422183051
Short name T108
Test name
Test status
Simulation time 103557749 ps
CPU time 1.94 seconds
Started Mar 21 03:29:05 PM PDT 24
Finished Mar 21 03:29:07 PM PDT 24
Peak memory 239912 kb
Host smart-4844f0dd-8483-440a-8cba-68d722aeae37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422183051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.2422183051
Directory /workspace/43.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.otp_ctrl_check_fail.3621896555
Short name T123
Test name
Test status
Simulation time 3246504324 ps
CPU time 40.17 seconds
Started Mar 21 03:29:05 PM PDT 24
Finished Mar 21 03:29:45 PM PDT 24
Peak memory 243540 kb
Host smart-efd3fcea-b4f4-4608-8589-26e44592cb66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621896555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.3621896555
Directory /workspace/43.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_errs.2828381818
Short name T366
Test name
Test status
Simulation time 4376453331 ps
CPU time 34.91 seconds
Started Mar 21 03:29:01 PM PDT 24
Finished Mar 21 03:29:36 PM PDT 24
Peak memory 245780 kb
Host smart-bcf5e950-5188-44fc-bb7a-adf4528e68ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828381818 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.2828381818
Directory /workspace/43.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_lock.1168429040
Short name T611
Test name
Test status
Simulation time 3644116352 ps
CPU time 8.91 seconds
Started Mar 21 03:29:02 PM PDT 24
Finished Mar 21 03:29:11 PM PDT 24
Peak memory 241840 kb
Host smart-fc829d55-7da0-4332-8604-4d06d0f4ec27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168429040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_lock.1168429040
Directory /workspace/43.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/43.otp_ctrl_init_fail.1094601980
Short name T1173
Test name
Test status
Simulation time 130285407 ps
CPU time 3.71 seconds
Started Mar 21 03:29:07 PM PDT 24
Finished Mar 21 03:29:11 PM PDT 24
Peak memory 241300 kb
Host smart-1696c88b-2807-45a2-a625-7853fd9151e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094601980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.1094601980
Directory /workspace/43.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_macro_errs.2579772524
Short name T1103
Test name
Test status
Simulation time 11144709861 ps
CPU time 25.08 seconds
Started Mar 21 03:29:01 PM PDT 24
Finished Mar 21 03:29:26 PM PDT 24
Peak memory 243076 kb
Host smart-0aa4d3c7-5a02-4c58-bb82-1ab613d66e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579772524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.2579772524
Directory /workspace/43.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_key_req.2331949773
Short name T401
Test name
Test status
Simulation time 318206178 ps
CPU time 14.86 seconds
Started Mar 21 03:29:02 PM PDT 24
Finished Mar 21 03:29:17 PM PDT 24
Peak memory 241380 kb
Host smart-549b24cb-3485-4c41-98f9-390c90ad7a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331949773 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_key_req.2331949773
Directory /workspace/43.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_esc.4193012601
Short name T907
Test name
Test status
Simulation time 5432127541 ps
CPU time 15.46 seconds
Started Mar 21 03:29:03 PM PDT 24
Finished Mar 21 03:29:19 PM PDT 24
Peak memory 241384 kb
Host smart-e14f3599-0f5a-40db-ac45-fef089bbc159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193012601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.4193012601
Directory /workspace/43.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_req.293920465
Short name T597
Test name
Test status
Simulation time 11778675399 ps
CPU time 31.55 seconds
Started Mar 21 03:29:05 PM PDT 24
Finished Mar 21 03:29:37 PM PDT 24
Peak memory 241444 kb
Host smart-ba971746-7eb7-41d3-8794-6454c4188b9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=293920465 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.293920465
Directory /workspace/43.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_regwen.4240060665
Short name T387
Test name
Test status
Simulation time 721714892 ps
CPU time 10.61 seconds
Started Mar 21 03:29:02 PM PDT 24
Finished Mar 21 03:29:12 PM PDT 24
Peak memory 241396 kb
Host smart-c0c6a577-a889-4732-aae4-570f8a9ebf16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4240060665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.4240060665
Directory /workspace/43.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/43.otp_ctrl_smoke.3989913550
Short name T869
Test name
Test status
Simulation time 154084449 ps
CPU time 6.14 seconds
Started Mar 21 03:29:02 PM PDT 24
Finished Mar 21 03:29:08 PM PDT 24
Peak memory 241636 kb
Host smart-08b2a102-4eb5-410d-bb1c-3968831ccc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989913550 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_smoke.3989913550
Directory /workspace/43.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all_with_rand_reset.4171667211
Short name T591
Test name
Test status
Simulation time 17963862416 ps
CPU time 386.17 seconds
Started Mar 21 03:29:02 PM PDT 24
Finished Mar 21 03:35:28 PM PDT 24
Peak memory 256644 kb
Host smart-663f80a4-7822-4e2d-b93a-3a998633797d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171667211 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all_with_rand_reset.4171667211
Directory /workspace/43.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.otp_ctrl_alert_test.3125030167
Short name T667
Test name
Test status
Simulation time 580528038 ps
CPU time 2.26 seconds
Started Mar 21 03:29:05 PM PDT 24
Finished Mar 21 03:29:07 PM PDT 24
Peak memory 239816 kb
Host smart-1ba03e7b-8a6e-4008-9029-bc57cf26f78b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125030167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.3125030167
Directory /workspace/44.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.otp_ctrl_check_fail.3897411152
Short name T63
Test name
Test status
Simulation time 1878379121 ps
CPU time 22.29 seconds
Started Mar 21 03:29:02 PM PDT 24
Finished Mar 21 03:29:25 PM PDT 24
Peak memory 241896 kb
Host smart-7c37e916-3358-48d7-b10a-159bd3725581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897411152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_check_fail.3897411152
Directory /workspace/44.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_errs.2150416293
Short name T738
Test name
Test status
Simulation time 4321485494 ps
CPU time 36.24 seconds
Started Mar 21 03:29:02 PM PDT 24
Finished Mar 21 03:29:38 PM PDT 24
Peak memory 248436 kb
Host smart-7ccba3d8-06ec-41bd-8619-3497a0d9eea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150416293 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_errs.2150416293
Directory /workspace/44.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_lock.3350157281
Short name T961
Test name
Test status
Simulation time 4267621909 ps
CPU time 23.15 seconds
Started Mar 21 03:29:04 PM PDT 24
Finished Mar 21 03:29:27 PM PDT 24
Peak memory 241408 kb
Host smart-7f29c09d-a8d9-4c4e-b31a-ceb9d674c09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350157281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_lock.3350157281
Directory /workspace/44.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/44.otp_ctrl_init_fail.3774475177
Short name T461
Test name
Test status
Simulation time 255495987 ps
CPU time 4.39 seconds
Started Mar 21 03:29:01 PM PDT 24
Finished Mar 21 03:29:05 PM PDT 24
Peak memory 241308 kb
Host smart-174e09e2-3f3c-4858-aa65-a7f97ad918e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774475177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.3774475177
Directory /workspace/44.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_macro_errs.3103775964
Short name T478
Test name
Test status
Simulation time 761666662 ps
CPU time 9.82 seconds
Started Mar 21 03:29:01 PM PDT 24
Finished Mar 21 03:29:11 PM PDT 24
Peak memory 241732 kb
Host smart-34be2fc9-234f-477c-9aa7-44237b0e00ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103775964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_macro_errs.3103775964
Directory /workspace/44.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_key_req.2038739837
Short name T973
Test name
Test status
Simulation time 5100734559 ps
CPU time 19.13 seconds
Started Mar 21 03:29:03 PM PDT 24
Finished Mar 21 03:29:22 PM PDT 24
Peak memory 242140 kb
Host smart-c3d95849-7393-4572-82b7-55688ba1a494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038739837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.2038739837
Directory /workspace/44.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_esc.3588027556
Short name T815
Test name
Test status
Simulation time 768638726 ps
CPU time 10.38 seconds
Started Mar 21 03:28:59 PM PDT 24
Finished Mar 21 03:29:10 PM PDT 24
Peak memory 241224 kb
Host smart-978629a9-6878-44e9-854b-4f00e5eab778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588027556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.3588027556
Directory /workspace/44.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_req.599734636
Short name T1071
Test name
Test status
Simulation time 1225478587 ps
CPU time 16.8 seconds
Started Mar 21 03:29:04 PM PDT 24
Finished Mar 21 03:29:21 PM PDT 24
Peak memory 241268 kb
Host smart-ed10569b-2ed5-44ff-a2f9-798d09f49ff4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=599734636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.599734636
Directory /workspace/44.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_regwen.3274321404
Short name T659
Test name
Test status
Simulation time 210239383 ps
CPU time 5.54 seconds
Started Mar 21 03:29:02 PM PDT 24
Finished Mar 21 03:29:08 PM PDT 24
Peak memory 241408 kb
Host smart-98281225-6da9-410c-b45d-b98d0f820393
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3274321404 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.3274321404
Directory /workspace/44.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/44.otp_ctrl_smoke.1898589269
Short name T492
Test name
Test status
Simulation time 3069917343 ps
CPU time 5.62 seconds
Started Mar 21 03:29:00 PM PDT 24
Finished Mar 21 03:29:06 PM PDT 24
Peak memory 241564 kb
Host smart-2fe6eb18-ee21-4b02-8d72-28bf7d091d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898589269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.1898589269
Directory /workspace/44.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all_with_rand_reset.2429218058
Short name T15
Test name
Test status
Simulation time 52558110474 ps
CPU time 1233.24 seconds
Started Mar 21 03:29:08 PM PDT 24
Finished Mar 21 03:49:41 PM PDT 24
Peak memory 340096 kb
Host smart-0c44aabe-9070-4264-b009-62c2fb535e7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429218058 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all_with_rand_reset.2429218058
Directory /workspace/44.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.otp_ctrl_test_access.181810956
Short name T774
Test name
Test status
Simulation time 8216743294 ps
CPU time 16.81 seconds
Started Mar 21 03:29:02 PM PDT 24
Finished Mar 21 03:29:19 PM PDT 24
Peak memory 242004 kb
Host smart-a9f1d8c0-4cd3-4f92-a9d3-e630911d8c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181810956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.181810956
Directory /workspace/44.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/45.otp_ctrl_alert_test.1905990682
Short name T490
Test name
Test status
Simulation time 52080175 ps
CPU time 1.79 seconds
Started Mar 21 03:29:21 PM PDT 24
Finished Mar 21 03:29:23 PM PDT 24
Peak memory 239904 kb
Host smart-10e8097b-9338-451c-bb64-3ee4980c777d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905990682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.1905990682
Directory /workspace/45.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.otp_ctrl_check_fail.4294790199
Short name T957
Test name
Test status
Simulation time 1446169393 ps
CPU time 24.52 seconds
Started Mar 21 03:29:07 PM PDT 24
Finished Mar 21 03:29:32 PM PDT 24
Peak memory 248252 kb
Host smart-23001ebb-0703-4343-a5d1-b1d2a1ed826e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294790199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.4294790199
Directory /workspace/45.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_errs.3888445677
Short name T1075
Test name
Test status
Simulation time 303438496 ps
CPU time 15.47 seconds
Started Mar 21 03:29:07 PM PDT 24
Finished Mar 21 03:29:23 PM PDT 24
Peak memory 241324 kb
Host smart-331814e2-9281-4cad-adf9-9b7502d6851e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888445677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_errs.3888445677
Directory /workspace/45.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_lock.1274628052
Short name T519
Test name
Test status
Simulation time 3909278038 ps
CPU time 39.81 seconds
Started Mar 21 03:29:02 PM PDT 24
Finished Mar 21 03:29:42 PM PDT 24
Peak memory 242204 kb
Host smart-336ac0c3-e188-4540-b703-0f5460e13b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274628052 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.1274628052
Directory /workspace/45.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/45.otp_ctrl_macro_errs.863133150
Short name T539
Test name
Test status
Simulation time 1635976984 ps
CPU time 17.18 seconds
Started Mar 21 03:29:01 PM PDT 24
Finished Mar 21 03:29:18 PM PDT 24
Peak memory 243428 kb
Host smart-53c35fe6-d001-4aff-90e3-831d9940be48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863133150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.863133150
Directory /workspace/45.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_key_req.2501643115
Short name T886
Test name
Test status
Simulation time 1249037702 ps
CPU time 22.81 seconds
Started Mar 21 03:29:02 PM PDT 24
Finished Mar 21 03:29:25 PM PDT 24
Peak memory 241680 kb
Host smart-bc9316f1-7c7b-4de1-bfc6-12439de19017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501643115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_key_req.2501643115
Directory /workspace/45.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_esc.3234478084
Short name T304
Test name
Test status
Simulation time 155473963 ps
CPU time 3.94 seconds
Started Mar 21 03:29:05 PM PDT 24
Finished Mar 21 03:29:09 PM PDT 24
Peak memory 241560 kb
Host smart-539ec239-638c-40be-881e-ee55f2b57f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234478084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.3234478084
Directory /workspace/45.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_req.2957667849
Short name T636
Test name
Test status
Simulation time 1050038197 ps
CPU time 19.24 seconds
Started Mar 21 03:29:04 PM PDT 24
Finished Mar 21 03:29:23 PM PDT 24
Peak memory 241200 kb
Host smart-3358a56a-695b-449d-b2e6-9d50d42a6f94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2957667849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.2957667849
Directory /workspace/45.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_regwen.2187733205
Short name T352
Test name
Test status
Simulation time 586880064 ps
CPU time 9.19 seconds
Started Mar 21 03:29:02 PM PDT 24
Finished Mar 21 03:29:11 PM PDT 24
Peak memory 241756 kb
Host smart-3fdc743b-7841-4fb0-9723-58f56562e3c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2187733205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.2187733205
Directory /workspace/45.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/45.otp_ctrl_smoke.3068929964
Short name T955
Test name
Test status
Simulation time 173516312 ps
CPU time 7.24 seconds
Started Mar 21 03:29:04 PM PDT 24
Finished Mar 21 03:29:11 PM PDT 24
Peak memory 241432 kb
Host smart-2bd90aca-d4ee-47a8-9c99-1a41bc87e8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068929964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_smoke.3068929964
Directory /workspace/45.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all.123043789
Short name T903
Test name
Test status
Simulation time 21500451358 ps
CPU time 277.92 seconds
Started Mar 21 03:29:02 PM PDT 24
Finished Mar 21 03:33:40 PM PDT 24
Peak memory 256664 kb
Host smart-87fff52a-2a94-43fe-90d3-e9a5a7ddbdc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123043789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all.
123043789
Directory /workspace/45.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.otp_ctrl_test_access.1793929820
Short name T1000
Test name
Test status
Simulation time 1036560656 ps
CPU time 20.88 seconds
Started Mar 21 03:29:03 PM PDT 24
Finished Mar 21 03:29:24 PM PDT 24
Peak memory 241356 kb
Host smart-5b9aadb1-f158-4e7b-9948-ef41bf9e391c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793929820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.1793929820
Directory /workspace/45.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/46.otp_ctrl_alert_test.3452721265
Short name T1119
Test name
Test status
Simulation time 99232398 ps
CPU time 1.82 seconds
Started Mar 21 03:29:20 PM PDT 24
Finished Mar 21 03:29:22 PM PDT 24
Peak memory 239888 kb
Host smart-56b2f781-def1-4314-8f19-a9f8504a8711
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452721265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.3452721265
Directory /workspace/46.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.otp_ctrl_check_fail.2001765781
Short name T61
Test name
Test status
Simulation time 8188778430 ps
CPU time 26.73 seconds
Started Mar 21 03:29:21 PM PDT 24
Finished Mar 21 03:29:47 PM PDT 24
Peak memory 248332 kb
Host smart-d4a6e1fb-9be5-41b2-b8ca-c3c421d10d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001765781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.2001765781
Directory /workspace/46.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_errs.2309844256
Short name T919
Test name
Test status
Simulation time 1621620340 ps
CPU time 22.92 seconds
Started Mar 21 03:29:21 PM PDT 24
Finished Mar 21 03:29:44 PM PDT 24
Peak memory 241684 kb
Host smart-645d108a-ad96-4397-b979-ed1eb10d0e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309844256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.2309844256
Directory /workspace/46.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_lock.2819112431
Short name T1038
Test name
Test status
Simulation time 417915619 ps
CPU time 9.16 seconds
Started Mar 21 03:29:18 PM PDT 24
Finished Mar 21 03:29:28 PM PDT 24
Peak memory 248132 kb
Host smart-6e860b95-3bd8-4680-a24a-c06f02f5b866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819112431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.2819112431
Directory /workspace/46.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/46.otp_ctrl_init_fail.358633807
Short name T231
Test name
Test status
Simulation time 194353968 ps
CPU time 4.02 seconds
Started Mar 21 03:29:22 PM PDT 24
Finished Mar 21 03:29:26 PM PDT 24
Peak memory 241372 kb
Host smart-a7617780-0e2c-4f06-b4bd-1ae46bf004b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358633807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.358633807
Directory /workspace/46.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_macro_errs.85219215
Short name T917
Test name
Test status
Simulation time 1412298568 ps
CPU time 24.13 seconds
Started Mar 21 03:29:21 PM PDT 24
Finished Mar 21 03:29:45 PM PDT 24
Peak memory 243152 kb
Host smart-022fc932-079b-4822-bbf7-561a27db8b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85219215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_macro_errs.85219215
Directory /workspace/46.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_key_req.3175727133
Short name T1116
Test name
Test status
Simulation time 437029727 ps
CPU time 17.09 seconds
Started Mar 21 03:29:16 PM PDT 24
Finished Mar 21 03:29:33 PM PDT 24
Peak memory 241680 kb
Host smart-1fd6e15a-4517-4bb5-bf1f-8c97a0ffab56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175727133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_key_req.3175727133
Directory /workspace/46.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_esc.3609731410
Short name T278
Test name
Test status
Simulation time 747472319 ps
CPU time 5.39 seconds
Started Mar 21 03:29:18 PM PDT 24
Finished Mar 21 03:29:24 PM PDT 24
Peak memory 241232 kb
Host smart-da89f6c0-9b2a-4259-9f52-e49c1e6a8699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609731410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.3609731410
Directory /workspace/46.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_req.3335900285
Short name T1156
Test name
Test status
Simulation time 689704211 ps
CPU time 11.9 seconds
Started Mar 21 03:29:22 PM PDT 24
Finished Mar 21 03:29:34 PM PDT 24
Peak memory 241272 kb
Host smart-60745799-efff-483d-b5a6-5230b43ce8e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3335900285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.3335900285
Directory /workspace/46.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_regwen.3374573160
Short name T853
Test name
Test status
Simulation time 228236862 ps
CPU time 7.21 seconds
Started Mar 21 03:29:20 PM PDT 24
Finished Mar 21 03:29:27 PM PDT 24
Peak memory 241492 kb
Host smart-24eab338-1e07-4114-ab44-21c153340e13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3374573160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.3374573160
Directory /workspace/46.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/46.otp_ctrl_smoke.695790063
Short name T416
Test name
Test status
Simulation time 699391354 ps
CPU time 6.7 seconds
Started Mar 21 03:29:19 PM PDT 24
Finished Mar 21 03:29:26 PM PDT 24
Peak memory 241300 kb
Host smart-4f093dbc-b12b-48dd-bbb6-6fdc0b9272e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695790063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_smoke.695790063
Directory /workspace/46.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all.2250988803
Short name T673
Test name
Test status
Simulation time 10704047420 ps
CPU time 19.34 seconds
Started Mar 21 03:29:23 PM PDT 24
Finished Mar 21 03:29:43 PM PDT 24
Peak memory 241076 kb
Host smart-7e7ddad7-5751-4157-8ca3-3d544278576e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250988803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all
.2250988803
Directory /workspace/46.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all_with_rand_reset.2725628916
Short name T556
Test name
Test status
Simulation time 132240587728 ps
CPU time 1756.93 seconds
Started Mar 21 03:29:17 PM PDT 24
Finished Mar 21 03:58:35 PM PDT 24
Peak memory 319328 kb
Host smart-2eab6ec9-a1b1-4060-9dc4-8b8e41e15f45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725628916 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all_with_rand_reset.2725628916
Directory /workspace/46.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.otp_ctrl_test_access.2209239917
Short name T456
Test name
Test status
Simulation time 2916866377 ps
CPU time 38.18 seconds
Started Mar 21 03:29:22 PM PDT 24
Finished Mar 21 03:30:01 PM PDT 24
Peak memory 241344 kb
Host smart-42faa10a-683d-49ee-ae73-826c5a435858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209239917 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.2209239917
Directory /workspace/46.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/47.otp_ctrl_alert_test.3914503751
Short name T18
Test name
Test status
Simulation time 190200646 ps
CPU time 2.08 seconds
Started Mar 21 03:29:23 PM PDT 24
Finished Mar 21 03:29:26 PM PDT 24
Peak memory 239840 kb
Host smart-db82e780-22bb-44dc-a81a-2046ad906a55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914503751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.3914503751
Directory /workspace/47.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_errs.3510737223
Short name T725
Test name
Test status
Simulation time 1059543705 ps
CPU time 32.23 seconds
Started Mar 21 03:29:23 PM PDT 24
Finished Mar 21 03:29:55 PM PDT 24
Peak memory 244948 kb
Host smart-9ca3d6c6-a216-434d-bb83-be6080adbdd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510737223 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_errs.3510737223
Directory /workspace/47.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_lock.4050023500
Short name T751
Test name
Test status
Simulation time 5208747976 ps
CPU time 53.44 seconds
Started Mar 21 03:29:21 PM PDT 24
Finished Mar 21 03:30:14 PM PDT 24
Peak memory 241788 kb
Host smart-c7b8bc92-fa1e-4479-9dae-2738695f6919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050023500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_lock.4050023500
Directory /workspace/47.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/47.otp_ctrl_init_fail.3072546451
Short name T1043
Test name
Test status
Simulation time 150694113 ps
CPU time 3.96 seconds
Started Mar 21 03:29:22 PM PDT 24
Finished Mar 21 03:29:26 PM PDT 24
Peak memory 241660 kb
Host smart-901b5dc8-45ec-4c1a-84fe-be662f626265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072546451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.3072546451
Directory /workspace/47.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_macro_errs.3941457607
Short name T167
Test name
Test status
Simulation time 17115320744 ps
CPU time 155.3 seconds
Started Mar 21 03:29:17 PM PDT 24
Finished Mar 21 03:31:52 PM PDT 24
Peak memory 248228 kb
Host smart-33323abf-df9e-4776-b44b-2d8f8fa3bdea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941457607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_macro_errs.3941457607
Directory /workspace/47.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_key_req.1604755567
Short name T467
Test name
Test status
Simulation time 800122826 ps
CPU time 25.87 seconds
Started Mar 21 03:29:22 PM PDT 24
Finished Mar 21 03:29:48 PM PDT 24
Peak memory 241528 kb
Host smart-bc2a582c-f6c7-4de7-85f4-e84cbaba158b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604755567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.1604755567
Directory /workspace/47.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_esc.4243251221
Short name T632
Test name
Test status
Simulation time 919487042 ps
CPU time 10.04 seconds
Started Mar 21 03:29:21 PM PDT 24
Finished Mar 21 03:29:31 PM PDT 24
Peak memory 241664 kb
Host smart-2475592f-6bf9-46a2-bcf1-15d6c840a202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243251221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.4243251221
Directory /workspace/47.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_req.1653546254
Short name T1092
Test name
Test status
Simulation time 1140484522 ps
CPU time 8.61 seconds
Started Mar 21 03:29:25 PM PDT 24
Finished Mar 21 03:29:34 PM PDT 24
Peak memory 241184 kb
Host smart-180322d5-b32c-4890-962c-a6a70cc931b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1653546254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.1653546254
Directory /workspace/47.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_regwen.2777977980
Short name T1144
Test name
Test status
Simulation time 417639710 ps
CPU time 9.55 seconds
Started Mar 21 03:29:25 PM PDT 24
Finished Mar 21 03:29:35 PM PDT 24
Peak memory 241412 kb
Host smart-93a0f9be-3dd6-4d7d-9186-ae972942ebee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2777977980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.2777977980
Directory /workspace/47.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/47.otp_ctrl_smoke.1922403673
Short name T428
Test name
Test status
Simulation time 1852434244 ps
CPU time 11.47 seconds
Started Mar 21 03:29:28 PM PDT 24
Finished Mar 21 03:29:39 PM PDT 24
Peak memory 241284 kb
Host smart-aa67a093-549d-4918-bfdc-66ebcbeb0798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922403673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_smoke.1922403673
Directory /workspace/47.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all.28815563
Short name T554
Test name
Test status
Simulation time 2078870582 ps
CPU time 20.31 seconds
Started Mar 21 03:29:24 PM PDT 24
Finished Mar 21 03:29:45 PM PDT 24
Peak memory 240964 kb
Host smart-7c69f3b2-60c5-4c3f-a353-e9739a179091
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28815563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all.28815563
Directory /workspace/47.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all_with_rand_reset.2543488216
Short name T120
Test name
Test status
Simulation time 40242788921 ps
CPU time 302.36 seconds
Started Mar 21 03:29:16 PM PDT 24
Finished Mar 21 03:34:19 PM PDT 24
Peak memory 276220 kb
Host smart-e350f5ca-56d5-493a-a2a0-a4c5fd6f1bdd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543488216 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all_with_rand_reset.2543488216
Directory /workspace/47.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.otp_ctrl_test_access.1352973990
Short name T1055
Test name
Test status
Simulation time 555998307 ps
CPU time 13.14 seconds
Started Mar 21 03:29:20 PM PDT 24
Finished Mar 21 03:29:34 PM PDT 24
Peak memory 241684 kb
Host smart-4a702ac1-3064-4108-b0b0-6d1732470f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352973990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_test_access.1352973990
Directory /workspace/47.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/48.otp_ctrl_alert_test.3503019469
Short name T187
Test name
Test status
Simulation time 42537461 ps
CPU time 1.62 seconds
Started Mar 21 03:29:21 PM PDT 24
Finished Mar 21 03:29:22 PM PDT 24
Peak memory 239904 kb
Host smart-fb2b5e71-fe15-445a-8975-3b98e7583959
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503019469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.3503019469
Directory /workspace/48.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.otp_ctrl_check_fail.3240739834
Short name T51
Test name
Test status
Simulation time 1422994567 ps
CPU time 17.87 seconds
Started Mar 21 03:29:20 PM PDT 24
Finished Mar 21 03:29:38 PM PDT 24
Peak memory 241744 kb
Host smart-842ed052-c7d2-4dec-a65a-97e43f9aebd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240739834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.3240739834
Directory /workspace/48.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_errs.4260814350
Short name T171
Test name
Test status
Simulation time 2898787436 ps
CPU time 43.24 seconds
Started Mar 21 03:29:17 PM PDT 24
Finished Mar 21 03:30:00 PM PDT 24
Peak memory 252440 kb
Host smart-327c2449-4d83-4335-b0e8-8977dccf1915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260814350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.4260814350
Directory /workspace/48.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_lock.1063928084
Short name T858
Test name
Test status
Simulation time 2380567292 ps
CPU time 23.02 seconds
Started Mar 21 03:29:21 PM PDT 24
Finished Mar 21 03:29:44 PM PDT 24
Peak memory 241824 kb
Host smart-87eb0e54-081f-47ee-8ee8-c8761328da30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063928084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.1063928084
Directory /workspace/48.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/48.otp_ctrl_init_fail.2310426654
Short name T769
Test name
Test status
Simulation time 1599563883 ps
CPU time 5.12 seconds
Started Mar 21 03:29:22 PM PDT 24
Finished Mar 21 03:29:27 PM PDT 24
Peak memory 241236 kb
Host smart-f125ac57-f2e7-4603-ae5e-907eeeec7ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310426654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.2310426654
Directory /workspace/48.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_macro_errs.2839013700
Short name T217
Test name
Test status
Simulation time 4505202788 ps
CPU time 19.57 seconds
Started Mar 21 03:29:19 PM PDT 24
Finished Mar 21 03:29:39 PM PDT 24
Peak memory 244972 kb
Host smart-db6ab078-5837-40e9-a7f3-b17a87b1e280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839013700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_macro_errs.2839013700
Directory /workspace/48.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_key_req.4070573907
Short name T937
Test name
Test status
Simulation time 1302362590 ps
CPU time 22.45 seconds
Started Mar 21 03:29:18 PM PDT 24
Finished Mar 21 03:29:41 PM PDT 24
Peak memory 241328 kb
Host smart-dc823587-e5d7-4347-b8f3-fa64a569eb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070573907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_key_req.4070573907
Directory /workspace/48.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_esc.1624757115
Short name T1153
Test name
Test status
Simulation time 6951579226 ps
CPU time 16.33 seconds
Started Mar 21 03:29:21 PM PDT 24
Finished Mar 21 03:29:37 PM PDT 24
Peak memory 241720 kb
Host smart-db1a60b8-cc84-4287-a2ee-b1748f0479e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624757115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.1624757115
Directory /workspace/48.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_req.3051194668
Short name T1014
Test name
Test status
Simulation time 1380363618 ps
CPU time 11.34 seconds
Started Mar 21 03:29:18 PM PDT 24
Finished Mar 21 03:29:30 PM PDT 24
Peak memory 241540 kb
Host smart-cf20af04-a027-443f-ba55-a4fed3f6af6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3051194668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.3051194668
Directory /workspace/48.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_regwen.350979779
Short name T388
Test name
Test status
Simulation time 82818041 ps
CPU time 3.12 seconds
Started Mar 21 03:29:23 PM PDT 24
Finished Mar 21 03:29:26 PM PDT 24
Peak memory 241288 kb
Host smart-76a4959f-f3df-4fbb-9c68-ad22c882d156
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=350979779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.350979779
Directory /workspace/48.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/48.otp_ctrl_smoke.3620697156
Short name T787
Test name
Test status
Simulation time 1684385538 ps
CPU time 4.4 seconds
Started Mar 21 03:29:28 PM PDT 24
Finished Mar 21 03:29:32 PM PDT 24
Peak memory 241640 kb
Host smart-06160bbf-effc-4174-81f3-2b72de74fafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620697156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_smoke.3620697156
Directory /workspace/48.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all.1214505407
Short name T271
Test name
Test status
Simulation time 4347509931 ps
CPU time 96.46 seconds
Started Mar 21 03:29:23 PM PDT 24
Finished Mar 21 03:31:00 PM PDT 24
Peak memory 248652 kb
Host smart-1f3c4641-9bb6-4a78-8d68-5bcd82728f6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214505407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all
.1214505407
Directory /workspace/48.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all_with_rand_reset.1403340521
Short name T926
Test name
Test status
Simulation time 1251305805983 ps
CPU time 5546.94 seconds
Started Mar 21 03:29:20 PM PDT 24
Finished Mar 21 05:01:47 PM PDT 24
Peak memory 383080 kb
Host smart-0f465ee9-4542-468c-8f7e-22ee987d4105
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403340521 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all_with_rand_reset.1403340521
Directory /workspace/48.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.otp_ctrl_test_access.1484989577
Short name T609
Test name
Test status
Simulation time 941982566 ps
CPU time 19.02 seconds
Started Mar 21 03:29:22 PM PDT 24
Finished Mar 21 03:29:41 PM PDT 24
Peak memory 241668 kb
Host smart-7a434780-cfa1-4b20-963a-91fbceb46ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484989577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_test_access.1484989577
Directory /workspace/48.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/49.otp_ctrl_alert_test.1583967767
Short name T885
Test name
Test status
Simulation time 723161525 ps
CPU time 2.35 seconds
Started Mar 21 03:29:25 PM PDT 24
Finished Mar 21 03:29:27 PM PDT 24
Peak memory 238960 kb
Host smart-d4a10895-32a2-46c3-9dd8-a37f7e4d85e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583967767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.1583967767
Directory /workspace/49.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_errs.3175975744
Short name T560
Test name
Test status
Simulation time 387331585 ps
CPU time 16.96 seconds
Started Mar 21 03:29:25 PM PDT 24
Finished Mar 21 03:29:43 PM PDT 24
Peak memory 241528 kb
Host smart-0d721daa-b626-4aaf-af47-ef13cb8f49b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175975744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_errs.3175975744
Directory /workspace/49.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_lock.1047729873
Short name T1183
Test name
Test status
Simulation time 695538492 ps
CPU time 14.35 seconds
Started Mar 21 03:29:21 PM PDT 24
Finished Mar 21 03:29:36 PM PDT 24
Peak memory 241724 kb
Host smart-c442ee9f-dc92-434e-b542-5429c74045aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047729873 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_lock.1047729873
Directory /workspace/49.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/49.otp_ctrl_init_fail.1776314093
Short name T829
Test name
Test status
Simulation time 163598467 ps
CPU time 3.63 seconds
Started Mar 21 03:29:18 PM PDT 24
Finished Mar 21 03:29:22 PM PDT 24
Peak memory 241644 kb
Host smart-d20becd2-d2e1-499b-8e45-8980dcc5ba72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776314093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.1776314093
Directory /workspace/49.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_macro_errs.1646059367
Short name T515
Test name
Test status
Simulation time 866922945 ps
CPU time 20.29 seconds
Started Mar 21 03:29:23 PM PDT 24
Finished Mar 21 03:29:43 PM PDT 24
Peak memory 241916 kb
Host smart-b37bae1d-3c1c-44fb-8f22-a78716a8ce62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646059367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_macro_errs.1646059367
Directory /workspace/49.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_key_req.4287753612
Short name T1120
Test name
Test status
Simulation time 1747243430 ps
CPU time 20.01 seconds
Started Mar 21 03:29:19 PM PDT 24
Finished Mar 21 03:29:39 PM PDT 24
Peak memory 242068 kb
Host smart-4ddbd5a3-eb42-48c1-a88e-78404b25d65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287753612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.4287753612
Directory /workspace/49.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_esc.2465724142
Short name T3
Test name
Test status
Simulation time 1684055409 ps
CPU time 3.4 seconds
Started Mar 21 03:29:19 PM PDT 24
Finished Mar 21 03:29:22 PM PDT 24
Peak memory 241312 kb
Host smart-17f9f90a-6f57-443c-8bcf-e84b752b3955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465724142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.2465724142
Directory /workspace/49.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_req.2428758123
Short name T683
Test name
Test status
Simulation time 667385842 ps
CPU time 10.27 seconds
Started Mar 21 03:29:18 PM PDT 24
Finished Mar 21 03:29:29 PM PDT 24
Peak memory 241144 kb
Host smart-19b849c9-a9eb-402e-9a2c-190f429a50ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2428758123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_req.2428758123
Directory /workspace/49.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_regwen.3143391475
Short name T988
Test name
Test status
Simulation time 282602512 ps
CPU time 8.49 seconds
Started Mar 21 03:29:21 PM PDT 24
Finished Mar 21 03:29:30 PM PDT 24
Peak memory 241440 kb
Host smart-e9aa3f0b-d028-4c40-a60e-d4757a25c5cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3143391475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.3143391475
Directory /workspace/49.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/49.otp_ctrl_smoke.2799270703
Short name T252
Test name
Test status
Simulation time 613444345 ps
CPU time 7.01 seconds
Started Mar 21 03:29:18 PM PDT 24
Finished Mar 21 03:29:25 PM PDT 24
Peak memory 241264 kb
Host smart-da94d27e-f44b-45a9-a404-f54ba1301307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799270703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.2799270703
Directory /workspace/49.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all.1644252371
Short name T846
Test name
Test status
Simulation time 10125682741 ps
CPU time 150.53 seconds
Started Mar 21 03:29:28 PM PDT 24
Finished Mar 21 03:31:59 PM PDT 24
Peak memory 256548 kb
Host smart-2f70ba5d-91fa-4001-b2b7-b99e3c9635fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644252371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all
.1644252371
Directory /workspace/49.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all_with_rand_reset.2900167406
Short name T298
Test name
Test status
Simulation time 61601291344 ps
CPU time 484.46 seconds
Started Mar 21 03:29:20 PM PDT 24
Finished Mar 21 03:37:25 PM PDT 24
Peak memory 257184 kb
Host smart-e6de2847-ad55-4ad3-996d-2862123cbbc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900167406 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all_with_rand_reset.2900167406
Directory /workspace/49.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.otp_ctrl_test_access.3418011174
Short name T568
Test name
Test status
Simulation time 1072335834 ps
CPU time 7.79 seconds
Started Mar 21 03:29:22 PM PDT 24
Finished Mar 21 03:29:29 PM PDT 24
Peak memory 241688 kb
Host smart-e79dbf88-9eeb-499b-a3c5-02158d357a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418011174 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_test_access.3418011174
Directory /workspace/49.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/5.otp_ctrl_alert_test.1869167253
Short name T236
Test name
Test status
Simulation time 181138949 ps
CPU time 1.73 seconds
Started Mar 21 03:27:12 PM PDT 24
Finished Mar 21 03:27:14 PM PDT 24
Peak memory 240148 kb
Host smart-5013bdc4-1dcf-49f7-9144-25d934944c8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869167253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.1869167253
Directory /workspace/5.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.otp_ctrl_background_chks.822000127
Short name T750
Test name
Test status
Simulation time 834544693 ps
CPU time 20.08 seconds
Started Mar 21 03:27:12 PM PDT 24
Finished Mar 21 03:27:32 PM PDT 24
Peak memory 241744 kb
Host smart-75d1a9be-5f9f-442d-854e-c00c31f29c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822000127 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.822000127
Directory /workspace/5.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/5.otp_ctrl_check_fail.2483369659
Short name T1018
Test name
Test status
Simulation time 5601291710 ps
CPU time 11.12 seconds
Started Mar 21 03:27:11 PM PDT 24
Finished Mar 21 03:27:23 PM PDT 24
Peak memory 248320 kb
Host smart-ac354b3c-2244-4936-b033-06905fe7b8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483369659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.2483369659
Directory /workspace/5.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_errs.523809463
Short name T585
Test name
Test status
Simulation time 681904654 ps
CPU time 18.77 seconds
Started Mar 21 03:27:12 PM PDT 24
Finished Mar 21 03:27:31 PM PDT 24
Peak memory 241744 kb
Host smart-de247684-f599-41ea-8607-e7d37abd8f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523809463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.523809463
Directory /workspace/5.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_lock.3367535706
Short name T901
Test name
Test status
Simulation time 969151745 ps
CPU time 19.23 seconds
Started Mar 21 03:27:10 PM PDT 24
Finished Mar 21 03:27:29 PM PDT 24
Peak memory 241436 kb
Host smart-f890cec7-cff1-4f35-bd09-8f465cda1886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367535706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.3367535706
Directory /workspace/5.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/5.otp_ctrl_init_fail.3696043259
Short name T1056
Test name
Test status
Simulation time 2215212657 ps
CPU time 6.71 seconds
Started Mar 21 03:27:11 PM PDT 24
Finished Mar 21 03:27:18 PM PDT 24
Peak memory 241492 kb
Host smart-cf03a1fd-2834-4db4-8fba-75e01b2c9c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696043259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.3696043259
Directory /workspace/5.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_macro_errs.3698557236
Short name T863
Test name
Test status
Simulation time 4338598124 ps
CPU time 9.64 seconds
Started Mar 21 03:27:16 PM PDT 24
Finished Mar 21 03:27:26 PM PDT 24
Peak memory 241520 kb
Host smart-f2df4aa3-a33d-4331-9c27-b069b1b304d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698557236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.3698557236
Directory /workspace/5.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_key_req.3294937835
Short name T6
Test name
Test status
Simulation time 3389735053 ps
CPU time 7.83 seconds
Started Mar 21 03:27:11 PM PDT 24
Finished Mar 21 03:27:19 PM PDT 24
Peak memory 242220 kb
Host smart-1e5445cb-40d6-4560-89fa-7cc3d69956af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294937835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.3294937835
Directory /workspace/5.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_esc.4144932995
Short name T1165
Test name
Test status
Simulation time 231303029 ps
CPU time 11.71 seconds
Started Mar 21 03:27:13 PM PDT 24
Finished Mar 21 03:27:24 PM PDT 24
Peak memory 241700 kb
Host smart-3df3b3a1-21d9-4b4c-8bd7-bc67da1220a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144932995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.4144932995
Directory /workspace/5.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_req.3336674045
Short name T571
Test name
Test status
Simulation time 1341367066 ps
CPU time 19.89 seconds
Started Mar 21 03:27:12 PM PDT 24
Finished Mar 21 03:27:32 PM PDT 24
Peak memory 241632 kb
Host smart-cdbd2e21-fa03-40db-ba90-82c12400e0f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3336674045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.3336674045
Directory /workspace/5.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_regwen.326273635
Short name T771
Test name
Test status
Simulation time 317686610 ps
CPU time 9.36 seconds
Started Mar 21 03:27:11 PM PDT 24
Finished Mar 21 03:27:20 PM PDT 24
Peak memory 241680 kb
Host smart-3bb83687-d50d-49cc-8b94-2b5f00d01255
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=326273635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.326273635
Directory /workspace/5.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/5.otp_ctrl_smoke.4119235211
Short name T784
Test name
Test status
Simulation time 406882178 ps
CPU time 7.31 seconds
Started Mar 21 03:27:12 PM PDT 24
Finished Mar 21 03:27:19 PM PDT 24
Peak memory 241356 kb
Host smart-6366610c-cbe5-4086-a862-974af1c1e5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119235211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.4119235211
Directory /workspace/5.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all.2760833044
Short name T559
Test name
Test status
Simulation time 12547021775 ps
CPU time 72.03 seconds
Started Mar 21 03:27:13 PM PDT 24
Finished Mar 21 03:28:26 PM PDT 24
Peak memory 244512 kb
Host smart-6da3bc7e-de1a-44f8-b7f8-754a570597bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760833044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all.
2760833044
Directory /workspace/5.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all_with_rand_reset.2321653337
Short name T153
Test name
Test status
Simulation time 96684634953 ps
CPU time 1735.08 seconds
Started Mar 21 03:27:11 PM PDT 24
Finished Mar 21 03:56:07 PM PDT 24
Peak memory 526072 kb
Host smart-a46741d0-655c-41a2-877b-2f123d445c7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321653337 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all_with_rand_reset.2321653337
Directory /workspace/5.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.otp_ctrl_test_access.2948946176
Short name T606
Test name
Test status
Simulation time 2871104579 ps
CPU time 29.85 seconds
Started Mar 21 03:27:12 PM PDT 24
Finished Mar 21 03:27:42 PM PDT 24
Peak memory 241940 kb
Host smart-7fa955ac-62cd-445f-82e9-be49be1a4b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948946176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.2948946176
Directory /workspace/5.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/50.otp_ctrl_init_fail.2147859360
Short name T686
Test name
Test status
Simulation time 104455603 ps
CPU time 4.23 seconds
Started Mar 21 03:29:24 PM PDT 24
Finished Mar 21 03:29:28 PM PDT 24
Peak memory 241540 kb
Host smart-94ced4b7-740e-4be5-944b-6ec078da9a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147859360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.2147859360
Directory /workspace/50.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/50.otp_ctrl_parallel_lc_esc.49525265
Short name T718
Test name
Test status
Simulation time 588876180 ps
CPU time 18.92 seconds
Started Mar 21 03:29:18 PM PDT 24
Finished Mar 21 03:29:37 PM PDT 24
Peak memory 241208 kb
Host smart-762134ca-7e4f-4cc5-b122-efba71480747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49525265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.49525265
Directory /workspace/50.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/50.otp_ctrl_stress_all_with_rand_reset.394321149
Short name T247
Test name
Test status
Simulation time 81841296552 ps
CPU time 438.33 seconds
Started Mar 21 03:29:20 PM PDT 24
Finished Mar 21 03:36:38 PM PDT 24
Peak memory 266048 kb
Host smart-ac26c535-30d0-4f2f-9c3e-2a5e31229b95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394321149 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_stress_all_with_rand_reset.394321149
Directory /workspace/50.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.otp_ctrl_init_fail.57601391
Short name T45
Test name
Test status
Simulation time 2946023524 ps
CPU time 6.13 seconds
Started Mar 21 03:29:22 PM PDT 24
Finished Mar 21 03:29:28 PM PDT 24
Peak memory 241536 kb
Host smart-eaf2eaee-e82f-4f23-b9d3-80c2626ec5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57601391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.57601391
Directory /workspace/51.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/51.otp_ctrl_parallel_lc_esc.4255646757
Short name T888
Test name
Test status
Simulation time 5603540352 ps
CPU time 24.79 seconds
Started Mar 21 03:29:20 PM PDT 24
Finished Mar 21 03:29:45 PM PDT 24
Peak memory 241680 kb
Host smart-064085aa-547d-4657-a9f7-d9fac2f30358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255646757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.4255646757
Directory /workspace/51.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/51.otp_ctrl_stress_all_with_rand_reset.3199428378
Short name T722
Test name
Test status
Simulation time 618651013644 ps
CPU time 1538.38 seconds
Started Mar 21 03:29:19 PM PDT 24
Finished Mar 21 03:54:57 PM PDT 24
Peak memory 314008 kb
Host smart-98ddb4cb-929d-4f1f-82b8-fcc39a68e8c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199428378 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_stress_all_with_rand_reset.3199428378
Directory /workspace/51.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.otp_ctrl_init_fail.3346565127
Short name T987
Test name
Test status
Simulation time 146858925 ps
CPU time 4.54 seconds
Started Mar 21 03:29:24 PM PDT 24
Finished Mar 21 03:29:28 PM PDT 24
Peak memory 241396 kb
Host smart-8d1f9193-ed5d-4057-bf74-2172515cbc90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346565127 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.3346565127
Directory /workspace/52.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/52.otp_ctrl_parallel_lc_esc.1705752371
Short name T265
Test name
Test status
Simulation time 234185047 ps
CPU time 10.56 seconds
Started Mar 21 03:29:25 PM PDT 24
Finished Mar 21 03:29:36 PM PDT 24
Peak memory 241080 kb
Host smart-970d1cfb-a368-46b8-bd1a-13089095e812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705752371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.1705752371
Directory /workspace/52.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/52.otp_ctrl_stress_all_with_rand_reset.744742082
Short name T1181
Test name
Test status
Simulation time 197180173488 ps
CPU time 487.15 seconds
Started Mar 21 03:29:20 PM PDT 24
Finished Mar 21 03:37:27 PM PDT 24
Peak memory 341488 kb
Host smart-98e6654e-3b4b-4c14-9c75-a5c0844da745
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744742082 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_stress_all_with_rand_reset.744742082
Directory /workspace/52.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.otp_ctrl_init_fail.354465137
Short name T1133
Test name
Test status
Simulation time 128894730 ps
CPU time 4.3 seconds
Started Mar 21 03:29:23 PM PDT 24
Finished Mar 21 03:29:28 PM PDT 24
Peak memory 241336 kb
Host smart-b936c646-c3cd-4cbd-8b50-36f332946b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354465137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.354465137
Directory /workspace/53.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/53.otp_ctrl_parallel_lc_esc.4018662466
Short name T794
Test name
Test status
Simulation time 268844657 ps
CPU time 7.58 seconds
Started Mar 21 03:29:21 PM PDT 24
Finished Mar 21 03:29:28 PM PDT 24
Peak memory 241340 kb
Host smart-489a563f-c1d8-4ff7-b82a-b5dc5568f769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018662466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.4018662466
Directory /workspace/53.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/53.otp_ctrl_stress_all_with_rand_reset.4103647923
Short name T308
Test name
Test status
Simulation time 1358874495463 ps
CPU time 2111.04 seconds
Started Mar 21 03:29:25 PM PDT 24
Finished Mar 21 04:04:36 PM PDT 24
Peak memory 565364 kb
Host smart-36cb4092-7416-49c9-a96f-1b995e10c1ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103647923 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_stress_all_with_rand_reset.4103647923
Directory /workspace/53.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.otp_ctrl_init_fail.3660062428
Short name T454
Test name
Test status
Simulation time 163308068 ps
CPU time 4.49 seconds
Started Mar 21 03:29:28 PM PDT 24
Finished Mar 21 03:29:32 PM PDT 24
Peak memory 241388 kb
Host smart-7e2a0eef-1476-4e92-b928-73a65bfcd7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660062428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.3660062428
Directory /workspace/54.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/54.otp_ctrl_parallel_lc_esc.3304598294
Short name T601
Test name
Test status
Simulation time 548840793 ps
CPU time 3.96 seconds
Started Mar 21 03:29:23 PM PDT 24
Finished Mar 21 03:29:27 PM PDT 24
Peak memory 241604 kb
Host smart-bd5f7e7d-31ab-48d9-a7c9-1ae3cf06bde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304598294 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.3304598294
Directory /workspace/54.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/55.otp_ctrl_init_fail.2482225666
Short name T448
Test name
Test status
Simulation time 96699145 ps
CPU time 3.81 seconds
Started Mar 21 03:29:23 PM PDT 24
Finished Mar 21 03:29:27 PM PDT 24
Peak memory 241388 kb
Host smart-fff8631e-bd44-4882-9b41-b4b4ab5bf688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482225666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.2482225666
Directory /workspace/55.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/55.otp_ctrl_parallel_lc_esc.3373314095
Short name T898
Test name
Test status
Simulation time 6142146088 ps
CPU time 18.26 seconds
Started Mar 21 03:29:22 PM PDT 24
Finished Mar 21 03:29:40 PM PDT 24
Peak memory 241344 kb
Host smart-80a5ed32-a647-413f-89a3-96290b24d385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373314095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.3373314095
Directory /workspace/55.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/55.otp_ctrl_stress_all_with_rand_reset.73677198
Short name T480
Test name
Test status
Simulation time 17119335087 ps
CPU time 457.11 seconds
Started Mar 21 03:29:22 PM PDT 24
Finished Mar 21 03:36:59 PM PDT 24
Peak memory 321256 kb
Host smart-b136db54-acf1-4974-a9fc-c80db1818a38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73677198 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_stress_all_with_rand_reset.73677198
Directory /workspace/55.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.otp_ctrl_init_fail.1607148819
Short name T329
Test name
Test status
Simulation time 252277069 ps
CPU time 3.63 seconds
Started Mar 21 03:29:18 PM PDT 24
Finished Mar 21 03:29:22 PM PDT 24
Peak memory 241400 kb
Host smart-2a825573-414a-48a7-9661-c0551a491a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607148819 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.1607148819
Directory /workspace/56.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/56.otp_ctrl_parallel_lc_esc.154857486
Short name T1020
Test name
Test status
Simulation time 953663670 ps
CPU time 18.05 seconds
Started Mar 21 03:29:23 PM PDT 24
Finished Mar 21 03:29:41 PM PDT 24
Peak memory 241332 kb
Host smart-accfb4ee-e786-49f1-ab24-79858f28eae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154857486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.154857486
Directory /workspace/56.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/56.otp_ctrl_stress_all_with_rand_reset.1161799337
Short name T902
Test name
Test status
Simulation time 484222360182 ps
CPU time 1476.08 seconds
Started Mar 21 03:29:23 PM PDT 24
Finished Mar 21 03:53:59 PM PDT 24
Peak memory 411224 kb
Host smart-b42867b9-1267-4519-a4ed-b1cfbd265e49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161799337 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_stress_all_with_rand_reset.1161799337
Directory /workspace/56.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.otp_ctrl_init_fail.4113369616
Short name T664
Test name
Test status
Simulation time 239205694 ps
CPU time 3.94 seconds
Started Mar 21 03:29:40 PM PDT 24
Finished Mar 21 03:29:44 PM PDT 24
Peak memory 241612 kb
Host smart-02490c80-0521-4535-949d-b6f1ebb2d23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113369616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.4113369616
Directory /workspace/57.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/57.otp_ctrl_parallel_lc_esc.2688182242
Short name T156
Test name
Test status
Simulation time 484272434 ps
CPU time 7.52 seconds
Started Mar 21 03:29:41 PM PDT 24
Finished Mar 21 03:29:49 PM PDT 24
Peak memory 241396 kb
Host smart-b80afed7-6ea5-492a-abff-eb653f11af6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688182242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.2688182242
Directory /workspace/57.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/57.otp_ctrl_stress_all_with_rand_reset.3696922678
Short name T1067
Test name
Test status
Simulation time 1156535432408 ps
CPU time 2966.35 seconds
Started Mar 21 03:29:38 PM PDT 24
Finished Mar 21 04:19:05 PM PDT 24
Peak memory 315692 kb
Host smart-3ca187dc-633b-495e-85b2-89e07d4efd27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696922678 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_stress_all_with_rand_reset.3696922678
Directory /workspace/57.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.otp_ctrl_init_fail.3569284369
Short name T453
Test name
Test status
Simulation time 144663722 ps
CPU time 3.74 seconds
Started Mar 21 03:29:43 PM PDT 24
Finished Mar 21 03:29:47 PM PDT 24
Peak memory 241360 kb
Host smart-0ddc4b9b-fa32-4e2c-b815-575e0fc7ad93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569284369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.3569284369
Directory /workspace/58.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/58.otp_ctrl_parallel_lc_esc.2766682349
Short name T796
Test name
Test status
Simulation time 511591321 ps
CPU time 12.17 seconds
Started Mar 21 03:29:40 PM PDT 24
Finished Mar 21 03:29:52 PM PDT 24
Peak memory 241208 kb
Host smart-dda17195-0544-48db-abaf-effa4616165a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766682349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.2766682349
Directory /workspace/58.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/58.otp_ctrl_stress_all_with_rand_reset.552216840
Short name T1172
Test name
Test status
Simulation time 52692732665 ps
CPU time 1426.32 seconds
Started Mar 21 03:29:42 PM PDT 24
Finished Mar 21 03:53:29 PM PDT 24
Peak memory 463672 kb
Host smart-e85c1a3c-2428-4c05-b79a-1f9e135d50df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552216840 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_stress_all_with_rand_reset.552216840
Directory /workspace/58.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.otp_ctrl_init_fail.2500876966
Short name T583
Test name
Test status
Simulation time 1567997784 ps
CPU time 4.77 seconds
Started Mar 21 03:29:41 PM PDT 24
Finished Mar 21 03:29:46 PM PDT 24
Peak memory 241672 kb
Host smart-838de3d0-a227-4125-bd7a-28e8f5f22306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500876966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.2500876966
Directory /workspace/59.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/59.otp_ctrl_parallel_lc_esc.608535895
Short name T1086
Test name
Test status
Simulation time 3884914268 ps
CPU time 37.18 seconds
Started Mar 21 03:29:44 PM PDT 24
Finished Mar 21 03:30:21 PM PDT 24
Peak memory 241324 kb
Host smart-c5ddfb97-13f2-4f45-826f-4ea03d653504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608535895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.608535895
Directory /workspace/59.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/59.otp_ctrl_stress_all_with_rand_reset.4228456026
Short name T635
Test name
Test status
Simulation time 485433714605 ps
CPU time 905.9 seconds
Started Mar 21 03:29:40 PM PDT 24
Finished Mar 21 03:44:46 PM PDT 24
Peak memory 264900 kb
Host smart-116582e5-2e81-4136-8ab3-bfc8a13670f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228456026 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_stress_all_with_rand_reset.4228456026
Directory /workspace/59.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.otp_ctrl_alert_test.638798195
Short name T1082
Test name
Test status
Simulation time 710718648 ps
CPU time 2.25 seconds
Started Mar 21 03:27:13 PM PDT 24
Finished Mar 21 03:27:15 PM PDT 24
Peak memory 240028 kb
Host smart-409a3684-6793-4e24-a8ee-104eb106a9ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638798195 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.638798195
Directory /workspace/6.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.otp_ctrl_background_chks.3148044856
Short name T1011
Test name
Test status
Simulation time 3301602184 ps
CPU time 31.6 seconds
Started Mar 21 03:27:17 PM PDT 24
Finished Mar 21 03:27:49 PM PDT 24
Peak memory 242536 kb
Host smart-f7b8ef4d-ab8e-469d-a592-764c444b189b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148044856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.3148044856
Directory /workspace/6.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/6.otp_ctrl_check_fail.3472782703
Short name T126
Test name
Test status
Simulation time 2782518034 ps
CPU time 27.27 seconds
Started Mar 21 03:27:11 PM PDT 24
Finished Mar 21 03:27:39 PM PDT 24
Peak memory 242824 kb
Host smart-d62438fb-cc01-4b34-a19c-1348b2a3bea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472782703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.3472782703
Directory /workspace/6.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_errs.1832321211
Short name T1111
Test name
Test status
Simulation time 799836727 ps
CPU time 23.77 seconds
Started Mar 21 03:27:11 PM PDT 24
Finished Mar 21 03:27:35 PM PDT 24
Peak memory 241644 kb
Host smart-6c5afe7a-fb22-4218-96d2-74284687c72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832321211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.1832321211
Directory /workspace/6.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_lock.3164330737
Short name T818
Test name
Test status
Simulation time 918838307 ps
CPU time 20.89 seconds
Started Mar 21 03:27:14 PM PDT 24
Finished Mar 21 03:27:35 PM PDT 24
Peak memory 241684 kb
Host smart-814090c0-6847-410d-9f0e-f1585442dc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164330737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.3164330737
Directory /workspace/6.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/6.otp_ctrl_init_fail.628419766
Short name T557
Test name
Test status
Simulation time 270283512 ps
CPU time 4.98 seconds
Started Mar 21 03:27:15 PM PDT 24
Finished Mar 21 03:27:20 PM PDT 24
Peak memory 241676 kb
Host smart-7afaed9c-690e-4ded-a931-c4a58d0a4c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628419766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.628419766
Directory /workspace/6.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_macro_errs.3292878561
Short name T599
Test name
Test status
Simulation time 1506093314 ps
CPU time 13.02 seconds
Started Mar 21 03:27:15 PM PDT 24
Finished Mar 21 03:27:28 PM PDT 24
Peak memory 241532 kb
Host smart-bf61468a-83a7-4716-a085-a3cea1483003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292878561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.3292878561
Directory /workspace/6.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_key_req.868536913
Short name T576
Test name
Test status
Simulation time 1367973037 ps
CPU time 34.99 seconds
Started Mar 21 03:27:09 PM PDT 24
Finished Mar 21 03:27:44 PM PDT 24
Peak memory 241824 kb
Host smart-ea900259-ba6b-421b-a14d-f1d102724113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868536913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.868536913
Directory /workspace/6.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_esc.1355335505
Short name T127
Test name
Test status
Simulation time 727117124 ps
CPU time 23.61 seconds
Started Mar 21 03:27:13 PM PDT 24
Finished Mar 21 03:27:37 PM PDT 24
Peak memory 241392 kb
Host smart-a2c3c7d8-0085-40e6-a6e6-23672060578e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355335505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.1355335505
Directory /workspace/6.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_req.735442736
Short name T1051
Test name
Test status
Simulation time 1079033076 ps
CPU time 16.44 seconds
Started Mar 21 03:27:11 PM PDT 24
Finished Mar 21 03:27:28 PM PDT 24
Peak memory 241604 kb
Host smart-ca592df9-a58a-4e75-9ea6-8ce402b58ef3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=735442736 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.735442736
Directory /workspace/6.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_regwen.988062751
Short name T663
Test name
Test status
Simulation time 538440812 ps
CPU time 4.74 seconds
Started Mar 21 03:27:13 PM PDT 24
Finished Mar 21 03:27:18 PM PDT 24
Peak memory 241572 kb
Host smart-f669ea9e-20cd-4f33-a0ca-6c35764f3eb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=988062751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.988062751
Directory /workspace/6.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/6.otp_ctrl_smoke.2209660307
Short name T770
Test name
Test status
Simulation time 3527307760 ps
CPU time 22.11 seconds
Started Mar 21 03:27:12 PM PDT 24
Finished Mar 21 03:27:34 PM PDT 24
Peak memory 241352 kb
Host smart-1bba5f8b-9c60-4a9b-a464-cfb837a48d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209660307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.2209660307
Directory /workspace/6.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all.3444106273
Short name T142
Test name
Test status
Simulation time 26368226567 ps
CPU time 286.06 seconds
Started Mar 21 03:27:12 PM PDT 24
Finished Mar 21 03:31:59 PM PDT 24
Peak memory 282476 kb
Host smart-53659187-7fae-4bf2-83cf-51dc3a876d81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444106273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all.
3444106273
Directory /workspace/6.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all_with_rand_reset.3632349032
Short name T682
Test name
Test status
Simulation time 270064340668 ps
CPU time 656.68 seconds
Started Mar 21 03:27:13 PM PDT 24
Finished Mar 21 03:38:10 PM PDT 24
Peak memory 279584 kb
Host smart-944097d3-47ae-4942-82b1-65eae7ccaacd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632349032 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all_with_rand_reset.3632349032
Directory /workspace/6.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.otp_ctrl_test_access.1122738077
Short name T407
Test name
Test status
Simulation time 1015049487 ps
CPU time 10.01 seconds
Started Mar 21 03:27:11 PM PDT 24
Finished Mar 21 03:27:21 PM PDT 24
Peak memory 241780 kb
Host smart-136bcebc-7cbb-4ce8-822d-45118a938b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122738077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.1122738077
Directory /workspace/6.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/60.otp_ctrl_init_fail.942473946
Short name T139
Test name
Test status
Simulation time 243498311 ps
CPU time 4.36 seconds
Started Mar 21 03:29:42 PM PDT 24
Finished Mar 21 03:29:47 PM PDT 24
Peak memory 241596 kb
Host smart-b2a45eeb-dadc-4261-b41a-963c4f98accd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942473946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.942473946
Directory /workspace/60.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/60.otp_ctrl_parallel_lc_esc.4074942288
Short name T1006
Test name
Test status
Simulation time 424577799 ps
CPU time 7.76 seconds
Started Mar 21 03:29:39 PM PDT 24
Finished Mar 21 03:29:47 PM PDT 24
Peak memory 241320 kb
Host smart-b5106d51-3af0-4713-b56d-1a4fab683626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074942288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.4074942288
Directory /workspace/60.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/60.otp_ctrl_stress_all_with_rand_reset.481025247
Short name T316
Test name
Test status
Simulation time 56978303672 ps
CPU time 476.27 seconds
Started Mar 21 03:29:42 PM PDT 24
Finished Mar 21 03:37:38 PM PDT 24
Peak memory 278652 kb
Host smart-f66a769e-9ce5-471a-8a79-a0318d7e7c7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481025247 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_stress_all_with_rand_reset.481025247
Directory /workspace/60.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.otp_ctrl_init_fail.881798254
Short name T736
Test name
Test status
Simulation time 2413417432 ps
CPU time 5.35 seconds
Started Mar 21 03:29:40 PM PDT 24
Finished Mar 21 03:29:46 PM PDT 24
Peak memory 241512 kb
Host smart-8f6fe479-9274-432e-a064-118a0740e6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881798254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.881798254
Directory /workspace/61.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/61.otp_ctrl_parallel_lc_esc.3368831296
Short name T710
Test name
Test status
Simulation time 164368566 ps
CPU time 6.61 seconds
Started Mar 21 03:29:41 PM PDT 24
Finished Mar 21 03:29:48 PM PDT 24
Peak memory 241556 kb
Host smart-cee890fe-4216-4a0e-a43b-dc7485d439c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368831296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.3368831296
Directory /workspace/61.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/61.otp_ctrl_stress_all_with_rand_reset.3965400123
Short name T1195
Test name
Test status
Simulation time 146464529338 ps
CPU time 1258.15 seconds
Started Mar 21 03:29:43 PM PDT 24
Finished Mar 21 03:50:42 PM PDT 24
Peak memory 292044 kb
Host smart-896ae6fd-5fc4-48ed-8395-0bd6f618029f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965400123 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_stress_all_with_rand_reset.3965400123
Directory /workspace/61.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.otp_ctrl_init_fail.893489954
Short name T897
Test name
Test status
Simulation time 436220334 ps
CPU time 4.44 seconds
Started Mar 21 03:29:41 PM PDT 24
Finished Mar 21 03:29:46 PM PDT 24
Peak memory 241316 kb
Host smart-24197635-4a81-40ba-85b9-cc4d21b5e6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893489954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.893489954
Directory /workspace/62.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/62.otp_ctrl_parallel_lc_esc.2568158963
Short name T734
Test name
Test status
Simulation time 5508092297 ps
CPU time 12.87 seconds
Started Mar 21 03:29:42 PM PDT 24
Finished Mar 21 03:29:55 PM PDT 24
Peak memory 241516 kb
Host smart-e0b15e8b-2c19-4db8-9cf8-ed7251cdfbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568158963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.2568158963
Directory /workspace/62.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/62.otp_ctrl_stress_all_with_rand_reset.2644163835
Short name T503
Test name
Test status
Simulation time 173690506518 ps
CPU time 534.7 seconds
Started Mar 21 03:29:42 PM PDT 24
Finished Mar 21 03:38:37 PM PDT 24
Peak memory 256516 kb
Host smart-49c6041b-aae2-40f1-a762-490e4aaa4080
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644163835 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_stress_all_with_rand_reset.2644163835
Directory /workspace/62.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.otp_ctrl_init_fail.1618837439
Short name T566
Test name
Test status
Simulation time 104477856 ps
CPU time 3.89 seconds
Started Mar 21 03:29:44 PM PDT 24
Finished Mar 21 03:29:48 PM PDT 24
Peak memory 241664 kb
Host smart-76b590e4-7604-48ce-bb33-8bb8f71970c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618837439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.1618837439
Directory /workspace/63.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/63.otp_ctrl_parallel_lc_esc.990494439
Short name T1010
Test name
Test status
Simulation time 343174586 ps
CPU time 6 seconds
Started Mar 21 03:29:42 PM PDT 24
Finished Mar 21 03:29:48 PM PDT 24
Peak memory 241280 kb
Host smart-bb1e9185-685e-4362-a70b-894933345866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990494439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.990494439
Directory /workspace/63.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/64.otp_ctrl_init_fail.2899687815
Short name T121
Test name
Test status
Simulation time 212746005 ps
CPU time 3.81 seconds
Started Mar 21 03:29:46 PM PDT 24
Finished Mar 21 03:29:50 PM PDT 24
Peak memory 241556 kb
Host smart-6282e397-8a00-4b11-ad4e-0a13ba57d235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899687815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.2899687815
Directory /workspace/64.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/64.otp_ctrl_parallel_lc_esc.1042200310
Short name T463
Test name
Test status
Simulation time 975507722 ps
CPU time 16.63 seconds
Started Mar 21 03:29:41 PM PDT 24
Finished Mar 21 03:29:58 PM PDT 24
Peak memory 241204 kb
Host smart-14af8292-bd2b-4fd9-8ac7-1ad1291826bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042200310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.1042200310
Directory /workspace/64.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/64.otp_ctrl_stress_all_with_rand_reset.2340454012
Short name T340
Test name
Test status
Simulation time 684181894541 ps
CPU time 1509.41 seconds
Started Mar 21 03:29:47 PM PDT 24
Finished Mar 21 03:54:57 PM PDT 24
Peak memory 347968 kb
Host smart-23249c91-8620-4c3b-b6ac-63e70d49f1b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340454012 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_stress_all_with_rand_reset.2340454012
Directory /workspace/64.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.otp_ctrl_parallel_lc_esc.773078487
Short name T158
Test name
Test status
Simulation time 256449377 ps
CPU time 7.28 seconds
Started Mar 21 03:29:40 PM PDT 24
Finished Mar 21 03:29:47 PM PDT 24
Peak memory 241212 kb
Host smart-5d251a8b-7308-46e9-9753-2038d2987380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773078487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.773078487
Directory /workspace/65.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.1521553758
Short name T24
Test name
Test status
Simulation time 48023939260 ps
CPU time 891.58 seconds
Started Mar 21 03:29:45 PM PDT 24
Finished Mar 21 03:44:37 PM PDT 24
Peak memory 265440 kb
Host smart-401f80ec-c927-4d3e-b57f-4cc070083656
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521553758 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_stress_all_with_rand_reset.1521553758
Directory /workspace/65.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.otp_ctrl_init_fail.432589500
Short name T470
Test name
Test status
Simulation time 522501929 ps
CPU time 4.51 seconds
Started Mar 21 03:29:41 PM PDT 24
Finished Mar 21 03:29:46 PM PDT 24
Peak memory 241312 kb
Host smart-58f6420a-8203-48ff-a77a-b371d2137ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432589500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.432589500
Directory /workspace/66.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/66.otp_ctrl_parallel_lc_esc.411022994
Short name T966
Test name
Test status
Simulation time 129103418 ps
CPU time 6.15 seconds
Started Mar 21 03:29:45 PM PDT 24
Finished Mar 21 03:29:51 PM PDT 24
Peak memory 241724 kb
Host smart-a3e97aed-dc22-4178-9a7c-34623ce1b58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411022994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.411022994
Directory /workspace/66.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/66.otp_ctrl_stress_all_with_rand_reset.4101163248
Short name T405
Test name
Test status
Simulation time 18832024793 ps
CPU time 280.84 seconds
Started Mar 21 03:29:42 PM PDT 24
Finished Mar 21 03:34:23 PM PDT 24
Peak memory 256684 kb
Host smart-378bfbde-8d17-4d9a-bc96-e61f14ad0ca4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101163248 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_stress_all_with_rand_reset.4101163248
Directory /workspace/66.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.otp_ctrl_init_fail.952598703
Short name T938
Test name
Test status
Simulation time 1799674403 ps
CPU time 5.92 seconds
Started Mar 21 03:29:44 PM PDT 24
Finished Mar 21 03:29:50 PM PDT 24
Peak memory 241644 kb
Host smart-c10f4419-af8a-4d30-b676-b065a178b340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952598703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.952598703
Directory /workspace/67.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/67.otp_ctrl_parallel_lc_esc.4090672033
Short name T598
Test name
Test status
Simulation time 253430009 ps
CPU time 7.04 seconds
Started Mar 21 03:29:46 PM PDT 24
Finished Mar 21 03:29:54 PM PDT 24
Peak memory 241244 kb
Host smart-e0b2d7e1-8b10-439c-aea6-4cac8196f3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090672033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.4090672033
Directory /workspace/67.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/67.otp_ctrl_stress_all_with_rand_reset.2883683316
Short name T143
Test name
Test status
Simulation time 60591605446 ps
CPU time 365.62 seconds
Started Mar 21 03:29:45 PM PDT 24
Finished Mar 21 03:35:51 PM PDT 24
Peak memory 279296 kb
Host smart-ebcf9efd-f552-4a31-b2a0-f05f1dcc226e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883683316 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_stress_all_with_rand_reset.2883683316
Directory /workspace/67.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.otp_ctrl_init_fail.4141231320
Short name T222
Test name
Test status
Simulation time 103933337 ps
CPU time 3.77 seconds
Started Mar 21 03:29:42 PM PDT 24
Finished Mar 21 03:29:47 PM PDT 24
Peak memory 241548 kb
Host smart-750551c6-45c3-4b60-99ad-a272c2319e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141231320 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.4141231320
Directory /workspace/68.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/68.otp_ctrl_parallel_lc_esc.3057829968
Short name T922
Test name
Test status
Simulation time 419013066 ps
CPU time 11.98 seconds
Started Mar 21 03:29:42 PM PDT 24
Finished Mar 21 03:29:55 PM PDT 24
Peak memory 241256 kb
Host smart-e126dd5d-2581-44e9-ba29-34cf7c6a12e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057829968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.3057829968
Directory /workspace/68.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/68.otp_ctrl_stress_all_with_rand_reset.46534234
Short name T697
Test name
Test status
Simulation time 264788381691 ps
CPU time 3397.9 seconds
Started Mar 21 03:29:40 PM PDT 24
Finished Mar 21 04:26:19 PM PDT 24
Peak memory 290320 kb
Host smart-a3039765-89a2-4f25-8926-cb4b64933f61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46534234 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_stress_all_with_rand_reset.46534234
Directory /workspace/68.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.otp_ctrl_init_fail.1395249652
Short name T674
Test name
Test status
Simulation time 128751764 ps
CPU time 3.46 seconds
Started Mar 21 03:29:44 PM PDT 24
Finished Mar 21 03:29:47 PM PDT 24
Peak memory 241392 kb
Host smart-ba5f8932-8927-4fda-a835-c999bf41ddfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395249652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.1395249652
Directory /workspace/69.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/69.otp_ctrl_parallel_lc_esc.1536091615
Short name T149
Test name
Test status
Simulation time 362303608 ps
CPU time 8.08 seconds
Started Mar 21 03:29:46 PM PDT 24
Finished Mar 21 03:29:55 PM PDT 24
Peak memory 241260 kb
Host smart-acbaeecd-ec70-472c-8f11-f27e67475f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536091615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.1536091615
Directory /workspace/69.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/69.otp_ctrl_stress_all_with_rand_reset.2359186259
Short name T21
Test name
Test status
Simulation time 361382829047 ps
CPU time 1545.62 seconds
Started Mar 21 03:29:46 PM PDT 24
Finished Mar 21 03:55:33 PM PDT 24
Peak memory 262916 kb
Host smart-47311f85-428d-4145-a813-2033bc45088c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359186259 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_stress_all_with_rand_reset.2359186259
Directory /workspace/69.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.otp_ctrl_alert_test.720597732
Short name T730
Test name
Test status
Simulation time 186570163 ps
CPU time 1.74 seconds
Started Mar 21 03:27:12 PM PDT 24
Finished Mar 21 03:27:14 PM PDT 24
Peak memory 239856 kb
Host smart-1d13b68b-4350-4f96-a0bd-1dcba47de89f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720597732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.720597732
Directory /workspace/7.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.otp_ctrl_background_chks.902451605
Short name T1089
Test name
Test status
Simulation time 1089016788 ps
CPU time 21.98 seconds
Started Mar 21 03:27:12 PM PDT 24
Finished Mar 21 03:27:34 PM PDT 24
Peak memory 242356 kb
Host smart-5c39cfcd-5f9e-4aee-a556-b468a0772e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902451605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.902451605
Directory /workspace/7.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/7.otp_ctrl_check_fail.369012715
Short name T1044
Test name
Test status
Simulation time 1612982207 ps
CPU time 10.79 seconds
Started Mar 21 03:27:15 PM PDT 24
Finished Mar 21 03:27:27 PM PDT 24
Peak memory 241704 kb
Host smart-7095d768-5872-4994-9b13-2416e5eec837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369012715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.369012715
Directory /workspace/7.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_errs.2066362920
Short name T837
Test name
Test status
Simulation time 592107846 ps
CPU time 7.82 seconds
Started Mar 21 03:27:11 PM PDT 24
Finished Mar 21 03:27:19 PM PDT 24
Peak memory 241784 kb
Host smart-aec8ada6-5f9e-4fb4-861f-e36ef288616c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066362920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.2066362920
Directory /workspace/7.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_lock.3349059947
Short name T940
Test name
Test status
Simulation time 2524290406 ps
CPU time 24.91 seconds
Started Mar 21 03:27:15 PM PDT 24
Finished Mar 21 03:27:40 PM PDT 24
Peak memory 241624 kb
Host smart-b07013f1-f758-42ae-8760-f224e33ae1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349059947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.3349059947
Directory /workspace/7.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/7.otp_ctrl_init_fail.3408580552
Short name T162
Test name
Test status
Simulation time 197394965 ps
CPU time 3.33 seconds
Started Mar 21 03:27:11 PM PDT 24
Finished Mar 21 03:27:14 PM PDT 24
Peak memory 241428 kb
Host smart-b6b1d934-b6ff-4dfa-b409-ff3d076800c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408580552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.3408580552
Directory /workspace/7.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_macro_errs.4258564842
Short name T219
Test name
Test status
Simulation time 5359871099 ps
CPU time 30.44 seconds
Started Mar 21 03:27:11 PM PDT 24
Finished Mar 21 03:27:42 PM PDT 24
Peak memory 242624 kb
Host smart-28738169-0b56-4782-9978-44d8014ab003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258564842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.4258564842
Directory /workspace/7.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_key_req.469785126
Short name T740
Test name
Test status
Simulation time 2649618195 ps
CPU time 57.24 seconds
Started Mar 21 03:27:12 PM PDT 24
Finished Mar 21 03:28:09 PM PDT 24
Peak memory 242412 kb
Host smart-8b87310a-e429-4aa8-8494-dc4a244129b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469785126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.469785126
Directory /workspace/7.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_esc.804441561
Short name T228
Test name
Test status
Simulation time 739455389 ps
CPU time 7.01 seconds
Started Mar 21 03:27:13 PM PDT 24
Finished Mar 21 03:27:20 PM PDT 24
Peak memory 241816 kb
Host smart-75802bf8-2d34-46e6-806d-21ace8cd42d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804441561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.804441561
Directory /workspace/7.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_req.2986529326
Short name T1130
Test name
Test status
Simulation time 473506900 ps
CPU time 11.73 seconds
Started Mar 21 03:27:11 PM PDT 24
Finished Mar 21 03:27:23 PM PDT 24
Peak memory 241288 kb
Host smart-9978abf8-c972-4024-87f8-dea256b7c0cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2986529326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.2986529326
Directory /workspace/7.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_regwen.705795209
Short name T927
Test name
Test status
Simulation time 119585566 ps
CPU time 3.17 seconds
Started Mar 21 03:27:15 PM PDT 24
Finished Mar 21 03:27:18 PM PDT 24
Peak memory 241316 kb
Host smart-d21bd906-3aa0-4d04-b46e-64f951e2e42b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=705795209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.705795209
Directory /workspace/7.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/7.otp_ctrl_smoke.3229744148
Short name T426
Test name
Test status
Simulation time 10498172684 ps
CPU time 91.65 seconds
Started Mar 21 03:27:15 PM PDT 24
Finished Mar 21 03:28:46 PM PDT 24
Peak memory 241416 kb
Host smart-30842ae5-7936-4403-ad70-299634e1e6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229744148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.3229744148
Directory /workspace/7.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all.3772154831
Short name T958
Test name
Test status
Simulation time 13851523044 ps
CPU time 195.48 seconds
Started Mar 21 03:27:16 PM PDT 24
Finished Mar 21 03:30:32 PM PDT 24
Peak memory 248288 kb
Host smart-06b1fcd5-dbb6-4ec3-9a81-6cc4f9ca5d9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772154831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all.
3772154831
Directory /workspace/7.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all_with_rand_reset.590683019
Short name T947
Test name
Test status
Simulation time 408735600805 ps
CPU time 1506.25 seconds
Started Mar 21 03:27:11 PM PDT 24
Finished Mar 21 03:52:17 PM PDT 24
Peak memory 339012 kb
Host smart-1da79bb2-9650-43ec-9c98-c2fc5ebc673d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590683019 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all_with_rand_reset.590683019
Directory /workspace/7.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.otp_ctrl_test_access.2539016461
Short name T1088
Test name
Test status
Simulation time 287197355 ps
CPU time 7.34 seconds
Started Mar 21 03:27:11 PM PDT 24
Finished Mar 21 03:27:18 PM PDT 24
Peak memory 241352 kb
Host smart-5eee2a06-49d4-407b-8d84-e9d2a3c7cdaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539016461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.2539016461
Directory /workspace/7.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/70.otp_ctrl_init_fail.3139266691
Short name T618
Test name
Test status
Simulation time 120020910 ps
CPU time 3.43 seconds
Started Mar 21 03:29:47 PM PDT 24
Finished Mar 21 03:29:51 PM PDT 24
Peak memory 241124 kb
Host smart-9c37735a-2d0b-4b27-8e01-a70e23f320f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139266691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.3139266691
Directory /workspace/70.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/70.otp_ctrl_parallel_lc_esc.2835443834
Short name T814
Test name
Test status
Simulation time 437869441 ps
CPU time 6.9 seconds
Started Mar 21 03:29:44 PM PDT 24
Finished Mar 21 03:29:51 PM PDT 24
Peak memory 241336 kb
Host smart-22d3c533-32dc-4425-b634-45b5d3c750ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835443834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.2835443834
Directory /workspace/70.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/70.otp_ctrl_stress_all_with_rand_reset.4063049083
Short name T410
Test name
Test status
Simulation time 119472185732 ps
CPU time 2691.76 seconds
Started Mar 21 03:29:43 PM PDT 24
Finished Mar 21 04:14:36 PM PDT 24
Peak memory 329556 kb
Host smart-a263e89e-bcdd-4f63-958b-241eca766705
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063049083 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_stress_all_with_rand_reset.4063049083
Directory /workspace/70.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.otp_ctrl_init_fail.940818051
Short name T1009
Test name
Test status
Simulation time 2398414178 ps
CPU time 7.17 seconds
Started Mar 21 03:29:43 PM PDT 24
Finished Mar 21 03:29:51 PM PDT 24
Peak memory 241392 kb
Host smart-450c9a72-9c1c-4ec1-8a4d-fe0b3598ad41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940818051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.940818051
Directory /workspace/71.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/71.otp_ctrl_parallel_lc_esc.1431525103
Short name T214
Test name
Test status
Simulation time 3113414110 ps
CPU time 7.11 seconds
Started Mar 21 03:29:48 PM PDT 24
Finished Mar 21 03:29:55 PM PDT 24
Peak memory 241240 kb
Host smart-3d390f90-66f3-4f52-99da-94afdf9abb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431525103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.1431525103
Directory /workspace/71.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/71.otp_ctrl_stress_all_with_rand_reset.3346697429
Short name T704
Test name
Test status
Simulation time 199729299091 ps
CPU time 2649.22 seconds
Started Mar 21 03:29:43 PM PDT 24
Finished Mar 21 04:13:53 PM PDT 24
Peak memory 371156 kb
Host smart-0f6b4582-cb02-4cda-a41a-95406f7bceef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346697429 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_stress_all_with_rand_reset.3346697429
Directory /workspace/71.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.otp_ctrl_init_fail.750781000
Short name T195
Test name
Test status
Simulation time 106643161 ps
CPU time 4 seconds
Started Mar 21 03:29:47 PM PDT 24
Finished Mar 21 03:29:52 PM PDT 24
Peak memory 241048 kb
Host smart-06f988c0-4b1d-43d2-8be5-968582783729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750781000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.750781000
Directory /workspace/72.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/72.otp_ctrl_parallel_lc_esc.878198255
Short name T739
Test name
Test status
Simulation time 523622261 ps
CPU time 13.35 seconds
Started Mar 21 03:29:46 PM PDT 24
Finished Mar 21 03:30:01 PM PDT 24
Peak memory 241372 kb
Host smart-2cb9524c-5e89-4a47-961d-d081d1643626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878198255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.878198255
Directory /workspace/72.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/73.otp_ctrl_init_fail.9656276
Short name T114
Test name
Test status
Simulation time 94782347 ps
CPU time 4.28 seconds
Started Mar 21 03:29:41 PM PDT 24
Finished Mar 21 03:29:46 PM PDT 24
Peak memory 241344 kb
Host smart-eccaa97d-dad8-4064-ba49-c5381004dea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9656276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.9656276
Directory /workspace/73.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/73.otp_ctrl_stress_all_with_rand_reset.3125839982
Short name T260
Test name
Test status
Simulation time 523538628611 ps
CPU time 1672.53 seconds
Started Mar 21 03:29:38 PM PDT 24
Finished Mar 21 03:57:31 PM PDT 24
Peak memory 342852 kb
Host smart-e67858ba-75ff-447f-9907-1cd3b9ea0079
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125839982 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_stress_all_with_rand_reset.3125839982
Directory /workspace/73.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.otp_ctrl_init_fail.3770362199
Short name T136
Test name
Test status
Simulation time 273293049 ps
CPU time 4.98 seconds
Started Mar 21 03:29:41 PM PDT 24
Finished Mar 21 03:29:46 PM PDT 24
Peak memory 241432 kb
Host smart-bccb40fa-4397-49e6-bf8a-d2aece39bbc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770362199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.3770362199
Directory /workspace/74.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/74.otp_ctrl_parallel_lc_esc.1085234551
Short name T225
Test name
Test status
Simulation time 288776030 ps
CPU time 4.11 seconds
Started Mar 21 03:29:42 PM PDT 24
Finished Mar 21 03:29:46 PM PDT 24
Peak memory 241348 kb
Host smart-0a832fb5-660f-404a-af07-5c45f20155e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085234551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.1085234551
Directory /workspace/74.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/74.otp_ctrl_stress_all_with_rand_reset.2718876974
Short name T1085
Test name
Test status
Simulation time 78955385940 ps
CPU time 1044.51 seconds
Started Mar 21 03:29:41 PM PDT 24
Finished Mar 21 03:47:05 PM PDT 24
Peak memory 263996 kb
Host smart-e6bb045b-7ffd-411e-88da-ce7c4002e9a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718876974 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_stress_all_with_rand_reset.2718876974
Directory /workspace/74.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.otp_ctrl_init_fail.3409388925
Short name T640
Test name
Test status
Simulation time 2258405385 ps
CPU time 5.52 seconds
Started Mar 21 03:29:41 PM PDT 24
Finished Mar 21 03:29:46 PM PDT 24
Peak memory 241448 kb
Host smart-bcb2b88d-a952-402e-b169-ddd825e2f801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409388925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.3409388925
Directory /workspace/75.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/75.otp_ctrl_parallel_lc_esc.1211052688
Short name T982
Test name
Test status
Simulation time 584486418 ps
CPU time 6.78 seconds
Started Mar 21 03:29:39 PM PDT 24
Finished Mar 21 03:29:46 PM PDT 24
Peak memory 241140 kb
Host smart-5b737957-4638-44e6-8f5b-32347d98510a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211052688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.1211052688
Directory /workspace/75.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/76.otp_ctrl_init_fail.418700793
Short name T194
Test name
Test status
Simulation time 1995485971 ps
CPU time 4.41 seconds
Started Mar 21 03:29:42 PM PDT 24
Finished Mar 21 03:29:46 PM PDT 24
Peak memory 241604 kb
Host smart-754dc5dc-0db9-483d-bf14-d59bbbbd0094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418700793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.418700793
Directory /workspace/76.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/76.otp_ctrl_parallel_lc_esc.539026323
Short name T979
Test name
Test status
Simulation time 1673854188 ps
CPU time 5.88 seconds
Started Mar 21 03:29:40 PM PDT 24
Finished Mar 21 03:29:46 PM PDT 24
Peak memory 241328 kb
Host smart-ce81e4d0-2816-49b1-b2cc-b67839db8139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539026323 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.539026323
Directory /workspace/76.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/76.otp_ctrl_stress_all_with_rand_reset.1102189522
Short name T296
Test name
Test status
Simulation time 147405128862 ps
CPU time 1359.22 seconds
Started Mar 21 03:29:38 PM PDT 24
Finished Mar 21 03:52:18 PM PDT 24
Peak memory 382032 kb
Host smart-dfe15d5e-0996-4b0f-b7d1-974f88e7dc7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102189522 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_stress_all_with_rand_reset.1102189522
Directory /workspace/76.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.otp_ctrl_init_fail.1960711327
Short name T53
Test name
Test status
Simulation time 128786162 ps
CPU time 4.9 seconds
Started Mar 21 03:29:38 PM PDT 24
Finished Mar 21 03:29:43 PM PDT 24
Peak memory 241212 kb
Host smart-c6e0650e-9755-47d2-be6a-6997a235e501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960711327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.1960711327
Directory /workspace/77.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/77.otp_ctrl_parallel_lc_esc.4247887843
Short name T1059
Test name
Test status
Simulation time 295387674 ps
CPU time 8.94 seconds
Started Mar 21 03:29:43 PM PDT 24
Finished Mar 21 03:29:53 PM PDT 24
Peak memory 241252 kb
Host smart-bc5d1d07-6cd5-4cb2-a0ed-2f8eef60948a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247887843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.4247887843
Directory /workspace/77.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/77.otp_ctrl_stress_all_with_rand_reset.2143830147
Short name T297
Test name
Test status
Simulation time 866485359766 ps
CPU time 1688.62 seconds
Started Mar 21 03:29:43 PM PDT 24
Finished Mar 21 03:57:52 PM PDT 24
Peak memory 326216 kb
Host smart-a143e752-cd00-4ad3-94e3-41a498e8f67d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143830147 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_stress_all_with_rand_reset.2143830147
Directory /workspace/77.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.otp_ctrl_init_fail.3499141535
Short name T621
Test name
Test status
Simulation time 185164577 ps
CPU time 5.44 seconds
Started Mar 21 03:29:42 PM PDT 24
Finished Mar 21 03:29:47 PM PDT 24
Peak memory 241692 kb
Host smart-d4790f41-0299-482c-8313-a0120a09ddf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499141535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.3499141535
Directory /workspace/78.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/78.otp_ctrl_parallel_lc_esc.3296557015
Short name T746
Test name
Test status
Simulation time 452844990 ps
CPU time 16.9 seconds
Started Mar 21 03:29:42 PM PDT 24
Finished Mar 21 03:29:59 PM PDT 24
Peak memory 241320 kb
Host smart-401bc3b5-1f26-4754-a0c3-6dc3d9fe3aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296557015 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.3296557015
Directory /workspace/78.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/78.otp_ctrl_stress_all_with_rand_reset.3642688410
Short name T871
Test name
Test status
Simulation time 301698173307 ps
CPU time 1071.9 seconds
Started Mar 21 03:29:40 PM PDT 24
Finished Mar 21 03:47:33 PM PDT 24
Peak memory 330436 kb
Host smart-55dc800b-0ea1-4c26-a1e3-cd3283937014
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642688410 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_stress_all_with_rand_reset.3642688410
Directory /workspace/78.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.otp_ctrl_init_fail.2179981171
Short name T242
Test name
Test status
Simulation time 572733285 ps
CPU time 4.53 seconds
Started Mar 21 03:29:40 PM PDT 24
Finished Mar 21 03:29:45 PM PDT 24
Peak memory 241336 kb
Host smart-348e9342-ed9b-40e5-81c2-93efed9bd754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179981171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.2179981171
Directory /workspace/79.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/79.otp_ctrl_parallel_lc_esc.5447345
Short name T918
Test name
Test status
Simulation time 2358872248 ps
CPU time 17.79 seconds
Started Mar 21 03:29:46 PM PDT 24
Finished Mar 21 03:30:04 PM PDT 24
Peak memory 241432 kb
Host smart-0c7bad55-ae42-4f31-981a-f3e0c9cdbdca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5447345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.5447345
Directory /workspace/79.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/79.otp_ctrl_stress_all_with_rand_reset.402078575
Short name T96
Test name
Test status
Simulation time 132337903823 ps
CPU time 2290.71 seconds
Started Mar 21 03:29:44 PM PDT 24
Finished Mar 21 04:07:56 PM PDT 24
Peak memory 333596 kb
Host smart-7fb239d2-490b-4ba9-b1ed-7262536b7511
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402078575 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_stress_all_with_rand_reset.402078575
Directory /workspace/79.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.otp_ctrl_alert_test.1238550826
Short name T1069
Test name
Test status
Simulation time 218605803 ps
CPU time 1.91 seconds
Started Mar 21 03:27:27 PM PDT 24
Finished Mar 21 03:27:29 PM PDT 24
Peak memory 239888 kb
Host smart-e2936296-b0ff-4298-b1f6-2f2ab5041e0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238550826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.1238550826
Directory /workspace/8.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.otp_ctrl_background_chks.1799253191
Short name T507
Test name
Test status
Simulation time 9072692512 ps
CPU time 27.09 seconds
Started Mar 21 03:27:13 PM PDT 24
Finished Mar 21 03:27:40 PM PDT 24
Peak memory 242652 kb
Host smart-d792caa6-8c34-45c2-a2af-88c084b6f486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799253191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.1799253191
Directory /workspace/8.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/8.otp_ctrl_check_fail.2000119035
Short name T1121
Test name
Test status
Simulation time 1058761021 ps
CPU time 7.52 seconds
Started Mar 21 03:27:24 PM PDT 24
Finished Mar 21 03:27:32 PM PDT 24
Peak memory 241372 kb
Host smart-42ebe234-32a1-4a15-b2aa-1fa8d6b89023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000119035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.2000119035
Directory /workspace/8.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_errs.3924603183
Short name T783
Test name
Test status
Simulation time 726457988 ps
CPU time 25.84 seconds
Started Mar 21 03:27:31 PM PDT 24
Finished Mar 21 03:27:57 PM PDT 24
Peak memory 241444 kb
Host smart-cf767b98-4dab-4612-8e7c-24513d410f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924603183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.3924603183
Directory /workspace/8.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_lock.141752801
Short name T235
Test name
Test status
Simulation time 3155040232 ps
CPU time 9.5 seconds
Started Mar 21 03:27:23 PM PDT 24
Finished Mar 21 03:27:33 PM PDT 24
Peak memory 241552 kb
Host smart-cd0acfae-3e18-467f-8604-c8d9a298e4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141752801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.141752801
Directory /workspace/8.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/8.otp_ctrl_init_fail.3559241223
Short name T1076
Test name
Test status
Simulation time 360901285 ps
CPU time 4.29 seconds
Started Mar 21 03:27:16 PM PDT 24
Finished Mar 21 03:27:21 PM PDT 24
Peak memory 241416 kb
Host smart-4f6c7e15-b199-4b09-85ad-50fbda5bae52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559241223 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.3559241223
Directory /workspace/8.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_macro_errs.2376173265
Short name T237
Test name
Test status
Simulation time 799705196 ps
CPU time 6.98 seconds
Started Mar 21 03:27:27 PM PDT 24
Finished Mar 21 03:27:34 PM PDT 24
Peak memory 241416 kb
Host smart-787c305a-1b04-49db-80b0-908fdd037689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376173265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.2376173265
Directory /workspace/8.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_key_req.249668428
Short name T1012
Test name
Test status
Simulation time 873635114 ps
CPU time 11.18 seconds
Started Mar 21 03:27:26 PM PDT 24
Finished Mar 21 03:27:37 PM PDT 24
Peak memory 241416 kb
Host smart-75a739fe-79d2-4e82-8388-75179ba11eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249668428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.249668428
Directory /workspace/8.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_esc.2826953333
Short name T417
Test name
Test status
Simulation time 1646072427 ps
CPU time 3.15 seconds
Started Mar 21 03:27:12 PM PDT 24
Finished Mar 21 03:27:15 PM PDT 24
Peak memory 241216 kb
Host smart-3bc7bfea-dac4-435c-88dc-064008064812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826953333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.2826953333
Directory /workspace/8.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_req.3166661011
Short name T186
Test name
Test status
Simulation time 1300730794 ps
CPU time 21.94 seconds
Started Mar 21 03:27:13 PM PDT 24
Finished Mar 21 03:27:36 PM PDT 24
Peak memory 248100 kb
Host smart-04b4d421-5d9f-4e6d-8135-f4ceea8422fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3166661011 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.3166661011
Directory /workspace/8.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_regwen.3246755645
Short name T1187
Test name
Test status
Simulation time 4083811624 ps
CPU time 11.72 seconds
Started Mar 21 03:27:28 PM PDT 24
Finished Mar 21 03:27:40 PM PDT 24
Peak memory 242320 kb
Host smart-f32e2451-8aa9-4c68-bb5e-1dd029f6d693
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3246755645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.3246755645
Directory /workspace/8.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/8.otp_ctrl_smoke.2591155596
Short name T434
Test name
Test status
Simulation time 137709030 ps
CPU time 5.19 seconds
Started Mar 21 03:27:14 PM PDT 24
Finished Mar 21 03:27:20 PM PDT 24
Peak memory 241572 kb
Host smart-e2c9ca21-0776-4d9a-b7d1-1057cfd4e5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591155596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.2591155596
Directory /workspace/8.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all.3885259982
Short name T1007
Test name
Test status
Simulation time 15440470953 ps
CPU time 144.33 seconds
Started Mar 21 03:27:25 PM PDT 24
Finished Mar 21 03:29:50 PM PDT 24
Peak memory 260896 kb
Host smart-326432b5-1596-4af8-9973-3e6cf5d3dc12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885259982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all.
3885259982
Directory /workspace/8.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.otp_ctrl_test_access.3266138225
Short name T292
Test name
Test status
Simulation time 1097704099 ps
CPU time 30.42 seconds
Started Mar 21 03:27:29 PM PDT 24
Finished Mar 21 03:28:00 PM PDT 24
Peak memory 241396 kb
Host smart-4f0ec64b-6a16-4bf4-9081-c5f7281665d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266138225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.3266138225
Directory /workspace/8.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/80.otp_ctrl_init_fail.876572887
Short name T669
Test name
Test status
Simulation time 568241360 ps
CPU time 4.13 seconds
Started Mar 21 03:29:41 PM PDT 24
Finished Mar 21 03:29:46 PM PDT 24
Peak memory 241372 kb
Host smart-b7ec59a7-e495-4543-8061-a2841a4f7b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876572887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.876572887
Directory /workspace/80.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/80.otp_ctrl_stress_all_with_rand_reset.3579001159
Short name T14
Test name
Test status
Simulation time 96209945863 ps
CPU time 1207.95 seconds
Started Mar 21 03:29:43 PM PDT 24
Finished Mar 21 03:49:51 PM PDT 24
Peak memory 375432 kb
Host smart-833bf543-1e86-48f9-a922-21f91d01948a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579001159 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_stress_all_with_rand_reset.3579001159
Directory /workspace/80.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.otp_ctrl_init_fail.3753572252
Short name T564
Test name
Test status
Simulation time 1965555045 ps
CPU time 7 seconds
Started Mar 21 03:29:42 PM PDT 24
Finished Mar 21 03:29:50 PM PDT 24
Peak memory 241380 kb
Host smart-310fbef9-a123-4ebe-943e-cf3db1c866b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753572252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.3753572252
Directory /workspace/81.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/81.otp_ctrl_parallel_lc_esc.1402498955
Short name T874
Test name
Test status
Simulation time 249755863 ps
CPU time 5.37 seconds
Started Mar 21 03:29:41 PM PDT 24
Finished Mar 21 03:29:47 PM PDT 24
Peak memory 241532 kb
Host smart-96d128c8-dd84-4493-a02c-dddf41b856a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402498955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.1402498955
Directory /workspace/81.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/81.otp_ctrl_stress_all_with_rand_reset.4197723471
Short name T307
Test name
Test status
Simulation time 53624386737 ps
CPU time 658.75 seconds
Started Mar 21 03:29:58 PM PDT 24
Finished Mar 21 03:40:57 PM PDT 24
Peak memory 314044 kb
Host smart-5b147237-bd54-49fd-9a95-bc7edcb62086
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197723471 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_stress_all_with_rand_reset.4197723471
Directory /workspace/81.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.otp_ctrl_init_fail.1114883345
Short name T451
Test name
Test status
Simulation time 479252097 ps
CPU time 3.47 seconds
Started Mar 21 03:30:00 PM PDT 24
Finished Mar 21 03:30:04 PM PDT 24
Peak memory 241444 kb
Host smart-58975690-fa34-4125-ac78-cf6cf3033e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114883345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.1114883345
Directory /workspace/82.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/82.otp_ctrl_parallel_lc_esc.4243803532
Short name T999
Test name
Test status
Simulation time 244185251 ps
CPU time 13.62 seconds
Started Mar 21 03:29:54 PM PDT 24
Finished Mar 21 03:30:08 PM PDT 24
Peak memory 241268 kb
Host smart-6504d2d9-451a-42c9-8ab3-21ee98dd2b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243803532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.4243803532
Directory /workspace/82.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/82.otp_ctrl_stress_all_with_rand_reset.3114217268
Short name T1030
Test name
Test status
Simulation time 371725101866 ps
CPU time 1463.6 seconds
Started Mar 21 03:30:03 PM PDT 24
Finished Mar 21 03:54:28 PM PDT 24
Peak memory 389804 kb
Host smart-581e1bda-55a6-471d-b9df-f2a90bc05e53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114217268 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_stress_all_with_rand_reset.3114217268
Directory /workspace/82.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.otp_ctrl_init_fail.1575638047
Short name T775
Test name
Test status
Simulation time 274041725 ps
CPU time 4.14 seconds
Started Mar 21 03:29:59 PM PDT 24
Finished Mar 21 03:30:03 PM PDT 24
Peak memory 241628 kb
Host smart-d88b0a78-d13c-48d6-82dc-bdf80e091972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575638047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.1575638047
Directory /workspace/83.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/83.otp_ctrl_parallel_lc_esc.2599187118
Short name T781
Test name
Test status
Simulation time 408031573 ps
CPU time 4.89 seconds
Started Mar 21 03:30:08 PM PDT 24
Finished Mar 21 03:30:14 PM PDT 24
Peak memory 241680 kb
Host smart-a3bd3fe7-b74f-429d-bdf4-c99cd09a021a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599187118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.2599187118
Directory /workspace/83.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/84.otp_ctrl_init_fail.2769614049
Short name T690
Test name
Test status
Simulation time 638191361 ps
CPU time 5.1 seconds
Started Mar 21 03:30:05 PM PDT 24
Finished Mar 21 03:30:10 PM PDT 24
Peak memory 241460 kb
Host smart-e8d6e48b-72ad-47b8-af4d-c903b0181aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769614049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.2769614049
Directory /workspace/84.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/84.otp_ctrl_parallel_lc_esc.3922730453
Short name T1047
Test name
Test status
Simulation time 460707441 ps
CPU time 9.23 seconds
Started Mar 21 03:30:00 PM PDT 24
Finished Mar 21 03:30:09 PM PDT 24
Peak memory 241336 kb
Host smart-8dba8f68-49af-4481-a395-26438d318dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922730453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.3922730453
Directory /workspace/84.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/85.otp_ctrl_init_fail.576940521
Short name T791
Test name
Test status
Simulation time 136655819 ps
CPU time 4 seconds
Started Mar 21 03:30:01 PM PDT 24
Finished Mar 21 03:30:05 PM PDT 24
Peak memory 241476 kb
Host smart-3957e6ff-bfad-46c8-a0e6-02385d317abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576940521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.576940521
Directory /workspace/85.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/85.otp_ctrl_parallel_lc_esc.3799802307
Short name T146
Test name
Test status
Simulation time 104810557 ps
CPU time 3.65 seconds
Started Mar 21 03:29:59 PM PDT 24
Finished Mar 21 03:30:03 PM PDT 24
Peak memory 241560 kb
Host smart-38486077-1185-46d5-92a4-0edaf5e936ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799802307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.3799802307
Directory /workspace/85.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/85.otp_ctrl_stress_all_with_rand_reset.4123250315
Short name T347
Test name
Test status
Simulation time 44798947749 ps
CPU time 706.9 seconds
Started Mar 21 03:30:03 PM PDT 24
Finished Mar 21 03:41:50 PM PDT 24
Peak memory 282688 kb
Host smart-08df8310-b74c-4b45-916d-5e16687bb52d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123250315 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_stress_all_with_rand_reset.4123250315
Directory /workspace/85.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.otp_ctrl_init_fail.2472521181
Short name T830
Test name
Test status
Simulation time 2209411053 ps
CPU time 6.15 seconds
Started Mar 21 03:29:57 PM PDT 24
Finished Mar 21 03:30:03 PM PDT 24
Peak memory 241484 kb
Host smart-9820ee2e-a20a-4137-9047-9b3bd0c42f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472521181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.2472521181
Directory /workspace/86.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/86.otp_ctrl_parallel_lc_esc.3920782261
Short name T216
Test name
Test status
Simulation time 580893427 ps
CPU time 7.16 seconds
Started Mar 21 03:30:00 PM PDT 24
Finished Mar 21 03:30:07 PM PDT 24
Peak memory 241400 kb
Host smart-dbaaf1f9-6638-4fb7-b76e-4c57a707b330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920782261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.3920782261
Directory /workspace/86.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/87.otp_ctrl_init_fail.1012681836
Short name T1045
Test name
Test status
Simulation time 88692901 ps
CPU time 2.99 seconds
Started Mar 21 03:30:06 PM PDT 24
Finished Mar 21 03:30:09 PM PDT 24
Peak memory 241336 kb
Host smart-425235b3-c4b1-401d-a53c-22153fa2a122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012681836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.1012681836
Directory /workspace/87.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/87.otp_ctrl_parallel_lc_esc.3026194210
Short name T1061
Test name
Test status
Simulation time 203176708 ps
CPU time 5.02 seconds
Started Mar 21 03:30:06 PM PDT 24
Finished Mar 21 03:30:11 PM PDT 24
Peak memory 241204 kb
Host smart-e04e1b08-af2d-43f6-8353-94981cd516eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026194210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.3026194210
Directory /workspace/87.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/87.otp_ctrl_stress_all_with_rand_reset.1150032332
Short name T299
Test name
Test status
Simulation time 68149136354 ps
CPU time 781.96 seconds
Started Mar 21 03:29:58 PM PDT 24
Finished Mar 21 03:43:00 PM PDT 24
Peak memory 281292 kb
Host smart-66bdaee8-dd25-4353-a78c-39eff1988c91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150032332 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_stress_all_with_rand_reset.1150032332
Directory /workspace/87.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.otp_ctrl_init_fail.3430550388
Short name T1084
Test name
Test status
Simulation time 244688500 ps
CPU time 3.81 seconds
Started Mar 21 03:29:58 PM PDT 24
Finished Mar 21 03:30:02 PM PDT 24
Peak memory 241308 kb
Host smart-ccf499e9-27a2-49af-9968-c54caddedf14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430550388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.3430550388
Directory /workspace/88.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/88.otp_ctrl_parallel_lc_esc.820147529
Short name T457
Test name
Test status
Simulation time 327192405 ps
CPU time 3.79 seconds
Started Mar 21 03:29:59 PM PDT 24
Finished Mar 21 03:30:02 PM PDT 24
Peak memory 241172 kb
Host smart-7b7c85b5-f43e-4526-8013-cb0b6ca30c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820147529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.820147529
Directory /workspace/88.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/88.otp_ctrl_stress_all_with_rand_reset.1374345238
Short name T506
Test name
Test status
Simulation time 729159255546 ps
CPU time 1566.98 seconds
Started Mar 21 03:30:05 PM PDT 24
Finished Mar 21 03:56:13 PM PDT 24
Peak memory 280656 kb
Host smart-d3bef341-6154-4947-a81c-6ffe2179782d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374345238 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_stress_all_with_rand_reset.1374345238
Directory /workspace/88.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.otp_ctrl_init_fail.2322966992
Short name T487
Test name
Test status
Simulation time 365278392 ps
CPU time 3.36 seconds
Started Mar 21 03:30:05 PM PDT 24
Finished Mar 21 03:30:09 PM PDT 24
Peak memory 241328 kb
Host smart-1bb6744e-f793-4d81-99e8-ea78f2405969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322966992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.2322966992
Directory /workspace/89.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/89.otp_ctrl_parallel_lc_esc.1560071361
Short name T1077
Test name
Test status
Simulation time 423297360 ps
CPU time 12.92 seconds
Started Mar 21 03:30:04 PM PDT 24
Finished Mar 21 03:30:18 PM PDT 24
Peak memory 241352 kb
Host smart-84d00ef9-bc2d-412b-b472-51fa7739348c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560071361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.1560071361
Directory /workspace/89.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/89.otp_ctrl_stress_all_with_rand_reset.2552261722
Short name T994
Test name
Test status
Simulation time 108854244351 ps
CPU time 2287.52 seconds
Started Mar 21 03:29:58 PM PDT 24
Finished Mar 21 04:08:06 PM PDT 24
Peak memory 621268 kb
Host smart-a07250f1-459a-4a47-98af-a79683f9ad03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552261722 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_stress_all_with_rand_reset.2552261722
Directory /workspace/89.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_alert_test.953884941
Short name T868
Test name
Test status
Simulation time 177785718 ps
CPU time 2.11 seconds
Started Mar 21 03:27:24 PM PDT 24
Finished Mar 21 03:27:26 PM PDT 24
Peak memory 239832 kb
Host smart-43dc1bbf-8522-4036-82d0-974aa4c61d16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953884941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.953884941
Directory /workspace/9.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.otp_ctrl_background_chks.1689138427
Short name T258
Test name
Test status
Simulation time 2066648494 ps
CPU time 15.91 seconds
Started Mar 21 03:27:31 PM PDT 24
Finished Mar 21 03:27:47 PM PDT 24
Peak memory 241556 kb
Host smart-eb72d176-d955-44bb-b41a-050d304fe3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689138427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.1689138427
Directory /workspace/9.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/9.otp_ctrl_check_fail.331837840
Short name T876
Test name
Test status
Simulation time 1071303595 ps
CPU time 18.19 seconds
Started Mar 21 03:27:29 PM PDT 24
Finished Mar 21 03:27:47 PM PDT 24
Peak memory 242016 kb
Host smart-a8cbc434-ef70-490f-b5ae-66d93afe2227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331837840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.331837840
Directory /workspace/9.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_errs.2774033803
Short name T650
Test name
Test status
Simulation time 2718947951 ps
CPU time 23.29 seconds
Started Mar 21 03:27:26 PM PDT 24
Finished Mar 21 03:27:50 PM PDT 24
Peak memory 241808 kb
Host smart-8ce20322-044a-40f0-bb59-836cab5b8856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774033803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.2774033803
Directory /workspace/9.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_lock.3283218525
Short name T887
Test name
Test status
Simulation time 1362671657 ps
CPU time 28.47 seconds
Started Mar 21 03:27:25 PM PDT 24
Finished Mar 21 03:27:53 PM PDT 24
Peak memory 241704 kb
Host smart-5297500d-50e9-47c4-b333-fea9d00b7370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283218525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.3283218525
Directory /workspace/9.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/9.otp_ctrl_init_fail.1003946808
Short name T40
Test name
Test status
Simulation time 597336181 ps
CPU time 4.24 seconds
Started Mar 21 03:27:24 PM PDT 24
Finished Mar 21 03:27:29 PM PDT 24
Peak memory 241420 kb
Host smart-fe01db05-7108-4642-91ec-d48ad94a72a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003946808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.1003946808
Directory /workspace/9.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_macro_errs.3668202765
Short name T768
Test name
Test status
Simulation time 739144498 ps
CPU time 9.03 seconds
Started Mar 21 03:27:26 PM PDT 24
Finished Mar 21 03:27:35 PM PDT 24
Peak memory 241720 kb
Host smart-4ab29b50-b217-47a8-be9d-f6551302e426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668202765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.3668202765
Directory /workspace/9.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_key_req.60843463
Short name T207
Test name
Test status
Simulation time 467423892 ps
CPU time 6.3 seconds
Started Mar 21 03:27:34 PM PDT 24
Finished Mar 21 03:27:41 PM PDT 24
Peak memory 241208 kb
Host smart-c647da59-25ba-45d7-8a43-8e075dc0b487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60843463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.60843463
Directory /workspace/9.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_esc.2693874586
Short name T276
Test name
Test status
Simulation time 169725313 ps
CPU time 4.27 seconds
Started Mar 21 03:27:28 PM PDT 24
Finished Mar 21 03:27:32 PM PDT 24
Peak memory 241220 kb
Host smart-f3ac12cd-5683-43bd-83b5-b1d05392f662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693874586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.2693874586
Directory /workspace/9.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_req.3531872854
Short name T422
Test name
Test status
Simulation time 156941951 ps
CPU time 4.1 seconds
Started Mar 21 03:27:24 PM PDT 24
Finished Mar 21 03:27:28 PM PDT 24
Peak memory 241288 kb
Host smart-f81bbcaa-e2b9-4bbe-8957-d29b14ee2ed0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3531872854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.3531872854
Directory /workspace/9.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_regwen.1411020038
Short name T385
Test name
Test status
Simulation time 616968740 ps
CPU time 4.57 seconds
Started Mar 21 03:27:31 PM PDT 24
Finished Mar 21 03:27:35 PM PDT 24
Peak memory 241644 kb
Host smart-9daf4074-4e29-4d22-bf54-f97edf045e82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1411020038 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.1411020038
Directory /workspace/9.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/9.otp_ctrl_smoke.2018829881
Short name T573
Test name
Test status
Simulation time 461959679 ps
CPU time 10.11 seconds
Started Mar 21 03:27:34 PM PDT 24
Finished Mar 21 03:27:45 PM PDT 24
Peak memory 241132 kb
Host smart-33b0d60a-3fe1-4258-b86a-dde7a69e222a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018829881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.2018829881
Directory /workspace/9.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all.2725514208
Short name T894
Test name
Test status
Simulation time 47621149287 ps
CPU time 217.8 seconds
Started Mar 21 03:27:28 PM PDT 24
Finished Mar 21 03:31:06 PM PDT 24
Peak memory 265644 kb
Host smart-3cf563f2-5cbd-4bb2-bf11-5e031572db75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725514208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all.
2725514208
Directory /workspace/9.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all_with_rand_reset.322226634
Short name T300
Test name
Test status
Simulation time 360975724698 ps
CPU time 1887.69 seconds
Started Mar 21 03:27:31 PM PDT 24
Finished Mar 21 03:58:59 PM PDT 24
Peak memory 264832 kb
Host smart-920fb691-6bd1-48a2-a7c0-e75715ed0695
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322226634 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all_with_rand_reset.322226634
Directory /workspace/9.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_test_access.3003475938
Short name T208
Test name
Test status
Simulation time 11827536601 ps
CPU time 27.27 seconds
Started Mar 21 03:27:31 PM PDT 24
Finished Mar 21 03:27:59 PM PDT 24
Peak memory 242100 kb
Host smart-6204593e-aa06-4f7b-afae-cf1a13b9de92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003475938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.3003475938
Directory /workspace/9.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/90.otp_ctrl_init_fail.2250036653
Short name T891
Test name
Test status
Simulation time 555901595 ps
CPU time 4.31 seconds
Started Mar 21 03:29:58 PM PDT 24
Finished Mar 21 03:30:03 PM PDT 24
Peak memory 241408 kb
Host smart-c363bf21-8887-4107-b910-8f3fafe92cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250036653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.2250036653
Directory /workspace/90.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/90.otp_ctrl_parallel_lc_esc.688472533
Short name T510
Test name
Test status
Simulation time 214200713 ps
CPU time 5.4 seconds
Started Mar 21 03:29:57 PM PDT 24
Finished Mar 21 03:30:02 PM PDT 24
Peak memory 241268 kb
Host smart-450eba51-58d0-4e74-b11c-eb35d89ad269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688472533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.688472533
Directory /workspace/90.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/91.otp_ctrl_init_fail.2244842217
Short name T772
Test name
Test status
Simulation time 150298348 ps
CPU time 4.14 seconds
Started Mar 21 03:29:57 PM PDT 24
Finished Mar 21 03:30:02 PM PDT 24
Peak memory 241732 kb
Host smart-1538b444-5ae9-4d90-8e3e-60d772569cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244842217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.2244842217
Directory /workspace/91.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/91.otp_ctrl_parallel_lc_esc.3832871788
Short name T155
Test name
Test status
Simulation time 412307764 ps
CPU time 9.43 seconds
Started Mar 21 03:30:02 PM PDT 24
Finished Mar 21 03:30:11 PM PDT 24
Peak memory 241272 kb
Host smart-5e97c7e9-fb6f-4e4d-b2c9-e267d3108cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832871788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.3832871788
Directory /workspace/91.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/92.otp_ctrl_init_fail.2820372768
Short name T178
Test name
Test status
Simulation time 381385791 ps
CPU time 4.32 seconds
Started Mar 21 03:29:56 PM PDT 24
Finished Mar 21 03:30:00 PM PDT 24
Peak memory 241504 kb
Host smart-52263601-3049-4027-b6d5-8ff5ac5d4e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820372768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.2820372768
Directory /workspace/92.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/92.otp_ctrl_parallel_lc_esc.1624307898
Short name T1191
Test name
Test status
Simulation time 1671352991 ps
CPU time 27.54 seconds
Started Mar 21 03:30:02 PM PDT 24
Finished Mar 21 03:30:29 PM PDT 24
Peak memory 241452 kb
Host smart-78edf8c5-2fc6-447c-a0df-74cd22190a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624307898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.1624307898
Directory /workspace/92.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/92.otp_ctrl_stress_all_with_rand_reset.4173782739
Short name T342
Test name
Test status
Simulation time 559934491862 ps
CPU time 1820.37 seconds
Started Mar 21 03:30:04 PM PDT 24
Finished Mar 21 04:00:26 PM PDT 24
Peak memory 373092 kb
Host smart-1963e5a0-9e72-4685-8d0b-46cfcf50f3e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173782739 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_stress_all_with_rand_reset.4173782739
Directory /workspace/92.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.otp_ctrl_init_fail.1738515784
Short name T424
Test name
Test status
Simulation time 1890386972 ps
CPU time 4.76 seconds
Started Mar 21 03:29:56 PM PDT 24
Finished Mar 21 03:30:01 PM PDT 24
Peak memory 241372 kb
Host smart-0a05d381-312a-45c3-ab47-3b61f0f001f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738515784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.1738515784
Directory /workspace/93.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/93.otp_ctrl_parallel_lc_esc.890529655
Short name T584
Test name
Test status
Simulation time 715946370 ps
CPU time 15.44 seconds
Started Mar 21 03:30:06 PM PDT 24
Finished Mar 21 03:30:22 PM PDT 24
Peak memory 241792 kb
Host smart-42821823-1537-4e73-8b1d-880914001c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890529655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.890529655
Directory /workspace/93.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/93.otp_ctrl_stress_all_with_rand_reset.2909344062
Short name T295
Test name
Test status
Simulation time 24479844955 ps
CPU time 525.64 seconds
Started Mar 21 03:29:58 PM PDT 24
Finished Mar 21 03:38:43 PM PDT 24
Peak memory 258024 kb
Host smart-520d5209-180d-4197-b3c0-d45d3dd3a7b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909344062 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_stress_all_with_rand_reset.2909344062
Directory /workspace/93.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.otp_ctrl_init_fail.2519310534
Short name T773
Test name
Test status
Simulation time 584335456 ps
CPU time 5.41 seconds
Started Mar 21 03:29:51 PM PDT 24
Finished Mar 21 03:29:58 PM PDT 24
Peak memory 241376 kb
Host smart-efb2d229-dbb7-4d13-9210-35e014843098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519310534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.2519310534
Directory /workspace/94.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/94.otp_ctrl_parallel_lc_esc.4236067751
Short name T824
Test name
Test status
Simulation time 4496187477 ps
CPU time 10.44 seconds
Started Mar 21 03:30:03 PM PDT 24
Finished Mar 21 03:30:14 PM PDT 24
Peak memory 241456 kb
Host smart-bb40117b-bca1-485c-b827-34337420d73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236067751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.4236067751
Directory /workspace/94.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.2497715526
Short name T302
Test name
Test status
Simulation time 7471374890 ps
CPU time 139.5 seconds
Started Mar 21 03:30:02 PM PDT 24
Finished Mar 21 03:32:23 PM PDT 24
Peak memory 258652 kb
Host smart-af3e2447-3d8e-4a15-a388-d3b8c22c9033
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497715526 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_stress_all_with_rand_reset.2497715526
Directory /workspace/94.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.otp_ctrl_init_fail.3919938410
Short name T972
Test name
Test status
Simulation time 115452454 ps
CPU time 4.6 seconds
Started Mar 21 03:29:57 PM PDT 24
Finished Mar 21 03:30:01 PM PDT 24
Peak memory 241436 kb
Host smart-426c9a8c-0294-4ff8-ab43-e94637ae6a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919938410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.3919938410
Directory /workspace/95.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/95.otp_ctrl_parallel_lc_esc.2015171664
Short name T834
Test name
Test status
Simulation time 581666204 ps
CPU time 9.23 seconds
Started Mar 21 03:30:03 PM PDT 24
Finished Mar 21 03:30:14 PM PDT 24
Peak memory 241308 kb
Host smart-7b7be46d-18f8-4d6b-9168-dca02095b71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015171664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.2015171664
Directory /workspace/95.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/96.otp_ctrl_init_fail.528262780
Short name T1160
Test name
Test status
Simulation time 421273077 ps
CPU time 5.07 seconds
Started Mar 21 03:30:05 PM PDT 24
Finished Mar 21 03:30:11 PM PDT 24
Peak memory 241368 kb
Host smart-5275dcb0-f3d1-488c-be1d-4c7786d4468b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528262780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.528262780
Directory /workspace/96.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/96.otp_ctrl_parallel_lc_esc.3805096257
Short name T1090
Test name
Test status
Simulation time 163850822 ps
CPU time 7.9 seconds
Started Mar 21 03:30:05 PM PDT 24
Finished Mar 21 03:30:13 PM PDT 24
Peak memory 241320 kb
Host smart-98ca3512-4e5b-403c-91a2-d4ecab515a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805096257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.3805096257
Directory /workspace/96.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/96.otp_ctrl_stress_all_with_rand_reset.394230036
Short name T670
Test name
Test status
Simulation time 300095474975 ps
CPU time 1051.53 seconds
Started Mar 21 03:29:58 PM PDT 24
Finished Mar 21 03:47:30 PM PDT 24
Peak memory 259180 kb
Host smart-f2d0570b-c0ff-4eea-86dc-f585d9441aae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394230036 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_stress_all_with_rand_reset.394230036
Directory /workspace/96.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.otp_ctrl_init_fail.458812179
Short name T702
Test name
Test status
Simulation time 341129542 ps
CPU time 4.17 seconds
Started Mar 21 03:30:04 PM PDT 24
Finished Mar 21 03:30:09 PM PDT 24
Peak memory 241404 kb
Host smart-9e11dcff-8e18-40cf-925b-0ccee88d8fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458812179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.458812179
Directory /workspace/97.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/97.otp_ctrl_parallel_lc_esc.1701546545
Short name T303
Test name
Test status
Simulation time 159517575 ps
CPU time 4.89 seconds
Started Mar 21 03:30:03 PM PDT 24
Finished Mar 21 03:30:08 PM PDT 24
Peak memory 241652 kb
Host smart-5c938d1c-24df-4280-b0a3-111434619646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701546545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.1701546545
Directory /workspace/97.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/97.otp_ctrl_stress_all_with_rand_reset.1939698687
Short name T42
Test name
Test status
Simulation time 45417903305 ps
CPU time 922.33 seconds
Started Mar 21 03:30:00 PM PDT 24
Finished Mar 21 03:45:23 PM PDT 24
Peak memory 362228 kb
Host smart-340885fb-4233-49ba-8ff2-cdd1e98d0eda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939698687 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_stress_all_with_rand_reset.1939698687
Directory /workspace/97.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.otp_ctrl_init_fail.19302830
Short name T929
Test name
Test status
Simulation time 329028419 ps
CPU time 4.61 seconds
Started Mar 21 03:30:02 PM PDT 24
Finished Mar 21 03:30:06 PM PDT 24
Peak memory 241404 kb
Host smart-7cf7766b-71ac-4483-abde-7a44e6022455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19302830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.19302830
Directory /workspace/98.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/98.otp_ctrl_parallel_lc_esc.974641739
Short name T549
Test name
Test status
Simulation time 637308776 ps
CPU time 5.86 seconds
Started Mar 21 03:30:01 PM PDT 24
Finished Mar 21 03:30:07 PM PDT 24
Peak memory 241224 kb
Host smart-5dafc474-e925-4f82-8366-6c2f8d3e5918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974641739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.974641739
Directory /workspace/98.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/99.otp_ctrl_init_fail.2427788836
Short name T191
Test name
Test status
Simulation time 100099714 ps
CPU time 3.73 seconds
Started Mar 21 03:30:03 PM PDT 24
Finished Mar 21 03:30:07 PM PDT 24
Peak memory 241348 kb
Host smart-b41afb0b-71ae-4ac8-b163-30551842a09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427788836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.2427788836
Directory /workspace/99.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/99.otp_ctrl_parallel_lc_esc.906805025
Short name T2
Test name
Test status
Simulation time 2122511255 ps
CPU time 31.62 seconds
Started Mar 21 03:30:01 PM PDT 24
Finished Mar 21 03:30:33 PM PDT 24
Peak memory 242260 kb
Host smart-083ffcbe-f02b-4270-8166-b0a47e67f5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906805025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.906805025
Directory /workspace/99.otp_ctrl_parallel_lc_esc/latest
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