Summary for Variable operation_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for operation_type
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
read_op |
29225 |
1 |
|
|
T1 |
17 |
|
T3 |
4 |
|
T9 |
9 |
write_op |
6789 |
1 |
|
|
T1 |
1 |
|
T3 |
2 |
|
T9 |
4 |
Summary for Variable read_access_locked
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for read_access_locked
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11785 |
1 |
|
|
T1 |
2 |
|
T3 |
6 |
|
T9 |
4 |
auto[1] |
24229 |
1 |
|
|
T1 |
16 |
|
T9 |
9 |
|
T5 |
64 |
Summary for Variable write_access_locked
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for write_access_locked
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
26375 |
1 |
|
|
T1 |
18 |
|
T3 |
6 |
|
T9 |
13 |
auto[1] |
9639 |
1 |
|
|
T5 |
52 |
|
T27 |
47 |
|
T92 |
3 |
Summary for Cross unbuf_part_access_cross
Samples crossed: read_access_locked write_access_locked operation_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for unbuf_part_access_cross
Bins
read_access_locked | write_access_locked | operation_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
read_op |
5244 |
1 |
|
|
T1 |
1 |
|
T3 |
4 |
|
T9 |
2 |
auto[0] |
auto[0] |
write_op |
2890 |
1 |
|
|
T1 |
1 |
|
T3 |
2 |
|
T9 |
2 |
auto[0] |
auto[1] |
read_op |
2789 |
1 |
|
|
T5 |
14 |
|
T27 |
15 |
|
T28 |
11 |
auto[0] |
auto[1] |
write_op |
862 |
1 |
|
|
T5 |
2 |
|
T27 |
6 |
|
T28 |
1 |
auto[1] |
auto[0] |
read_op |
16160 |
1 |
|
|
T1 |
16 |
|
T9 |
7 |
|
T5 |
23 |
auto[1] |
auto[0] |
write_op |
2081 |
1 |
|
|
T9 |
2 |
|
T5 |
5 |
|
T6 |
11 |
auto[1] |
auto[1] |
read_op |
5032 |
1 |
|
|
T5 |
30 |
|
T27 |
20 |
|
T92 |
2 |
auto[1] |
auto[1] |
write_op |
956 |
1 |
|
|
T5 |
6 |
|
T27 |
6 |
|
T92 |
1 |
Summary for Variable operation_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for operation_type
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
read_op |
29985 |
1 |
|
|
T1 |
7 |
|
T2 |
4 |
|
T3 |
1 |
write_op |
6618 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable read_access_locked
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for read_access_locked
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12004 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
2 |
auto[1] |
24599 |
1 |
|
|
T1 |
7 |
|
T2 |
4 |
|
T9 |
12 |
Summary for Variable write_access_locked
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for write_access_locked
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
29986 |
1 |
|
|
T1 |
8 |
|
T2 |
6 |
|
T3 |
2 |
auto[1] |
6617 |
1 |
|
|
T5 |
44 |
|
T27 |
29 |
|
T28 |
32 |
Summary for Cross unbuf_part_access_cross
Samples crossed: read_access_locked write_access_locked operation_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for unbuf_part_access_cross
Bins
read_access_locked | write_access_locked | operation_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
read_op |
6313 |
1 |
|
|
T3 |
1 |
|
T4 |
4 |
|
T11 |
8 |
auto[0] |
auto[0] |
write_op |
3193 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
auto[0] |
auto[1] |
read_op |
1912 |
1 |
|
|
T5 |
18 |
|
T27 |
7 |
|
T28 |
7 |
auto[0] |
auto[1] |
write_op |
586 |
1 |
|
|
T5 |
4 |
|
T27 |
4 |
|
T28 |
2 |
auto[1] |
auto[0] |
read_op |
18272 |
1 |
|
|
T1 |
7 |
|
T2 |
4 |
|
T9 |
10 |
auto[1] |
auto[0] |
write_op |
2208 |
1 |
|
|
T9 |
2 |
|
T5 |
4 |
|
T6 |
21 |
auto[1] |
auto[1] |
read_op |
3488 |
1 |
|
|
T5 |
20 |
|
T27 |
15 |
|
T28 |
19 |
auto[1] |
auto[1] |
write_op |
631 |
1 |
|
|
T5 |
2 |
|
T27 |
3 |
|
T28 |
4 |
Summary for Variable operation_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for operation_type
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
read_op |
29591 |
1 |
|
|
T1 |
5 |
|
T2 |
2 |
|
T3 |
5 |
write_op |
7071 |
1 |
|
|
T1 |
1 |
|
T9 |
2 |
|
T4 |
2 |
Summary for Variable read_access_locked
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for read_access_locked
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12110 |
1 |
|
|
T1 |
3 |
|
T3 |
5 |
|
T4 |
6 |
auto[1] |
24552 |
1 |
|
|
T1 |
3 |
|
T2 |
2 |
|
T9 |
7 |
Summary for Variable write_access_locked
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for write_access_locked
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
26956 |
1 |
|
|
T1 |
6 |
|
T2 |
2 |
|
T3 |
5 |
auto[1] |
9706 |
1 |
|
|
T5 |
54 |
|
T92 |
12 |
|
T28 |
16 |
Summary for Cross unbuf_part_access_cross
Samples crossed: read_access_locked write_access_locked operation_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for unbuf_part_access_cross
Bins
read_access_locked | write_access_locked | operation_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
read_op |
5438 |
1 |
|
|
T1 |
2 |
|
T3 |
5 |
|
T4 |
4 |
auto[0] |
auto[0] |
write_op |
3082 |
1 |
|
|
T1 |
1 |
|
T4 |
2 |
|
T11 |
6 |
auto[0] |
auto[1] |
read_op |
2682 |
1 |
|
|
T5 |
18 |
|
T92 |
3 |
|
T28 |
4 |
auto[0] |
auto[1] |
write_op |
908 |
1 |
|
|
T5 |
3 |
|
T92 |
2 |
|
T28 |
2 |
auto[1] |
auto[0] |
read_op |
16273 |
1 |
|
|
T1 |
3 |
|
T2 |
2 |
|
T9 |
5 |
auto[1] |
auto[0] |
write_op |
2163 |
1 |
|
|
T9 |
2 |
|
T5 |
7 |
|
T6 |
14 |
auto[1] |
auto[1] |
read_op |
5198 |
1 |
|
|
T5 |
26 |
|
T92 |
7 |
|
T28 |
9 |
auto[1] |
auto[1] |
write_op |
918 |
1 |
|
|
T5 |
7 |
|
T28 |
1 |
|
T94 |
4 |
Summary for Variable operation_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for operation_type
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
read_op |
28816 |
1 |
|
|
T1 |
7 |
|
T2 |
2 |
|
T3 |
6 |
write_op |
4945 |
1 |
|
|
T3 |
1 |
|
T9 |
1 |
|
T4 |
4 |
Summary for Variable read_access_locked
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for read_access_locked
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10688 |
1 |
|
|
T3 |
7 |
|
T4 |
14 |
|
T11 |
18 |
auto[1] |
23073 |
1 |
|
|
T1 |
7 |
|
T2 |
2 |
|
T9 |
1 |
Summary for Variable write_access_locked
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for write_access_locked
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
30321 |
1 |
|
|
T1 |
7 |
|
T2 |
2 |
|
T3 |
7 |
auto[1] |
3440 |
1 |
|
|
T92 |
7 |
|
T105 |
7 |
|
T101 |
14 |
Summary for Cross unbuf_part_access_cross
Samples crossed: read_access_locked write_access_locked operation_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for unbuf_part_access_cross
Bins
read_access_locked | write_access_locked | operation_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
read_op |
6759 |
1 |
|
|
T3 |
6 |
|
T4 |
10 |
|
T11 |
12 |
auto[0] |
auto[0] |
write_op |
2706 |
1 |
|
|
T3 |
1 |
|
T4 |
4 |
|
T11 |
6 |
auto[0] |
auto[1] |
read_op |
987 |
1 |
|
|
T92 |
3 |
|
T105 |
2 |
|
T101 |
1 |
auto[0] |
auto[1] |
write_op |
236 |
1 |
|
|
T92 |
1 |
|
T105 |
1 |
|
T101 |
1 |
auto[1] |
auto[0] |
read_op |
19077 |
1 |
|
|
T1 |
7 |
|
T2 |
2 |
|
T5 |
55 |
auto[1] |
auto[0] |
write_op |
1779 |
1 |
|
|
T9 |
1 |
|
T5 |
5 |
|
T6 |
6 |
auto[1] |
auto[1] |
read_op |
1993 |
1 |
|
|
T92 |
2 |
|
T105 |
3 |
|
T101 |
10 |
auto[1] |
auto[1] |
write_op |
224 |
1 |
|
|
T92 |
1 |
|
T105 |
1 |
|
T101 |
2 |
Summary for Variable operation_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for operation_type
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
read_op |
28380 |
1 |
|
|
T1 |
15 |
|
T3 |
5 |
|
T9 |
7 |
write_op |
6204 |
1 |
|
|
T2 |
1 |
|
T3 |
2 |
|
T9 |
1 |
Summary for Variable read_access_locked
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for read_access_locked
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11198 |
1 |
|
|
T1 |
3 |
|
T2 |
1 |
|
T3 |
7 |
auto[1] |
23386 |
1 |
|
|
T1 |
12 |
|
T9 |
6 |
|
T5 |
41 |
Summary for Variable write_access_locked
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for write_access_locked
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
25149 |
1 |
|
|
T1 |
15 |
|
T2 |
1 |
|
T3 |
7 |
auto[1] |
9435 |
1 |
|
|
T5 |
47 |
|
T27 |
39 |
|
T92 |
5 |
Summary for Cross unbuf_part_access_cross
Samples crossed: read_access_locked write_access_locked operation_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for unbuf_part_access_cross
Bins
read_access_locked | write_access_locked | operation_type | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
read_op |
4958 |
1 |
|
|
T1 |
3 |
|
T3 |
5 |
|
T9 |
2 |
auto[0] |
auto[0] |
write_op |
2760 |
1 |
|
|
T2 |
1 |
|
T3 |
2 |
|
T4 |
3 |
auto[0] |
auto[1] |
read_op |
2700 |
1 |
|
|
T5 |
7 |
|
T27 |
7 |
|
T92 |
1 |
auto[0] |
auto[1] |
write_op |
780 |
1 |
|
|
T5 |
1 |
|
T27 |
2 |
|
T92 |
1 |
auto[1] |
auto[0] |
read_op |
15550 |
1 |
|
|
T1 |
12 |
|
T9 |
5 |
|
T5 |
2 |
auto[1] |
auto[0] |
write_op |
1881 |
1 |
|
|
T9 |
1 |
|
T6 |
15 |
|
T92 |
1 |
auto[1] |
auto[1] |
read_op |
5172 |
1 |
|
|
T5 |
35 |
|
T27 |
28 |
|
T92 |
3 |
auto[1] |
auto[1] |
write_op |
783 |
1 |
|
|
T5 |
4 |
|
T27 |
2 |
|
T28 |
3 |