Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7540228	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7194552

1

T1

1217

T2

303

T3

392

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8875514	1			T1	3010		T2	737		T3	1129
values[0x0]	2237607	1			T1	168		T2	53		T3	54
values[0x1]	3621659	1			T1	174		T2	46		T3	57

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4958923	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

9775857

1

T1

1719

T2

432

T3

597

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53704	1			T2	3		T3	5		T9	10
valid_sources[0x01]	50003	1			T3	3		T9	7		T10	9
valid_sources[0x02]	123460	1			T3	1		T9	5		T10	11
valid_sources[0x03]	54596	1			T3	8		T9	8		T10	17
valid_sources[0x04]	53318	1			T2	2		T3	5		T9	8
valid_sources[0x05]	157212	1			T3	4		T10	17		T11	14
valid_sources[0x06]	49037	1			T3	9		T9	2		T10	13
valid_sources[0x07]	51167	1			T2	2		T3	6		T9	2
valid_sources[0x08]	53832	1			T2	4		T3	1		T9	11
valid_sources[0x09]	61596	1			T2	7		T3	2		T9	14
valid_sources[0x0a]	49305	1			T2	11		T3	1		T9	14
valid_sources[0x0b]	59140	1			T2	2		T3	2		T9	2
valid_sources[0x0c]	49670	1			T2	4		T3	4		T9	5
valid_sources[0x0d]	51500	1			T2	2		T3	2		T9	9
valid_sources[0x0e]	50267	1			T3	4		T9	5		T10	16
valid_sources[0x0f]	54224	1			T2	2		T3	7		T9	11
valid_sources[0x10]	61544	1			T3	4		T9	3		T10	10
valid_sources[0x11]	50711	1			T2	1		T3	4		T9	2
valid_sources[0x12]	61457	1			T2	1		T3	4		T9	6
valid_sources[0x13]	49968	1			T2	3		T3	2		T9	8
valid_sources[0x14]	51593	1			T2	6		T3	2		T10	10
valid_sources[0x15]	54026	1			T3	1		T9	17		T10	11
valid_sources[0x16]	56545	1			T3	8		T9	11		T10	11
valid_sources[0x17]	58164	1			T2	4		T3	6		T9	5
valid_sources[0x18]	55505	1			T2	5		T3	6		T9	2
valid_sources[0x19]	53358	1			T2	2		T3	3		T9	3
valid_sources[0x1a]	49148	1			T2	2		T3	1		T9	6
valid_sources[0x1b]	51283	1			T2	4		T3	8		T9	14
valid_sources[0x1c]	69823	1			T2	3		T3	5		T9	7
valid_sources[0x1d]	52247	1			T2	4		T3	4		T9	15
valid_sources[0x1e]	60182	1			T2	6		T3	4		T9	5
valid_sources[0x1f]	55053	1			T2	7		T3	1		T9	8
valid_sources[0x20]	51365	1			T2	1		T3	4		T9	3
valid_sources[0x21]	54380	1			T2	15		T3	1		T9	5
valid_sources[0x22]	52020	1			T2	3		T3	2		T9	2
valid_sources[0x23]	52499	1			T2	3		T3	4		T9	6
valid_sources[0x24]	48992	1			T2	7		T3	10		T9	6
valid_sources[0x25]	56313	1			T3	9		T9	4		T10	17
valid_sources[0x26]	53279	1			T2	4		T9	5		T10	9
valid_sources[0x27]	66455	1			T2	2		T3	3		T9	9
valid_sources[0x28]	54798	1			T2	11		T3	8		T9	10
valid_sources[0x29]	51219	1			T2	4		T3	7		T9	4
valid_sources[0x2a]	55454	1			T2	4		T3	6		T9	4
valid_sources[0x2b]	53559	1			T3	5		T9	10		T10	19
valid_sources[0x2c]	69246	1			T3	2		T9	7		T10	16
valid_sources[0x2d]	59065	1			T2	1		T3	2		T9	7
valid_sources[0x2e]	54883	1			T2	2		T3	11		T9	16
valid_sources[0x2f]	52140	1			T2	1		T3	3		T9	8
valid_sources[0x30]	57638	1			T3	3		T9	6		T10	14
valid_sources[0x31]	52967	1			T2	4		T3	6		T9	3
valid_sources[0x32]	54098	1			T2	5		T3	2		T9	11
valid_sources[0x33]	48918	1			T2	3		T3	1		T9	12
valid_sources[0x34]	52808	1			T2	9		T3	5		T9	12
valid_sources[0x35]	57230	1			T3	3		T9	7		T10	12
valid_sources[0x36]	71048	1			T2	2		T3	1		T9	8
valid_sources[0x37]	53810	1			T2	7		T3	2		T9	9
valid_sources[0x38]	59970	1			T3	3		T9	12		T10	4
valid_sources[0x39]	54806	1			T2	1		T3	2		T9	2
valid_sources[0x3a]	56966	1			T3	3		T9	8		T10	8
valid_sources[0x3b]	50486	1			T2	1		T3	4		T9	13
valid_sources[0x3c]	54442	1			T2	5		T3	1		T9	3
valid_sources[0x3d]	64102	1			T2	1		T3	4		T9	9
valid_sources[0x3e]	51550	1			T2	1		T3	5		T9	3
valid_sources[0x3f]	64232	1			T1	3352		T2	2		T3	4
valid_sources[0x40]	52593	1			T2	6		T3	3		T9	9
valid_sources[0x41]	52562	1			T2	3		T3	3		T9	8
valid_sources[0x42]	67956	1			T3	14		T9	1		T10	13
valid_sources[0x43]	55045	1			T2	2		T3	5		T9	6
valid_sources[0x44]	54387	1			T3	1		T9	11		T10	12
valid_sources[0x45]	62514	1			T2	3		T3	2		T9	3
valid_sources[0x46]	51750	1			T2	6		T3	2		T9	5
valid_sources[0x47]	60658	1			T2	2		T3	5		T9	5
valid_sources[0x48]	59204	1			T2	2		T3	7		T9	17
valid_sources[0x49]	55369	1			T3	6		T9	7		T10	17
valid_sources[0x4a]	51145	1			T2	5		T3	7		T9	5
valid_sources[0x4b]	52433	1			T2	3		T9	7		T10	13
valid_sources[0x4c]	55059	1			T3	3		T9	15		T10	21
valid_sources[0x4d]	60094	1			T2	2		T3	5		T9	6
valid_sources[0x4e]	50968	1			T2	1		T3	4		T9	7
valid_sources[0x4f]	49939	1			T2	4		T3	3		T9	12
valid_sources[0x50]	60141	1			T3	10		T9	3		T10	17
valid_sources[0x51]	50695	1			T2	13		T3	11		T9	8
valid_sources[0x52]	55678	1			T2	3		T3	3		T9	5
valid_sources[0x53]	74194	1			T2	3		T3	6		T9	9
valid_sources[0x54]	49079	1			T2	3		T3	5		T9	4
valid_sources[0x55]	51839	1			T3	4		T9	10		T10	16
valid_sources[0x56]	68412	1			T3	3		T9	10		T10	21
valid_sources[0x57]	54476	1			T3	1		T9	5		T10	20
valid_sources[0x58]	55337	1			T2	2		T3	8		T9	2
valid_sources[0x59]	50837	1			T2	1		T3	8		T10	19
valid_sources[0x5a]	53034	1			T2	9		T3	8		T9	8
valid_sources[0x5b]	62381	1			T3	1		T9	9		T10	14
valid_sources[0x5c]	51571	1			T2	5		T3	4		T9	5
valid_sources[0x5d]	50945	1			T3	5		T9	18		T10	22
valid_sources[0x5e]	51390	1			T2	3		T3	8		T9	9
valid_sources[0x5f]	69143	1			T3	10		T9	6		T10	17
valid_sources[0x60]	49130	1			T2	2		T3	2		T9	2
valid_sources[0x61]	49800	1			T2	5		T3	1		T9	11
valid_sources[0x62]	51054	1			T2	5		T3	8		T9	7
valid_sources[0x63]	55863	1			T2	3		T3	12		T9	10
valid_sources[0x64]	52392	1			T2	2		T3	5		T9	2
valid_sources[0x65]	51296	1			T2	7		T3	7		T9	3
valid_sources[0x66]	62386	1			T2	9		T3	4		T9	9
valid_sources[0x67]	71237	1			T2	5		T3	2		T9	2
valid_sources[0x68]	51523	1			T2	1		T3	7		T9	10
valid_sources[0x69]	51697	1			T2	2		T3	3		T9	2
valid_sources[0x6a]	172357	1			T2	1		T3	6		T9	7
valid_sources[0x6b]	52193	1			T2	1		T3	8		T9	4
valid_sources[0x6c]	54607	1			T3	2		T9	8		T10	10
valid_sources[0x6d]	69800	1			T2	3		T3	1		T10	18
valid_sources[0x6e]	51265	1			T2	1		T3	4		T9	11
valid_sources[0x6f]	51350	1			T3	8		T9	10		T10	17
valid_sources[0x70]	53701	1			T2	9		T3	10		T9	4
valid_sources[0x71]	48733	1			T2	5		T3	2		T9	1
valid_sources[0x72]	54771	1			T2	2		T3	2		T9	5
valid_sources[0x73]	50694	1			T2	9		T3	4		T9	2
valid_sources[0x74]	51874	1			T2	5		T3	3		T9	8
valid_sources[0x75]	52486	1			T2	4		T3	7		T9	17
valid_sources[0x76]	62592	1			T2	2		T3	2		T9	11
valid_sources[0x77]	53068	1			T2	1		T3	6		T9	10
valid_sources[0x78]	50478	1			T2	1		T3	3		T9	12
valid_sources[0x79]	50962	1			T2	6		T3	10		T9	6
valid_sources[0x7a]	49321	1			T3	5		T9	6		T10	19
valid_sources[0x7b]	60740	1			T2	19		T3	11		T9	2
valid_sources[0x7c]	63155	1			T2	4		T9	8		T10	12
valid_sources[0x7d]	52805	1			T2	10		T3	7		T9	11
valid_sources[0x7e]	76743	1			T2	9		T3	6		T9	2
valid_sources[0x7f]	50131	1			T2	5		T3	3		T9	6
valid_sources[0x80]	52461	1			T2	1		T3	2		T9	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3616148

1

T1

1081

T2

254

T3

349

values[0x0]

all_enables

biggest_size

1830066

1

T1

74

T2

29

T3

24

values[0x1]

all_enables

biggest_size

1748338

1

T1

62

T2

20

T3

19

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	238332	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

8435639

1

T1

160

T2

60

T3

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2162690	1			T1	80		T2	30		T3	10
values[0x0]	3161290	1			T1	44		T2	13		T3	6
values[0x1]	3349991	1			T1	36		T2	17		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	86175	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

8587796

1

T1

160

T2

60

T3

20

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	35305	1			T6	699		T8	623		T14	2470
valid_sources[0x01]	34887	1			T3	1		T6	618		T108	6
valid_sources[0x02]	32419	1			T5	1		T6	630		T27	1
valid_sources[0x03]	33376	1			T1	13		T5	1		T6	634
valid_sources[0x04]	33511	1			T6	629		T92	2		T8	625
valid_sources[0x05]	34391	1			T5	2		T6	620		T8	674
valid_sources[0x06]	33692	1			T6	676		T8	628		T14	1167
valid_sources[0x07]	33318	1			T6	682		T108	1		T27	2
valid_sources[0x08]	36837	1			T6	668		T108	2		T92	1
valid_sources[0x09]	35450	1			T3	1		T6	685		T8	658
valid_sources[0x0a]	33833	1			T5	1		T6	691		T27	1
valid_sources[0x0b]	31290	1			T6	676		T108	2		T92	1
valid_sources[0x0c]	33596	1			T6	584		T108	1		T27	2
valid_sources[0x0d]	31815	1			T6	661		T8	653		T100	8
valid_sources[0x0e]	33759	1			T2	1		T6	667		T92	2
valid_sources[0x0f]	31357	1			T6	686		T8	620		T15	1
valid_sources[0x10]	37938	1			T5	4		T6	644		T27	2
valid_sources[0x11]	36066	1			T6	718		T108	4		T27	1
valid_sources[0x12]	35369	1			T6	703		T8	686		T14	2116
valid_sources[0x13]	34676	1			T5	2		T6	605		T108	2
valid_sources[0x14]	33175	1			T5	2		T6	630		T8	715
valid_sources[0x15]	35174	1			T6	708		T92	3		T8	593
valid_sources[0x16]	31701	1			T5	1		T6	639		T8	628
valid_sources[0x17]	34008	1			T3	1		T6	716		T27	1
valid_sources[0x18]	35819	1			T1	38		T6	659		T108	2
valid_sources[0x19]	34509	1			T6	711		T27	1		T8	608
valid_sources[0x1a]	34952	1			T6	671		T27	1		T8	690
valid_sources[0x1b]	31246	1			T6	636		T108	3		T8	630
valid_sources[0x1c]	32435	1			T6	587		T8	594		T14	858
valid_sources[0x1d]	31830	1			T6	599		T92	2		T8	649
valid_sources[0x1e]	31505	1			T2	1		T6	602		T27	3
valid_sources[0x1f]	38348	1			T6	705		T8	642		T14	2910
valid_sources[0x20]	36759	1			T5	1		T50	40		T6	673
valid_sources[0x21]	34096	1			T6	588		T8	643		T15	1
valid_sources[0x22]	32549	1			T2	1		T6	667		T8	671
valid_sources[0x23]	32478	1			T2	2		T6	640		T92	1
valid_sources[0x24]	34614	1			T5	2		T6	692		T27	2
valid_sources[0x25]	37309	1			T5	3		T6	674		T28	4
valid_sources[0x26]	33476	1			T2	2		T6	588		T8	652
valid_sources[0x27]	32426	1			T6	694		T27	1		T8	657
valid_sources[0x28]	31853	1			T5	1		T6	623		T27	1
valid_sources[0x29]	36969	1			T6	645		T27	1		T8	627
valid_sources[0x2a]	35362	1			T5	3		T6	681		T8	603
valid_sources[0x2b]	32547	1			T2	1		T6	692		T8	645
valid_sources[0x2c]	30872	1			T6	639		T27	5		T92	1
valid_sources[0x2d]	34041	1			T6	602		T27	2		T28	7
valid_sources[0x2e]	33359	1			T5	2		T6	610		T108	9
valid_sources[0x2f]	33843	1			T5	1		T6	603		T92	1
valid_sources[0x30]	35735	1			T5	1		T6	652		T92	1
valid_sources[0x31]	33678	1			T6	658		T27	1		T8	669
valid_sources[0x32]	33942	1			T6	750		T8	626		T14	1902
valid_sources[0x33]	38034	1			T5	1		T6	637		T8	645
valid_sources[0x34]	32996	1			T2	1		T6	581		T108	8
valid_sources[0x35]	34507	1			T6	689		T27	2		T8	660
valid_sources[0x36]	35555	1			T6	681		T27	1		T8	656
valid_sources[0x37]	35810	1			T1	38		T6	676		T27	1
valid_sources[0x38]	32584	1			T6	577		T27	1		T8	691
valid_sources[0x39]	33406	1			T5	1		T6	682		T27	1
valid_sources[0x3a]	31613	1			T5	1		T6	679		T27	1
valid_sources[0x3b]	30590	1			T5	1		T6	731		T8	598
valid_sources[0x3c]	32996	1			T6	590		T92	1		T8	601
valid_sources[0x3d]	35390	1			T5	1		T6	646		T8	572
valid_sources[0x3e]	30463	1			T5	1		T6	619		T8	621
valid_sources[0x3f]	31266	1			T6	683		T8	691		T14	336
valid_sources[0x40]	36653	1			T13	200		T6	644		T8	634
valid_sources[0x41]	32792	1			T6	626		T108	1		T27	1
valid_sources[0x42]	31344	1			T6	676		T27	1		T8	704
valid_sources[0x43]	32523	1			T2	1		T6	623		T8	657
valid_sources[0x44]	33794	1			T5	2		T6	680		T27	4
valid_sources[0x45]	35978	1			T2	1		T5	2		T6	667
valid_sources[0x46]	39499	1			T5	2		T6	652		T8	635
valid_sources[0x47]	34397	1			T3	2		T6	714		T8	710
valid_sources[0x48]	37377	1			T5	1		T6	730		T8	664
valid_sources[0x49]	35777	1			T9	20		T5	3		T6	638
valid_sources[0x4a]	34316	1			T5	2		T6	713		T27	1
valid_sources[0x4b]	37134	1			T6	690		T8	709		T15	1
valid_sources[0x4c]	33521	1			T6	692		T92	1		T8	660
valid_sources[0x4d]	34223	1			T5	1		T6	643		T27	1
valid_sources[0x4e]	34305	1			T6	689		T8	657		T14	1297
valid_sources[0x4f]	34012	1			T6	649		T8	621		T14	1369
valid_sources[0x50]	30796	1			T5	1		T6	766		T8	662
valid_sources[0x51]	36473	1			T5	3		T6	714		T92	2
valid_sources[0x52]	30905	1			T6	686		T108	8		T27	3
valid_sources[0x53]	33282	1			T6	527		T108	4		T27	1
valid_sources[0x54]	34393	1			T6	639		T27	2		T28	8
valid_sources[0x55]	32825	1			T2	1		T6	688		T8	628
valid_sources[0x56]	35115	1			T5	1		T6	633		T8	638
valid_sources[0x57]	34139	1			T5	2		T6	619		T8	600
valid_sources[0x58]	34718	1			T5	1		T6	624		T8	623
valid_sources[0x59]	31317	1			T6	649		T8	588		T14	380
valid_sources[0x5a]	32824	1			T6	702		T27	1		T92	1
valid_sources[0x5b]	32842	1			T6	643		T8	672		T14	1711
valid_sources[0x5c]	34722	1			T2	1		T6	588		T8	643
valid_sources[0x5d]	34088	1			T3	2		T5	1		T6	624
valid_sources[0x5e]	32299	1			T6	643		T27	4		T8	650
valid_sources[0x5f]	35456	1			T5	2		T6	648		T8	591
valid_sources[0x60]	32131	1			T6	695		T92	1		T8	621
valid_sources[0x61]	33256	1			T2	3		T6	611		T8	646
valid_sources[0x62]	34270	1			T6	702		T27	1		T8	619
valid_sources[0x63]	31788	1			T2	1		T6	680		T92	1
valid_sources[0x64]	30524	1			T5	1		T6	686		T27	1
valid_sources[0x65]	34729	1			T2	1		T6	574		T108	3
valid_sources[0x66]	33272	1			T2	1		T5	1		T6	624
valid_sources[0x67]	32823	1			T6	652		T92	1		T8	607
valid_sources[0x68]	35266	1			T1	2		T2	1		T6	620
valid_sources[0x69]	32049	1			T6	655		T8	662		T14	1177
valid_sources[0x6a]	31530	1			T5	1		T6	656		T27	1
valid_sources[0x6b]	34235	1			T6	708		T8	735		T16	3
valid_sources[0x6c]	35140	1			T5	1		T6	614		T8	567
valid_sources[0x6d]	33248	1			T6	695		T27	2		T92	3
valid_sources[0x6e]	34930	1			T2	1		T3	3		T6	589
valid_sources[0x6f]	31233	1			T6	547		T8	642		T100	3
valid_sources[0x70]	34767	1			T5	2		T6	677		T8	737
valid_sources[0x71]	31952	1			T2	1		T5	2		T6	694
valid_sources[0x72]	31686	1			T5	3		T6	667		T8	702
valid_sources[0x73]	32763	1			T6	690		T27	1		T8	585
valid_sources[0x74]	35027	1			T5	3		T6	647		T92	1
valid_sources[0x75]	32653	1			T6	688		T27	4		T8	670
valid_sources[0x76]	32635	1			T3	1		T5	1		T6	664
valid_sources[0x77]	34266	1			T3	1		T5	1		T6	619
valid_sources[0x78]	30409	1			T6	668		T92	1		T8	678
valid_sources[0x79]	33185	1			T6	618		T8	601		T14	2002
valid_sources[0x7a]	32917	1			T6	630		T27	3		T92	1
valid_sources[0x7b]	31434	1			T5	1		T6	614		T27	2
valid_sources[0x7c]	31428	1			T5	2		T6	635		T27	2
valid_sources[0x7d]	34314	1			T6	670		T92	1		T8	696
valid_sources[0x7e]	33165	1			T2	1		T5	1		T6	720
valid_sources[0x7f]	31831	1			T6	653		T8	710		T15	2
valid_sources[0x80]	34718	1			T6	676		T27	1		T8	642

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2148883

1

T1

80

T2

30

T3

10

values[0x0]

all_enables

biggest_size

3145028

1

T1

44

T2

13

T3

6

values[0x1]

all_enables

biggest_size

3141728

1

T1

36

T2

17

T3

4