Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

24752825

1

T1

2135

T2

533

T3

848

full_word

8235842

1

T1

1217

T2

303

T3

392

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	32988367	1			T1	3352		T2	836		T3	1240
auto[TlIntgErrCmd]	111	1			T263	5		T264	3		T265	7
auto[TlIntgErrData]	108	1			T263	3		T264	3		T265	10
auto[TlIntgErrBoth]	81	1			T263	2		T264	4		T265	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10122208

1

T1

3010

T2

737

T3

1129

auto[1]

22866459

1

T1

342

T2

99

T3

111

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6379976	1			T1	1929		T2	483		T3	780
auto[TlIntgErrNone]	partial	auto[1]	18372570	1			T1	206		T2	50		T3	68
auto[TlIntgErrNone]	full_word	auto[0]	3742112	1			T1	1081		T2	254		T3	349
auto[TlIntgErrNone]	full_word	auto[1]	4493709	1			T1	136		T2	49		T3	43
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T263	2		T264	2		T265	2
auto[TlIntgErrCmd]	partial	auto[1]	65	1			T263	2		T265	5		T328	3
auto[TlIntgErrCmd]	full_word	auto[0]	8	1			T264	1		T334	2		T332	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T263	1		T335	1		-	-
auto[TlIntgErrData]	partial	auto[0]	41	1			T264	2		T265	4		T328	1
auto[TlIntgErrData]	partial	auto[1]	62	1			T263	3		T264	1		T265	6
auto[TlIntgErrData]	full_word	auto[0]	2	1			T336	1		T337	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	3	1			T333	1		T336	1		T338	1
auto[TlIntgErrBoth]	partial	auto[0]	31	1			T263	1		T264	1		T265	1
auto[TlIntgErrBoth]	partial	auto[1]	44	1			T263	1		T264	3		T265	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T339	1		T338	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T329	1		T333	1		T339	1