Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7304887	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7178112

1

T1

2478

T2

2933

T3

481

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8384932	1			T1	5899		T2	5211		T3	1215
values[0x0]	2313099	1			T1	345		T2	473		T3	79
values[0x1]	3784968	1			T1	324		T2	445		T3	88

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4719587	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

9763412

1

T1

3523

T2

3581

T3

709

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	50150	1			T8	8		T9	7		T10	79
valid_sources[0x01]	60137	1			T7	8		T8	2		T9	8
valid_sources[0x02]	50368	1			T8	3		T9	2		T10	57
valid_sources[0x03]	48675	1			T8	6		T9	1		T10	20
valid_sources[0x04]	58760	1			T7	6		T8	3		T10	51
valid_sources[0x05]	74533	1			T8	3		T9	5		T10	26
valid_sources[0x06]	51329	1			T7	4		T8	5		T9	8
valid_sources[0x07]	51139	1			T8	4		T9	4		T10	6
valid_sources[0x08]	55607	1			T8	3		T9	4		T10	6
valid_sources[0x09]	80406	1			T8	8		T10	28		T11	1
valid_sources[0x0a]	60097	1			T8	8		T9	1		T10	51
valid_sources[0x0b]	56512	1			T8	4		T9	5		T10	74
valid_sources[0x0c]	50155	1			T7	3		T8	5		T10	29
valid_sources[0x0d]	64808	1			T7	2		T8	5		T9	3
valid_sources[0x0e]	53512	1			T8	6		T9	12		T10	21
valid_sources[0x0f]	62240	1			T8	5		T10	26		T11	2
valid_sources[0x10]	56884	1			T8	9		T10	44		T11	2
valid_sources[0x11]	49963	1			T7	3		T8	4		T9	1
valid_sources[0x12]	63308	1			T7	4		T8	4		T9	3
valid_sources[0x13]	53209	1			T8	4		T9	3		T10	64
valid_sources[0x14]	48876	1			T7	8		T8	2		T10	6
valid_sources[0x15]	50158	1			T8	6		T10	37		T11	5
valid_sources[0x16]	64873	1			T8	5		T10	34		T11	1
valid_sources[0x17]	54013	1			T8	5		T10	14		T105	14
valid_sources[0x18]	54085	1			T8	4		T10	49		T11	2
valid_sources[0x19]	50406	1			T8	5		T9	5		T10	78
valid_sources[0x1a]	62116	1			T7	2		T8	7		T10	42
valid_sources[0x1b]	51191	1			T8	6		T9	4		T10	73
valid_sources[0x1c]	56661	1			T7	1		T8	5		T10	67
valid_sources[0x1d]	64201	1			T7	5		T8	1		T9	6
valid_sources[0x1e]	49616	1			T7	7		T8	13		T9	5
valid_sources[0x1f]	61619	1			T7	3		T8	7		T9	1
valid_sources[0x20]	48674	1			T8	7		T9	4		T10	48
valid_sources[0x21]	50517	1			T7	2		T8	6		T9	7
valid_sources[0x22]	49214	1			T7	4		T8	3		T9	3
valid_sources[0x23]	53872	1			T7	9		T8	3		T9	4
valid_sources[0x24]	50169	1			T8	7		T9	1		T10	66
valid_sources[0x25]	62952	1			T8	3		T9	4		T10	40
valid_sources[0x26]	58251	1			T8	4		T10	29		T12	37
valid_sources[0x27]	51697	1			T8	2		T10	30		T11	3
valid_sources[0x28]	51391	1			T8	4		T10	20		T11	1
valid_sources[0x29]	50702	1			T8	1		T9	8		T10	52
valid_sources[0x2a]	53874	1			T7	1		T8	5		T10	77
valid_sources[0x2b]	66849	1			T7	16		T8	2		T9	5
valid_sources[0x2c]	49766	1			T8	6		T10	21		T105	8
valid_sources[0x2d]	53708	1			T7	2		T8	3		T9	1
valid_sources[0x2e]	59690	1			T8	5		T9	7		T10	53
valid_sources[0x2f]	50505	1			T8	6		T10	40		T11	1
valid_sources[0x30]	49853	1			T8	6		T10	27		T11	6
valid_sources[0x31]	54096	1			T7	1		T8	8		T9	8
valid_sources[0x32]	49326	1			T7	4		T8	5		T9	2
valid_sources[0x33]	51458	1			T7	4		T8	8		T9	6
valid_sources[0x34]	67732	1			T7	1		T8	5		T9	1
valid_sources[0x35]	73861	1			T8	5		T9	1		T10	18
valid_sources[0x36]	51972	1			T8	7		T9	2		T10	17
valid_sources[0x37]	144680	1			T7	10		T8	6		T9	2
valid_sources[0x38]	50429	1			T8	3		T10	17		T11	2
valid_sources[0x39]	53969	1			T8	5		T10	67		T11	4
valid_sources[0x3a]	54881	1			T8	7		T10	44		T11	8
valid_sources[0x3b]	57707	1			T8	5		T9	3		T10	31
valid_sources[0x3c]	67564	1			T7	4		T8	9		T10	25
valid_sources[0x3d]	70190	1			T8	5		T9	1		T10	75
valid_sources[0x3e]	54636	1			T8	3		T9	1		T10	63
valid_sources[0x3f]	50756	1			T7	7		T8	5		T9	4
valid_sources[0x40]	50259	1			T7	2		T8	4		T9	11
valid_sources[0x41]	49010	1			T7	3		T8	8		T9	3
valid_sources[0x42]	53365	1			T7	10		T8	8		T9	2
valid_sources[0x43]	117437	1			T7	3		T8	4		T9	2
valid_sources[0x44]	69299	1			T5	7787		T8	4		T9	3
valid_sources[0x45]	50487	1			T8	5		T9	5		T10	33
valid_sources[0x46]	61530	1			T8	2		T9	2		T10	29
valid_sources[0x47]	53946	1			T7	16		T8	2		T9	3
valid_sources[0x48]	57518	1			T8	2		T9	1		T10	34
valid_sources[0x49]	54074	1			T8	1		T9	6		T10	34
valid_sources[0x4a]	54689	1			T7	1		T8	5		T10	18
valid_sources[0x4b]	51347	1			T7	1		T8	13		T10	31
valid_sources[0x4c]	56980	1			T8	6		T9	1		T10	70
valid_sources[0x4d]	55240	1			T7	5		T8	5		T9	4
valid_sources[0x4e]	53473	1			T7	4		T8	6		T10	16
valid_sources[0x4f]	52110	1			T8	7		T10	9		T11	1
valid_sources[0x50]	49695	1			T7	7		T8	4		T9	2
valid_sources[0x51]	54183	1			T8	9		T9	5		T10	72
valid_sources[0x52]	50242	1			T8	7		T9	6		T10	19
valid_sources[0x53]	74457	1			T3	1382		T7	1		T8	9
valid_sources[0x54]	51335	1			T8	9		T9	2		T10	30
valid_sources[0x55]	58403	1			T8	8		T9	3		T10	70
valid_sources[0x56]	66850	1			T8	6		T9	4		T10	28
valid_sources[0x57]	52563	1			T8	5		T9	11		T10	51
valid_sources[0x58]	57687	1			T7	2		T8	1		T9	1
valid_sources[0x59]	59650	1			T7	1		T8	4		T9	5
valid_sources[0x5a]	50031	1			T7	5		T8	3		T9	2
valid_sources[0x5b]	56493	1			T8	7		T9	5		T10	57
valid_sources[0x5c]	51369	1			T8	5		T10	13		T105	12
valid_sources[0x5d]	62659	1			T8	6		T10	24		T11	2
valid_sources[0x5e]	58436	1			T8	2		T9	2		T10	50
valid_sources[0x5f]	62122	1			T8	5		T10	46		T11	1
valid_sources[0x60]	55195	1			T7	7		T8	11		T9	1
valid_sources[0x61]	57134	1			T1	6568		T7	1		T8	3
valid_sources[0x62]	50375	1			T7	1		T8	8		T9	7
valid_sources[0x63]	50255	1			T7	5		T8	2		T10	74
valid_sources[0x64]	51298	1			T7	1		T8	5		T9	9
valid_sources[0x65]	52265	1			T8	3		T9	2		T10	89
valid_sources[0x66]	55884	1			T7	1		T8	2		T9	1
valid_sources[0x67]	51891	1			T8	5		T10	56		T11	2
valid_sources[0x68]	60944	1			T8	2		T10	13		T11	1
valid_sources[0x69]	59207	1			T7	1		T8	8		T9	1
valid_sources[0x6a]	112803	1			T8	5		T9	4		T10	64
valid_sources[0x6b]	54714	1			T7	2		T8	1		T9	6
valid_sources[0x6c]	53391	1			T8	4		T9	1		T10	3
valid_sources[0x6d]	52242	1			T8	6		T9	1		T10	82
valid_sources[0x6e]	53280	1			T8	9		T9	4		T10	50
valid_sources[0x6f]	52937	1			T7	5		T8	3		T9	2
valid_sources[0x70]	48985	1			T7	5		T8	3		T9	1
valid_sources[0x71]	50288	1			T7	7		T8	4		T9	4
valid_sources[0x72]	54622	1			T7	4		T8	1		T9	7
valid_sources[0x73]	150112	1			T7	4		T8	7		T9	5
valid_sources[0x74]	50953	1			T8	5		T10	27		T11	1
valid_sources[0x75]	53483	1			T8	7		T9	1		T10	67
valid_sources[0x76]	50118	1			T7	18		T8	1		T9	8
valid_sources[0x77]	48922	1			T7	8		T8	4		T9	7
valid_sources[0x78]	62713	1			T8	3		T10	22		T11	4
valid_sources[0x79]	52262	1			T8	3		T9	6		T10	18
valid_sources[0x7a]	48877	1			T7	2		T8	4		T9	2
valid_sources[0x7b]	56961	1			T7	10		T8	1		T9	7
valid_sources[0x7c]	51208	1			T8	6		T9	2		T10	31
valid_sources[0x7d]	49660	1			T7	8		T8	4		T10	83
valid_sources[0x7e]	49478	1			T8	3		T9	2		T10	2
valid_sources[0x7f]	57178	1			T8	2		T9	3		T10	49
valid_sources[0x80]	56418	1			T7	7		T8	4		T9	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3416464

1

T1

2201

T2

2522

T3

426

values[0x0]

all_enables

biggest_size

1920394

1

T1

180

T2

231

T3

34

values[0x1]

all_enables

biggest_size

1841254

1

T1

97

T2

180

T3

21

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	254542	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

9014927

1

T1

120

T2

20

T3

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2302783	1			T1	60		T2	10		T3	10
values[0x0]	3380006	1			T1	29		T2	4		T3	8
values[0x1]	3586680	1			T1	31		T2	6		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	91788	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

9177681

1

T1

120

T2

20

T3

20

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	35578	1			T109	2		T110	2		T35	3
valid_sources[0x01]	36487	1			T110	1		T6	414		T15	2
valid_sources[0x02]	33629	1			T10	1		T109	1		T110	2
valid_sources[0x03]	36515	1			T109	2		T110	2		T6	390
valid_sources[0x04]	36251	1			T6	401		T36	1		T98	5
valid_sources[0x05]	38012	1			T109	3		T35	4		T6	398
valid_sources[0x06]	36227	1			T110	2		T6	479		T36	2
valid_sources[0x07]	34360	1			T1	120		T110	1		T35	2
valid_sources[0x08]	37525	1			T108	1		T35	1		T6	484
valid_sources[0x09]	37111	1			T5	1		T109	1		T110	2
valid_sources[0x0a]	38350	1			T2	1		T42	5		T25	1
valid_sources[0x0b]	35901	1			T108	1		T6	423		T112	1
valid_sources[0x0c]	36985	1			T6	370		T36	5		T97	1
valid_sources[0x0d]	40479	1			T5	1		T10	1		T110	1
valid_sources[0x0e]	34105	1			T6	376		T36	6		T13	341
valid_sources[0x0f]	37743	1			T109	2		T6	431		T111	1
valid_sources[0x10]	37640	1			T25	1		T110	3		T6	438
valid_sources[0x11]	38839	1			T108	2		T6	360		T36	12
valid_sources[0x12]	35277	1			T25	1		T110	1		T6	448
valid_sources[0x13]	35334	1			T10	1		T109	1		T6	385
valid_sources[0x14]	37361	1			T10	1		T105	1		T35	1
valid_sources[0x15]	36896	1			T109	1		T6	355		T15	1
valid_sources[0x16]	34173	1			T108	4		T35	2		T6	376
valid_sources[0x17]	37304	1			T35	4		T6	369		T36	2
valid_sources[0x18]	37022	1			T2	1		T10	2		T108	2
valid_sources[0x19]	34042	1			T25	1		T110	2		T35	2
valid_sources[0x1a]	38573	1			T109	4		T35	2		T6	375
valid_sources[0x1b]	36234	1			T10	1		T6	456		T102	1
valid_sources[0x1c]	35667	1			T110	2		T6	417		T36	1
valid_sources[0x1d]	35756	1			T10	1		T6	396		T15	2
valid_sources[0x1e]	34928	1			T108	2		T110	1		T6	465
valid_sources[0x1f]	35883	1			T6	470		T111	1		T36	8
valid_sources[0x20]	34199	1			T42	14		T35	2		T6	436
valid_sources[0x21]	36426	1			T105	1		T109	1		T6	362
valid_sources[0x22]	34798	1			T108	3		T109	2		T110	2
valid_sources[0x23]	34031	1			T110	1		T6	435		T112	1
valid_sources[0x24]	36485	1			T2	2		T109	1		T110	1
valid_sources[0x25]	34606	1			T110	1		T6	406		T102	2
valid_sources[0x26]	33932	1			T25	1		T110	1		T6	404
valid_sources[0x27]	36982	1			T2	1		T10	4		T110	2
valid_sources[0x28]	36108	1			T10	2		T25	2		T109	1
valid_sources[0x29]	34430	1			T105	1		T109	1		T6	415
valid_sources[0x2a]	36996	1			T109	4		T110	4		T6	411
valid_sources[0x2b]	34239	1			T5	1		T42	23		T6	419
valid_sources[0x2c]	38743	1			T2	1		T35	1		T6	383
valid_sources[0x2d]	37888	1			T5	1		T108	2		T109	1
valid_sources[0x2e]	34313	1			T6	424		T102	2		T36	4
valid_sources[0x2f]	36870	1			T109	1		T6	414		T112	1
valid_sources[0x30]	33385	1			T2	1		T108	1		T110	1
valid_sources[0x31]	37330	1			T109	3		T6	337		T102	3
valid_sources[0x32]	34661	1			T109	1		T110	1		T6	413
valid_sources[0x33]	36769	1			T10	2		T25	2		T108	2
valid_sources[0x34]	37132	1			T5	1		T6	408		T36	2
valid_sources[0x35]	36031	1			T10	2		T25	1		T35	1
valid_sources[0x36]	33339	1			T6	411		T15	1		T36	2
valid_sources[0x37]	36047	1			T109	1		T35	1		T6	374
valid_sources[0x38]	39205	1			T10	2		T6	448		T36	3
valid_sources[0x39]	36132	1			T110	1		T6	383		T112	1
valid_sources[0x3a]	33832	1			T109	3		T110	2		T6	451
valid_sources[0x3b]	40515	1			T2	1		T25	1		T108	1
valid_sources[0x3c]	37140	1			T110	1		T6	422		T15	2
valid_sources[0x3d]	37904	1			T109	1		T6	388		T36	5
valid_sources[0x3e]	35197	1			T105	1		T109	1		T6	394
valid_sources[0x3f]	36842	1			T109	1		T6	404		T36	4
valid_sources[0x40]	38902	1			T109	1		T6	417		T15	1
valid_sources[0x41]	36533	1			T6	446		T36	6		T160	1
valid_sources[0x42]	37179	1			T6	418		T36	1		T26	12
valid_sources[0x43]	36181	1			T10	2		T109	2		T35	1
valid_sources[0x44]	39651	1			T25	1		T110	1		T6	404
valid_sources[0x45]	35289	1			T2	1		T6	471		T15	2
valid_sources[0x46]	37374	1			T109	1		T110	1		T6	382
valid_sources[0x47]	37518	1			T35	3		T6	430		T36	3
valid_sources[0x48]	38798	1			T110	2		T6	408		T102	6
valid_sources[0x49]	37173	1			T110	1		T35	1		T6	433
valid_sources[0x4a]	35150	1			T10	4		T110	1		T6	446
valid_sources[0x4b]	35798	1			T109	2		T6	357		T102	1
valid_sources[0x4c]	36162	1			T6	379		T36	3		T13	314
valid_sources[0x4d]	39641	1			T6	381		T36	5		T98	1
valid_sources[0x4e]	36114	1			T10	1		T109	1		T6	388
valid_sources[0x4f]	38269	1			T108	2		T109	1		T6	514
valid_sources[0x50]	36005	1			T10	1		T42	12		T110	3
valid_sources[0x51]	37637	1			T6	376		T36	3		T160	1
valid_sources[0x52]	35781	1			T2	1		T10	1		T6	359
valid_sources[0x53]	34334	1			T5	1		T10	12		T110	1
valid_sources[0x54]	36428	1			T110	2		T6	432		T112	1
valid_sources[0x55]	33791	1			T3	20		T110	1		T6	418
valid_sources[0x56]	37983	1			T105	1		T109	1		T35	2
valid_sources[0x57]	35569	1			T6	424		T15	1		T36	4
valid_sources[0x58]	39125	1			T110	2		T6	364		T102	2
valid_sources[0x59]	36013	1			T110	3		T6	450		T111	2
valid_sources[0x5a]	38513	1			T109	1		T110	1		T35	2
valid_sources[0x5b]	37867	1			T109	1		T110	4		T35	1
valid_sources[0x5c]	35445	1			T109	1		T110	1		T6	469
valid_sources[0x5d]	35892	1			T110	1		T6	359		T36	6
valid_sources[0x5e]	36456	1			T6	373		T15	1		T36	4
valid_sources[0x5f]	37047	1			T110	1		T6	420		T36	5
valid_sources[0x60]	37336	1			T10	2		T108	1		T6	375
valid_sources[0x61]	34404	1			T108	2		T109	3		T6	420
valid_sources[0x62]	35452	1			T42	3		T109	1		T6	376
valid_sources[0x63]	35070	1			T6	412		T15	1		T102	8
valid_sources[0x64]	34525	1			T5	1		T105	1		T109	1
valid_sources[0x65]	38041	1			T10	1		T108	1		T110	1
valid_sources[0x66]	36796	1			T110	1		T6	464		T102	1
valid_sources[0x67]	34582	1			T6	420		T111	1		T36	2
valid_sources[0x68]	34741	1			T2	1		T105	1		T110	1
valid_sources[0x69]	37565	1			T6	421		T15	1		T36	7
valid_sources[0x6a]	34561	1			T110	2		T35	1		T6	424
valid_sources[0x6b]	35735	1			T10	2		T109	1		T110	1
valid_sources[0x6c]	34982	1			T109	2		T6	374		T112	1
valid_sources[0x6d]	34868	1			T109	1		T110	2		T6	403
valid_sources[0x6e]	35917	1			T109	2		T6	399		T36	2
valid_sources[0x6f]	36497	1			T109	2		T6	413		T15	1
valid_sources[0x70]	35625	1			T110	4		T6	490		T112	1
valid_sources[0x71]	35641	1			T108	1		T109	1		T6	431
valid_sources[0x72]	36705	1			T10	6		T25	1		T108	1
valid_sources[0x73]	34569	1			T109	1		T6	397		T36	8
valid_sources[0x74]	35842	1			T6	426		T36	2		T160	2
valid_sources[0x75]	38073	1			T10	2		T110	1		T6	392
valid_sources[0x76]	37483	1			T108	1		T35	1		T6	445
valid_sources[0x77]	35680	1			T6	385		T36	4		T160	1
valid_sources[0x78]	36824	1			T110	4		T6	411		T15	1
valid_sources[0x79]	36341	1			T10	1		T12	20		T109	1
valid_sources[0x7a]	36391	1			T10	1		T109	1		T6	489
valid_sources[0x7b]	37289	1			T108	1		T110	1		T6	403
valid_sources[0x7c]	36466	1			T108	1		T6	399		T36	4
valid_sources[0x7d]	35623	1			T25	1		T110	1		T6	425
valid_sources[0x7e]	35776	1			T6	365		T15	1		T36	2
valid_sources[0x7f]	36968	1			T10	1		T35	2		T6	414
valid_sources[0x80]	36466	1			T109	2		T6	440		T36	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2289188

1

T1

60

T2

10

T3

10

values[0x0]

all_enables

biggest_size

3362595

1

T1

29

T2

4

T3

8

values[0x1]

all_enables

biggest_size

3363144

1

T1

31

T2

6

T3

2