Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

25750399

1

T1

4090

T2

3196

T3

901

full_word

8301280

1

T1

2478

T2

2933

T3

481

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	34051379	1			T1	6568		T2	6129		T3	1382
auto[TlIntgErrCmd]	90	1			T262	8		T263	4		T264	5
auto[TlIntgErrData]	117	1			T262	6		T263	4		T264	3
auto[TlIntgErrBoth]	93	1			T262	6		T263	2		T264	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9734192

1

T1

5899

T2

5211

T3

1215

auto[1]

24317487

1

T1

669

T2

918

T3

167

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6179813	1			T1	3698		T2	2689		T3	789
auto[TlIntgErrNone]	partial	auto[1]	19570311	1			T1	392		T2	507		T3	112
auto[TlIntgErrNone]	full_word	auto[0]	3554238	1			T1	2201		T2	2522		T3	426
auto[TlIntgErrNone]	full_word	auto[1]	4747017	1			T1	277		T2	411		T3	55
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T262	2		T264	2		T270	1
auto[TlIntgErrCmd]	partial	auto[1]	45	1			T262	3		T263	4		T264	3
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T262	2		T364	2		T371	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T262	1		T364	1		T372	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T262	3		T263	1		T264	1
auto[TlIntgErrData]	partial	auto[1]	54	1			T262	1		T263	2		T264	1
auto[TlIntgErrData]	full_word	auto[0]	8	1			T262	2		T263	1		T364	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T264	1		T270	1		T373	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T262	2		T270	3		T367	2
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T262	4		T263	2		T264	2
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T370	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T364	1		T269	1		-	-