Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	98.05	96.15	97.04		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	454397098	8123284	0	0
check_regwen_rd_A	454397098	3200	0	0
check_timeout_rd_A	454397098	2193	0	0
check_trigger_regwen_rd_A	454397098	2989	0	0
consistency_check_period_rd_A	454397098	3046	0	0
creator_sw_cfg_read_lock_rd_A	454397098	2330	0	0
direct_access_address_rd_A	454397098	1965	0	0
direct_access_wdata_0_rd_A	454397098	1256	0	0
direct_access_wdata_1_rd_A	454397098	1419	0	0
integrity_check_period_rd_A	454397098	3085	0	0
intr_enable_rd_A	454397098	3876	0	0
owner_sw_cfg_read_lock_rd_A	454397098	2025	0	0
rot_creator_auth_codesign_read_lock_rd_A	454397098	2273	0	0
rot_creator_auth_state_read_lock_rd_A	454397098	2015	0	0
vendor_test_read_lock_rd_A	454397098	2055	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454397098	8123284	0	0
T6	866796	91460	0	0
T13	0	76101	0	0
T14	0	169669	0	0
T15	84965	0	0	0
T24	0	81088	0	0
T34	0	29433	0	0
T36	103070	0	0	0
T102	45586	0	0	0
T111	49156	0	0	0
T112	106410	0	0	0
T144	0	22796	0	0
T160	197142	0	0	0
T165	21268	0	0	0
T166	30791	0	0	0
T174	11688	0	0	0
T212	0	88796	0	0
T254	0	85613	0	0
T271	0	113139	0	0
T272	0	159289	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454397098	3200	0	0
T50	14315	0	0	0
T52	55739	0	0	0
T89	63468	0	0	0
T90	9993	0	0	0
T91	15503	0	0	0
T92	11488	0	0	0
T93	133763	0	0	0
T94	57364	0	0	0
T95	18693	0	0	0
T143	0	141	0	0
T144	119316	38	0	0
T145	0	148	0	0
T180	0	139	0	0
T249	0	172	0	0
T254	0	145	0	0
T337	0	52	0	0
T343	0	49	0	0
T344	0	61	0	0
T345	0	22	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454397098	2193	0	0
T50	14315	0	0	0
T52	55739	0	0	0
T89	63468	0	0	0
T90	9993	0	0	0
T91	15503	0	0	0
T92	11488	0	0	0
T93	133763	0	0	0
T94	57364	0	0	0
T95	18693	0	0	0
T143	0	110	0	0
T144	119316	13	0	0
T145	0	121	0	0
T180	0	146	0	0
T249	0	215	0	0
T254	0	90	0	0
T337	0	57	0	0
T343	0	59	0	0
T344	0	71	0	0
T345	0	13	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454397098	2989	0	0
T50	14315	0	0	0
T52	55739	0	0	0
T89	63468	0	0	0
T90	9993	0	0	0
T91	15503	0	0	0
T92	11488	0	0	0
T93	133763	0	0	0
T94	57364	0	0	0
T95	18693	0	0	0
T143	0	126	0	0
T144	119316	19	0	0
T145	0	75	0	0
T180	0	143	0	0
T249	0	149	0	0
T254	0	127	0	0
T337	0	56	0	0
T343	0	47	0	0
T344	0	26	0	0
T345	0	7	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454397098	3046	0	0
T50	14315	0	0	0
T52	55739	0	0	0
T89	63468	0	0	0
T90	9993	0	0	0
T91	15503	0	0	0
T92	11488	0	0	0
T93	133763	0	0	0
T94	57364	0	0	0
T95	18693	0	0	0
T143	0	116	0	0
T144	119316	21	0	0
T145	0	103	0	0
T180	0	158	0	0
T249	0	180	0	0
T254	0	133	0	0
T337	0	58	0	0
T343	0	69	0	0
T344	0	79	0	0
T345	0	15	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454397098	2330	0	0
T50	14315	0	0	0
T52	55739	0	0	0
T89	63468	0	0	0
T90	9993	0	0	0
T91	15503	0	0	0
T92	11488	0	0	0
T93	133763	0	0	0
T94	57364	0	0	0
T95	18693	0	0	0
T143	0	138	0	0
T144	119316	7	0	0
T145	0	97	0	0
T180	0	201	0	0
T249	0	217	0	0
T254	0	105	0	0
T337	0	39	0	0
T343	0	59	0	0
T344	0	75	0	0
T345	0	30	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454397098	1965	0	0
T50	14315	0	0	0
T52	55739	0	0	0
T89	63468	0	0	0
T90	9993	0	0	0
T91	15503	0	0	0
T92	11488	0	0	0
T93	133763	0	0	0
T94	57364	0	0	0
T95	18693	0	0	0
T143	0	166	0	0
T144	119316	9	0	0
T145	0	96	0	0
T180	0	150	0	0
T249	0	208	0	0
T254	0	145	0	0
T337	0	56	0	0
T343	0	56	0	0
T344	0	111	0	0
T345	0	30	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454397098	1256	0	0
T50	14315	0	0	0
T52	55739	0	0	0
T89	63468	0	0	0
T90	9993	0	0	0
T91	15503	0	0	0
T92	11488	0	0	0
T93	133763	0	0	0
T94	57364	0	0	0
T95	18693	0	0	0
T143	0	104	0	0
T144	119316	13	0	0
T145	0	97	0	0
T180	0	110	0	0
T249	0	190	0	0
T254	0	61	0	0
T337	0	24	0	0
T343	0	24	0	0
T344	0	36	0	0
T345	0	14	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454397098	1419	0	0
T50	14315	0	0	0
T52	55739	0	0	0
T89	63468	0	0	0
T90	9993	0	0	0
T91	15503	0	0	0
T92	11488	0	0	0
T93	133763	0	0	0
T94	57364	0	0	0
T95	18693	0	0	0
T143	0	125	0	0
T144	119316	12	0	0
T145	0	135	0	0
T180	0	133	0	0
T249	0	180	0	0
T254	0	55	0	0
T337	0	47	0	0
T343	0	55	0	0
T344	0	67	0	0
T345	0	1	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454397098	3085	0	0
T50	14315	0	0	0
T52	55739	0	0	0
T89	63468	0	0	0
T90	9993	0	0	0
T91	15503	0	0	0
T92	11488	0	0	0
T93	133763	0	0	0
T94	57364	0	0	0
T95	18693	0	0	0
T143	0	122	0	0
T144	119316	26	0	0
T145	0	97	0	0
T180	0	128	0	0
T249	0	155	0	0
T254	0	132	0	0
T337	0	89	0	0
T343	0	93	0	0
T344	0	49	0	0
T345	0	21	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454397098	3876	0	0
T48	17329	0	0	0
T62	13586	0	0	0
T101	679540	6	0	0
T131	97668	0	0	0
T144	0	20	0	0
T145	0	114	0	0
T151	14361	0	0	0
T180	0	144	0	0
T209	52946	0	0	0
T211	9152	0	0	0
T212	385538	0	0	0
T249	0	228	0	0
T254	0	123	0	0
T259	0	6	0	0
T273	15158	0	0	0
T337	0	49	0	0
T343	0	51	0	0
T346	0	14	0	0
T347	10891	0	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454397098	2025	0	0
T50	14315	0	0	0
T52	55739	0	0	0
T89	63468	0	0	0
T90	9993	0	0	0
T91	15503	0	0	0
T92	11488	0	0	0
T93	133763	0	0	0
T94	57364	0	0	0
T95	18693	0	0	0
T143	0	98	0	0
T144	119316	32	0	0
T145	0	128	0	0
T180	0	155	0	0
T249	0	157	0	0
T254	0	145	0	0
T337	0	56	0	0
T343	0	58	0	0
T344	0	72	0	0
T345	0	19	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454397098	2273	0	0
T50	14315	0	0	0
T52	55739	0	0	0
T89	63468	0	0	0
T90	9993	0	0	0
T91	15503	0	0	0
T92	11488	0	0	0
T93	133763	0	0	0
T94	57364	0	0	0
T95	18693	0	0	0
T143	0	138	0	0
T144	119316	13	0	0
T145	0	129	0	0
T180	0	197	0	0
T249	0	185	0	0
T254	0	118	0	0
T337	0	62	0	0
T343	0	69	0	0
T344	0	35	0	0
T345	0	30	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454397098	2015	0	0
T50	14315	0	0	0
T52	55739	0	0	0
T89	63468	0	0	0
T90	9993	0	0	0
T91	15503	0	0	0
T92	11488	0	0	0
T93	133763	0	0	0
T94	57364	0	0	0
T95	18693	0	0	0
T143	0	118	0	0
T144	119316	3	0	0
T145	0	100	0	0
T180	0	148	0	0
T249	0	136	0	0
T254	0	106	0	0
T337	0	26	0	0
T343	0	45	0	0
T344	0	84	0	0
T345	0	14	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454397098	2055	0	0
T50	14315	0	0	0
T52	55739	0	0	0
T89	63468	0	0	0
T90	9993	0	0	0
T91	15503	0	0	0
T92	11488	0	0	0
T93	133763	0	0	0
T94	57364	0	0	0
T95	18693	0	0	0
T143	0	120	0	0
T144	119316	9	0	0
T145	0	123	0	0
T180	0	125	0	0
T249	0	189	0	0
T254	0	122	0	0
T337	0	37	0	0
T343	0	58	0	0
T344	0	51	0	0
T345	0	10	0	0