Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7344806	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7218442

1

T1

208

T2

1332

T3

5048

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8472977	1			T1	418		T2	3393		T3	12939
values[0x0]	2312227	1			T1	114		T2	207		T3	737
values[0x1]	3778044	1			T1	128		T2	201		T3	707

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4761013	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

9802235

1

T1

336

T2

1940

T3

7470

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	54435	1			T2	21		T7	3		T8	5
valid_sources[0x01]	51763	1			T2	25		T7	6		T8	2
valid_sources[0x02]	52410	1			T2	26		T7	6		T8	1
valid_sources[0x03]	54230	1			T2	7		T7	6		T8	1
valid_sources[0x04]	122585	1			T2	6		T7	5		T8	9
valid_sources[0x05]	57373	1			T2	11		T7	9		T8	3
valid_sources[0x06]	55177	1			T2	21		T7	1		T8	4
valid_sources[0x07]	52556	1			T2	5		T7	8		T8	7
valid_sources[0x08]	51468	1			T2	6		T7	6		T8	7
valid_sources[0x09]	59448	1			T2	3		T7	5		T8	6
valid_sources[0x0a]	56115	1			T2	28		T7	12		T4	73
valid_sources[0x0b]	50402	1			T2	8		T7	5		T8	5
valid_sources[0x0c]	57801	1			T1	9		T2	14		T7	3
valid_sources[0x0d]	55641	1			T2	4		T7	4		T8	4
valid_sources[0x0e]	50524	1			T2	4		T7	4		T8	3
valid_sources[0x0f]	51327	1			T2	12		T7	2		T8	16
valid_sources[0x10]	62197	1			T2	15		T7	9		T8	2
valid_sources[0x11]	61651	1			T1	26		T2	27		T7	2
valid_sources[0x12]	53063	1			T2	5		T7	14		T8	13
valid_sources[0x13]	54471	1			T2	28		T7	7		T8	4
valid_sources[0x14]	60464	1			T2	31		T7	4		T8	6
valid_sources[0x15]	48630	1			T2	19		T7	5		T8	6
valid_sources[0x16]	58002	1			T2	2		T7	8		T8	9
valid_sources[0x17]	60562	1			T2	10		T7	10		T8	7
valid_sources[0x18]	49652	1			T2	23		T7	2		T8	7
valid_sources[0x19]	48731	1			T2	18		T7	4		T4	51
valid_sources[0x1a]	66300	1			T2	20		T7	12		T4	29
valid_sources[0x1b]	48620	1			T2	1		T7	9		T8	5
valid_sources[0x1c]	59163	1			T1	3		T2	19		T7	4
valid_sources[0x1d]	55342	1			T2	8		T7	7		T8	1
valid_sources[0x1e]	52050	1			T2	7		T7	4		T8	7
valid_sources[0x1f]	51441	1			T2	9		T7	2		T8	12
valid_sources[0x20]	49687	1			T2	6		T7	9		T8	7
valid_sources[0x21]	55160	1			T2	18		T7	5		T8	1
valid_sources[0x22]	56850	1			T2	18		T7	13		T8	16
valid_sources[0x23]	52469	1			T2	11		T7	9		T8	9
valid_sources[0x24]	51923	1			T2	25		T7	8		T8	11
valid_sources[0x25]	53750	1			T2	17		T7	10		T8	4
valid_sources[0x26]	55400	1			T2	12		T7	3		T8	7
valid_sources[0x27]	61053	1			T2	10		T7	3		T8	6
valid_sources[0x28]	55275	1			T2	11		T7	4		T8	5
valid_sources[0x29]	69939	1			T2	13		T7	2		T8	1
valid_sources[0x2a]	56652	1			T1	77		T2	16		T7	11
valid_sources[0x2b]	48339	1			T2	31		T7	10		T8	4
valid_sources[0x2c]	61418	1			T2	14		T7	2		T8	8
valid_sources[0x2d]	49742	1			T2	7		T7	2		T8	7
valid_sources[0x2e]	68637	1			T2	6		T7	2		T8	1
valid_sources[0x2f]	61318	1			T2	11		T7	2		T8	3
valid_sources[0x30]	53864	1			T2	21		T7	3		T8	10
valid_sources[0x31]	58117	1			T2	26		T7	2		T8	8
valid_sources[0x32]	51808	1			T2	24		T7	4		T8	2
valid_sources[0x33]	54840	1			T2	6		T7	8		T8	10
valid_sources[0x34]	47836	1			T1	5		T2	25		T7	4
valid_sources[0x35]	50409	1			T2	10		T7	3		T8	1
valid_sources[0x36]	51921	1			T2	29		T7	5		T8	2
valid_sources[0x37]	52083	1			T2	10		T8	5		T4	43
valid_sources[0x38]	53615	1			T2	2		T7	2		T4	72
valid_sources[0x39]	53477	1			T2	2		T7	5		T8	7
valid_sources[0x3a]	58274	1			T1	89		T2	26		T7	15
valid_sources[0x3b]	55789	1			T2	17		T7	2		T8	10
valid_sources[0x3c]	62455	1			T2	16		T7	6		T8	1
valid_sources[0x3d]	50403	1			T2	22		T7	2		T8	2
valid_sources[0x3e]	52795	1			T2	15		T7	8		T8	4
valid_sources[0x3f]	48826	1			T2	28		T7	3		T8	9
valid_sources[0x40]	50759	1			T1	44		T2	4		T7	3
valid_sources[0x41]	54208	1			T2	6		T7	2		T8	6
valid_sources[0x42]	47669	1			T2	7		T7	7		T8	7
valid_sources[0x43]	75135	1			T2	14		T7	2		T8	4
valid_sources[0x44]	61535	1			T2	10		T8	1		T4	58
valid_sources[0x45]	48000	1			T2	28		T7	3		T8	7
valid_sources[0x46]	54252	1			T2	13		T7	6		T8	2
valid_sources[0x47]	50868	1			T2	23		T7	7		T8	9
valid_sources[0x48]	75204	1			T2	9		T7	2		T4	52
valid_sources[0x49]	65110	1			T2	11		T7	6		T8	3
valid_sources[0x4a]	61357	1			T2	8		T7	2		T8	10
valid_sources[0x4b]	68461	1			T2	18		T7	2		T8	10
valid_sources[0x4c]	51848	1			T1	77		T2	9		T7	2
valid_sources[0x4d]	49038	1			T2	9		T7	8		T4	49
valid_sources[0x4e]	48376	1			T2	4		T7	8		T8	5
valid_sources[0x4f]	53489	1			T2	16		T7	7		T4	40
valid_sources[0x50]	55240	1			T2	25		T7	4		T4	35
valid_sources[0x51]	177755	1			T2	14		T7	8		T8	12
valid_sources[0x52]	64128	1			T2	21		T7	12		T8	10
valid_sources[0x53]	48506	1			T2	5		T7	11		T8	7
valid_sources[0x54]	54573	1			T2	20		T7	4		T8	5
valid_sources[0x55]	48976	1			T2	27		T7	5		T8	5
valid_sources[0x56]	53399	1			T2	18		T7	4		T8	9
valid_sources[0x57]	52282	1			T2	26		T7	3		T8	1
valid_sources[0x58]	49836	1			T2	6		T7	4		T8	8
valid_sources[0x59]	53133	1			T2	3		T7	8		T4	25
valid_sources[0x5a]	64028	1			T2	16		T7	6		T8	5
valid_sources[0x5b]	58297	1			T2	18		T7	5		T8	2
valid_sources[0x5c]	49706	1			T2	9		T7	8		T8	6
valid_sources[0x5d]	62897	1			T2	28		T8	6		T4	52
valid_sources[0x5e]	64366	1			T1	1		T2	11		T7	14
valid_sources[0x5f]	49099	1			T2	21		T7	2		T8	18
valid_sources[0x60]	58855	1			T2	9		T7	10		T8	2
valid_sources[0x61]	50314	1			T2	22		T7	2		T8	6
valid_sources[0x62]	56372	1			T2	1		T7	5		T8	4
valid_sources[0x63]	56769	1			T2	6		T7	6		T4	51
valid_sources[0x64]	52828	1			T2	12		T8	1		T4	74
valid_sources[0x65]	66028	1			T2	12		T7	12		T8	7
valid_sources[0x66]	50076	1			T2	14		T7	10		T8	1
valid_sources[0x67]	50258	1			T2	7		T7	3		T8	2
valid_sources[0x68]	48141	1			T2	25		T7	8		T8	5
valid_sources[0x69]	53195	1			T2	27		T7	4		T8	3
valid_sources[0x6a]	51659	1			T2	16		T7	7		T8	8
valid_sources[0x6b]	53573	1			T2	22		T7	5		T8	2
valid_sources[0x6c]	50604	1			T2	6		T7	10		T8	4
valid_sources[0x6d]	49520	1			T2	23		T7	8		T8	8
valid_sources[0x6e]	50825	1			T1	8		T2	32		T7	3
valid_sources[0x6f]	57793	1			T2	13		T7	1		T8	15
valid_sources[0x70]	49288	1			T2	7		T7	6		T8	6
valid_sources[0x71]	51349	1			T2	21		T7	3		T8	3
valid_sources[0x72]	50227	1			T2	19		T7	5		T8	7
valid_sources[0x73]	55355	1			T2	19		T7	13		T8	4
valid_sources[0x74]	55857	1			T2	19		T7	4		T8	2
valid_sources[0x75]	66218	1			T2	6		T7	1		T8	8
valid_sources[0x76]	50919	1			T2	19		T7	5		T8	10
valid_sources[0x77]	125269	1			T1	5		T2	15		T7	5
valid_sources[0x78]	46920	1			T2	9		T7	6		T8	9
valid_sources[0x79]	52780	1			T2	15		T7	3		T8	6
valid_sources[0x7a]	52426	1			T2	18		T7	7		T8	6
valid_sources[0x7b]	51136	1			T2	49		T7	1		T8	2
valid_sources[0x7c]	51854	1			T2	20		T7	2		T8	7
valid_sources[0x7d]	50985	1			T2	16		T7	7		T8	4
valid_sources[0x7e]	55904	1			T2	13		T7	16		T8	9
valid_sources[0x7f]	50242	1			T2	23		T7	9		T8	1
valid_sources[0x80]	53742	1			T2	27		T7	3		T8	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3470616

1

T1

105

T2

1162

T3

4406

values[0x0]

all_enables

biggest_size

1913206

1

T1

58

T2

94

T3

376

values[0x1]

all_enables

biggest_size

1834620

1

T1

45

T2

76

T3

266

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	252154	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

8941347

1

T2

80

T3

160

T4

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2288435	1			T2	40		T3	80		T4	10
values[0x0]	3351326	1			T2	22		T3	42		T4	5
values[0x1]	3553740	1			T2	18		T3	38		T4	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	90572	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

9102929

1

T2

80

T3

160

T4

20

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	36090	1			T5	258		T6	223		T12	268
valid_sources[0x01]	34676	1			T3	1		T5	307		T32	1
valid_sources[0x02]	38062	1			T2	3		T5	286		T6	672
valid_sources[0x03]	37398	1			T5	311		T6	450		T12	256
valid_sources[0x04]	35072	1			T3	1		T5	262		T32	2
valid_sources[0x05]	34988	1			T5	288		T11	1		T32	2
valid_sources[0x06]	34275	1			T3	2		T5	272		T32	1
valid_sources[0x07]	35263	1			T5	229		T98	1		T6	572
valid_sources[0x08]	35891	1			T5	299		T32	1		T6	336
valid_sources[0x09]	34756	1			T5	265		T98	1		T6	337
valid_sources[0x0a]	33817	1			T5	285		T98	1		T6	288
valid_sources[0x0b]	35098	1			T5	259		T6	451		T12	223
valid_sources[0x0c]	37599	1			T4	2		T5	276		T6	555
valid_sources[0x0d]	35767	1			T3	1		T5	275		T6	429
valid_sources[0x0e]	35854	1			T5	260		T98	1		T99	2
valid_sources[0x0f]	35886	1			T5	267		T98	1		T6	364
valid_sources[0x10]	37319	1			T3	3		T5	295		T32	2
valid_sources[0x11]	40761	1			T5	276		T6	224		T12	295
valid_sources[0x12]	34510	1			T5	269		T11	2		T32	1
valid_sources[0x13]	37596	1			T3	2		T5	284		T6	219
valid_sources[0x14]	38328	1			T5	266		T11	4		T32	1
valid_sources[0x15]	36491	1			T5	288		T11	3		T6	207
valid_sources[0x16]	36845	1			T3	5		T4	1		T5	296
valid_sources[0x17]	36879	1			T3	3		T5	304		T98	5
valid_sources[0x18]	34618	1			T5	283		T32	1		T6	631
valid_sources[0x19]	35876	1			T5	252		T6	558		T12	188
valid_sources[0x1a]	34436	1			T3	2		T5	270		T11	1
valid_sources[0x1b]	37588	1			T3	1		T5	249		T6	214
valid_sources[0x1c]	36232	1			T4	4		T5	295		T98	3
valid_sources[0x1d]	34367	1			T5	272		T98	1		T99	1
valid_sources[0x1e]	34780	1			T3	2		T5	262		T32	1
valid_sources[0x1f]	37083	1			T5	264		T11	1		T6	285
valid_sources[0x20]	34873	1			T5	245		T32	3		T99	1
valid_sources[0x21]	34500	1			T2	5		T5	286		T6	250
valid_sources[0x22]	35354	1			T3	2		T5	263		T6	448
valid_sources[0x23]	38137	1			T5	253		T98	3		T6	374
valid_sources[0x24]	37098	1			T5	241		T98	1		T6	309
valid_sources[0x25]	35013	1			T3	2		T5	278		T98	1
valid_sources[0x26]	38335	1			T3	1		T5	288		T98	2
valid_sources[0x27]	38118	1			T5	279		T6	321		T12	201
valid_sources[0x28]	35829	1			T3	1		T5	267		T98	3
valid_sources[0x29]	36367	1			T5	239		T11	3		T32	1
valid_sources[0x2a]	34946	1			T3	1		T5	247		T98	1
valid_sources[0x2b]	35471	1			T5	255		T32	1		T98	1
valid_sources[0x2c]	37354	1			T3	1		T5	294		T11	1
valid_sources[0x2d]	36228	1			T5	280		T6	358		T12	219
valid_sources[0x2e]	35828	1			T3	2		T5	269		T98	1
valid_sources[0x2f]	34091	1			T5	288		T32	1		T6	592
valid_sources[0x30]	36520	1			T5	275		T32	2		T6	567
valid_sources[0x31]	35535	1			T5	285		T6	287		T12	243
valid_sources[0x32]	34808	1			T3	1		T5	268		T32	1
valid_sources[0x33]	38190	1			T5	252		T98	1		T6	503
valid_sources[0x34]	34918	1			T3	2		T5	263		T32	4
valid_sources[0x35]	35411	1			T3	2		T5	294		T32	1
valid_sources[0x36]	35145	1			T3	2		T5	269		T11	3
valid_sources[0x37]	35483	1			T5	302		T98	4		T6	279
valid_sources[0x38]	35838	1			T5	263		T32	1		T6	567
valid_sources[0x39]	34052	1			T5	278		T6	324		T12	287
valid_sources[0x3a]	35758	1			T3	2		T5	288		T32	1
valid_sources[0x3b]	36400	1			T5	278		T11	5		T6	310
valid_sources[0x3c]	33393	1			T3	1		T5	289		T11	1
valid_sources[0x3d]	34802	1			T5	278		T32	3		T6	242
valid_sources[0x3e]	36065	1			T3	1		T5	300		T32	1
valid_sources[0x3f]	36126	1			T3	1		T5	261		T11	1
valid_sources[0x40]	35448	1			T5	244		T98	1		T6	349
valid_sources[0x41]	37642	1			T2	7		T5	300		T98	1
valid_sources[0x42]	37483	1			T5	260		T98	1		T6	562
valid_sources[0x43]	35180	1			T5	277		T98	1		T6	243
valid_sources[0x44]	35766	1			T5	284		T32	4		T6	339
valid_sources[0x45]	35414	1			T2	5		T3	3		T5	281
valid_sources[0x46]	35694	1			T3	2		T5	304		T6	367
valid_sources[0x47]	36468	1			T5	263		T6	218		T12	256
valid_sources[0x48]	36095	1			T3	1		T5	292		T32	1
valid_sources[0x49]	34554	1			T5	263		T32	1		T6	636
valid_sources[0x4a]	35447	1			T5	310		T98	1		T6	235
valid_sources[0x4b]	35957	1			T5	242		T98	1		T6	292
valid_sources[0x4c]	36170	1			T3	1		T5	279		T6	477
valid_sources[0x4d]	35217	1			T3	1		T4	2		T5	252
valid_sources[0x4e]	32838	1			T3	2		T5	268		T11	3
valid_sources[0x4f]	36930	1			T3	1		T5	273		T6	762
valid_sources[0x50]	35863	1			T3	1		T5	259		T6	202
valid_sources[0x51]	36346	1			T3	2		T5	266		T6	537
valid_sources[0x52]	35410	1			T5	278		T6	427		T12	243
valid_sources[0x53]	36621	1			T3	2		T5	278		T6	380
valid_sources[0x54]	35202	1			T5	261		T32	5		T6	361
valid_sources[0x55]	35927	1			T5	279		T32	1		T6	374
valid_sources[0x56]	35787	1			T5	285		T6	541		T12	218
valid_sources[0x57]	36127	1			T5	271		T11	2		T6	378
valid_sources[0x58]	35595	1			T5	304		T6	238		T12	261
valid_sources[0x59]	36088	1			T5	309		T11	2		T32	1
valid_sources[0x5a]	36832	1			T3	1		T5	284		T32	2
valid_sources[0x5b]	36899	1			T5	295		T11	1		T32	1
valid_sources[0x5c]	35314	1			T3	4		T5	296		T32	1
valid_sources[0x5d]	36190	1			T3	1		T5	266		T11	1
valid_sources[0x5e]	37175	1			T5	271		T11	1		T6	410
valid_sources[0x5f]	36362	1			T5	274		T98	1		T6	438
valid_sources[0x60]	35074	1			T5	237		T6	235		T12	278
valid_sources[0x61]	35773	1			T2	1		T3	1		T5	285
valid_sources[0x62]	37571	1			T3	1		T5	249		T6	409
valid_sources[0x63]	35937	1			T5	311		T32	1		T6	243
valid_sources[0x64]	35667	1			T3	2		T5	261		T11	3
valid_sources[0x65]	34544	1			T3	2		T5	264		T6	453
valid_sources[0x66]	35451	1			T3	2		T5	264		T11	8
valid_sources[0x67]	35887	1			T2	7		T5	264		T6	341
valid_sources[0x68]	34208	1			T3	1		T5	273		T32	1
valid_sources[0x69]	34554	1			T3	1		T5	259		T32	1
valid_sources[0x6a]	37656	1			T3	2		T5	277		T98	1
valid_sources[0x6b]	36576	1			T5	257		T11	3		T6	537
valid_sources[0x6c]	37494	1			T5	280		T6	551		T12	266
valid_sources[0x6d]	35631	1			T3	1		T5	250		T98	2
valid_sources[0x6e]	37825	1			T5	261		T11	1		T32	2
valid_sources[0x6f]	35084	1			T3	2		T5	264		T32	1
valid_sources[0x70]	33765	1			T3	1		T5	277		T32	1
valid_sources[0x71]	35224	1			T5	247		T98	1		T6	267
valid_sources[0x72]	37996	1			T5	231		T6	351		T12	200
valid_sources[0x73]	34905	1			T5	286		T99	3		T6	270
valid_sources[0x74]	34958	1			T5	261		T98	1		T6	258
valid_sources[0x75]	38869	1			T3	2		T5	266		T32	1
valid_sources[0x76]	36503	1			T5	273		T98	1		T99	1
valid_sources[0x77]	38988	1			T5	268		T11	2		T6	629
valid_sources[0x78]	35626	1			T5	294		T6	359		T12	274
valid_sources[0x79]	36283	1			T5	304		T11	3		T32	1
valid_sources[0x7a]	37702	1			T2	15		T5	275		T98	1
valid_sources[0x7b]	34549	1			T5	258		T6	260		T12	384
valid_sources[0x7c]	34980	1			T5	262		T32	2		T6	346
valid_sources[0x7d]	34449	1			T3	1		T5	273		T11	2
valid_sources[0x7e]	35142	1			T3	1		T5	297		T6	403
valid_sources[0x7f]	35793	1			T5	296		T6	519		T12	256
valid_sources[0x80]	36504	1			T5	263		T11	1		T32	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2275463

1

T2

40

T3

80

T4

10

values[0x0]

all_enables

biggest_size

3334166

1

T2

22

T3

42

T4

5

values[0x1]

all_enables

biggest_size

3331718

1

T2

18

T3

38

T4

5