Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

25604037

1

T1

452

T2

2469

T3

9335

full_word

8326857

1

T1

208

T2

1332

T3

5048

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	33930614	1			T1	660		T2	3801		T3	14383
auto[TlIntgErrCmd]	88	1			T275	6		T276	1		T277	2
auto[TlIntgErrData]	102	1			T275	2		T276	3		T277	3
auto[TlIntgErrBoth]	90	1			T275	2		T276	6		T277	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9803143

1

T1

418

T2

3393

T3

12939

auto[1]

24127751

1

T1

242

T2

408

T3

1444

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6197064	1			T1	313		T2	2231		T3	8533
auto[TlIntgErrNone]	partial	auto[1]	19406719	1			T1	139		T2	238		T3	802
auto[TlIntgErrNone]	full_word	auto[0]	3605975	1			T1	105		T2	1162		T3	4406
auto[TlIntgErrNone]	full_word	auto[1]	4720856	1			T1	103		T2	170		T3	642
auto[TlIntgErrCmd]	partial	auto[0]	28	1			T275	2		T276	1		T371	3
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T275	3		T277	2		T371	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T372	1		T373	1		T374	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T275	1		T372	1		T373	1
auto[TlIntgErrData]	partial	auto[0]	34	1			T371	2		T375	3		T373	3
auto[TlIntgErrData]	partial	auto[1]	53	1			T275	1		T276	1		T277	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T276	1		T373	1		T376	1
auto[TlIntgErrData]	full_word	auto[1]	11	1			T275	1		T276	1		T375	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T275	1		T276	1		T277	4
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T275	1		T276	5		T277	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T377	1		T378	1		-	-