Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.99	98.05	96.15	97.16		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	467836650	8069133	0	0
check_regwen_rd_A	467836650	3519	0	0
check_timeout_rd_A	467836650	3275	0	0
check_trigger_regwen_rd_A	467836650	3446	0	0
consistency_check_period_rd_A	467836650	3650	0	0
creator_sw_cfg_read_lock_rd_A	467836650	3118	0	0
direct_access_address_rd_A	467836650	2308	0	0
direct_access_wdata_0_rd_A	467836650	1452	0	0
direct_access_wdata_1_rd_A	467836650	1538	0	0
integrity_check_period_rd_A	467836650	3702	0	0
intr_enable_rd_A	467836650	4299	0	0
owner_sw_cfg_read_lock_rd_A	467836650	2925	0	0
rot_creator_auth_codesign_read_lock_rd_A	467836650	3358	0	0
rot_creator_auth_state_read_lock_rd_A	467836650	2969	0	0
vendor_test_read_lock_rd_A	467836650	3172	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467836650	8069133	0	0
T5	288963	62591	0	0
T6	0	85545	0	0
T10	21338	0	0	0
T11	103266	0	0	0
T12	0	55483	0	0
T13	0	72420	0	0
T14	0	156635	0	0
T32	99217	0	0	0
T48	14166	0	0	0
T65	14765	0	0	0
T89	0	172185	0	0
T97	11679	0	0	0
T98	104450	0	0	0
T99	28484	0	0	0
T100	13719	0	0	0
T144	0	88981	0	0
T284	0	109167	0	0
T285	0	92826	0	0
T286	0	133179	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467836650	3519	0	0
T12	276544	34	0	0
T13	0	65	0	0
T23	71359	0	0	0
T24	88965	0	0	0
T90	0	85	0	0
T91	272392	0	0	0
T101	68861	0	0	0
T104	23543	0	0	0
T105	21966	0	0	0
T108	16535	0	0	0
T117	11117	0	0	0
T144	0	142	0	0
T167	20113	0	0	0
T290	0	197	0	0
T292	0	69	0	0
T349	0	140	0	0
T354	0	55	0	0
T355	0	54	0	0
T356	0	94	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467836650	3275	0	0
T12	276544	54	0	0
T13	0	77	0	0
T23	71359	0	0	0
T24	88965	0	0	0
T90	0	98	0	0
T91	272392	0	0	0
T101	68861	0	0	0
T104	23543	0	0	0
T105	21966	0	0	0
T108	16535	0	0	0
T117	11117	0	0	0
T144	0	169	0	0
T167	20113	0	0	0
T290	0	204	0	0
T292	0	116	0	0
T349	0	223	0	0
T354	0	44	0	0
T355	0	33	0	0
T356	0	106	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467836650	3446	0	0
T12	276544	27	0	0
T13	0	80	0	0
T23	71359	0	0	0
T24	88965	0	0	0
T90	0	95	0	0
T91	272392	0	0	0
T101	68861	0	0	0
T104	23543	0	0	0
T105	21966	0	0	0
T108	16535	0	0	0
T117	11117	0	0	0
T144	0	119	0	0
T167	20113	0	0	0
T290	0	200	0	0
T292	0	84	0	0
T349	0	227	0	0
T354	0	33	0	0
T355	0	32	0	0
T356	0	105	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467836650	3650	0	0
T12	276544	28	0	0
T13	0	113	0	0
T23	71359	0	0	0
T24	88965	0	0	0
T90	0	115	0	0
T91	272392	0	0	0
T101	68861	0	0	0
T104	23543	0	0	0
T105	21966	0	0	0
T108	16535	0	0	0
T117	11117	0	0	0
T144	0	170	0	0
T167	20113	0	0	0
T290	0	218	0	0
T292	0	72	0	0
T349	0	124	0	0
T354	0	36	0	0
T355	0	24	0	0
T356	0	132	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467836650	3118	0	0
T12	276544	36	0	0
T13	0	91	0	0
T23	71359	0	0	0
T24	88965	0	0	0
T90	0	109	0	0
T91	272392	0	0	0
T101	68861	0	0	0
T104	23543	0	0	0
T105	21966	0	0	0
T108	16535	0	0	0
T117	11117	0	0	0
T144	0	126	0	0
T167	20113	0	0	0
T290	0	202	0	0
T292	0	161	0	0
T349	0	175	0	0
T354	0	29	0	0
T355	0	17	0	0
T356	0	105	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467836650	2308	0	0
T12	276544	54	0	0
T13	0	186	0	0
T23	71359	0	0	0
T24	88965	0	0	0
T90	0	123	0	0
T91	272392	0	0	0
T101	68861	0	0	0
T104	23543	0	0	0
T105	21966	0	0	0
T108	16535	0	0	0
T117	11117	0	0	0
T144	0	164	0	0
T167	20113	0	0	0
T290	0	233	0	0
T292	0	77	0	0
T349	0	161	0	0
T354	0	39	0	0
T355	0	43	0	0
T356	0	113	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467836650	1452	0	0
T12	276544	31	0	0
T13	0	56	0	0
T23	71359	0	0	0
T24	88965	0	0	0
T90	0	91	0	0
T91	272392	0	0	0
T101	68861	0	0	0
T104	23543	0	0	0
T105	21966	0	0	0
T108	16535	0	0	0
T117	11117	0	0	0
T144	0	76	0	0
T167	20113	0	0	0
T290	0	137	0	0
T292	0	87	0	0
T349	0	157	0	0
T354	0	36	0	0
T355	0	19	0	0
T356	0	60	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467836650	1538	0	0
T12	276544	26	0	0
T13	0	61	0	0
T23	71359	0	0	0
T24	88965	0	0	0
T90	0	76	0	0
T91	272392	0	0	0
T101	68861	0	0	0
T104	23543	0	0	0
T105	21966	0	0	0
T108	16535	0	0	0
T117	11117	0	0	0
T144	0	98	0	0
T167	20113	0	0	0
T290	0	164	0	0
T292	0	78	0	0
T349	0	138	0	0
T354	0	24	0	0
T355	0	11	0	0
T356	0	55	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467836650	3702	0	0
T12	276544	38	0	0
T13	0	146	0	0
T23	71359	0	0	0
T24	88965	0	0	0
T90	0	99	0	0
T91	272392	0	0	0
T101	68861	0	0	0
T104	23543	0	0	0
T105	21966	0	0	0
T108	16535	0	0	0
T117	11117	0	0	0
T144	0	170	0	0
T167	20113	0	0	0
T290	0	208	0	0
T292	0	111	0	0
T349	0	192	0	0
T354	0	32	0	0
T355	0	14	0	0
T356	0	104	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467836650	4299	0	0
T12	276544	13	0	0
T13	0	137	0	0
T23	71359	0	0	0
T24	88965	0	0	0
T90	0	165	0	0
T91	272392	0	0	0
T101	68861	0	0	0
T104	23543	0	0	0
T105	21966	0	0	0
T108	16535	0	0	0
T117	11117	0	0	0
T130	0	39	0	0
T144	0	125	0	0
T156	0	24	0	0
T167	20113	0	0	0
T289	0	7	0	0
T354	0	79	0	0
T355	0	32	0	0
T357	0	28	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467836650	2925	0	0
T12	276544	44	0	0
T13	0	68	0	0
T23	71359	0	0	0
T24	88965	0	0	0
T90	0	93	0	0
T91	272392	0	0	0
T101	68861	0	0	0
T104	23543	0	0	0
T105	21966	0	0	0
T108	16535	0	0	0
T117	11117	0	0	0
T144	0	147	0	0
T167	20113	0	0	0
T290	0	155	0	0
T292	0	72	0	0
T349	0	174	0	0
T354	0	55	0	0
T355	0	13	0	0
T356	0	95	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467836650	3358	0	0
T12	276544	43	0	0
T13	0	85	0	0
T23	71359	0	0	0
T24	88965	0	0	0
T90	0	125	0	0
T91	272392	0	0	0
T101	68861	0	0	0
T104	23543	0	0	0
T105	21966	0	0	0
T108	16535	0	0	0
T117	11117	0	0	0
T144	0	183	0	0
T167	20113	0	0	0
T290	0	175	0	0
T292	0	82	0	0
T349	0	190	0	0
T354	0	47	0	0
T355	0	27	0	0
T356	0	136	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467836650	2969	0	0
T12	276544	17	0	0
T13	0	104	0	0
T23	71359	0	0	0
T24	88965	0	0	0
T90	0	90	0	0
T91	272392	0	0	0
T101	68861	0	0	0
T104	23543	0	0	0
T105	21966	0	0	0
T108	16535	0	0	0
T117	11117	0	0	0
T144	0	85	0	0
T167	20113	0	0	0
T290	0	188	0	0
T292	0	100	0	0
T349	0	177	0	0
T354	0	27	0	0
T355	0	33	0	0
T356	0	102	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467836650	3172	0	0
T12	276544	41	0	0
T13	0	127	0	0
T23	71359	0	0	0
T24	88965	0	0	0
T90	0	104	0	0
T91	272392	0	0	0
T101	68861	0	0	0
T104	23543	0	0	0
T105	21966	0	0	0
T108	16535	0	0	0
T117	11117	0	0	0
T144	0	141	0	0
T167	20113	0	0	0
T290	0	200	0	0
T292	0	87	0	0
T349	0	214	0	0
T354	0	34	0	0
T355	0	8	0	0
T356	0	102	0	0