Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.23	100.00	100.00		90.00	100.00	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.56	100.00	100.00	100.00	90.00	98.15	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.99	98.05	96.15	97.16		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.99	98.05	96.15	97.16		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.99	98.05	96.15	97.16		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		86	86	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	61	61	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
153	1	1
154	1	1
156	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			==> MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
224		excluded
			Exclude Annotation: VC_COV_UNR
225		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
276		excluded
			Exclude Annotation: VC_COV_UNR
277		excluded
			Exclude Annotation: VC_COV_UNR
279		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
339	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T2,T3,T7
1	Excluded		VC_COV_UNR

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T16,T17,T18

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T161,T163
1	Covered	T161,T163

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T3,T7

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T2,T3,T7

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T8

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T8

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	11	84.62
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T3,T7
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T3,T7
ReadWaitSt	252	Covered	T2,T3,T7
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T3,T7
IdleSt->ReadSt	236	Covered	T2,T3,T7
InitSt->ErrorSt	315	Covered	T211
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T108,T63,T212
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T4,T5,T11
ReadSt->ReadWaitSt	252	Covered	T2,T3,T7
ReadWaitSt->ErrorSt	276	Not Covered
ReadWaitSt->IdleSt	270	Covered	T2,T3,T7
ResetSt->ErrorSt	315	Covered	T72,T73,T74
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests	Exclude Annotation
AccessError	256	Covered	T4,T5,T11
CheckFailError	317	Covered	T161,T163
FsmStateError	289	Covered	T1,T3,T7
MacroEccCorrError	221	Excluded		VC_COV_UNR
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded
AccessError->FsmStateError	325	Covered	T4,T5,T6
AccessError->MacroEccCorrError	221	Excluded
AccessError->NoError	235	Covered	T4,T5,T11
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded
CheckFailError->NoError	235	Covered	T161,T163
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded
FsmStateError->NoError	235	Covered	T1,T3,T7
MacroEccCorrError->AccessError	256	Excluded
MacroEccCorrError->CheckFailError	317	Excluded
MacroEccCorrError->FsmStateError	325	Excluded
MacroEccCorrError->NoError	235	Excluded
NoError->AccessError	256	Covered	T4,T5,T11
NoError->CheckFailError	317	Covered	T161,T163
NoError->FsmStateError	289	Covered	T1,T3,T7
NoError->MacroEccCorrError	221	Excluded

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	18	18	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T7

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T7

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests	Exclude Annotation
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T7
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T7
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T6,T91,T102
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T4,T5,T11
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T7
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T17,T18
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T3,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T4,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T3,T4,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T3,T7
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T161,T163
1	0	Covered	T161,T163
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	464973092	464088968	0	0
DigestKnown_A	464973092	464088968	0	0
DigestOffsetMustBeRepresentable_A	1148	1148	0	0
EccErrorState_A	464973092	6615	0	0
ErrorKnown_A	464973092	464088968	0	0
FsmStateKnown_A	464973092	464088968	0	0
InitDoneKnown_A	464973092	464088968	0	0
InitReadLocksPartition_A	464973092	97798277	0	0
InitWriteLocksPartition_A	464973092	97798277	0	0
OffsetMustBeBlockAligned_A	1148	1148	0	0
OtpAddrKnown_A	464973092	464088968	0	0
OtpCmdKnown_A	464973092	464088968	0	0
OtpErrorState_A	464973092	0	0	0
OtpReqKnown_A	464973092	464088968	0	0
OtpSizeKnown_A	464973092	464088968	0	0
OtpWdataKnown_A	464973092	464088968	0	0
ReadLockPropagation_A	464973092	203709620	0	0
SizeMustBeBlockAligned_A	1148	1148	0	0
TlulGntKnown_A	464973092	464088968	0	0
TlulRdataKnown_A	464973092	464088968	0	0
TlulReadOnReadLock_A	464973092	7891	0	0
TlulRerrorKnown_A	464973092	464088968	0	0
TlulRvalidKnown_A	464973092	464088968	0	0
WriteLockPropagation_A	464973092	2144540	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	464973092	26414369	0	0
u_state_regs_A	464973092	464088968	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	6615	0	0
T161	10847	2876	0	0
T163	0	3739	0	0
T179	15188	0	0	0
T180	15350	0	0	0
T181	9714	0	0	0
T182	14454	0	0	0
T183	22529	0	0	0
T184	41362	0	0	0
T185	10664	0	0	0
T186	192541	0	0	0
T187	93277	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	97798277	0	0
T1	14028	3013	0	0
T2	163780	8316	0	0
T3	93953	21960	0	0
T4	161903	131183	0	0
T5	288963	723816	0	0
T7	11814	4624	0	0
T8	9939	4228	0	0
T9	12719	3164	0	0
T10	21338	179	0	0
T11	103266	19605	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	97798277	0	0
T1	14028	3013	0	0
T2	163780	8316	0	0
T3	93953	21960	0	0
T4	161903	131183	0	0
T5	288963	723816	0	0
T7	11814	4624	0	0
T8	9939	4228	0	0
T9	12719	3164	0	0
T10	21338	179	0	0
T11	103266	19605	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	203709620	0	0
T2	163780	12460	0	0
T3	93953	0	0	0
T4	161903	145701	0	0
T5	288963	204602	0	0
T6	0	193335	0	0
T7	11814	0	0	0
T8	9939	0	0	0
T9	12719	0	0	0
T10	21338	0	0	0
T11	103266	27007	0	0
T12	0	905316	0	0
T32	0	30381	0	0
T97	11679	0	0	0
T98	0	8822	0	0
T99	0	7753	0	0
T108	0	1470	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	7891	0	0
T3	93953	14	0	0
T4	161903	23	0	0
T5	288963	32	0	0
T6	0	28	0	0
T7	11814	0	0	0
T8	9939	0	0	0
T9	12719	0	0	0
T10	21338	0	0	0
T11	103266	7	0	0
T12	0	24	0	0
T32	99217	11	0	0
T97	11679	0	0	0
T98	0	10	0	0
T99	0	2	0	0
T108	0	5	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	2144540	0	0
T6	407721	0	0	0
T12	276544	0	0	0
T23	0	1862	0	0
T24	0	18944	0	0
T32	99217	15860	0	0
T33	0	5380	0	0
T48	14166	0	0	0
T63	0	7662	0	0
T65	14765	0	0	0
T91	0	3575	0	0
T92	0	10127	0	0
T93	0	438	0	0
T94	0	27597	0	0
T98	104450	0	0	0
T99	28484	0	0	0
T100	13719	0	0	0
T101	0	4537	0	0
T108	16535	0	0	0
T117	11117	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	26414369	0	0
T1	14028	3289	0	0
T2	163780	116035	0	0
T3	93953	0	0	0
T4	161903	0	0	0
T5	288963	0	0	0
T7	11814	0	0	0
T8	9939	3141	0	0
T9	12719	0	0	0
T10	21338	0	0	0
T11	103266	85237	0	0
T23	0	32536	0	0
T32	0	48084	0	0
T98	0	6362	0	0
T99	0	16835	0	0
T100	0	2313	0	0
T108	0	2929	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T65,T117

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T11,T33,T62

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T16,T17,T18

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T161,T163
1	Covered	T161,T163

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T3,T7

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T7

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T9

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T9

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T3,T7
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T7
ReadWaitSt	252	Covered	T1,T2,T7
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T3,T7
IdleSt->ReadSt	236	Covered	T1,T2,T7
InitSt->ErrorSt	315	Covered	T108,T63,T212
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T9,T195,T196
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T2,T4,T5
ReadSt->ReadWaitSt	252	Covered	T1,T2,T7
ReadWaitSt->ErrorSt	276	Covered	T170,T171,T213
ReadWaitSt->IdleSt	270	Covered	T1,T2,T7
ResetSt->ErrorSt	315	Covered	T72,T73,T74
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T2,T4,T5
CheckFailError	317	Covered	T161,T163
FsmStateError	289	Covered	T1,T3,T7
MacroEccCorrError	221	Covered	T1,T11,T65
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T4,T5,T6
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T2,T4,T5
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T161,T163
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T3,T7
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T1,T65,T117
MacroEccCorrError->NoError	235	Covered	T11,T33,T62
NoError->AccessError	256	Covered	T2,T4,T5
NoError->CheckFailError	317	Covered	T161,T163
NoError->FsmStateError	289	Covered	T3,T7,T8
NoError->MacroEccCorrError	221	Covered	T1,T11,T65

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T1,T65,T117
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T9,T195,T196
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T7
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T6,T91,T93
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T4,T5
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T11,T33,T62
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T7
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T170,T171,T213
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T17,T18
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T3,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T4,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T3,T4,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T3,T7
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T161,T163
1	0	Covered	T161,T163
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	464973092	464088968	0	0
DigestKnown_A	464973092	464088968	0	0
DigestOffsetMustBeRepresentable_A	1148	1148	0	0
EccErrorState_A	464973092	6615	0	0
ErrorKnown_A	464973092	464088968	0	0
FsmStateKnown_A	464973092	464088968	0	0
InitDoneKnown_A	464973092	464088968	0	0
InitReadLocksPartition_A	464973092	97984617	0	0
InitWriteLocksPartition_A	464973092	97984617	0	0
OffsetMustBeBlockAligned_A	1148	1148	0	0
OtpAddrKnown_A	464973092	464088968	0	0
OtpCmdKnown_A	464973092	464088968	0	0
OtpErrorState_A	464973092	67	0	0
OtpReqKnown_A	464973092	464088968	0	0
OtpSizeKnown_A	464973092	464088968	0	0
OtpWdataKnown_A	464973092	464088968	0	0
ReadLockPropagation_A	464973092	203401135	0	0
SizeMustBeBlockAligned_A	1148	1148	0	0
TlulGntKnown_A	464973092	464088968	0	0
TlulRdataKnown_A	464973092	464088968	0	0
TlulReadOnReadLock_A	464973092	8211	0	0
TlulRerrorKnown_A	464973092	464088968	0	0
TlulRvalidKnown_A	464973092	464088968	0	0
WriteLockPropagation_A	464973092	1982162	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	464973092	25458115	0	0
u_state_regs_A	464973092	464088968	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	6615	0	0
T161	10847	2876	0	0
T163	0	3739	0	0
T179	15188	0	0	0
T180	15350	0	0	0
T181	9714	0	0	0
T182	14454	0	0	0
T183	22529	0	0	0
T184	41362	0	0	0
T185	10664	0	0	0
T186	192541	0	0	0
T187	93277	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	97984617	0	0
T1	14028	3064	0	0
T2	163780	8418	0	0
T3	93953	22351	0	0
T4	161903	131234	0	0
T5	288963	723918	0	0
T7	11814	4675	0	0
T8	9939	4262	0	0
T9	12719	3188	0	0
T10	21338	247	0	0
T11	103266	19843	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	97984617	0	0
T1	14028	3064	0	0
T2	163780	8418	0	0
T3	93953	22351	0	0
T4	161903	131234	0	0
T5	288963	723918	0	0
T7	11814	4675	0	0
T8	9939	4262	0	0
T9	12719	3188	0	0
T10	21338	247	0	0
T11	103266	19843	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	67	0	0
T4	161903	0	0	0
T5	288963	0	0	0
T9	12719	1	0	0
T10	21338	0	0	0
T11	103266	0	0	0
T32	99217	0	0	0
T65	14765	0	0	0
T97	11679	0	0	0
T98	104450	0	0	0
T99	28484	0	0	0
T170	0	1	0	0
T195	0	1	0	0
T196	0	1	0	0
T197	0	1	0	0
T198	0	1	0	0
T199	0	1	0	0
T200	0	1	0	0
T206	0	1	0	0
T207	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	203401135	0	0
T2	163780	11153	0	0
T3	93953	6936	0	0
T4	161903	145687	0	0
T5	288963	205488	0	0
T6	0	190655	0	0
T7	11814	0	0	0
T8	9939	0	0	0
T9	12719	0	0	0
T10	21338	0	0	0
T11	103266	24298	0	0
T12	0	888416	0	0
T32	0	18943	0	0
T97	11679	0	0	0
T98	0	8815	0	0
T99	0	864	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	8211	0	0
T2	163780	2	0	0
T3	93953	20	0	0
T4	161903	13	0	0
T5	288963	39	0	0
T6	0	33	0	0
T7	11814	0	0	0
T8	9939	0	0	0
T9	12719	0	0	0
T10	21338	0	0	0
T11	103266	9	0	0
T12	0	15	0	0
T32	0	1	0	0
T97	11679	0	0	0
T98	0	12	0	0
T108	0	4	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	1982162	0	0
T2	163780	6542	0	0
T3	93953	0	0	0
T4	161903	0	0	0
T5	288963	0	0	0
T7	11814	0	0	0
T8	9939	0	0	0
T9	12719	0	0	0
T10	21338	0	0	0
T11	103266	21856	0	0
T23	0	118	0	0
T24	0	18944	0	0
T32	0	10884	0	0
T33	0	23421	0	0
T91	0	3341	0	0
T92	0	16195	0	0
T97	11679	0	0	0
T99	0	3335	0	0
T101	0	2945	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	25458115	0	0
T2	163780	115967	0	0
T3	93953	6112	0	0
T4	161903	0	0	0
T5	288963	0	0	0
T7	11814	0	0	0
T8	9939	0	0	0
T9	12719	2339	0	0
T10	21338	0	0	0
T11	103266	85033	0	0
T23	0	32366	0	0
T24	0	73654	0	0
T32	0	82662	0	0
T97	11679	0	0	0
T98	0	3279	0	0
T99	0	16784	0	0
T108	0	2912	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T65,T67,T177

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T11,T99,T33

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T16,T17,T18

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T163
1	Covered	T163

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T3,T7

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T7

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00111101000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T11

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T11

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T3,T7
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T7
ReadWaitSt	252	Covered	T1,T2,T7
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T3,T7
IdleSt->ReadSt	236	Covered	T1,T2,T7
InitSt->ErrorSt	315	Covered	T108,T214,T63
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T9,T97,T100
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T2,T5,T11
ReadSt->ReadWaitSt	252	Covered	T1,T2,T7
ReadWaitSt->ErrorSt	276	Covered	T98,T178,T215
ReadWaitSt->IdleSt	270	Covered	T1,T2,T7
ResetSt->ErrorSt	315	Covered	T72,T73,T74
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T2,T5,T11
CheckFailError	317	Covered	T163
FsmStateError	289	Covered	T1,T3,T7
MacroEccCorrError	221	Covered	T11,T65,T99
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T5,T105,T13
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T2,T5,T11
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T163
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T3,T7
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T65,T172,T67
MacroEccCorrError->NoError	235	Covered	T11,T99,T33
NoError->AccessError	256	Covered	T2,T5,T11
NoError->CheckFailError	317	Covered	T163
NoError->FsmStateError	289	Covered	T1,T3,T7
NoError->MacroEccCorrError	221	Covered	T11,T65,T99

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T65,T67,T177
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T97,T100,T117
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T7
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T91,T13,T93
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T5,T11
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T11,T99,T33
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T7
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T98,T178,T215
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T17,T18
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T3,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T4,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T3,T4,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T3,T7
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T163
1	0	Covered	T163
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	464973092	464088968	0	0
DigestKnown_A	464973092	464088968	0	0
DigestOffsetMustBeRepresentable_A	1148	1148	0	0
EccErrorState_A	464973092	3739	0	0
ErrorKnown_A	464973092	464088968	0	0
FsmStateKnown_A	464973092	464088968	0	0
InitDoneKnown_A	464973092	464088968	0	0
InitReadLocksPartition_A	464973092	98169834	0	0
InitWriteLocksPartition_A	464973092	98169834	0	0
OffsetMustBeBlockAligned_A	1148	1148	0	0
OtpAddrKnown_A	464973092	464088968	0	0
OtpCmdKnown_A	464973092	464088968	0	0
OtpErrorState_A	464973092	51	0	0
OtpReqKnown_A	464973092	464088968	0	0
OtpSizeKnown_A	464973092	464088968	0	0
OtpWdataKnown_A	464973092	464088968	0	0
ReadLockPropagation_A	464973092	208288019	0	0
SizeMustBeBlockAligned_A	1148	1148	0	0
TlulGntKnown_A	464973092	464088968	0	0
TlulRdataKnown_A	464973092	464088968	0	0
TlulReadOnReadLock_A	464973092	8485	0	0
TlulRerrorKnown_A	464973092	464088968	0	0
TlulRvalidKnown_A	464973092	464088968	0	0
WriteLockPropagation_A	464973092	1176700	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	464973092	16434244	0	0
u_state_regs_A	464973092	464088968	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	3739	0	0
T20	14212	0	0	0
T127	117475	0	0	0
T163	15978	3739	0	0
T188	5272	0	0	0
T189	11013	0	0	0
T190	48206	0	0	0
T191	13711	0	0	0
T192	30109	0	0	0
T193	64799	0	0	0
T194	37531	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	98169834	0	0
T1	14028	3115	0	0
T2	163780	8520	0	0
T3	93953	22742	0	0
T4	161903	131285	0	0
T5	288963	724020	0	0
T7	11814	4726	0	0
T8	9939	4296	0	0
T9	12719	3205	0	0
T10	21338	315	0	0
T11	103266	20081	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	98169834	0	0
T1	14028	3115	0	0
T2	163780	8520	0	0
T3	93953	22742	0	0
T4	161903	131285	0	0
T5	288963	724020	0	0
T7	11814	4726	0	0
T8	9939	4296	0	0
T9	12719	3205	0	0
T10	21338	315	0	0
T11	103266	20081	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	51	0	0
T6	407721	0	0	0
T12	276544	0	0	0
T32	99217	0	0	0
T48	14166	0	0	0
T65	14765	0	0	0
T97	11679	1	0	0
T98	104450	1	0	0
T99	28484	0	0	0
T100	13719	1	0	0
T117	11117	1	0	0
T178	0	1	0	0
T201	0	1	0	0
T202	0	1	0	0
T203	0	1	0	0
T204	0	1	0	0
T205	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	208288019	0	0
T2	163780	8144	0	0
T3	93953	0	0	0
T4	161903	133386	0	0
T5	288963	204994	0	0
T6	0	193137	0	0
T7	11814	0	0	0
T8	9939	0	0	0
T9	12719	0	0	0
T10	21338	0	0	0
T11	103266	24017	0	0
T12	0	514308	0	0
T32	0	21789	0	0
T97	11679	0	0	0
T98	0	8808	0	0
T99	0	2839	0	0
T108	0	3103	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	8485	0	0
T2	163780	1	0	0
T3	93953	17	0	0
T4	161903	24	0	0
T5	288963	27	0	0
T6	0	30	0	0
T7	11814	0	0	0
T8	9939	0	0	0
T9	12719	0	0	0
T10	21338	0	0	0
T11	103266	11	0	0
T12	0	16	0	0
T32	0	3	0	0
T97	11679	0	0	0
T98	0	14	0	0
T108	0	7	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	1176700	0	0
T6	407721	0	0	0
T12	276544	0	0	0
T23	71359	217	0	0
T48	14166	0	0	0
T63	0	13466	0	0
T91	0	9242	0	0
T93	0	3980	0	0
T94	0	25744	0	0
T96	0	9385	0	0
T99	28484	3335	0	0
T100	13719	0	0	0
T103	0	23715	0	0
T104	23543	0	0	0
T108	16535	0	0	0
T116	0	2900	0	0
T117	11117	0	0	0
T167	20113	0	0	0
T209	0	3110	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	16434244	0	0
T2	163780	115899	0	0
T3	93953	6078	0	0
T4	161903	0	0	0
T5	288963	0	0	0
T7	11814	0	0	0
T8	9939	0	0	0
T9	12719	0	0	0
T10	21338	0	0	0
T11	103266	84829	0	0
T23	0	52107	0	0
T97	11679	2442	0	0
T98	0	3262	0	0
T99	0	16733	0	0
T100	0	2291	0	0
T108	0	2895	0	0
T117	0	3914	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464973092	464088968	0	0
T1	14028	13772	0	0
T2	163780	163201	0	0
T3	93953	92372	0	0
T4	161903	161672	0	0
T5	288963	288952	0	0
T7	11814	11555	0	0
T8	9939	9709	0	0
T9	12719	12415	0	0
T10	21338	21056	0	0
T11	103266	102317	0	0