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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.02 93.94 96.35 95.79 92.36 97.10 96.33 93.28


Total test records in report: 1323
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html

T1052 /workspace/coverage/default/157.otp_ctrl_parallel_lc_esc.2815360045 Mar 28 03:34:39 PM PDT 24 Mar 28 03:34:45 PM PDT 24 284475491 ps
T1053 /workspace/coverage/default/42.otp_ctrl_alert_test.1167904944 Mar 28 03:33:18 PM PDT 24 Mar 28 03:33:20 PM PDT 24 48934403 ps
T1054 /workspace/coverage/default/51.otp_ctrl_init_fail.2197679163 Mar 28 03:33:43 PM PDT 24 Mar 28 03:33:48 PM PDT 24 613101054 ps
T1055 /workspace/coverage/default/13.otp_ctrl_dai_lock.118651393 Mar 28 03:31:37 PM PDT 24 Mar 28 03:31:53 PM PDT 24 4658894135 ps
T1056 /workspace/coverage/default/218.otp_ctrl_init_fail.147218890 Mar 28 03:34:53 PM PDT 24 Mar 28 03:34:56 PM PDT 24 364139114 ps
T1057 /workspace/coverage/default/298.otp_ctrl_init_fail.989057682 Mar 28 03:35:27 PM PDT 24 Mar 28 03:35:35 PM PDT 24 2298331327 ps
T1058 /workspace/coverage/default/21.otp_ctrl_dai_errs.1954722529 Mar 28 03:32:20 PM PDT 24 Mar 28 03:32:41 PM PDT 24 366453853 ps
T1059 /workspace/coverage/default/48.otp_ctrl_regwen.1067935569 Mar 28 03:33:40 PM PDT 24 Mar 28 03:33:45 PM PDT 24 203937907 ps
T15 /workspace/coverage/default/57.otp_ctrl_stress_all_with_rand_reset.456580055 Mar 28 03:33:43 PM PDT 24 Mar 28 03:43:29 PM PDT 24 228612915983 ps
T1060 /workspace/coverage/default/24.otp_ctrl_stress_all.2479162469 Mar 28 03:32:19 PM PDT 24 Mar 28 03:36:14 PM PDT 24 25113759675 ps
T1061 /workspace/coverage/default/139.otp_ctrl_parallel_lc_esc.4027059230 Mar 28 03:34:22 PM PDT 24 Mar 28 03:34:26 PM PDT 24 350370529 ps
T1062 /workspace/coverage/default/164.otp_ctrl_parallel_lc_esc.4203553239 Mar 28 03:34:38 PM PDT 24 Mar 28 03:35:01 PM PDT 24 3523982446 ps
T1063 /workspace/coverage/default/120.otp_ctrl_init_fail.3250760720 Mar 28 03:34:21 PM PDT 24 Mar 28 03:34:25 PM PDT 24 503982653 ps
T1064 /workspace/coverage/default/29.otp_ctrl_test_access.954921205 Mar 28 03:32:44 PM PDT 24 Mar 28 03:33:00 PM PDT 24 1779232567 ps
T1065 /workspace/coverage/default/1.otp_ctrl_dai_errs.2531867514 Mar 28 03:30:58 PM PDT 24 Mar 28 03:31:35 PM PDT 24 6078204909 ps
T1066 /workspace/coverage/default/0.otp_ctrl_macro_errs.3556158091 Mar 28 03:31:03 PM PDT 24 Mar 28 03:31:15 PM PDT 24 352083204 ps
T146 /workspace/coverage/default/191.otp_ctrl_parallel_lc_esc.783056446 Mar 28 03:34:51 PM PDT 24 Mar 28 03:34:59 PM PDT 24 1021352423 ps
T1067 /workspace/coverage/default/75.otp_ctrl_parallel_lc_esc.586977559 Mar 28 03:34:03 PM PDT 24 Mar 28 03:34:09 PM PDT 24 131692363 ps
T1068 /workspace/coverage/default/89.otp_ctrl_init_fail.1145695000 Mar 28 03:34:01 PM PDT 24 Mar 28 03:34:05 PM PDT 24 221706338 ps
T1069 /workspace/coverage/default/200.otp_ctrl_init_fail.4267992483 Mar 28 03:34:54 PM PDT 24 Mar 28 03:34:58 PM PDT 24 169699573 ps
T1070 /workspace/coverage/default/256.otp_ctrl_init_fail.3513724654 Mar 28 03:34:55 PM PDT 24 Mar 28 03:35:02 PM PDT 24 2574872845 ps
T267 /workspace/coverage/default/3.otp_ctrl_stress_all.3618058088 Mar 28 03:31:19 PM PDT 24 Mar 28 03:34:41 PM PDT 24 29261964358 ps
T1071 /workspace/coverage/default/18.otp_ctrl_dai_errs.1749735326 Mar 28 03:32:02 PM PDT 24 Mar 28 03:32:12 PM PDT 24 1297863700 ps
T1072 /workspace/coverage/default/17.otp_ctrl_parallel_lc_req.3657658724 Mar 28 03:31:54 PM PDT 24 Mar 28 03:32:05 PM PDT 24 3547694501 ps
T1073 /workspace/coverage/default/63.otp_ctrl_parallel_lc_esc.2314596816 Mar 28 03:33:40 PM PDT 24 Mar 28 03:33:47 PM PDT 24 772556440 ps
T1074 /workspace/coverage/default/114.otp_ctrl_init_fail.3315214862 Mar 28 03:34:23 PM PDT 24 Mar 28 03:34:28 PM PDT 24 293104167 ps
T1075 /workspace/coverage/default/3.otp_ctrl_dai_lock.4118038910 Mar 28 03:30:57 PM PDT 24 Mar 28 03:31:02 PM PDT 24 172588145 ps
T1076 /workspace/coverage/default/14.otp_ctrl_macro_errs.1741110262 Mar 28 03:31:46 PM PDT 24 Mar 28 03:32:19 PM PDT 24 1024180081 ps
T1077 /workspace/coverage/default/84.otp_ctrl_parallel_lc_esc.4037333390 Mar 28 03:34:00 PM PDT 24 Mar 28 03:34:07 PM PDT 24 2888144227 ps
T1078 /workspace/coverage/default/179.otp_ctrl_init_fail.533970103 Mar 28 03:34:40 PM PDT 24 Mar 28 03:34:48 PM PDT 24 108163880 ps
T1079 /workspace/coverage/default/26.otp_ctrl_macro_errs.3508090074 Mar 28 03:32:37 PM PDT 24 Mar 28 03:33:08 PM PDT 24 2441498091 ps
T1080 /workspace/coverage/default/102.otp_ctrl_parallel_lc_esc.1966303696 Mar 28 03:34:20 PM PDT 24 Mar 28 03:34:29 PM PDT 24 1121524817 ps
T1081 /workspace/coverage/default/8.otp_ctrl_dai_lock.3420293661 Mar 28 03:31:19 PM PDT 24 Mar 28 03:31:32 PM PDT 24 6188057377 ps
T1082 /workspace/coverage/default/29.otp_ctrl_stress_all.295192318 Mar 28 03:32:38 PM PDT 24 Mar 28 03:32:40 PM PDT 24 74956999 ps
T1083 /workspace/coverage/default/0.otp_ctrl_dai_lock.142734272 Mar 28 03:30:59 PM PDT 24 Mar 28 03:31:17 PM PDT 24 2543773599 ps
T1084 /workspace/coverage/default/24.otp_ctrl_parallel_lc_esc.2187354538 Mar 28 03:32:16 PM PDT 24 Mar 28 03:32:28 PM PDT 24 2698257194 ps
T1085 /workspace/coverage/default/23.otp_ctrl_parallel_lc_req.4247015535 Mar 28 03:32:17 PM PDT 24 Mar 28 03:32:34 PM PDT 24 1032410940 ps
T1086 /workspace/coverage/default/115.otp_ctrl_parallel_lc_esc.3914543835 Mar 28 03:34:22 PM PDT 24 Mar 28 03:34:29 PM PDT 24 708654463 ps
T1087 /workspace/coverage/default/45.otp_ctrl_init_fail.1845784277 Mar 28 03:33:21 PM PDT 24 Mar 28 03:33:29 PM PDT 24 145038706 ps
T1088 /workspace/coverage/default/31.otp_ctrl_parallel_lc_esc.3770249367 Mar 28 03:32:45 PM PDT 24 Mar 28 03:32:55 PM PDT 24 749010694 ps
T1089 /workspace/coverage/default/47.otp_ctrl_smoke.1129364199 Mar 28 03:33:19 PM PDT 24 Mar 28 03:33:25 PM PDT 24 2751779879 ps
T122 /workspace/coverage/default/6.otp_ctrl_parallel_lc_esc.194341252 Mar 28 03:31:20 PM PDT 24 Mar 28 03:31:30 PM PDT 24 394701234 ps
T1090 /workspace/coverage/default/131.otp_ctrl_parallel_lc_esc.3601422681 Mar 28 03:34:27 PM PDT 24 Mar 28 03:34:34 PM PDT 24 551760116 ps
T1091 /workspace/coverage/default/25.otp_ctrl_alert_test.2890535743 Mar 28 03:32:39 PM PDT 24 Mar 28 03:32:41 PM PDT 24 56757782 ps
T1092 /workspace/coverage/default/183.otp_ctrl_parallel_lc_esc.4113384395 Mar 28 03:34:44 PM PDT 24 Mar 28 03:34:53 PM PDT 24 516060349 ps
T1093 /workspace/coverage/default/19.otp_ctrl_parallel_lc_req.78906187 Mar 28 03:31:57 PM PDT 24 Mar 28 03:32:07 PM PDT 24 971494226 ps
T1094 /workspace/coverage/default/81.otp_ctrl_init_fail.3262425160 Mar 28 03:34:00 PM PDT 24 Mar 28 03:34:04 PM PDT 24 451347669 ps
T1095 /workspace/coverage/default/25.otp_ctrl_regwen.1999257703 Mar 28 03:32:17 PM PDT 24 Mar 28 03:32:21 PM PDT 24 249527051 ps
T1096 /workspace/coverage/default/57.otp_ctrl_init_fail.2135449884 Mar 28 03:33:37 PM PDT 24 Mar 28 03:33:41 PM PDT 24 85810222 ps
T1097 /workspace/coverage/default/180.otp_ctrl_parallel_lc_esc.3269896133 Mar 28 03:34:42 PM PDT 24 Mar 28 03:34:52 PM PDT 24 436599995 ps
T1098 /workspace/coverage/default/87.otp_ctrl_parallel_lc_esc.4007173585 Mar 28 03:34:01 PM PDT 24 Mar 28 03:34:05 PM PDT 24 240043461 ps
T1099 /workspace/coverage/default/295.otp_ctrl_init_fail.3151644745 Mar 28 03:35:31 PM PDT 24 Mar 28 03:35:36 PM PDT 24 573855151 ps
T264 /workspace/coverage/default/92.otp_ctrl_parallel_lc_esc.3530402266 Mar 28 03:34:02 PM PDT 24 Mar 28 03:34:13 PM PDT 24 1426978071 ps
T1100 /workspace/coverage/default/1.otp_ctrl_test_access.3543242485 Mar 28 03:30:59 PM PDT 24 Mar 28 03:31:24 PM PDT 24 866776518 ps
T1101 /workspace/coverage/default/18.otp_ctrl_stress_all.1458770802 Mar 28 03:32:00 PM PDT 24 Mar 28 03:33:00 PM PDT 24 9455385901 ps
T1102 /workspace/coverage/default/134.otp_ctrl_init_fail.564833735 Mar 28 03:34:23 PM PDT 24 Mar 28 03:34:27 PM PDT 24 451467128 ps
T1103 /workspace/coverage/default/73.otp_ctrl_parallel_lc_esc.3025770002 Mar 28 03:33:59 PM PDT 24 Mar 28 03:34:04 PM PDT 24 283393348 ps
T1104 /workspace/coverage/default/30.otp_ctrl_dai_errs.250924323 Mar 28 03:32:40 PM PDT 24 Mar 28 03:32:56 PM PDT 24 351792278 ps
T1105 /workspace/coverage/default/23.otp_ctrl_macro_errs.376790900 Mar 28 03:32:17 PM PDT 24 Mar 28 03:32:49 PM PDT 24 5404581277 ps
T1106 /workspace/coverage/default/129.otp_ctrl_parallel_lc_esc.3284444511 Mar 28 03:34:25 PM PDT 24 Mar 28 03:34:31 PM PDT 24 235176612 ps
T1107 /workspace/coverage/default/20.otp_ctrl_parallel_lc_esc.385949519 Mar 28 03:31:54 PM PDT 24 Mar 28 03:32:24 PM PDT 24 1226950942 ps
T1108 /workspace/coverage/default/31.otp_ctrl_regwen.1934025746 Mar 28 03:32:45 PM PDT 24 Mar 28 03:32:54 PM PDT 24 280396439 ps
T1109 /workspace/coverage/default/0.otp_ctrl_background_chks.1789592523 Mar 28 03:31:00 PM PDT 24 Mar 28 03:31:09 PM PDT 24 1012603706 ps
T1110 /workspace/coverage/default/46.otp_ctrl_test_access.4026833203 Mar 28 03:33:24 PM PDT 24 Mar 28 03:33:45 PM PDT 24 452897734 ps
T1111 /workspace/coverage/default/30.otp_ctrl_parallel_lc_req.1628503056 Mar 28 03:32:39 PM PDT 24 Mar 28 03:33:04 PM PDT 24 1367267876 ps
T1112 /workspace/coverage/default/26.otp_ctrl_check_fail.1674597052 Mar 28 03:32:34 PM PDT 24 Mar 28 03:33:09 PM PDT 24 5089777179 ps
T1113 /workspace/coverage/default/40.otp_ctrl_parallel_key_req.1668608728 Mar 28 03:32:59 PM PDT 24 Mar 28 03:33:25 PM PDT 24 843472575 ps
T1114 /workspace/coverage/default/8.otp_ctrl_background_chks.1779796450 Mar 28 03:31:17 PM PDT 24 Mar 28 03:31:53 PM PDT 24 16461303308 ps
T1115 /workspace/coverage/default/136.otp_ctrl_init_fail.3967042628 Mar 28 03:34:27 PM PDT 24 Mar 28 03:34:32 PM PDT 24 148465158 ps
T1116 /workspace/coverage/default/170.otp_ctrl_init_fail.1609720635 Mar 28 03:34:41 PM PDT 24 Mar 28 03:34:48 PM PDT 24 129634481 ps
T1117 /workspace/coverage/default/141.otp_ctrl_parallel_lc_esc.1984540023 Mar 28 03:34:23 PM PDT 24 Mar 28 03:34:29 PM PDT 24 263525037 ps
T1118 /workspace/coverage/default/90.otp_ctrl_stress_all_with_rand_reset.3109399391 Mar 28 03:34:02 PM PDT 24 Mar 28 03:40:41 PM PDT 24 28597922512 ps
T1119 /workspace/coverage/default/99.otp_ctrl_init_fail.2651840181 Mar 28 03:34:18 PM PDT 24 Mar 28 03:34:23 PM PDT 24 523558728 ps
T1120 /workspace/coverage/default/170.otp_ctrl_parallel_lc_esc.215626064 Mar 28 03:34:40 PM PDT 24 Mar 28 03:34:51 PM PDT 24 337587624 ps
T1121 /workspace/coverage/default/19.otp_ctrl_smoke.1054358776 Mar 28 03:31:58 PM PDT 24 Mar 28 03:32:05 PM PDT 24 813165317 ps
T1122 /workspace/coverage/default/24.otp_ctrl_dai_errs.3806443262 Mar 28 03:32:19 PM PDT 24 Mar 28 03:32:36 PM PDT 24 299107515 ps
T1123 /workspace/coverage/default/21.otp_ctrl_parallel_lc_req.3995068144 Mar 28 03:32:16 PM PDT 24 Mar 28 03:32:33 PM PDT 24 994485010 ps
T1124 /workspace/coverage/default/249.otp_ctrl_init_fail.2380840546 Mar 28 03:34:57 PM PDT 24 Mar 28 03:35:03 PM PDT 24 1631458888 ps
T1125 /workspace/coverage/default/45.otp_ctrl_stress_all_with_rand_reset.1653758762 Mar 28 03:33:24 PM PDT 24 Mar 28 03:42:17 PM PDT 24 52719466480 ps
T301 /workspace/coverage/default/3.otp_ctrl_test_access.283999312 Mar 28 03:31:16 PM PDT 24 Mar 28 03:31:25 PM PDT 24 1113251266 ps
T1126 /workspace/coverage/default/32.otp_ctrl_macro_errs.1971085482 Mar 28 03:32:46 PM PDT 24 Mar 28 03:33:17 PM PDT 24 1720272555 ps
T1127 /workspace/coverage/default/11.otp_ctrl_test_access.2444996613 Mar 28 03:31:32 PM PDT 24 Mar 28 03:32:12 PM PDT 24 1730383661 ps
T1128 /workspace/coverage/default/14.otp_ctrl_parallel_lc_esc.2150680766 Mar 28 03:31:40 PM PDT 24 Mar 28 03:31:43 PM PDT 24 79358778 ps
T1129 /workspace/coverage/default/52.otp_ctrl_stress_all_with_rand_reset.2424190178 Mar 28 03:33:42 PM PDT 24 Mar 28 03:46:27 PM PDT 24 176213787285 ps
T1130 /workspace/coverage/default/21.otp_ctrl_regwen.1184260290 Mar 28 03:32:18 PM PDT 24 Mar 28 03:32:25 PM PDT 24 537598092 ps
T1131 /workspace/coverage/default/56.otp_ctrl_init_fail.803455481 Mar 28 03:33:38 PM PDT 24 Mar 28 03:33:43 PM PDT 24 285281401 ps
T1132 /workspace/coverage/default/26.otp_ctrl_parallel_key_req.1244341141 Mar 28 03:32:40 PM PDT 24 Mar 28 03:32:58 PM PDT 24 951224832 ps
T1133 /workspace/coverage/default/31.otp_ctrl_parallel_lc_req.2027483850 Mar 28 03:32:41 PM PDT 24 Mar 28 03:33:00 PM PDT 24 709751226 ps
T1134 /workspace/coverage/default/238.otp_ctrl_init_fail.1736186619 Mar 28 03:34:53 PM PDT 24 Mar 28 03:34:57 PM PDT 24 467301260 ps
T1135 /workspace/coverage/default/44.otp_ctrl_stress_all_with_rand_reset.2896260579 Mar 28 03:33:22 PM PDT 24 Mar 28 03:46:47 PM PDT 24 320282958473 ps
T302 /workspace/coverage/default/34.otp_ctrl_stress_all_with_rand_reset.2042056021 Mar 28 03:32:58 PM PDT 24 Mar 28 04:01:53 PM PDT 24 719102289364 ps
T1136 /workspace/coverage/default/206.otp_ctrl_init_fail.2062962013 Mar 28 03:34:52 PM PDT 24 Mar 28 03:34:56 PM PDT 24 103871144 ps
T1137 /workspace/coverage/default/118.otp_ctrl_init_fail.429527464 Mar 28 03:34:21 PM PDT 24 Mar 28 03:34:27 PM PDT 24 458634551 ps
T1138 /workspace/coverage/default/11.otp_ctrl_init_fail.1728994149 Mar 28 03:31:33 PM PDT 24 Mar 28 03:31:38 PM PDT 24 154135953 ps
T1139 /workspace/coverage/default/50.otp_ctrl_init_fail.2460000459 Mar 28 03:33:39 PM PDT 24 Mar 28 03:33:44 PM PDT 24 429677534 ps
T1140 /workspace/coverage/default/13.otp_ctrl_parallel_key_req.678254910 Mar 28 03:31:36 PM PDT 24 Mar 28 03:31:49 PM PDT 24 496063601 ps
T128 /workspace/coverage/default/62.otp_ctrl_parallel_lc_esc.403436304 Mar 28 03:33:42 PM PDT 24 Mar 28 03:33:49 PM PDT 24 211804557 ps
T1141 /workspace/coverage/default/34.otp_ctrl_parallel_key_req.3912982549 Mar 28 03:32:59 PM PDT 24 Mar 28 03:33:24 PM PDT 24 1655774617 ps
T1142 /workspace/coverage/default/215.otp_ctrl_init_fail.547481948 Mar 28 03:34:55 PM PDT 24 Mar 28 03:34:59 PM PDT 24 111602195 ps
T1143 /workspace/coverage/default/155.otp_ctrl_init_fail.1662669999 Mar 28 03:34:37 PM PDT 24 Mar 28 03:34:41 PM PDT 24 284303786 ps
T1144 /workspace/coverage/default/43.otp_ctrl_regwen.1844239660 Mar 28 03:33:20 PM PDT 24 Mar 28 03:33:27 PM PDT 24 338687471 ps
T1145 /workspace/coverage/default/11.otp_ctrl_check_fail.725180102 Mar 28 03:31:36 PM PDT 24 Mar 28 03:31:43 PM PDT 24 384947716 ps
T37 /workspace/coverage/default/208.otp_ctrl_init_fail.3372847166 Mar 28 03:34:57 PM PDT 24 Mar 28 03:35:03 PM PDT 24 312117409 ps
T1146 /workspace/coverage/default/97.otp_ctrl_parallel_lc_esc.2966982446 Mar 28 03:34:21 PM PDT 24 Mar 28 03:34:28 PM PDT 24 457415206 ps
T303 /workspace/coverage/default/25.otp_ctrl_test_access.1103090549 Mar 28 03:32:20 PM PDT 24 Mar 28 03:32:39 PM PDT 24 930830151 ps
T1147 /workspace/coverage/default/240.otp_ctrl_init_fail.1848958308 Mar 28 03:34:54 PM PDT 24 Mar 28 03:34:59 PM PDT 24 206271472 ps
T1148 /workspace/coverage/default/2.otp_ctrl_stress_all.353800206 Mar 28 03:31:10 PM PDT 24 Mar 28 03:33:49 PM PDT 24 21184913122 ps
T1149 /workspace/coverage/default/13.otp_ctrl_test_access.3734316937 Mar 28 03:31:46 PM PDT 24 Mar 28 03:31:56 PM PDT 24 493766368 ps
T1150 /workspace/coverage/default/14.otp_ctrl_smoke.2676943718 Mar 28 03:31:37 PM PDT 24 Mar 28 03:31:52 PM PDT 24 6398621690 ps
T1151 /workspace/coverage/default/19.otp_ctrl_dai_errs.3419087987 Mar 28 03:32:03 PM PDT 24 Mar 28 03:32:21 PM PDT 24 295095763 ps
T1152 /workspace/coverage/default/182.otp_ctrl_init_fail.847502368 Mar 28 03:34:51 PM PDT 24 Mar 28 03:34:56 PM PDT 24 1580502518 ps
T1153 /workspace/coverage/default/161.otp_ctrl_init_fail.1476188058 Mar 28 03:34:39 PM PDT 24 Mar 28 03:34:44 PM PDT 24 384939698 ps
T1154 /workspace/coverage/default/5.otp_ctrl_regwen.3946565466 Mar 28 03:31:19 PM PDT 24 Mar 28 03:31:25 PM PDT 24 527805598 ps
T1155 /workspace/coverage/default/49.otp_ctrl_stress_all_with_rand_reset.3122575802 Mar 28 03:33:42 PM PDT 24 Mar 28 03:37:19 PM PDT 24 7934019458 ps
T1156 /workspace/coverage/default/33.otp_ctrl_test_access.4046574222 Mar 28 03:32:56 PM PDT 24 Mar 28 03:33:08 PM PDT 24 4235004736 ps
T1157 /workspace/coverage/default/15.otp_ctrl_macro_errs.919154790 Mar 28 03:31:54 PM PDT 24 Mar 28 03:32:32 PM PDT 24 12174496555 ps
T1158 /workspace/coverage/default/11.otp_ctrl_stress_all_with_rand_reset.330974860 Mar 28 03:31:45 PM PDT 24 Mar 28 04:11:39 PM PDT 24 163593512075 ps
T1159 /workspace/coverage/default/38.otp_ctrl_alert_test.3437353031 Mar 28 03:33:01 PM PDT 24 Mar 28 03:33:05 PM PDT 24 98846295 ps
T1160 /workspace/coverage/default/46.otp_ctrl_stress_all.3139721227 Mar 28 03:33:22 PM PDT 24 Mar 28 03:36:09 PM PDT 24 4613554001 ps
T1161 /workspace/coverage/default/42.otp_ctrl_dai_errs.1812786111 Mar 28 03:33:20 PM PDT 24 Mar 28 03:33:29 PM PDT 24 382286594 ps
T1162 /workspace/coverage/default/177.otp_ctrl_init_fail.3539498634 Mar 28 03:34:38 PM PDT 24 Mar 28 03:34:44 PM PDT 24 200628913 ps
T1163 /workspace/coverage/default/13.otp_ctrl_dai_errs.1499799858 Mar 28 03:31:38 PM PDT 24 Mar 28 03:31:54 PM PDT 24 537472111 ps
T1164 /workspace/coverage/default/61.otp_ctrl_init_fail.3411826078 Mar 28 03:33:42 PM PDT 24 Mar 28 03:33:47 PM PDT 24 142794953 ps
T1165 /workspace/coverage/default/44.otp_ctrl_parallel_lc_esc.3653588170 Mar 28 03:33:21 PM PDT 24 Mar 28 03:34:03 PM PDT 24 12730612493 ps
T1166 /workspace/coverage/default/12.otp_ctrl_parallel_lc_req.2350559117 Mar 28 03:31:39 PM PDT 24 Mar 28 03:31:49 PM PDT 24 393465248 ps
T1167 /workspace/coverage/default/37.otp_ctrl_check_fail.3450781945 Mar 28 03:33:03 PM PDT 24 Mar 28 03:33:46 PM PDT 24 3565610519 ps
T1168 /workspace/coverage/default/36.otp_ctrl_dai_lock.2813948183 Mar 28 03:32:58 PM PDT 24 Mar 28 03:33:13 PM PDT 24 1551888182 ps
T1169 /workspace/coverage/default/16.otp_ctrl_parallel_key_req.2373671839 Mar 28 03:31:57 PM PDT 24 Mar 28 03:32:29 PM PDT 24 8409961349 ps
T1170 /workspace/coverage/default/143.otp_ctrl_init_fail.584813583 Mar 28 03:34:51 PM PDT 24 Mar 28 03:34:57 PM PDT 24 285591024 ps
T1171 /workspace/coverage/default/190.otp_ctrl_parallel_lc_esc.703371764 Mar 28 03:34:44 PM PDT 24 Mar 28 03:34:56 PM PDT 24 799326693 ps
T1172 /workspace/coverage/default/61.otp_ctrl_parallel_lc_esc.4071010212 Mar 28 03:33:47 PM PDT 24 Mar 28 03:33:58 PM PDT 24 786803015 ps
T1173 /workspace/coverage/default/25.otp_ctrl_parallel_lc_esc.219149815 Mar 28 03:32:18 PM PDT 24 Mar 28 03:32:39 PM PDT 24 4180128351 ps
T1174 /workspace/coverage/default/21.otp_ctrl_parallel_lc_esc.12072600 Mar 28 03:32:18 PM PDT 24 Mar 28 03:32:31 PM PDT 24 513095354 ps
T1175 /workspace/coverage/default/108.otp_ctrl_init_fail.2637742991 Mar 28 03:34:20 PM PDT 24 Mar 28 03:34:25 PM PDT 24 118617770 ps
T1176 /workspace/coverage/default/41.otp_ctrl_parallel_key_req.102421943 Mar 28 03:33:20 PM PDT 24 Mar 28 03:34:17 PM PDT 24 22443773233 ps
T147 /workspace/coverage/default/25.otp_ctrl_stress_all.2884805730 Mar 28 03:32:37 PM PDT 24 Mar 28 03:35:52 PM PDT 24 12323999144 ps
T1177 /workspace/coverage/default/10.otp_ctrl_macro_errs.576159124 Mar 28 03:31:35 PM PDT 24 Mar 28 03:31:43 PM PDT 24 2796644775 ps
T1178 /workspace/coverage/default/30.otp_ctrl_regwen.2413979058 Mar 28 03:32:39 PM PDT 24 Mar 28 03:32:51 PM PDT 24 290417385 ps
T1179 /workspace/coverage/default/40.otp_ctrl_dai_errs.3721743501 Mar 28 03:33:05 PM PDT 24 Mar 28 03:33:15 PM PDT 24 186005205 ps
T1180 /workspace/coverage/default/37.otp_ctrl_parallel_key_req.1603359784 Mar 28 03:33:02 PM PDT 24 Mar 28 03:33:22 PM PDT 24 2626058922 ps
T1181 /workspace/coverage/default/284.otp_ctrl_init_fail.3031169651 Mar 28 03:35:29 PM PDT 24 Mar 28 03:35:33 PM PDT 24 346709462 ps
T1182 /workspace/coverage/default/80.otp_ctrl_init_fail.1354122617 Mar 28 03:33:59 PM PDT 24 Mar 28 03:34:03 PM PDT 24 337028336 ps
T1183 /workspace/coverage/default/220.otp_ctrl_init_fail.3165624403 Mar 28 03:34:52 PM PDT 24 Mar 28 03:34:56 PM PDT 24 383464853 ps
T1184 /workspace/coverage/default/26.otp_ctrl_dai_lock.581599147 Mar 28 03:32:36 PM PDT 24 Mar 28 03:32:54 PM PDT 24 9683323260 ps
T1185 /workspace/coverage/default/31.otp_ctrl_stress_all.22066520 Mar 28 03:32:40 PM PDT 24 Mar 28 03:36:07 PM PDT 24 20236344190 ps
T1186 /workspace/coverage/default/42.otp_ctrl_stress_all_with_rand_reset.2316979508 Mar 28 03:33:26 PM PDT 24 Mar 28 03:54:31 PM PDT 24 73721562830 ps
T1187 /workspace/coverage/default/169.otp_ctrl_init_fail.492560389 Mar 28 03:34:39 PM PDT 24 Mar 28 03:34:45 PM PDT 24 2517487326 ps
T1188 /workspace/coverage/default/162.otp_ctrl_init_fail.3341584772 Mar 28 03:34:38 PM PDT 24 Mar 28 03:34:43 PM PDT 24 425176175 ps
T1189 /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.1094870361 Mar 28 12:59:20 PM PDT 24 Mar 28 12:59:23 PM PDT 24 106203143 ps
T1190 /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.901715715 Mar 28 01:00:09 PM PDT 24 Mar 28 01:00:11 PM PDT 24 40615341 ps
T1191 /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.1750342556 Mar 28 12:59:08 PM PDT 24 Mar 28 12:59:13 PM PDT 24 70334982 ps
T281 /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.382602878 Mar 28 12:59:45 PM PDT 24 Mar 28 12:59:47 PM PDT 24 142226672 ps
T282 /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.3882543925 Mar 28 12:59:43 PM PDT 24 Mar 28 12:59:45 PM PDT 24 154019974 ps
T278 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.2951611082 Mar 28 12:59:19 PM PDT 24 Mar 28 12:59:22 PM PDT 24 117973822 ps
T279 /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.3870888751 Mar 28 12:59:57 PM PDT 24 Mar 28 01:00:00 PM PDT 24 111923717 ps
T1192 /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.3952889826 Mar 28 12:59:43 PM PDT 24 Mar 28 12:59:48 PM PDT 24 80301924 ps
T398 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.2817399646 Mar 28 12:59:20 PM PDT 24 Mar 28 12:59:22 PM PDT 24 76856931 ps
T275 /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.724011549 Mar 28 12:59:57 PM PDT 24 Mar 28 01:00:08 PM PDT 24 1304290413 ps
T280 /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.2531137547 Mar 28 12:59:56 PM PDT 24 Mar 28 12:59:59 PM PDT 24 159730215 ps
T333 /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.2782090832 Mar 28 01:00:07 PM PDT 24 Mar 28 01:00:10 PM PDT 24 108565630 ps
T1193 /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.4276951826 Mar 28 01:00:08 PM PDT 24 Mar 28 01:00:09 PM PDT 24 39532073 ps
T1194 /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.1171568255 Mar 28 12:59:43 PM PDT 24 Mar 28 12:59:47 PM PDT 24 106255609 ps
T334 /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.1390628555 Mar 28 12:59:08 PM PDT 24 Mar 28 12:59:10 PM PDT 24 166606452 ps
T1195 /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.3531727585 Mar 28 12:59:31 PM PDT 24 Mar 28 12:59:32 PM PDT 24 47528636 ps
T335 /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.2771111092 Mar 28 12:59:10 PM PDT 24 Mar 28 12:59:13 PM PDT 24 137908550 ps
T312 /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.4288131939 Mar 28 12:59:31 PM PDT 24 Mar 28 12:59:33 PM PDT 24 73295575 ps
T1196 /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.2039112721 Mar 28 12:59:33 PM PDT 24 Mar 28 12:59:37 PM PDT 24 103270364 ps
T1197 /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.1102442614 Mar 28 12:59:35 PM PDT 24 Mar 28 12:59:39 PM PDT 24 1124962852 ps
T1198 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.491059415 Mar 28 12:59:07 PM PDT 24 Mar 28 12:59:11 PM PDT 24 306177606 ps
T1199 /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.2680714600 Mar 28 01:00:15 PM PDT 24 Mar 28 01:00:16 PM PDT 24 38508313 ps
T313 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.1316760288 Mar 28 12:59:07 PM PDT 24 Mar 28 12:59:13 PM PDT 24 135563935 ps
T1200 /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.2777098842 Mar 28 12:59:18 PM PDT 24 Mar 28 12:59:21 PM PDT 24 87486006 ps
T276 /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.1181194212 Mar 28 12:59:57 PM PDT 24 Mar 28 01:00:07 PM PDT 24 1215705304 ps
T336 /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.4039319024 Mar 28 12:59:34 PM PDT 24 Mar 28 12:59:36 PM PDT 24 48589090 ps
T1201 /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.1188458065 Mar 28 12:59:08 PM PDT 24 Mar 28 12:59:09 PM PDT 24 70059401 ps
T337 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.2550940123 Mar 28 12:59:09 PM PDT 24 Mar 28 12:59:10 PM PDT 24 74246558 ps
T1202 /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.1239246803 Mar 28 12:59:44 PM PDT 24 Mar 28 12:59:46 PM PDT 24 73734712 ps
T314 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.1846935684 Mar 28 12:59:07 PM PDT 24 Mar 28 12:59:09 PM PDT 24 369425261 ps
T326 /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.3450738656 Mar 28 01:00:35 PM PDT 24 Mar 28 01:00:37 PM PDT 24 73597375 ps
T1203 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.1232665175 Mar 28 12:59:14 PM PDT 24 Mar 28 12:59:20 PM PDT 24 242240143 ps
T1204 /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.374152162 Mar 28 01:00:49 PM PDT 24 Mar 28 01:00:50 PM PDT 24 73166419 ps
T277 /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.1290274602 Mar 28 12:59:59 PM PDT 24 Mar 28 01:00:18 PM PDT 24 10276377010 ps
T327 /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.3818276158 Mar 28 12:59:57 PM PDT 24 Mar 28 12:59:59 PM PDT 24 711333849 ps
T1205 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.1683310817 Mar 28 12:59:58 PM PDT 24 Mar 28 01:00:00 PM PDT 24 71768351 ps
T1206 /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.1749898847 Mar 28 12:59:56 PM PDT 24 Mar 28 12:59:58 PM PDT 24 556510194 ps
T1207 /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.2682792689 Mar 28 01:00:11 PM PDT 24 Mar 28 01:00:13 PM PDT 24 269691743 ps
T338 /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.4239887556 Mar 28 12:59:31 PM PDT 24 Mar 28 12:59:34 PM PDT 24 1062764087 ps
T1208 /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.3261115534 Mar 28 01:00:22 PM PDT 24 Mar 28 01:00:25 PM PDT 24 565490016 ps
T1209 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.3256263402 Mar 28 12:59:30 PM PDT 24 Mar 28 12:59:38 PM PDT 24 346745695 ps
T1210 /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.889264890 Mar 28 01:00:24 PM PDT 24 Mar 28 01:00:26 PM PDT 24 143337135 ps
T1211 /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.185771301 Mar 28 01:00:08 PM PDT 24 Mar 28 01:00:10 PM PDT 24 64855648 ps
T1212 /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.468863796 Mar 28 12:59:32 PM PDT 24 Mar 28 12:59:39 PM PDT 24 363551861 ps
T1213 /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.2075181415 Mar 28 01:00:35 PM PDT 24 Mar 28 01:00:39 PM PDT 24 209476394 ps
T1214 /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.1706097301 Mar 28 01:00:08 PM PDT 24 Mar 28 01:00:10 PM PDT 24 63185886 ps
T1215 /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.1613758025 Mar 28 01:00:12 PM PDT 24 Mar 28 01:00:14 PM PDT 24 140306487 ps
T1216 /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.3105463334 Mar 28 12:59:56 PM PDT 24 Mar 28 12:59:58 PM PDT 24 90187368 ps
T371 /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.3727561389 Mar 28 12:59:42 PM PDT 24 Mar 28 12:59:57 PM PDT 24 9735565085 ps
T1217 /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.3201752721 Mar 28 12:59:44 PM PDT 24 Mar 28 12:59:46 PM PDT 24 108676586 ps
T1218 /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.235738049 Mar 28 12:59:35 PM PDT 24 Mar 28 12:59:37 PM PDT 24 175001623 ps
T1219 /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.1912476787 Mar 28 12:59:44 PM PDT 24 Mar 28 12:59:47 PM PDT 24 942163547 ps
T1220 /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.1634033504 Mar 28 12:59:56 PM PDT 24 Mar 28 01:00:06 PM PDT 24 2583168103 ps
T1221 /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.3920181157 Mar 28 12:59:18 PM PDT 24 Mar 28 12:59:20 PM PDT 24 517489888 ps
T1222 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.2695947225 Mar 28 12:59:32 PM PDT 24 Mar 28 12:59:35 PM PDT 24 55560864 ps
T328 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.988042344 Mar 28 12:59:56 PM PDT 24 Mar 28 12:59:58 PM PDT 24 82204349 ps
T1223 /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.1499933257 Mar 28 01:00:10 PM PDT 24 Mar 28 01:00:11 PM PDT 24 49150778 ps
T1224 /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.2601603385 Mar 28 12:59:57 PM PDT 24 Mar 28 01:00:00 PM PDT 24 203148859 ps
T375 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.2026577121 Mar 28 12:59:30 PM PDT 24 Mar 28 12:59:41 PM PDT 24 783040500 ps
T1225 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.1747144541 Mar 28 12:59:57 PM PDT 24 Mar 28 01:00:00 PM PDT 24 109856027 ps
T372 /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.3418186606 Mar 28 12:59:34 PM PDT 24 Mar 28 01:00:04 PM PDT 24 20240349722 ps
T1226 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.93490556 Mar 28 12:59:20 PM PDT 24 Mar 28 12:59:22 PM PDT 24 75750101 ps
T373 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.4055509798 Mar 28 12:59:44 PM PDT 24 Mar 28 12:59:54 PM PDT 24 1373441639 ps
T1227 /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.3816877564 Mar 28 01:00:20 PM PDT 24 Mar 28 01:00:21 PM PDT 24 36555785 ps
T1228 /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.3960001091 Mar 28 01:00:01 PM PDT 24 Mar 28 01:00:03 PM PDT 24 42233687 ps
T1229 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.3527571207 Mar 28 12:59:07 PM PDT 24 Mar 28 12:59:12 PM PDT 24 209318683 ps
T315 /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.120919684 Mar 28 12:59:45 PM PDT 24 Mar 28 12:59:47 PM PDT 24 41485897 ps
T1230 /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.3343934355 Mar 28 01:00:08 PM PDT 24 Mar 28 01:00:10 PM PDT 24 42775837 ps
T1231 /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.3292248622 Mar 28 12:59:19 PM PDT 24 Mar 28 12:59:21 PM PDT 24 48038486 ps
T316 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.419695583 Mar 28 12:59:08 PM PDT 24 Mar 28 12:59:09 PM PDT 24 42100483 ps
T1232 /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.2244416513 Mar 28 12:59:43 PM PDT 24 Mar 28 12:59:45 PM PDT 24 552263370 ps
T1233 /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.2413032629 Mar 28 12:59:35 PM PDT 24 Mar 28 12:59:37 PM PDT 24 543193089 ps
T1234 /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.1437200863 Mar 28 12:59:56 PM PDT 24 Mar 28 12:59:58 PM PDT 24 76173687 ps
T1235 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.1381626271 Mar 28 12:59:07 PM PDT 24 Mar 28 12:59:11 PM PDT 24 372846451 ps
T1236 /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.2410950263 Mar 28 12:59:31 PM PDT 24 Mar 28 12:59:35 PM PDT 24 113863500 ps
T1237 /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.1563996146 Mar 28 01:00:35 PM PDT 24 Mar 28 01:00:37 PM PDT 24 151687291 ps
T1238 /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.1832786051 Mar 28 12:59:17 PM PDT 24 Mar 28 12:59:19 PM PDT 24 114962435 ps
T1239 /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.3649419615 Mar 28 12:59:43 PM PDT 24 Mar 28 12:59:46 PM PDT 24 146612951 ps
T1240 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.3785102048 Mar 28 12:59:08 PM PDT 24 Mar 28 12:59:11 PM PDT 24 133905522 ps
T1241 /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.135713550 Mar 28 12:59:10 PM PDT 24 Mar 28 12:59:17 PM PDT 24 183556758 ps
T1242 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.696614710 Mar 28 12:59:23 PM PDT 24 Mar 28 12:59:26 PM PDT 24 76139945 ps
T1243 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.3461730378 Mar 28 12:59:31 PM PDT 24 Mar 28 12:59:34 PM PDT 24 1147482466 ps
T317 /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.1683811906 Mar 28 12:59:30 PM PDT 24 Mar 28 12:59:32 PM PDT 24 46199580 ps
T1244 /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.1467933306 Mar 28 01:00:01 PM PDT 24 Mar 28 01:00:07 PM PDT 24 968861402 ps
T329 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.2011343874 Mar 28 12:59:24 PM PDT 24 Mar 28 12:59:30 PM PDT 24 323789341 ps
T1245 /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.1209259351 Mar 28 12:59:19 PM PDT 24 Mar 28 12:59:30 PM PDT 24 10330982466 ps
T1246 /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.2407327629 Mar 28 01:00:23 PM PDT 24 Mar 28 01:00:24 PM PDT 24 39508516 ps
T1247 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.389765656 Mar 28 12:59:17 PM PDT 24 Mar 28 12:59:20 PM PDT 24 153217302 ps
T331 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.2542912250 Mar 28 12:59:08 PM PDT 24 Mar 28 12:59:10 PM PDT 24 51944789 ps
T330 /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.2277377808 Mar 28 12:59:42 PM PDT 24 Mar 28 12:59:44 PM PDT 24 40757031 ps
T1248 /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.2488067727 Mar 28 01:00:09 PM PDT 24 Mar 28 01:00:11 PM PDT 24 42717295 ps
T1249 /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.2493337593 Mar 28 12:59:22 PM PDT 24 Mar 28 12:59:26 PM PDT 24 128205506 ps
T1250 /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.612539147 Mar 28 01:00:09 PM PDT 24 Mar 28 01:00:11 PM PDT 24 87498692 ps
T1251 /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.934031608 Mar 28 12:59:31 PM PDT 24 Mar 28 12:59:34 PM PDT 24 123402818 ps
T1252 /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.3667566421 Mar 28 01:00:00 PM PDT 24 Mar 28 01:00:02 PM PDT 24 261386585 ps
T1253 /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.3088796572 Mar 28 12:59:58 PM PDT 24 Mar 28 01:00:04 PM PDT 24 286656212 ps
T1254 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.3997389469 Mar 28 12:59:20 PM PDT 24 Mar 28 12:59:22 PM PDT 24 39840946 ps
T1255 /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.2302463257 Mar 28 12:59:56 PM PDT 24 Mar 28 12:59:59 PM PDT 24 1042640110 ps
T332 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.759825792 Mar 28 12:59:13 PM PDT 24 Mar 28 12:59:19 PM PDT 24 194807833 ps
T374 /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.3496615855 Mar 28 01:00:00 PM PDT 24 Mar 28 01:00:11 PM PDT 24 2249048504 ps
T1256 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.3012248650 Mar 28 12:59:18 PM PDT 24 Mar 28 12:59:22 PM PDT 24 85864493 ps
T379 /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.1584937307 Mar 28 12:59:11 PM PDT 24 Mar 28 12:59:36 PM PDT 24 5068948036 ps
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