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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.02 93.94 96.35 95.79 92.36 97.10 96.33 93.28


Total test records in report: 1323
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T1257 /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.1644361296 Mar 28 12:59:19 PM PDT 24 Mar 28 12:59:20 PM PDT 24 73386753 ps
T1258 /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.3854087241 Mar 28 01:00:11 PM PDT 24 Mar 28 01:00:13 PM PDT 24 217840580 ps
T1259 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.2332078437 Mar 28 12:59:56 PM PDT 24 Mar 28 01:00:00 PM PDT 24 349334646 ps
T1260 /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.656246314 Mar 28 12:59:58 PM PDT 24 Mar 28 01:00:00 PM PDT 24 576270761 ps
T380 /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.3194716812 Mar 28 01:00:08 PM PDT 24 Mar 28 01:00:20 PM PDT 24 1539780243 ps
T1261 /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.3074256179 Mar 28 01:00:09 PM PDT 24 Mar 28 01:00:13 PM PDT 24 247946278 ps
T1262 /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.2476616990 Mar 28 12:59:45 PM PDT 24 Mar 28 12:59:51 PM PDT 24 298208362 ps
T1263 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.2577940821 Mar 28 12:59:18 PM PDT 24 Mar 28 12:59:21 PM PDT 24 365118714 ps
T1264 /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.3115013021 Mar 28 12:59:10 PM PDT 24 Mar 28 12:59:11 PM PDT 24 38105095 ps
T1265 /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.1878021501 Mar 28 01:00:11 PM PDT 24 Mar 28 01:00:13 PM PDT 24 107105677 ps
T1266 /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.3068446191 Mar 28 01:00:35 PM PDT 24 Mar 28 01:00:37 PM PDT 24 38473681 ps
T1267 /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.1392301582 Mar 28 12:59:44 PM PDT 24 Mar 28 12:59:46 PM PDT 24 703847552 ps
T1268 /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.280559044 Mar 28 01:00:07 PM PDT 24 Mar 28 01:00:09 PM PDT 24 74486694 ps
T1269 /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.2612219533 Mar 28 12:59:57 PM PDT 24 Mar 28 12:59:59 PM PDT 24 673531475 ps
T1270 /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.2969456728 Mar 28 01:00:09 PM PDT 24 Mar 28 01:00:11 PM PDT 24 41961887 ps
T1271 /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.256826654 Mar 28 01:00:15 PM PDT 24 Mar 28 01:00:17 PM PDT 24 560484846 ps
T1272 /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.1887753453 Mar 28 12:59:34 PM PDT 24 Mar 28 12:59:36 PM PDT 24 48902381 ps
T1273 /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.2493840427 Mar 28 01:00:14 PM PDT 24 Mar 28 01:00:16 PM PDT 24 39823855 ps
T1274 /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.905210763 Mar 28 01:00:11 PM PDT 24 Mar 28 01:00:14 PM PDT 24 552270886 ps
T1275 /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.3394559653 Mar 28 12:59:13 PM PDT 24 Mar 28 12:59:15 PM PDT 24 126802483 ps
T1276 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.621710899 Mar 28 01:00:47 PM PDT 24 Mar 28 01:00:49 PM PDT 24 264832680 ps
T377 /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.3771271671 Mar 28 12:59:18 PM PDT 24 Mar 28 12:59:41 PM PDT 24 4846242604 ps
T1277 /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.1063928927 Mar 28 01:00:07 PM PDT 24 Mar 28 01:00:09 PM PDT 24 39070595 ps
T1278 /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.424403491 Mar 28 12:59:45 PM PDT 24 Mar 28 12:59:46 PM PDT 24 37958542 ps
T376 /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.4046444884 Mar 28 12:59:08 PM PDT 24 Mar 28 12:59:27 PM PDT 24 1232856573 ps
T1279 /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.3982481550 Mar 28 01:00:25 PM PDT 24 Mar 28 01:00:27 PM PDT 24 559758973 ps
T1280 /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.1636714064 Mar 28 12:59:09 PM PDT 24 Mar 28 12:59:10 PM PDT 24 130663913 ps
T1281 /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.2796453556 Mar 28 01:00:12 PM PDT 24 Mar 28 01:00:14 PM PDT 24 142712359 ps
T1282 /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.1436991849 Mar 28 12:59:31 PM PDT 24 Mar 28 12:59:32 PM PDT 24 129272569 ps
T1283 /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.1889400692 Mar 28 12:59:56 PM PDT 24 Mar 28 12:59:59 PM PDT 24 185624638 ps
T1284 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.2985271970 Mar 28 12:59:24 PM PDT 24 Mar 28 12:59:30 PM PDT 24 509838088 ps
T1285 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.3784625130 Mar 28 12:59:09 PM PDT 24 Mar 28 12:59:15 PM PDT 24 506303616 ps
T1286 /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.675269398 Mar 28 12:59:32 PM PDT 24 Mar 28 12:59:35 PM PDT 24 103783946 ps
T381 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.4254511442 Mar 28 01:00:01 PM PDT 24 Mar 28 01:00:23 PM PDT 24 2003866492 ps
T1287 /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.3301933475 Mar 28 12:59:13 PM PDT 24 Mar 28 12:59:14 PM PDT 24 109363302 ps
T1288 /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.3802698979 Mar 28 01:00:08 PM PDT 24 Mar 28 01:00:10 PM PDT 24 68919138 ps
T1289 /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.78445313 Mar 28 12:59:13 PM PDT 24 Mar 28 12:59:33 PM PDT 24 1307169168 ps
T1290 /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.3470669943 Mar 28 01:00:10 PM PDT 24 Mar 28 01:00:11 PM PDT 24 40266893 ps
T1291 /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.1946202945 Mar 28 01:00:11 PM PDT 24 Mar 28 01:00:15 PM PDT 24 63198814 ps
T1292 /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.575925135 Mar 28 12:59:30 PM PDT 24 Mar 28 12:59:33 PM PDT 24 136150114 ps
T1293 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.2852716825 Mar 28 12:59:31 PM PDT 24 Mar 28 12:59:34 PM PDT 24 108194530 ps
T1294 /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.3998266166 Mar 28 12:59:57 PM PDT 24 Mar 28 01:00:01 PM PDT 24 1401585300 ps
T1295 /workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.3265072443 Mar 28 01:00:09 PM PDT 24 Mar 28 01:00:11 PM PDT 24 586835817 ps
T1296 /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.2480435433 Mar 28 01:00:08 PM PDT 24 Mar 28 01:00:11 PM PDT 24 66673561 ps
T1297 /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.3468964932 Mar 28 12:59:43 PM PDT 24 Mar 28 12:59:53 PM PDT 24 1236498943 ps
T1298 /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.398250649 Mar 28 01:00:00 PM PDT 24 Mar 28 01:00:03 PM PDT 24 104140348 ps
T1299 /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.895114831 Mar 28 12:59:18 PM PDT 24 Mar 28 12:59:19 PM PDT 24 539832950 ps
T1300 /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.303341482 Mar 28 01:00:11 PM PDT 24 Mar 28 01:00:12 PM PDT 24 38181519 ps
T378 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.366110097 Mar 28 12:59:43 PM PDT 24 Mar 28 12:59:54 PM PDT 24 1258570679 ps
T1301 /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.929662404 Mar 28 12:59:57 PM PDT 24 Mar 28 12:59:59 PM PDT 24 38396224 ps
T1302 /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.2215016821 Mar 28 01:00:08 PM PDT 24 Mar 28 01:00:09 PM PDT 24 547887142 ps
T1303 /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.1135159107 Mar 28 01:00:11 PM PDT 24 Mar 28 01:00:13 PM PDT 24 41268868 ps
T1304 /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.1997482030 Mar 28 01:00:07 PM PDT 24 Mar 28 01:00:14 PM PDT 24 335888204 ps
T1305 /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.581695246 Mar 28 12:59:57 PM PDT 24 Mar 28 12:59:59 PM PDT 24 76171640 ps
T1306 /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.3763329385 Mar 28 12:59:44 PM PDT 24 Mar 28 12:59:46 PM PDT 24 71572551 ps
T283 /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.442314639 Mar 28 12:59:32 PM PDT 24 Mar 28 12:59:50 PM PDT 24 1284660671 ps
T1307 /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.245587688 Mar 28 12:59:32 PM PDT 24 Mar 28 12:59:35 PM PDT 24 136042340 ps
T1308 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.3848752693 Mar 28 12:59:13 PM PDT 24 Mar 28 12:59:15 PM PDT 24 94017610 ps
T1309 /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.1485979787 Mar 28 12:59:13 PM PDT 24 Mar 28 12:59:15 PM PDT 24 148257486 ps
T1310 /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.3388901442 Mar 28 12:59:07 PM PDT 24 Mar 28 12:59:09 PM PDT 24 70457301 ps
T1311 /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.1372364558 Mar 28 01:00:23 PM PDT 24 Mar 28 01:00:24 PM PDT 24 133761728 ps
T1312 /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.3238583314 Mar 28 12:59:43 PM PDT 24 Mar 28 12:59:45 PM PDT 24 119394366 ps
T1313 /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.1639859940 Mar 28 01:00:09 PM PDT 24 Mar 28 01:00:11 PM PDT 24 564043937 ps
T1314 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.459022303 Mar 28 12:59:30 PM PDT 24 Mar 28 12:59:51 PM PDT 24 3507667224 ps
T1315 /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.3262649060 Mar 28 12:59:12 PM PDT 24 Mar 28 12:59:19 PM PDT 24 183006262 ps
T1316 /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.3174845863 Mar 28 01:00:09 PM PDT 24 Mar 28 01:00:11 PM PDT 24 139479868 ps
T1317 /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.2798775896 Mar 28 01:00:01 PM PDT 24 Mar 28 01:00:04 PM PDT 24 125463512 ps
T1318 /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.1640096499 Mar 28 12:59:18 PM PDT 24 Mar 28 12:59:20 PM PDT 24 38874808 ps
T1319 /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.1534748531 Mar 28 01:00:08 PM PDT 24 Mar 28 01:00:11 PM PDT 24 38257922 ps
T1320 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.3762179311 Mar 28 01:00:00 PM PDT 24 Mar 28 01:00:02 PM PDT 24 50168726 ps
T1321 /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.3810164951 Mar 28 01:00:08 PM PDT 24 Mar 28 01:00:19 PM PDT 24 2444634540 ps
T1322 /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.3025839573 Mar 28 12:59:31 PM PDT 24 Mar 28 12:59:33 PM PDT 24 93066618 ps
T1323 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.847476483 Mar 28 12:59:43 PM PDT 24 Mar 28 12:59:47 PM PDT 24 199983599 ps

Test location /workspace/coverage/default/35.otp_ctrl_stress_all_with_rand_reset.120208427
Short name T5
Test name
Test status
Simulation time 120402546662 ps
CPU time 922.66 seconds
Started Mar 28 03:33:01 PM PDT 24
Finished Mar 28 03:48:26 PM PDT 24
Peak memory 330772 kb
Host smart-11bc1031-a01b-40ab-bc4a-edc9fcf2ce5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120208427 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all_with_rand_reset.120208427
Directory /workspace/35.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all.3632080303
Short name T63
Test name
Test status
Simulation time 9357047380 ps
CPU time 196.51 seconds
Started Mar 28 03:31:35 PM PDT 24
Finished Mar 28 03:34:52 PM PDT 24
Peak memory 258748 kb
Host smart-0565896d-4c2a-4968-99b6-88c60d5159c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632080303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all.
3632080303
Directory /workspace/8.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.otp_ctrl_check_fail.1557364446
Short name T11
Test name
Test status
Simulation time 17211247016 ps
CPU time 42.69 seconds
Started Mar 28 03:32:18 PM PDT 24
Finished Mar 28 03:33:01 PM PDT 24
Peak memory 246216 kb
Host smart-61a193bf-19aa-4b78-a822-46921d663798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557364446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.1557364446
Directory /workspace/24.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all.1841125073
Short name T129
Test name
Test status
Simulation time 55739018667 ps
CPU time 266.96 seconds
Started Mar 28 03:31:57 PM PDT 24
Finished Mar 28 03:36:26 PM PDT 24
Peak memory 256884 kb
Host smart-4ca8d26f-6aad-4ccd-8ef7-a05223ef364d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841125073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all
.1841125073
Directory /workspace/17.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all.2663738764
Short name T91
Test name
Test status
Simulation time 5726975547 ps
CPU time 88.54 seconds
Started Mar 28 03:33:37 PM PDT 24
Finished Mar 28 03:35:06 PM PDT 24
Peak memory 248716 kb
Host smart-4b50c873-df2d-44d2-b67f-9894a977b600
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663738764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all
.2663738764
Directory /workspace/49.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/191.otp_ctrl_init_fail.1644117396
Short name T163
Test name
Test status
Simulation time 159807817 ps
CPU time 3.97 seconds
Started Mar 28 03:34:43 PM PDT 24
Finished Mar 28 03:34:50 PM PDT 24
Peak memory 241816 kb
Host smart-b7bd787f-87ad-4051-b76d-3789a0526b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644117396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.1644117396
Directory /workspace/191.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_sec_cm.1277921882
Short name T18
Test name
Test status
Simulation time 166077740024 ps
CPU time 205.73 seconds
Started Mar 28 03:31:17 PM PDT 24
Finished Mar 28 03:34:43 PM PDT 24
Peak memory 267416 kb
Host smart-ffc6cec1-0c92-42c1-8a10-d61dee96b86a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277921882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.1277921882
Directory /workspace/3.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all_with_rand_reset.2082991033
Short name T12
Test name
Test status
Simulation time 91786879545 ps
CPU time 860.54 seconds
Started Mar 28 03:32:20 PM PDT 24
Finished Mar 28 03:46:41 PM PDT 24
Peak memory 263360 kb
Host smart-7b86bd2f-fd41-4ccd-b77b-f64b9cfd5454
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082991033 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all_with_rand_reset.2082991033
Directory /workspace/22.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.otp_ctrl_init_fail.133166749
Short name T65
Test name
Test status
Simulation time 191777498 ps
CPU time 4.78 seconds
Started Mar 28 03:34:00 PM PDT 24
Finished Mar 28 03:34:05 PM PDT 24
Peak memory 241836 kb
Host smart-59c54d8a-657b-4326-9eee-1ea50042e894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133166749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.133166749
Directory /workspace/86.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all.3134793124
Short name T94
Test name
Test status
Simulation time 30426270816 ps
CPU time 271.77 seconds
Started Mar 28 03:31:38 PM PDT 24
Finished Mar 28 03:36:10 PM PDT 24
Peak memory 282040 kb
Host smart-57872a83-1cc9-49ef-9e46-c41d46bb06c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134793124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all.
3134793124
Directory /workspace/9.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/107.otp_ctrl_init_fail.1428427808
Short name T22
Test name
Test status
Simulation time 634942520 ps
CPU time 5.03 seconds
Started Mar 28 03:34:20 PM PDT 24
Finished Mar 28 03:34:25 PM PDT 24
Peak memory 241708 kb
Host smart-e55c0681-582f-492f-9ef6-913171530c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428427808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.1428427808
Directory /workspace/107.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.724011549
Short name T275
Test name
Test status
Simulation time 1304290413 ps
CPU time 10.55 seconds
Started Mar 28 12:59:57 PM PDT 24
Finished Mar 28 01:00:08 PM PDT 24
Peak memory 244044 kb
Host smart-9f9236df-9132-4aa8-902a-ea28be1ceeeb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724011549 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_in
tg_err.724011549
Directory /workspace/13.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/283.otp_ctrl_init_fail.988756757
Short name T7
Test name
Test status
Simulation time 302945816 ps
CPU time 4.52 seconds
Started Mar 28 03:35:24 PM PDT 24
Finished Mar 28 03:35:29 PM PDT 24
Peak memory 241996 kb
Host smart-01de7beb-8e31-442e-bb75-751a29dcc251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988756757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.988756757
Directory /workspace/283.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all.4147139199
Short name T130
Test name
Test status
Simulation time 23771196683 ps
CPU time 357.13 seconds
Started Mar 28 03:33:09 PM PDT 24
Finished Mar 28 03:39:08 PM PDT 24
Peak memory 290732 kb
Host smart-d7e41dd9-2b4c-4c21-a8a4-3d6956e3cb60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147139199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all
.4147139199
Directory /workspace/39.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/93.otp_ctrl_init_fail.632105900
Short name T43
Test name
Test status
Simulation time 215420646 ps
CPU time 4.91 seconds
Started Mar 28 03:34:04 PM PDT 24
Finished Mar 28 03:34:09 PM PDT 24
Peak memory 241812 kb
Host smart-2a257cbc-ebc1-4b9c-b872-467ae3359017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632105900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.632105900
Directory /workspace/93.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_macro_errs.1588519390
Short name T171
Test name
Test status
Simulation time 6684323051 ps
CPU time 41.93 seconds
Started Mar 28 03:33:19 PM PDT 24
Finished Mar 28 03:34:01 PM PDT 24
Peak memory 252828 kb
Host smart-7cc3d00f-c04e-4a62-ab5c-42924ba277a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588519390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_macro_errs.1588519390
Directory /workspace/44.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_check_fail.1328790505
Short name T138
Test name
Test status
Simulation time 553232694 ps
CPU time 16.51 seconds
Started Mar 28 03:31:15 PM PDT 24
Finished Mar 28 03:31:32 PM PDT 24
Peak memory 242292 kb
Host smart-bb31d97a-c2a1-4790-9e0e-5e2d6bb9de48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328790505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.1328790505
Directory /workspace/3.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/166.otp_ctrl_init_fail.2823697980
Short name T19
Test name
Test status
Simulation time 664478055 ps
CPU time 5.43 seconds
Started Mar 28 03:34:38 PM PDT 24
Finished Mar 28 03:34:45 PM PDT 24
Peak memory 241900 kb
Host smart-f820ec5c-0a74-4f1e-80b8-29262b032c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823697980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.2823697980
Directory /workspace/166.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all.428715128
Short name T156
Test name
Test status
Simulation time 174160264157 ps
CPU time 360.29 seconds
Started Mar 28 03:33:37 PM PDT 24
Finished Mar 28 03:39:38 PM PDT 24
Peak memory 265036 kb
Host smart-8dfc355b-1344-4acc-a20e-03f2da66145b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428715128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all.
428715128
Directory /workspace/48.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.otp_ctrl_alert_test.3725112799
Short name T241
Test name
Test status
Simulation time 97999048 ps
CPU time 1.91 seconds
Started Mar 28 03:31:03 PM PDT 24
Finished Mar 28 03:31:05 PM PDT 24
Peak memory 240104 kb
Host smart-e4c549c7-d1f6-4439-813d-bfdc4865314c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725112799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.3725112799
Directory /workspace/1.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/79.otp_ctrl_stress_all_with_rand_reset.125468741
Short name T405
Test name
Test status
Simulation time 168784566660 ps
CPU time 1238.25 seconds
Started Mar 28 03:34:03 PM PDT 24
Finished Mar 28 03:54:41 PM PDT 24
Peak memory 342952 kb
Host smart-b787bc84-244c-4bca-b101-3acf6d881e9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125468741 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_stress_all_with_rand_reset.125468741
Directory /workspace/79.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.otp_ctrl_init_fail.3659446775
Short name T48
Test name
Test status
Simulation time 372845649 ps
CPU time 4.18 seconds
Started Mar 28 03:33:58 PM PDT 24
Finished Mar 28 03:34:02 PM PDT 24
Peak memory 241948 kb
Host smart-3c886db2-0a6a-4090-9ca0-97ab724899b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659446775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.3659446775
Directory /workspace/72.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_init_fail.1867541267
Short name T61
Test name
Test status
Simulation time 156731115 ps
CPU time 4.5 seconds
Started Mar 28 03:32:18 PM PDT 24
Finished Mar 28 03:32:23 PM PDT 24
Peak memory 241556 kb
Host smart-0dbfb16d-011d-49d3-9e26-b52ff3e1d040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867541267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.1867541267
Directory /workspace/25.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/268.otp_ctrl_init_fail.3204069542
Short name T118
Test name
Test status
Simulation time 2223475399 ps
CPU time 4.79 seconds
Started Mar 28 03:35:05 PM PDT 24
Finished Mar 28 03:35:09 PM PDT 24
Peak memory 241768 kb
Host smart-933c0540-9c66-4d9c-8f3c-663589c78d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204069542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.3204069542
Directory /workspace/268.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/87.otp_ctrl_init_fail.1733071460
Short name T134
Test name
Test status
Simulation time 2011380808 ps
CPU time 6.82 seconds
Started Mar 28 03:33:59 PM PDT 24
Finished Mar 28 03:34:06 PM PDT 24
Peak memory 241816 kb
Host smart-61674cce-9687-4442-8f3a-6eaa1a4e5fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733071460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.1733071460
Directory /workspace/87.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/205.otp_ctrl_init_fail.976694657
Short name T176
Test name
Test status
Simulation time 144167538 ps
CPU time 3.84 seconds
Started Mar 28 03:34:54 PM PDT 24
Finished Mar 28 03:34:59 PM PDT 24
Peak memory 241656 kb
Host smart-af2a9128-a384-4128-a6b2-bca5ae07846b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976694657 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.976694657
Directory /workspace/205.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.4288131939
Short name T312
Test name
Test status
Simulation time 73295575 ps
CPU time 1.74 seconds
Started Mar 28 12:59:31 PM PDT 24
Finished Mar 28 12:59:33 PM PDT 24
Peak memory 240220 kb
Host smart-80d929a9-6dfb-4ff4-aadb-1a53d6bf0387
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288131939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.4288131939
Directory /workspace/6.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/default/171.otp_ctrl_init_fail.2838920052
Short name T97
Test name
Test status
Simulation time 1946895066 ps
CPU time 6.38 seconds
Started Mar 28 03:34:37 PM PDT 24
Finished Mar 28 03:34:44 PM PDT 24
Peak memory 241732 kb
Host smart-033f97f7-f9f0-4d44-aae0-ae949c7b8de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838920052 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.2838920052
Directory /workspace/171.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all.2479162469
Short name T1060
Test name
Test status
Simulation time 25113759675 ps
CPU time 235.68 seconds
Started Mar 28 03:32:19 PM PDT 24
Finished Mar 28 03:36:14 PM PDT 24
Peak memory 262916 kb
Host smart-9f364237-8b67-48fd-8a5d-b93b5916e301
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479162469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all
.2479162469
Directory /workspace/24.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/142.otp_ctrl_init_fail.3094884922
Short name T35
Test name
Test status
Simulation time 594873549 ps
CPU time 5.76 seconds
Started Mar 28 03:34:22 PM PDT 24
Finished Mar 28 03:34:28 PM PDT 24
Peak memory 242068 kb
Host smart-a848e0d4-549d-4cb4-b85b-e3770361c18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094884922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.3094884922
Directory /workspace/142.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/57.otp_ctrl_stress_all_with_rand_reset.456580055
Short name T15
Test name
Test status
Simulation time 228612915983 ps
CPU time 586.05 seconds
Started Mar 28 03:33:43 PM PDT 24
Finished Mar 28 03:43:29 PM PDT 24
Peak memory 256984 kb
Host smart-d8953f0d-2c52-4195-950d-e495c825f014
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456580055 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_stress_all_with_rand_reset.456580055
Directory /workspace/57.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all.3888478779
Short name T359
Test name
Test status
Simulation time 21526233888 ps
CPU time 303.1 seconds
Started Mar 28 03:32:37 PM PDT 24
Finished Mar 28 03:37:40 PM PDT 24
Peak memory 293628 kb
Host smart-c136cba9-7154-48be-84dd-215dd546eeba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888478779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all
.3888478779
Directory /workspace/28.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.otp_ctrl_macro_errs.3588831477
Short name T178
Test name
Test status
Simulation time 2243360525 ps
CPU time 42.78 seconds
Started Mar 28 03:32:39 PM PDT 24
Finished Mar 28 03:33:22 PM PDT 24
Peak memory 248708 kb
Host smart-7951ac35-3b80-4763-8f7d-a05e85534576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588831477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.3588831477
Directory /workspace/33.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/73.otp_ctrl_stress_all_with_rand_reset.4167439503
Short name T14
Test name
Test status
Simulation time 54237731446 ps
CPU time 1708.68 seconds
Started Mar 28 03:33:57 PM PDT 24
Finished Mar 28 04:02:26 PM PDT 24
Peak memory 290924 kb
Host smart-c924178a-5cea-403d-baf0-08569050fc3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167439503 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_stress_all_with_rand_reset.4167439503
Directory /workspace/73.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all.2160909356
Short name T166
Test name
Test status
Simulation time 48403571437 ps
CPU time 157.52 seconds
Started Mar 28 03:33:21 PM PDT 24
Finished Mar 28 03:36:01 PM PDT 24
Peak memory 249304 kb
Host smart-0d0b3370-80fc-402d-bdbf-d2bdaccc9620
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160909356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all
.2160909356
Directory /workspace/43.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/116.otp_ctrl_init_fail.2679731881
Short name T200
Test name
Test status
Simulation time 363816424 ps
CPU time 3.68 seconds
Started Mar 28 03:34:20 PM PDT 24
Finished Mar 28 03:34:24 PM PDT 24
Peak memory 241784 kb
Host smart-b12ee9e0-4b7c-49b4-9972-59e4db4710ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679731881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.2679731881
Directory /workspace/116.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_check_fail.162814133
Short name T47
Test name
Test status
Simulation time 17578263164 ps
CPU time 23.09 seconds
Started Mar 28 03:32:45 PM PDT 24
Finished Mar 28 03:33:09 PM PDT 24
Peak memory 244688 kb
Host smart-024b4a44-c88d-441f-bcec-42276c0b2112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162814133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.162814133
Directory /workspace/31.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_init_fail.1386827770
Short name T28
Test name
Test status
Simulation time 2297197133 ps
CPU time 7.46 seconds
Started Mar 28 03:33:02 PM PDT 24
Finished Mar 28 03:33:11 PM PDT 24
Peak memory 241784 kb
Host smart-dc1c88dd-4a07-4731-a46f-bc5baa4c1a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386827770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.1386827770
Directory /workspace/40.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_regwen.469921674
Short name T388
Test name
Test status
Simulation time 307287089 ps
CPU time 8.62 seconds
Started Mar 28 03:31:59 PM PDT 24
Finished Mar 28 03:32:10 PM PDT 24
Peak memory 241152 kb
Host smart-8aefa692-1882-423d-8605-12543cf822ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=469921674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.469921674
Directory /workspace/18.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/63.otp_ctrl_stress_all_with_rand_reset.179197629
Short name T13
Test name
Test status
Simulation time 112320898918 ps
CPU time 1258.39 seconds
Started Mar 28 03:33:47 PM PDT 24
Finished Mar 28 03:54:46 PM PDT 24
Peak memory 316436 kb
Host smart-47ce61ca-f253-4af6-a1a1-285825c0536a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179197629 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_stress_all_with_rand_reset.179197629
Directory /workspace/63.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.otp_ctrl_init_fail.3344153524
Short name T259
Test name
Test status
Simulation time 302922946 ps
CPU time 3.72 seconds
Started Mar 28 03:34:41 PM PDT 24
Finished Mar 28 03:34:49 PM PDT 24
Peak memory 241720 kb
Host smart-155dbb44-07b1-4d2a-b4c3-2fc9c0242f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344153524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.3344153524
Directory /workspace/180.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_check_fail.1457644909
Short name T58
Test name
Test status
Simulation time 11363391167 ps
CPU time 36.89 seconds
Started Mar 28 03:31:52 PM PDT 24
Finished Mar 28 03:32:30 PM PDT 24
Peak memory 248712 kb
Host smart-157a8746-1e79-41ab-975a-6da99184c46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457644909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.1457644909
Directory /workspace/16.otp_ctrl_check_fail/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.442314639
Short name T283
Test name
Test status
Simulation time 1284660671 ps
CPU time 17.48 seconds
Started Mar 28 12:59:32 PM PDT 24
Finished Mar 28 12:59:50 PM PDT 24
Peak memory 244716 kb
Host smart-b91fca44-82f4-4ac7-88e6-a92cdeb82204
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442314639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_int
g_err.442314639
Directory /workspace/6.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all.1428187654
Short name T671
Test name
Test status
Simulation time 12473575774 ps
CPU time 265.28 seconds
Started Mar 28 03:32:38 PM PDT 24
Finished Mar 28 03:37:03 PM PDT 24
Peak memory 251652 kb
Host smart-609c671b-3096-4d96-b126-b40b0fb658b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428187654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all
.1428187654
Directory /workspace/30.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all.3383956287
Short name T211
Test name
Test status
Simulation time 16647588971 ps
CPU time 53.94 seconds
Started Mar 28 03:33:23 PM PDT 24
Finished Mar 28 03:34:18 PM PDT 24
Peak memory 245048 kb
Host smart-ae7e4103-e021-49d0-bea2-4f821bf5cd63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383956287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all
.3383956287
Directory /workspace/44.otp_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.3771271671
Short name T377
Test name
Test status
Simulation time 4846242604 ps
CPU time 22.81 seconds
Started Mar 28 12:59:18 PM PDT 24
Finished Mar 28 12:59:41 PM PDT 24
Peak memory 239288 kb
Host smart-4408006e-e807-4cf4-9c2f-64686def9686
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771271671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_in
tg_err.3771271671
Directory /workspace/4.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/43.otp_ctrl_check_fail.920781693
Short name T34
Test name
Test status
Simulation time 13227173738 ps
CPU time 29.18 seconds
Started Mar 28 03:33:20 PM PDT 24
Finished Mar 28 03:33:49 PM PDT 24
Peak memory 243564 kb
Host smart-e444b546-90c1-4f67-aefb-24283021bc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920781693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.920781693
Directory /workspace/43.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/60.otp_ctrl_parallel_lc_esc.1003136885
Short name T151
Test name
Test status
Simulation time 324815164 ps
CPU time 8.15 seconds
Started Mar 28 03:33:39 PM PDT 24
Finished Mar 28 03:33:48 PM PDT 24
Peak memory 242044 kb
Host smart-168dc315-77a0-4a3f-8950-306ea1b96a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003136885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.1003136885
Directory /workspace/60.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/48.otp_ctrl_check_fail.2281095401
Short name T135
Test name
Test status
Simulation time 1651565328 ps
CPU time 29.35 seconds
Started Mar 28 03:33:38 PM PDT 24
Finished Mar 28 03:34:08 PM PDT 24
Peak memory 244996 kb
Host smart-f30889c7-e710-4680-a52c-7510bdc989bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281095401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.2281095401
Directory /workspace/48.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_esc.2934369300
Short name T145
Test name
Test status
Simulation time 3480905922 ps
CPU time 8.34 seconds
Started Mar 28 03:31:34 PM PDT 24
Finished Mar 28 03:31:43 PM PDT 24
Peak memory 242156 kb
Host smart-f6114413-4224-4d43-9b06-17f5ab280ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934369300 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.2934369300
Directory /workspace/10.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/122.otp_ctrl_parallel_lc_esc.437895105
Short name T149
Test name
Test status
Simulation time 408051022 ps
CPU time 8.18 seconds
Started Mar 28 03:34:25 PM PDT 24
Finished Mar 28 03:34:33 PM PDT 24
Peak memory 241588 kb
Host smart-e98b0472-7e4b-498a-a61e-b0da5bf02304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437895105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.437895105
Directory /workspace/122.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/134.otp_ctrl_parallel_lc_esc.1661764662
Short name T73
Test name
Test status
Simulation time 1090518776 ps
CPU time 17.71 seconds
Started Mar 28 03:34:23 PM PDT 24
Finished Mar 28 03:34:41 PM PDT 24
Peak memory 241620 kb
Host smart-af4c4442-b602-4d64-8514-33f117b3af78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661764662 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.1661764662
Directory /workspace/134.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/156.otp_ctrl_parallel_lc_esc.3958945809
Short name T71
Test name
Test status
Simulation time 4531607890 ps
CPU time 21.61 seconds
Started Mar 28 03:34:38 PM PDT 24
Finished Mar 28 03:35:01 PM PDT 24
Peak memory 241852 kb
Host smart-94f98f21-b2ce-4a31-ab00-8314d7693be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958945809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.3958945809
Directory /workspace/156.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/163.otp_ctrl_parallel_lc_esc.895694761
Short name T69
Test name
Test status
Simulation time 195412372 ps
CPU time 9.95 seconds
Started Mar 28 03:34:42 PM PDT 24
Finished Mar 28 03:34:56 PM PDT 24
Peak memory 241524 kb
Host smart-352d718e-7b21-4702-b59a-5fa638ad5610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895694761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.895694761
Directory /workspace/163.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/189.otp_ctrl_parallel_lc_esc.2281634736
Short name T121
Test name
Test status
Simulation time 673272081 ps
CPU time 18.38 seconds
Started Mar 28 03:34:40 PM PDT 24
Finished Mar 28 03:35:02 PM PDT 24
Peak memory 241708 kb
Host smart-704e4d80-86f0-4a6f-a3ad-c4f69ff17b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281634736 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.2281634736
Directory /workspace/189.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all.3618058088
Short name T267
Test name
Test status
Simulation time 29261964358 ps
CPU time 201.18 seconds
Started Mar 28 03:31:19 PM PDT 24
Finished Mar 28 03:34:41 PM PDT 24
Peak memory 256980 kb
Host smart-6269e62f-c5b0-46df-a098-c20244d93d4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618058088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all.
3618058088
Directory /workspace/3.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.otp_ctrl_init_fail.345827438
Short name T68
Test name
Test status
Simulation time 413086502 ps
CPU time 3.86 seconds
Started Mar 28 03:32:46 PM PDT 24
Finished Mar 28 03:32:50 PM PDT 24
Peak memory 241712 kb
Host smart-593c8766-6105-47bc-a193-f5928c4b5a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345827438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.345827438
Directory /workspace/32.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/62.otp_ctrl_parallel_lc_esc.403436304
Short name T128
Test name
Test status
Simulation time 211804557 ps
CPU time 6.09 seconds
Started Mar 28 03:33:42 PM PDT 24
Finished Mar 28 03:33:49 PM PDT 24
Peak memory 241812 kb
Host smart-7c88b44c-bdb7-4cb2-a4fd-ff43ddcffa21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403436304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.403436304
Directory /workspace/62.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/83.otp_ctrl_init_fail.3800359467
Short name T51
Test name
Test status
Simulation time 2765324624 ps
CPU time 7.92 seconds
Started Mar 28 03:34:00 PM PDT 24
Finished Mar 28 03:34:08 PM PDT 24
Peak memory 241792 kb
Host smart-54f40920-1618-4c14-a261-56e4a61561e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800359467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.3800359467
Directory /workspace/83.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/92.otp_ctrl_parallel_lc_esc.3530402266
Short name T264
Test name
Test status
Simulation time 1426978071 ps
CPU time 11.01 seconds
Started Mar 28 03:34:02 PM PDT 24
Finished Mar 28 03:34:13 PM PDT 24
Peak memory 241624 kb
Host smart-a98a9fbb-5766-4ae8-841f-e6932901693e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530402266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.3530402266
Directory /workspace/92.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/0.otp_ctrl_regwen.1517819535
Short name T689
Test name
Test status
Simulation time 998869064 ps
CPU time 9.11 seconds
Started Mar 28 03:31:02 PM PDT 24
Finished Mar 28 03:31:12 PM PDT 24
Peak memory 241964 kb
Host smart-51036f85-c09a-4772-ba8b-0583166aa0b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1517819535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.1517819535
Directory /workspace/0.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/71.otp_ctrl_stress_all_with_rand_reset.3881941620
Short name T89
Test name
Test status
Simulation time 204088602503 ps
CPU time 2449.17 seconds
Started Mar 28 03:34:03 PM PDT 24
Finished Mar 28 04:14:54 PM PDT 24
Peak memory 358204 kb
Host smart-666b4648-f3a5-4c75-a2ec-8685a540ccf3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881941620 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_stress_all_with_rand_reset.3881941620
Directory /workspace/71.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.otp_ctrl_init_fail.3195951300
Short name T39
Test name
Test status
Simulation time 1507580759 ps
CPU time 4.48 seconds
Started Mar 28 03:33:17 PM PDT 24
Finished Mar 28 03:33:21 PM PDT 24
Peak memory 241604 kb
Host smart-cc9389c1-1283-41ef-8702-7f75550a1dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195951300 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.3195951300
Directory /workspace/41.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_test_access.1867149216
Short name T101
Test name
Test status
Simulation time 2869280534 ps
CPU time 29.67 seconds
Started Mar 28 03:31:57 PM PDT 24
Finished Mar 28 03:32:27 PM PDT 24
Peak memory 242240 kb
Host smart-ae4cd37e-f87e-470c-b37a-9ddeda290af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867149216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.1867149216
Directory /workspace/17.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/10.otp_ctrl_check_fail.2034044119
Short name T42
Test name
Test status
Simulation time 2336690217 ps
CPU time 28.7 seconds
Started Mar 28 03:31:35 PM PDT 24
Finished Mar 28 03:32:03 PM PDT 24
Peak memory 241940 kb
Host smart-fd72c390-5758-42cc-86af-da6b3e325eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034044119 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.2034044119
Directory /workspace/10.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_check_fail.1021974474
Short name T26
Test name
Test status
Simulation time 1722539121 ps
CPU time 24.34 seconds
Started Mar 28 03:31:52 PM PDT 24
Finished Mar 28 03:32:18 PM PDT 24
Peak memory 244832 kb
Host smart-1e5c2064-6897-474d-a901-1afd33dee4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021974474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.1021974474
Directory /workspace/15.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/101.otp_ctrl_init_fail.4157932488
Short name T668
Test name
Test status
Simulation time 522729993 ps
CPU time 4.42 seconds
Started Mar 28 03:34:20 PM PDT 24
Finished Mar 28 03:34:25 PM PDT 24
Peak memory 241712 kb
Host smart-fc1c1b73-4ce0-4d02-9429-06ed42c5ea30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157932488 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.4157932488
Directory /workspace/101.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_errs.1499799858
Short name T1163
Test name
Test status
Simulation time 537472111 ps
CPU time 15.63 seconds
Started Mar 28 03:31:38 PM PDT 24
Finished Mar 28 03:31:54 PM PDT 24
Peak memory 241972 kb
Host smart-c923e1e9-363e-4e72-902e-10dac5316542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499799858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.1499799858
Directory /workspace/13.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_regwen.3223015924
Short name T1040
Test name
Test status
Simulation time 4616174551 ps
CPU time 13.45 seconds
Started Mar 28 03:31:14 PM PDT 24
Finished Mar 28 03:31:28 PM PDT 24
Peak memory 241792 kb
Host smart-a763eb3c-6139-4d59-9658-75dfb4a4a4a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3223015924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.3223015924
Directory /workspace/3.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/64.otp_ctrl_stress_all_with_rand_reset.3263610242
Short name T294
Test name
Test status
Simulation time 41710414634 ps
CPU time 1076.22 seconds
Started Mar 28 03:33:50 PM PDT 24
Finished Mar 28 03:51:47 PM PDT 24
Peak memory 344212 kb
Host smart-fc14f8a5-0932-44f3-972d-fc80cbe50a00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263610242 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_stress_all_with_rand_reset.3263610242
Directory /workspace/64.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.otp_ctrl_check_fail.971380329
Short name T75
Test name
Test status
Simulation time 2110494536 ps
CPU time 25.59 seconds
Started Mar 28 03:32:33 PM PDT 24
Finished Mar 28 03:32:59 PM PDT 24
Peak memory 241700 kb
Host smart-fe2d3045-6442-4ecb-b538-e45dd8f0985a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971380329 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.971380329
Directory /workspace/27.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_macro_errs.3091939934
Short name T223
Test name
Test status
Simulation time 2221077451 ps
CPU time 39.33 seconds
Started Mar 28 03:33:38 PM PDT 24
Finished Mar 28 03:34:18 PM PDT 24
Peak memory 244692 kb
Host smart-302842ee-0b4e-4b15-905b-46f6ea47cf44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091939934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_macro_errs.3091939934
Directory /workspace/49.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_init_fail.3306663722
Short name T81
Test name
Test status
Simulation time 1693744756 ps
CPU time 5.72 seconds
Started Mar 28 03:31:36 PM PDT 24
Finished Mar 28 03:31:42 PM PDT 24
Peak memory 241444 kb
Host smart-b45f49bd-e9af-49c8-b04b-024030da7442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306663722 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.3306663722
Directory /workspace/10.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/115.otp_ctrl_init_fail.1019016931
Short name T217
Test name
Test status
Simulation time 136465767 ps
CPU time 3.76 seconds
Started Mar 28 03:34:20 PM PDT 24
Finished Mar 28 03:34:24 PM PDT 24
Peak memory 241808 kb
Host smart-3789abb9-b1fb-4d16-bc7d-6514a5b8194a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019016931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.1019016931
Directory /workspace/115.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_regwen.1869234931
Short name T84
Test name
Test status
Simulation time 3781049401 ps
CPU time 12.71 seconds
Started Mar 28 03:32:46 PM PDT 24
Finished Mar 28 03:33:00 PM PDT 24
Peak memory 241872 kb
Host smart-b6efbbe1-af59-40b9-af91-12abcd245e94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1869234931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.1869234931
Directory /workspace/32.otp_ctrl_regwen/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.3496615855
Short name T374
Test name
Test status
Simulation time 2249048504 ps
CPU time 10.71 seconds
Started Mar 28 01:00:00 PM PDT 24
Finished Mar 28 01:00:11 PM PDT 24
Peak memory 244392 kb
Host smart-fc8dcf28-1d64-4252-afa0-a029a35e1560
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496615855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_i
ntg_err.3496615855
Directory /workspace/16.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all_with_rand_reset.905619128
Short name T300
Test name
Test status
Simulation time 142622601906 ps
CPU time 1446.22 seconds
Started Mar 28 03:31:46 PM PDT 24
Finished Mar 28 03:55:53 PM PDT 24
Peak memory 332576 kb
Host smart-aeb9119a-7eb0-4081-853e-979f00d56d37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905619128 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all_with_rand_reset.905619128
Directory /workspace/13.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.419695583
Short name T316
Test name
Test status
Simulation time 42100483 ps
CPU time 1.54 seconds
Started Mar 28 12:59:08 PM PDT 24
Finished Mar 28 12:59:09 PM PDT 24
Peak memory 239096 kb
Host smart-988985e2-8b55-4539-a247-c8387c8546ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419695583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.419695583
Directory /workspace/1.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_req.4104640637
Short name T23
Test name
Test status
Simulation time 926756173 ps
CPU time 19.36 seconds
Started Mar 28 03:33:25 PM PDT 24
Finished Mar 28 03:33:45 PM PDT 24
Peak memory 241976 kb
Host smart-8e2f5d34-a081-4599-8f8c-def90f59bcce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4104640637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.4104640637
Directory /workspace/46.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/77.otp_ctrl_init_fail.3915253823
Short name T82
Test name
Test status
Simulation time 94921738 ps
CPU time 3.28 seconds
Started Mar 28 03:34:03 PM PDT 24
Finished Mar 28 03:34:06 PM PDT 24
Peak memory 241976 kb
Host smart-d6464b0b-e8c2-43cb-90f1-29c6b517ed66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915253823 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.3915253823
Directory /workspace/77.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_sec_cm.2949972936
Short name T16
Test name
Test status
Simulation time 39164259302 ps
CPU time 175.73 seconds
Started Mar 28 03:31:03 PM PDT 24
Finished Mar 28 03:33:59 PM PDT 24
Peak memory 270056 kb
Host smart-cd44d49d-1947-4e81-b8e5-83976507b362
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949972936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.2949972936
Directory /workspace/1.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all_with_rand_reset.4134561628
Short name T261
Test name
Test status
Simulation time 139933336743 ps
CPU time 2364.28 seconds
Started Mar 28 03:31:53 PM PDT 24
Finished Mar 28 04:11:18 PM PDT 24
Peak memory 407104 kb
Host smart-bdc00681-b930-4728-a3d1-9e52337fec88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134561628 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all_with_rand_reset.4134561628
Directory /workspace/16.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_errs.1138544116
Short name T143
Test name
Test status
Simulation time 315116579 ps
CPU time 11.84 seconds
Started Mar 28 03:32:59 PM PDT 24
Finished Mar 28 03:33:14 PM PDT 24
Peak memory 241636 kb
Host smart-2173ebf3-dfe0-46d2-b44a-c3d1d3f9d885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138544116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.1138544116
Directory /workspace/36.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all.269714401
Short name T480
Test name
Test status
Simulation time 5498730030 ps
CPU time 91.88 seconds
Started Mar 28 03:32:01 PM PDT 24
Finished Mar 28 03:33:34 PM PDT 24
Peak memory 244624 kb
Host smart-ea5c5394-bedd-4143-9f0b-a1048cdf3840
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269714401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all.
269714401
Directory /workspace/19.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all_with_rand_reset.2042056021
Short name T302
Test name
Test status
Simulation time 719102289364 ps
CPU time 1731.45 seconds
Started Mar 28 03:32:58 PM PDT 24
Finished Mar 28 04:01:53 PM PDT 24
Peak memory 293540 kb
Host smart-6642c4d6-f6c2-4032-a1ef-b9a41f6b315f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042056021 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all_with_rand_reset.2042056021
Directory /workspace/34.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.otp_ctrl_init_fail.1778764180
Short name T79
Test name
Test status
Simulation time 98615586 ps
CPU time 3.67 seconds
Started Mar 28 03:31:17 PM PDT 24
Finished Mar 28 03:31:21 PM PDT 24
Peak memory 241788 kb
Host smart-ac7179e0-3032-4b46-b8a0-a6ea6beea5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778764180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.1778764180
Directory /workspace/6.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_req.3657658724
Short name T1072
Test name
Test status
Simulation time 3547694501 ps
CPU time 8.06 seconds
Started Mar 28 03:31:54 PM PDT 24
Finished Mar 28 03:32:05 PM PDT 24
Peak memory 241480 kb
Host smart-24cd52ea-6707-4d3a-93e0-c043af7b8146
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3657658724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.3657658724
Directory /workspace/17.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.1381626271
Short name T1235
Test name
Test status
Simulation time 372846451 ps
CPU time 4.13 seconds
Started Mar 28 12:59:07 PM PDT 24
Finished Mar 28 12:59:11 PM PDT 24
Peak memory 239036 kb
Host smart-5e74c4e3-c6a2-4cb4-b32a-70aa03d46dfa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381626271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_alia
sing.1381626271
Directory /workspace/0.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.1316760288
Short name T313
Test name
Test status
Simulation time 135563935 ps
CPU time 6.13 seconds
Started Mar 28 12:59:07 PM PDT 24
Finished Mar 28 12:59:13 PM PDT 24
Peak memory 230828 kb
Host smart-dc270722-cd77-4e41-be1d-af6a95550123
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316760288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_
bash.1316760288
Directory /workspace/0.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.621710899
Short name T1276
Test name
Test status
Simulation time 264832680 ps
CPU time 1.81 seconds
Started Mar 28 01:00:47 PM PDT 24
Finished Mar 28 01:00:49 PM PDT 24
Peak memory 238928 kb
Host smart-8183c775-12b0-4a22-b584-d577af218b93
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621710899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_re
set.621710899
Directory /workspace/0.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.3785102048
Short name T1240
Test name
Test status
Simulation time 133905522 ps
CPU time 2.65 seconds
Started Mar 28 12:59:08 PM PDT 24
Finished Mar 28 12:59:11 PM PDT 24
Peak memory 247412 kb
Host smart-e4e4b3e5-7627-4e6d-b37c-28df76f61ea3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785102048 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.otp_ctrl_csr_mem_rw_with_rand_reset.3785102048
Directory /workspace/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.2542912250
Short name T331
Test name
Test status
Simulation time 51944789 ps
CPU time 1.48 seconds
Started Mar 28 12:59:08 PM PDT 24
Finished Mar 28 12:59:10 PM PDT 24
Peak memory 239016 kb
Host smart-9b98d11a-e56d-4119-bae5-8c4050386367
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542912250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.2542912250
Directory /workspace/0.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.1485979787
Short name T1309
Test name
Test status
Simulation time 148257486 ps
CPU time 1.55 seconds
Started Mar 28 12:59:13 PM PDT 24
Finished Mar 28 12:59:15 PM PDT 24
Peak memory 230664 kb
Host smart-102245e1-7c51-4807-851c-3d2ff95d3520
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485979787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.1485979787
Directory /workspace/0.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.1188458065
Short name T1201
Test name
Test status
Simulation time 70059401 ps
CPU time 1.34 seconds
Started Mar 28 12:59:08 PM PDT 24
Finished Mar 28 12:59:09 PM PDT 24
Peak memory 229204 kb
Host smart-6b360c23-2b1b-4c71-b9f2-f0bfed186a31
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188458065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctr
l_mem_partial_access.1188458065
Directory /workspace/0.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.3115013021
Short name T1264
Test name
Test status
Simulation time 38105095 ps
CPU time 1.37 seconds
Started Mar 28 12:59:10 PM PDT 24
Finished Mar 28 12:59:11 PM PDT 24
Peak memory 230916 kb
Host smart-c4453ff0-846f-472d-bf11-bcc77811d71a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115013021 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk
.3115013021
Directory /workspace/0.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.1390628555
Short name T334
Test name
Test status
Simulation time 166606452 ps
CPU time 1.85 seconds
Started Mar 28 12:59:08 PM PDT 24
Finished Mar 28 12:59:10 PM PDT 24
Peak memory 239092 kb
Host smart-2d70b3c4-f5b8-41a6-b5a6-2f0e746855ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390628555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_c
trl_same_csr_outstanding.1390628555
Directory /workspace/0.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.1750342556
Short name T1191
Test name
Test status
Simulation time 70334982 ps
CPU time 4.83 seconds
Started Mar 28 12:59:08 PM PDT 24
Finished Mar 28 12:59:13 PM PDT 24
Peak memory 246860 kb
Host smart-4c819aca-befd-4b4e-bac8-5993bf137fae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750342556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.1750342556
Directory /workspace/0.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.1584937307
Short name T379
Test name
Test status
Simulation time 5068948036 ps
CPU time 24.79 seconds
Started Mar 28 12:59:11 PM PDT 24
Finished Mar 28 12:59:36 PM PDT 24
Peak memory 245036 kb
Host smart-14ad7e6d-833d-41e4-afdb-8909e4064338
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584937307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_in
tg_err.1584937307
Directory /workspace/0.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.3784625130
Short name T1285
Test name
Test status
Simulation time 506303616 ps
CPU time 6.24 seconds
Started Mar 28 12:59:09 PM PDT 24
Finished Mar 28 12:59:15 PM PDT 24
Peak memory 239068 kb
Host smart-c5552f4f-631b-4155-a674-dc53ea2eea00
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784625130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_alia
sing.3784625130
Directory /workspace/1.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.1232665175
Short name T1203
Test name
Test status
Simulation time 242240143 ps
CPU time 6.45 seconds
Started Mar 28 12:59:14 PM PDT 24
Finished Mar 28 12:59:20 PM PDT 24
Peak memory 230880 kb
Host smart-2b929be0-90f7-40da-9ed3-6fdff1ce48a2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232665175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_
bash.1232665175
Directory /workspace/1.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.3848752693
Short name T1308
Test name
Test status
Simulation time 94017610 ps
CPU time 1.91 seconds
Started Mar 28 12:59:13 PM PDT 24
Finished Mar 28 12:59:15 PM PDT 24
Peak memory 239140 kb
Host smart-4640ccd2-762f-45bb-9267-78df2fcc8c39
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848752693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_r
eset.3848752693
Directory /workspace/1.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.3527571207
Short name T1229
Test name
Test status
Simulation time 209318683 ps
CPU time 4.42 seconds
Started Mar 28 12:59:07 PM PDT 24
Finished Mar 28 12:59:12 PM PDT 24
Peak memory 246472 kb
Host smart-f86a6cbf-c7c6-41e4-a17b-1be6cf5dd8d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527571207 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.otp_ctrl_csr_mem_rw_with_rand_reset.3527571207
Directory /workspace/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.3301933475
Short name T1287
Test name
Test status
Simulation time 109363302 ps
CPU time 1.42 seconds
Started Mar 28 12:59:13 PM PDT 24
Finished Mar 28 12:59:14 PM PDT 24
Peak memory 230828 kb
Host smart-82231486-0b3e-46e7-b0a8-a2a5cfc6c40b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301933475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.3301933475
Directory /workspace/1.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.1636714064
Short name T1280
Test name
Test status
Simulation time 130663913 ps
CPU time 1.46 seconds
Started Mar 28 12:59:09 PM PDT 24
Finished Mar 28 12:59:10 PM PDT 24
Peak memory 230532 kb
Host smart-55d3fc49-b106-458a-a831-a721a603a2b5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636714064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctr
l_mem_partial_access.1636714064
Directory /workspace/1.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.3068446191
Short name T1266
Test name
Test status
Simulation time 38473681 ps
CPU time 1.34 seconds
Started Mar 28 01:00:35 PM PDT 24
Finished Mar 28 01:00:37 PM PDT 24
Peak memory 228868 kb
Host smart-761b39dd-cc66-44ea-8104-a5998cfab183
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068446191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk
.3068446191
Directory /workspace/1.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.2075181415
Short name T1213
Test name
Test status
Simulation time 209476394 ps
CPU time 2.94 seconds
Started Mar 28 01:00:35 PM PDT 24
Finished Mar 28 01:00:39 PM PDT 24
Peak memory 236324 kb
Host smart-c81a80ad-ab2c-49a5-9e13-081adff587ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075181415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_c
trl_same_csr_outstanding.2075181415
Directory /workspace/1.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.135713550
Short name T1241
Test name
Test status
Simulation time 183556758 ps
CPU time 6.86 seconds
Started Mar 28 12:59:10 PM PDT 24
Finished Mar 28 12:59:17 PM PDT 24
Peak memory 246872 kb
Host smart-bd07c1e2-acbc-4522-b302-bd45ce98d34a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135713550 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.135713550
Directory /workspace/1.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.78445313
Short name T1289
Test name
Test status
Simulation time 1307169168 ps
CPU time 19.37 seconds
Started Mar 28 12:59:13 PM PDT 24
Finished Mar 28 12:59:33 PM PDT 24
Peak memory 244616 kb
Host smart-2a34aa1b-c2ce-4a6f-a340-b43013188fd8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78445313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_intg
_err.78445313
Directory /workspace/1.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.3763329385
Short name T1306
Test name
Test status
Simulation time 71572551 ps
CPU time 2.06 seconds
Started Mar 28 12:59:44 PM PDT 24
Finished Mar 28 12:59:46 PM PDT 24
Peak memory 243492 kb
Host smart-7bfd1181-c5c3-4899-9b91-1bee0f0ba8ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763329385 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.otp_ctrl_csr_mem_rw_with_rand_reset.3763329385
Directory /workspace/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.3882543925
Short name T282
Test name
Test status
Simulation time 154019974 ps
CPU time 1.68 seconds
Started Mar 28 12:59:43 PM PDT 24
Finished Mar 28 12:59:45 PM PDT 24
Peak memory 240052 kb
Host smart-3d907134-2b36-4d17-bc3f-5d87e7438182
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882543925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.3882543925
Directory /workspace/10.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.3201752721
Short name T1217
Test name
Test status
Simulation time 108676586 ps
CPU time 1.37 seconds
Started Mar 28 12:59:44 PM PDT 24
Finished Mar 28 12:59:46 PM PDT 24
Peak memory 230800 kb
Host smart-f9976bcb-2224-416e-9853-0f27dc951519
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201752721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.3201752721
Directory /workspace/10.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.3238583314
Short name T1312
Test name
Test status
Simulation time 119394366 ps
CPU time 1.96 seconds
Started Mar 28 12:59:43 PM PDT 24
Finished Mar 28 12:59:45 PM PDT 24
Peak memory 239100 kb
Host smart-d6982905-7c9a-4f5e-85c3-e4c68eabda8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238583314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_
ctrl_same_csr_outstanding.3238583314
Directory /workspace/10.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.3952889826
Short name T1192
Test name
Test status
Simulation time 80301924 ps
CPU time 4.64 seconds
Started Mar 28 12:59:43 PM PDT 24
Finished Mar 28 12:59:48 PM PDT 24
Peak memory 247184 kb
Host smart-aa19568a-1fdd-4629-8b00-790f85ef1c03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952889826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.3952889826
Directory /workspace/10.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.3468964932
Short name T1297
Test name
Test status
Simulation time 1236498943 ps
CPU time 9.92 seconds
Started Mar 28 12:59:43 PM PDT 24
Finished Mar 28 12:59:53 PM PDT 24
Peak memory 239104 kb
Host smart-8b672a04-35a6-4b3a-97a0-b2390e42f748
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468964932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_i
ntg_err.3468964932
Directory /workspace/10.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.1239246803
Short name T1202
Test name
Test status
Simulation time 73734712 ps
CPU time 2.25 seconds
Started Mar 28 12:59:44 PM PDT 24
Finished Mar 28 12:59:46 PM PDT 24
Peak memory 247388 kb
Host smart-6ea50f8f-f754-4f58-8460-9a5c4e068aaf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239246803 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.otp_ctrl_csr_mem_rw_with_rand_reset.1239246803
Directory /workspace/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.120919684
Short name T315
Test name
Test status
Simulation time 41485897 ps
CPU time 1.65 seconds
Started Mar 28 12:59:45 PM PDT 24
Finished Mar 28 12:59:47 PM PDT 24
Peak memory 240380 kb
Host smart-3d652ee3-0fb8-4e6c-a9ff-3b66e3cb5553
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120919684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.120919684
Directory /workspace/11.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.2244416513
Short name T1232
Test name
Test status
Simulation time 552263370 ps
CPU time 1.82 seconds
Started Mar 28 12:59:43 PM PDT 24
Finished Mar 28 12:59:45 PM PDT 24
Peak memory 230880 kb
Host smart-9aa85ee2-aab1-4ebb-b994-3c1f0ab50a6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244416513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.2244416513
Directory /workspace/11.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.1392301582
Short name T1267
Test name
Test status
Simulation time 703847552 ps
CPU time 1.97 seconds
Started Mar 28 12:59:44 PM PDT 24
Finished Mar 28 12:59:46 PM PDT 24
Peak memory 239116 kb
Host smart-36d27e7a-bbd3-433f-98e2-87dd68aec84b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392301582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_
ctrl_same_csr_outstanding.1392301582
Directory /workspace/11.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.847476483
Short name T1323
Test name
Test status
Simulation time 199983599 ps
CPU time 4.18 seconds
Started Mar 28 12:59:43 PM PDT 24
Finished Mar 28 12:59:47 PM PDT 24
Peak memory 246732 kb
Host smart-bc72b130-5797-4aa3-982d-78ce3db75050
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847476483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.847476483
Directory /workspace/11.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.366110097
Short name T378
Test name
Test status
Simulation time 1258570679 ps
CPU time 10.28 seconds
Started Mar 28 12:59:43 PM PDT 24
Finished Mar 28 12:59:54 PM PDT 24
Peak memory 239144 kb
Host smart-54629da4-8865-44df-a6b2-5de979098b19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366110097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_in
tg_err.366110097
Directory /workspace/11.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.2798775896
Short name T1317
Test name
Test status
Simulation time 125463512 ps
CPU time 3.21 seconds
Started Mar 28 01:00:01 PM PDT 24
Finished Mar 28 01:00:04 PM PDT 24
Peak memory 247328 kb
Host smart-7e8f9a33-a12b-41b3-8a80-35fed5e92c53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798775896 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.otp_ctrl_csr_mem_rw_with_rand_reset.2798775896
Directory /workspace/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.382602878
Short name T281
Test name
Test status
Simulation time 142226672 ps
CPU time 1.56 seconds
Started Mar 28 12:59:45 PM PDT 24
Finished Mar 28 12:59:47 PM PDT 24
Peak memory 240416 kb
Host smart-73d590a2-5c0e-4fae-9498-5dcf82ceb292
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382602878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.382602878
Directory /workspace/12.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.374152162
Short name T1204
Test name
Test status
Simulation time 73166419 ps
CPU time 1.39 seconds
Started Mar 28 01:00:49 PM PDT 24
Finished Mar 28 01:00:50 PM PDT 24
Peak memory 230592 kb
Host smart-b26c9170-643d-40ad-a243-2e202570baa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374152162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.374152162
Directory /workspace/12.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.1912476787
Short name T1219
Test name
Test status
Simulation time 942163547 ps
CPU time 2.78 seconds
Started Mar 28 12:59:44 PM PDT 24
Finished Mar 28 12:59:47 PM PDT 24
Peak memory 239056 kb
Host smart-a91fb1d4-6e00-45b7-bca0-a306f7d879a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912476787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_
ctrl_same_csr_outstanding.1912476787
Directory /workspace/12.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.2476616990
Short name T1262
Test name
Test status
Simulation time 298208362 ps
CPU time 5.08 seconds
Started Mar 28 12:59:45 PM PDT 24
Finished Mar 28 12:59:51 PM PDT 24
Peak memory 247164 kb
Host smart-8576a5c1-e5c2-4340-8b7d-5a1068aeca54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476616990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.2476616990
Directory /workspace/12.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.3727561389
Short name T371
Test name
Test status
Simulation time 9735565085 ps
CPU time 15.64 seconds
Started Mar 28 12:59:42 PM PDT 24
Finished Mar 28 12:59:57 PM PDT 24
Peak memory 244840 kb
Host smart-49a34ccb-457b-4ef5-8aa3-61ce210a4301
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727561389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_i
ntg_err.3727561389
Directory /workspace/12.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.2302463257
Short name T1255
Test name
Test status
Simulation time 1042640110 ps
CPU time 2.71 seconds
Started Mar 28 12:59:56 PM PDT 24
Finished Mar 28 12:59:59 PM PDT 24
Peak memory 246892 kb
Host smart-48c3b2ac-808b-467e-8218-e5cdde8f059c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302463257 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.otp_ctrl_csr_mem_rw_with_rand_reset.2302463257
Directory /workspace/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.3960001091
Short name T1228
Test name
Test status
Simulation time 42233687 ps
CPU time 1.62 seconds
Started Mar 28 01:00:01 PM PDT 24
Finished Mar 28 01:00:03 PM PDT 24
Peak memory 241552 kb
Host smart-b8c853a4-3baa-4dd0-a277-63aaadb8959b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960001091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.3960001091
Directory /workspace/13.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.581695246
Short name T1305
Test name
Test status
Simulation time 76171640 ps
CPU time 1.39 seconds
Started Mar 28 12:59:57 PM PDT 24
Finished Mar 28 12:59:59 PM PDT 24
Peak memory 230872 kb
Host smart-11bd81c8-1c0e-4134-8c89-7de9d814e6b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581695246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.581695246
Directory /workspace/13.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.2612219533
Short name T1269
Test name
Test status
Simulation time 673531475 ps
CPU time 2.51 seconds
Started Mar 28 12:59:57 PM PDT 24
Finished Mar 28 12:59:59 PM PDT 24
Peak memory 237876 kb
Host smart-30dc321e-b58b-4a33-accc-672dce100081
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612219533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_
ctrl_same_csr_outstanding.2612219533
Directory /workspace/13.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.3998266166
Short name T1294
Test name
Test status
Simulation time 1401585300 ps
CPU time 4.1 seconds
Started Mar 28 12:59:57 PM PDT 24
Finished Mar 28 01:00:01 PM PDT 24
Peak memory 246796 kb
Host smart-442543a6-0991-435b-9e12-a68c6ce07a35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998266166 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.3998266166
Directory /workspace/13.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.1683310817
Short name T1205
Test name
Test status
Simulation time 71768351 ps
CPU time 2.05 seconds
Started Mar 28 12:59:58 PM PDT 24
Finished Mar 28 01:00:00 PM PDT 24
Peak memory 244640 kb
Host smart-ceac634c-0cd9-47b9-ad82-e87928013476
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683310817 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.otp_ctrl_csr_mem_rw_with_rand_reset.1683310817
Directory /workspace/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.988042344
Short name T328
Test name
Test status
Simulation time 82204349 ps
CPU time 1.61 seconds
Started Mar 28 12:59:56 PM PDT 24
Finished Mar 28 12:59:58 PM PDT 24
Peak memory 239004 kb
Host smart-16e6bea2-a9d8-41ec-8a16-aad8b22be09f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988042344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.988042344
Directory /workspace/14.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.3105463334
Short name T1216
Test name
Test status
Simulation time 90187368 ps
CPU time 1.43 seconds
Started Mar 28 12:59:56 PM PDT 24
Finished Mar 28 12:59:58 PM PDT 24
Peak memory 230732 kb
Host smart-81008984-40b9-46a3-af13-7d7b0fe80c13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105463334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.3105463334
Directory /workspace/14.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.2531137547
Short name T280
Test name
Test status
Simulation time 159730215 ps
CPU time 2.83 seconds
Started Mar 28 12:59:56 PM PDT 24
Finished Mar 28 12:59:59 PM PDT 24
Peak memory 239004 kb
Host smart-4cc8f1f5-2917-4b8f-9205-d775cbd365a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531137547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_
ctrl_same_csr_outstanding.2531137547
Directory /workspace/14.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.1467933306
Short name T1244
Test name
Test status
Simulation time 968861402 ps
CPU time 5.54 seconds
Started Mar 28 01:00:01 PM PDT 24
Finished Mar 28 01:00:07 PM PDT 24
Peak memory 247324 kb
Host smart-e524ab02-6e35-458e-a801-cd80bde8b180
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467933306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.1467933306
Directory /workspace/14.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.1290274602
Short name T277
Test name
Test status
Simulation time 10276377010 ps
CPU time 19.17 seconds
Started Mar 28 12:59:59 PM PDT 24
Finished Mar 28 01:00:18 PM PDT 24
Peak memory 244708 kb
Host smart-826c5ff9-4e22-4990-a2ad-0244eb237129
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290274602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_i
ntg_err.1290274602
Directory /workspace/14.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.3870888751
Short name T279
Test name
Test status
Simulation time 111923717 ps
CPU time 3.07 seconds
Started Mar 28 12:59:57 PM PDT 24
Finished Mar 28 01:00:00 PM PDT 24
Peak memory 247284 kb
Host smart-3bbbba7c-3daf-48c2-98e8-b7edba2646a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870888751 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.otp_ctrl_csr_mem_rw_with_rand_reset.3870888751
Directory /workspace/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.3818276158
Short name T327
Test name
Test status
Simulation time 711333849 ps
CPU time 1.95 seconds
Started Mar 28 12:59:57 PM PDT 24
Finished Mar 28 12:59:59 PM PDT 24
Peak memory 241608 kb
Host smart-eb477a58-65b6-4d8d-9794-12fb0868ea00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818276158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.3818276158
Directory /workspace/15.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.929662404
Short name T1301
Test name
Test status
Simulation time 38396224 ps
CPU time 1.39 seconds
Started Mar 28 12:59:57 PM PDT 24
Finished Mar 28 12:59:59 PM PDT 24
Peak memory 229824 kb
Host smart-00488ee2-e141-4522-8434-91bc2709cc34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929662404 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.929662404
Directory /workspace/15.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.2601603385
Short name T1224
Test name
Test status
Simulation time 203148859 ps
CPU time 2.99 seconds
Started Mar 28 12:59:57 PM PDT 24
Finished Mar 28 01:00:00 PM PDT 24
Peak memory 239036 kb
Host smart-aecadf65-b38a-4d06-bbf7-99593f76896f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601603385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_
ctrl_same_csr_outstanding.2601603385
Directory /workspace/15.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.2332078437
Short name T1259
Test name
Test status
Simulation time 349334646 ps
CPU time 3.76 seconds
Started Mar 28 12:59:56 PM PDT 24
Finished Mar 28 01:00:00 PM PDT 24
Peak memory 246480 kb
Host smart-eb16bc99-28dd-449b-913c-1aed7c447e64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332078437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.2332078437
Directory /workspace/15.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.4254511442
Short name T381
Test name
Test status
Simulation time 2003866492 ps
CPU time 22.02 seconds
Started Mar 28 01:00:01 PM PDT 24
Finished Mar 28 01:00:23 PM PDT 24
Peak memory 243804 kb
Host smart-35e527ba-d20d-40cf-88e3-032f1adb51f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254511442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_i
ntg_err.4254511442
Directory /workspace/15.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.1747144541
Short name T1225
Test name
Test status
Simulation time 109856027 ps
CPU time 2.44 seconds
Started Mar 28 12:59:57 PM PDT 24
Finished Mar 28 01:00:00 PM PDT 24
Peak memory 245312 kb
Host smart-41fce119-0ced-4847-94c7-85f83d7cdd62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747144541 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.otp_ctrl_csr_mem_rw_with_rand_reset.1747144541
Directory /workspace/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.3762179311
Short name T1320
Test name
Test status
Simulation time 50168726 ps
CPU time 1.64 seconds
Started Mar 28 01:00:00 PM PDT 24
Finished Mar 28 01:00:02 PM PDT 24
Peak memory 240232 kb
Host smart-ca7f8683-7990-49e8-83ba-e87e7f6c9371
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762179311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.3762179311
Directory /workspace/16.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.1749898847
Short name T1206
Test name
Test status
Simulation time 556510194 ps
CPU time 1.81 seconds
Started Mar 28 12:59:56 PM PDT 24
Finished Mar 28 12:59:58 PM PDT 24
Peak memory 230896 kb
Host smart-7f47c34b-076b-4a5f-af92-993318d2c0ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749898847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.1749898847
Directory /workspace/16.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.398250649
Short name T1298
Test name
Test status
Simulation time 104140348 ps
CPU time 2.22 seconds
Started Mar 28 01:00:00 PM PDT 24
Finished Mar 28 01:00:03 PM PDT 24
Peak memory 239040 kb
Host smart-c126aa65-b691-4a81-bd27-d9ca7e4a3d83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398250649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_c
trl_same_csr_outstanding.398250649
Directory /workspace/16.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.1634033504
Short name T1220
Test name
Test status
Simulation time 2583168103 ps
CPU time 9.64 seconds
Started Mar 28 12:59:56 PM PDT 24
Finished Mar 28 01:00:06 PM PDT 24
Peak memory 239200 kb
Host smart-006e3554-8664-4f66-a036-02ae2b41d8e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634033504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.1634033504
Directory /workspace/16.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.3667566421
Short name T1252
Test name
Test status
Simulation time 261386585 ps
CPU time 2.17 seconds
Started Mar 28 01:00:00 PM PDT 24
Finished Mar 28 01:00:02 PM PDT 24
Peak memory 245220 kb
Host smart-027946c8-09c6-41ad-8105-cb082ddb1773
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667566421 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.otp_ctrl_csr_mem_rw_with_rand_reset.3667566421
Directory /workspace/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.1437200863
Short name T1234
Test name
Test status
Simulation time 76173687 ps
CPU time 1.67 seconds
Started Mar 28 12:59:56 PM PDT 24
Finished Mar 28 12:59:58 PM PDT 24
Peak memory 239976 kb
Host smart-9ff864ea-1be9-42b1-a371-1e2c98038d43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437200863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.1437200863
Directory /workspace/17.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.656246314
Short name T1260
Test name
Test status
Simulation time 576270761 ps
CPU time 2.1 seconds
Started Mar 28 12:59:58 PM PDT 24
Finished Mar 28 01:00:00 PM PDT 24
Peak memory 229476 kb
Host smart-c8cbc2e6-80fd-4302-a6d2-ee466939d5dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656246314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.656246314
Directory /workspace/17.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.1889400692
Short name T1283
Test name
Test status
Simulation time 185624638 ps
CPU time 2.92 seconds
Started Mar 28 12:59:56 PM PDT 24
Finished Mar 28 12:59:59 PM PDT 24
Peak memory 239108 kb
Host smart-e6d5dc98-e27e-463b-aa24-e9322dfd7169
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889400692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_
ctrl_same_csr_outstanding.1889400692
Directory /workspace/17.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.3088796572
Short name T1253
Test name
Test status
Simulation time 286656212 ps
CPU time 5.64 seconds
Started Mar 28 12:59:58 PM PDT 24
Finished Mar 28 01:00:04 PM PDT 24
Peak memory 247268 kb
Host smart-d3af156e-8384-4ad5-8a6c-af700a9124f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088796572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.3088796572
Directory /workspace/17.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.1181194212
Short name T276
Test name
Test status
Simulation time 1215705304 ps
CPU time 9.87 seconds
Started Mar 28 12:59:57 PM PDT 24
Finished Mar 28 01:00:07 PM PDT 24
Peak memory 244264 kb
Host smart-066b92bb-2390-4abf-808d-e0efaf0d4d4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181194212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_i
ntg_err.1181194212
Directory /workspace/17.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.3854087241
Short name T1258
Test name
Test status
Simulation time 217840580 ps
CPU time 2.31 seconds
Started Mar 28 01:00:11 PM PDT 24
Finished Mar 28 01:00:13 PM PDT 24
Peak memory 239188 kb
Host smart-10542986-483e-45f6-81d1-b5a5deb1b541
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854087241 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.otp_ctrl_csr_mem_rw_with_rand_reset.3854087241
Directory /workspace/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.612539147
Short name T1250
Test name
Test status
Simulation time 87498692 ps
CPU time 1.79 seconds
Started Mar 28 01:00:09 PM PDT 24
Finished Mar 28 01:00:11 PM PDT 24
Peak memory 239044 kb
Host smart-98da07d6-63a6-4905-ad48-e2a7c7279fc4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612539147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.612539147
Directory /workspace/18.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.1534748531
Short name T1319
Test name
Test status
Simulation time 38257922 ps
CPU time 1.45 seconds
Started Mar 28 01:00:08 PM PDT 24
Finished Mar 28 01:00:11 PM PDT 24
Peak memory 230700 kb
Host smart-e4d989b2-6170-4131-97f1-33dbe6db8126
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534748531 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.1534748531
Directory /workspace/18.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.3074256179
Short name T1261
Test name
Test status
Simulation time 247946278 ps
CPU time 3.56 seconds
Started Mar 28 01:00:09 PM PDT 24
Finished Mar 28 01:00:13 PM PDT 24
Peak memory 238800 kb
Host smart-74ed542c-4e22-412e-b1af-65a1562910ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074256179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_
ctrl_same_csr_outstanding.3074256179
Directory /workspace/18.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.1997482030
Short name T1304
Test name
Test status
Simulation time 335888204 ps
CPU time 6.44 seconds
Started Mar 28 01:00:07 PM PDT 24
Finished Mar 28 01:00:14 PM PDT 24
Peak memory 246968 kb
Host smart-6ed80c1e-8992-4427-b42c-f7ad0913af10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997482030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.1997482030
Directory /workspace/18.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.3810164951
Short name T1321
Test name
Test status
Simulation time 2444634540 ps
CPU time 10.32 seconds
Started Mar 28 01:00:08 PM PDT 24
Finished Mar 28 01:00:19 PM PDT 24
Peak memory 244508 kb
Host smart-6f97e2d4-652c-4712-88f0-372497e7c84a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810164951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_i
ntg_err.3810164951
Directory /workspace/18.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.2682792689
Short name T1207
Test name
Test status
Simulation time 269691743 ps
CPU time 2.42 seconds
Started Mar 28 01:00:11 PM PDT 24
Finished Mar 28 01:00:13 PM PDT 24
Peak memory 244704 kb
Host smart-2fd04344-61f4-4ff4-a0a8-f78dc5e12187
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682792689 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.otp_ctrl_csr_mem_rw_with_rand_reset.2682792689
Directory /workspace/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.2796453556
Short name T1281
Test name
Test status
Simulation time 142712359 ps
CPU time 1.68 seconds
Started Mar 28 01:00:12 PM PDT 24
Finished Mar 28 01:00:14 PM PDT 24
Peak memory 240216 kb
Host smart-9a5f2179-e9e8-49e5-90f4-2785066305ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796453556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.2796453556
Directory /workspace/19.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.1499933257
Short name T1223
Test name
Test status
Simulation time 49150778 ps
CPU time 1.46 seconds
Started Mar 28 01:00:10 PM PDT 24
Finished Mar 28 01:00:11 PM PDT 24
Peak memory 229320 kb
Host smart-8b1e5e14-766c-4d10-872e-676be66a06ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499933257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.1499933257
Directory /workspace/19.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.2782090832
Short name T333
Test name
Test status
Simulation time 108565630 ps
CPU time 1.94 seconds
Started Mar 28 01:00:07 PM PDT 24
Finished Mar 28 01:00:10 PM PDT 24
Peak memory 239084 kb
Host smart-fc82c9fe-6adb-44b9-be4c-e8dbe989d795
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782090832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_
ctrl_same_csr_outstanding.2782090832
Directory /workspace/19.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.1946202945
Short name T1291
Test name
Test status
Simulation time 63198814 ps
CPU time 3.63 seconds
Started Mar 28 01:00:11 PM PDT 24
Finished Mar 28 01:00:15 PM PDT 24
Peak memory 247064 kb
Host smart-6e433a2b-e95f-4bcc-b931-aa8db653d9d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946202945 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.1946202945
Directory /workspace/19.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.3194716812
Short name T380
Test name
Test status
Simulation time 1539780243 ps
CPU time 10.83 seconds
Started Mar 28 01:00:08 PM PDT 24
Finished Mar 28 01:00:20 PM PDT 24
Peak memory 239172 kb
Host smart-552e0188-261b-41bf-b71a-06d3d85e99a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194716812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_i
ntg_err.3194716812
Directory /workspace/19.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.759825792
Short name T332
Test name
Test status
Simulation time 194807833 ps
CPU time 6.05 seconds
Started Mar 28 12:59:13 PM PDT 24
Finished Mar 28 12:59:19 PM PDT 24
Peak memory 239104 kb
Host smart-25cc8ccc-4fda-4f9a-95b0-8e94bec16a30
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759825792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_alias
ing.759825792
Directory /workspace/2.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.491059415
Short name T1198
Test name
Test status
Simulation time 306177606 ps
CPU time 3.86 seconds
Started Mar 28 12:59:07 PM PDT 24
Finished Mar 28 12:59:11 PM PDT 24
Peak memory 230704 kb
Host smart-ec40daa3-241e-4689-9a94-730f4a03299b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491059415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_b
ash.491059415
Directory /workspace/2.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.1846935684
Short name T314
Test name
Test status
Simulation time 369425261 ps
CPU time 2.22 seconds
Started Mar 28 12:59:07 PM PDT 24
Finished Mar 28 12:59:09 PM PDT 24
Peak memory 239060 kb
Host smart-e98415ee-217c-4c6d-ae02-d839f201d8db
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846935684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_r
eset.1846935684
Directory /workspace/2.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.2817399646
Short name T398
Test name
Test status
Simulation time 76856931 ps
CPU time 2.13 seconds
Started Mar 28 12:59:20 PM PDT 24
Finished Mar 28 12:59:22 PM PDT 24
Peak memory 244952 kb
Host smart-deae71e1-3be9-4246-8232-c49fbeed65bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817399646 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.otp_ctrl_csr_mem_rw_with_rand_reset.2817399646
Directory /workspace/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.2550940123
Short name T337
Test name
Test status
Simulation time 74246558 ps
CPU time 1.55 seconds
Started Mar 28 12:59:09 PM PDT 24
Finished Mar 28 12:59:10 PM PDT 24
Peak memory 240336 kb
Host smart-13af8478-6635-4ad7-8c27-190237c99c6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550940123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.2550940123
Directory /workspace/2.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.3394559653
Short name T1275
Test name
Test status
Simulation time 126802483 ps
CPU time 1.38 seconds
Started Mar 28 12:59:13 PM PDT 24
Finished Mar 28 12:59:15 PM PDT 24
Peak memory 229520 kb
Host smart-bc9eef79-24fa-40c6-8960-ba11380fd22c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394559653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.3394559653
Directory /workspace/2.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.1563996146
Short name T1237
Test name
Test status
Simulation time 151687291 ps
CPU time 1.33 seconds
Started Mar 28 01:00:35 PM PDT 24
Finished Mar 28 01:00:37 PM PDT 24
Peak memory 228548 kb
Host smart-eebb2443-b365-4a6b-800a-6506a5c4eb33
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563996146 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctr
l_mem_partial_access.1563996146
Directory /workspace/2.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.3388901442
Short name T1310
Test name
Test status
Simulation time 70457301 ps
CPU time 1.47 seconds
Started Mar 28 12:59:07 PM PDT 24
Finished Mar 28 12:59:09 PM PDT 24
Peak memory 230712 kb
Host smart-b30dd40a-b9ea-4592-bf89-b01502f7967d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388901442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk
.3388901442
Directory /workspace/2.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.2771111092
Short name T335
Test name
Test status
Simulation time 137908550 ps
CPU time 3.36 seconds
Started Mar 28 12:59:10 PM PDT 24
Finished Mar 28 12:59:13 PM PDT 24
Peak memory 239028 kb
Host smart-3bb86ff2-fb81-495e-838d-3542b4a155e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771111092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_c
trl_same_csr_outstanding.2771111092
Directory /workspace/2.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.3262649060
Short name T1315
Test name
Test status
Simulation time 183006262 ps
CPU time 6.37 seconds
Started Mar 28 12:59:12 PM PDT 24
Finished Mar 28 12:59:19 PM PDT 24
Peak memory 246144 kb
Host smart-51656cc4-a10c-4afe-82c1-ae5d3771844e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262649060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.3262649060
Directory /workspace/2.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.4046444884
Short name T376
Test name
Test status
Simulation time 1232856573 ps
CPU time 18.34 seconds
Started Mar 28 12:59:08 PM PDT 24
Finished Mar 28 12:59:27 PM PDT 24
Peak memory 244576 kb
Host smart-016e4e8c-2c7d-4278-afd9-f143b978ae5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046444884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_in
tg_err.4046444884
Directory /workspace/2.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.1135159107
Short name T1303
Test name
Test status
Simulation time 41268868 ps
CPU time 1.55 seconds
Started Mar 28 01:00:11 PM PDT 24
Finished Mar 28 01:00:13 PM PDT 24
Peak memory 230868 kb
Host smart-bb63fa7c-830a-4116-b8f0-63d16a3dd6e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135159107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.1135159107
Directory /workspace/20.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.2969456728
Short name T1270
Test name
Test status
Simulation time 41961887 ps
CPU time 1.46 seconds
Started Mar 28 01:00:09 PM PDT 24
Finished Mar 28 01:00:11 PM PDT 24
Peak memory 230868 kb
Host smart-15efd24d-f6a9-4e9a-a5ef-ede869a851bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969456728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.2969456728
Directory /workspace/21.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.256826654
Short name T1271
Test name
Test status
Simulation time 560484846 ps
CPU time 2.02 seconds
Started Mar 28 01:00:15 PM PDT 24
Finished Mar 28 01:00:17 PM PDT 24
Peak memory 230808 kb
Host smart-e6576f3a-cfe0-471c-b1fc-03264d87f8c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256826654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.256826654
Directory /workspace/22.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.3265072443
Short name T1295
Test name
Test status
Simulation time 586835817 ps
CPU time 1.69 seconds
Started Mar 28 01:00:09 PM PDT 24
Finished Mar 28 01:00:11 PM PDT 24
Peak memory 229224 kb
Host smart-335e1898-701e-40f0-95ac-40ac494de159
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265072443 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.3265072443
Directory /workspace/23.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.1063928927
Short name T1277
Test name
Test status
Simulation time 39070595 ps
CPU time 1.38 seconds
Started Mar 28 01:00:07 PM PDT 24
Finished Mar 28 01:00:09 PM PDT 24
Peak memory 230688 kb
Host smart-91526948-7a17-4126-ba82-7966f7f7bd51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063928927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.1063928927
Directory /workspace/24.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.4276951826
Short name T1193
Test name
Test status
Simulation time 39532073 ps
CPU time 1.38 seconds
Started Mar 28 01:00:08 PM PDT 24
Finished Mar 28 01:00:09 PM PDT 24
Peak memory 230876 kb
Host smart-7dfeeb89-bde4-4f12-b399-4586db6fbe2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276951826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.4276951826
Directory /workspace/25.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.303341482
Short name T1300
Test name
Test status
Simulation time 38181519 ps
CPU time 1.45 seconds
Started Mar 28 01:00:11 PM PDT 24
Finished Mar 28 01:00:12 PM PDT 24
Peak memory 230756 kb
Host smart-42d803df-34a9-4299-904c-874a514366ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303341482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.303341482
Directory /workspace/26.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.905210763
Short name T1274
Test name
Test status
Simulation time 552270886 ps
CPU time 2.09 seconds
Started Mar 28 01:00:11 PM PDT 24
Finished Mar 28 01:00:14 PM PDT 24
Peak memory 229760 kb
Host smart-ae7eaf18-6c05-4a2f-905f-785f46205fb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905210763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.905210763
Directory /workspace/27.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.1706097301
Short name T1214
Test name
Test status
Simulation time 63185886 ps
CPU time 1.44 seconds
Started Mar 28 01:00:08 PM PDT 24
Finished Mar 28 01:00:10 PM PDT 24
Peak memory 230776 kb
Host smart-be02329e-c791-45dd-bd44-0c859c9b9853
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706097301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.1706097301
Directory /workspace/28.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.2493840427
Short name T1273
Test name
Test status
Simulation time 39823855 ps
CPU time 1.42 seconds
Started Mar 28 01:00:14 PM PDT 24
Finished Mar 28 01:00:16 PM PDT 24
Peak memory 229812 kb
Host smart-5bc0e0fd-397d-412c-b33e-2d1b40be1f3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493840427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.2493840427
Directory /workspace/29.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.2011343874
Short name T329
Test name
Test status
Simulation time 323789341 ps
CPU time 6.4 seconds
Started Mar 28 12:59:24 PM PDT 24
Finished Mar 28 12:59:30 PM PDT 24
Peak memory 237688 kb
Host smart-8d7c484c-ce25-4ad3-af8d-a4ddb0f04d04
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011343874 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_alia
sing.2011343874
Directory /workspace/3.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.2985271970
Short name T1284
Test name
Test status
Simulation time 509838088 ps
CPU time 6.38 seconds
Started Mar 28 12:59:24 PM PDT 24
Finished Mar 28 12:59:30 PM PDT 24
Peak memory 237736 kb
Host smart-ec05fcf5-659f-495e-8c91-f8e9f69845d7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985271970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_
bash.2985271970
Directory /workspace/3.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.2577940821
Short name T1263
Test name
Test status
Simulation time 365118714 ps
CPU time 2.46 seconds
Started Mar 28 12:59:18 PM PDT 24
Finished Mar 28 12:59:21 PM PDT 24
Peak memory 239132 kb
Host smart-97a223d8-9a8b-4d5e-ad82-6b1d5260fda8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577940821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_r
eset.2577940821
Directory /workspace/3.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.696614710
Short name T1242
Test name
Test status
Simulation time 76139945 ps
CPU time 2.35 seconds
Started Mar 28 12:59:23 PM PDT 24
Finished Mar 28 12:59:26 PM PDT 24
Peak memory 246784 kb
Host smart-757938fc-4df6-4402-a987-95c751c59fc3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696614710 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.otp_ctrl_csr_mem_rw_with_rand_reset.696614710
Directory /workspace/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.3997389469
Short name T1254
Test name
Test status
Simulation time 39840946 ps
CPU time 1.55 seconds
Started Mar 28 12:59:20 PM PDT 24
Finished Mar 28 12:59:22 PM PDT 24
Peak memory 239144 kb
Host smart-a3583d0d-1c75-4634-afe3-f61e5b499f12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997389469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.3997389469
Directory /workspace/3.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.1644361296
Short name T1257
Test name
Test status
Simulation time 73386753 ps
CPU time 1.37 seconds
Started Mar 28 12:59:19 PM PDT 24
Finished Mar 28 12:59:20 PM PDT 24
Peak memory 230748 kb
Host smart-3a17b0a6-108a-457c-8ace-7071f8b4c4c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644361296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.1644361296
Directory /workspace/3.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.1640096499
Short name T1318
Test name
Test status
Simulation time 38874808 ps
CPU time 1.3 seconds
Started Mar 28 12:59:18 PM PDT 24
Finished Mar 28 12:59:20 PM PDT 24
Peak memory 229144 kb
Host smart-50594aac-3176-4541-8911-2bf42bed9855
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640096499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctr
l_mem_partial_access.1640096499
Directory /workspace/3.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.3920181157
Short name T1221
Test name
Test status
Simulation time 517489888 ps
CPU time 1.9 seconds
Started Mar 28 12:59:18 PM PDT 24
Finished Mar 28 12:59:20 PM PDT 24
Peak memory 229468 kb
Host smart-3308e467-5c26-4a54-846a-a1ab779190b5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920181157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk
.3920181157
Directory /workspace/3.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.2493337593
Short name T1249
Test name
Test status
Simulation time 128205506 ps
CPU time 3.46 seconds
Started Mar 28 12:59:22 PM PDT 24
Finished Mar 28 12:59:26 PM PDT 24
Peak memory 239080 kb
Host smart-b3e472d6-7785-4f63-a61c-32417873c032
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493337593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_c
trl_same_csr_outstanding.2493337593
Directory /workspace/3.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.1094870361
Short name T1189
Test name
Test status
Simulation time 106203143 ps
CPU time 3.46 seconds
Started Mar 28 12:59:20 PM PDT 24
Finished Mar 28 12:59:23 PM PDT 24
Peak memory 239192 kb
Host smart-efcd359e-495a-46fc-ba6d-ef4e9a1515f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094870361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.1094870361
Directory /workspace/3.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.1209259351
Short name T1245
Test name
Test status
Simulation time 10330982466 ps
CPU time 10.6 seconds
Started Mar 28 12:59:19 PM PDT 24
Finished Mar 28 12:59:30 PM PDT 24
Peak memory 244780 kb
Host smart-366d1584-be51-4e41-8299-ebe0ef4805d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209259351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_in
tg_err.1209259351
Directory /workspace/3.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.1613758025
Short name T1215
Test name
Test status
Simulation time 140306487 ps
CPU time 1.43 seconds
Started Mar 28 01:00:12 PM PDT 24
Finished Mar 28 01:00:14 PM PDT 24
Peak memory 230772 kb
Host smart-6b0edfd7-fb89-47e0-b412-fef6b656482d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613758025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.1613758025
Directory /workspace/30.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.185771301
Short name T1211
Test name
Test status
Simulation time 64855648 ps
CPU time 1.38 seconds
Started Mar 28 01:00:08 PM PDT 24
Finished Mar 28 01:00:10 PM PDT 24
Peak memory 229468 kb
Host smart-165b09f9-ff77-4a36-a3aa-23a99705093e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185771301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.185771301
Directory /workspace/31.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.1639859940
Short name T1313
Test name
Test status
Simulation time 564043937 ps
CPU time 1.48 seconds
Started Mar 28 01:00:09 PM PDT 24
Finished Mar 28 01:00:11 PM PDT 24
Peak memory 230876 kb
Host smart-84d371da-2d91-4b0e-b0a2-6ea63012db74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639859940 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.1639859940
Directory /workspace/32.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.2488067727
Short name T1248
Test name
Test status
Simulation time 42717295 ps
CPU time 1.46 seconds
Started Mar 28 01:00:09 PM PDT 24
Finished Mar 28 01:00:11 PM PDT 24
Peak memory 229464 kb
Host smart-e396b920-1653-47b0-9fa6-ed893ca39211
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488067727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.2488067727
Directory /workspace/33.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.901715715
Short name T1190
Test name
Test status
Simulation time 40615341 ps
CPU time 1.36 seconds
Started Mar 28 01:00:09 PM PDT 24
Finished Mar 28 01:00:11 PM PDT 24
Peak memory 230700 kb
Host smart-eff5c8fd-6e61-4b54-bd9b-ab8f8e24ac57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901715715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.901715715
Directory /workspace/34.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.2480435433
Short name T1296
Test name
Test status
Simulation time 66673561 ps
CPU time 1.39 seconds
Started Mar 28 01:00:08 PM PDT 24
Finished Mar 28 01:00:11 PM PDT 24
Peak memory 230792 kb
Host smart-6e8d8cfd-3355-45ee-a83e-7f05a33c6792
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480435433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.2480435433
Directory /workspace/35.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.3174845863
Short name T1316
Test name
Test status
Simulation time 139479868 ps
CPU time 1.54 seconds
Started Mar 28 01:00:09 PM PDT 24
Finished Mar 28 01:00:11 PM PDT 24
Peak memory 230644 kb
Host smart-caaecc01-2978-4e5b-b6f0-52207f4d2087
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174845863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.3174845863
Directory /workspace/36.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.2215016821
Short name T1302
Test name
Test status
Simulation time 547887142 ps
CPU time 1.57 seconds
Started Mar 28 01:00:08 PM PDT 24
Finished Mar 28 01:00:09 PM PDT 24
Peak memory 229528 kb
Host smart-7f53d92e-8b9b-4a1a-9281-31ac943425c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215016821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.2215016821
Directory /workspace/37.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.3470669943
Short name T1290
Test name
Test status
Simulation time 40266893 ps
CPU time 1.4 seconds
Started Mar 28 01:00:10 PM PDT 24
Finished Mar 28 01:00:11 PM PDT 24
Peak memory 230364 kb
Host smart-bc7fcc83-ae33-4840-9e38-31821f309a81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470669943 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.3470669943
Directory /workspace/38.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.3802698979
Short name T1288
Test name
Test status
Simulation time 68919138 ps
CPU time 1.41 seconds
Started Mar 28 01:00:08 PM PDT 24
Finished Mar 28 01:00:10 PM PDT 24
Peak memory 230732 kb
Host smart-4fcd1150-00bf-47af-b406-8c799578c9a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802698979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.3802698979
Directory /workspace/39.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.2951611082
Short name T278
Test name
Test status
Simulation time 117973822 ps
CPU time 2.93 seconds
Started Mar 28 12:59:19 PM PDT 24
Finished Mar 28 12:59:22 PM PDT 24
Peak memory 230840 kb
Host smart-18846854-4cbc-496a-82ac-9ba53ca4da62
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951611082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_alia
sing.2951611082
Directory /workspace/4.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.3012248650
Short name T1256
Test name
Test status
Simulation time 85864493 ps
CPU time 3.84 seconds
Started Mar 28 12:59:18 PM PDT 24
Finished Mar 28 12:59:22 PM PDT 24
Peak memory 239104 kb
Host smart-3a1e4adf-5b46-4c42-b59b-06b0a80c5502
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012248650 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_
bash.3012248650
Directory /workspace/4.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.93490556
Short name T1226
Test name
Test status
Simulation time 75750101 ps
CPU time 1.96 seconds
Started Mar 28 12:59:20 PM PDT 24
Finished Mar 28 12:59:22 PM PDT 24
Peak memory 239084 kb
Host smart-fa59b313-5d18-4ccb-99c4-8c608119ddda
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93490556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_res
et.93490556
Directory /workspace/4.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.3461730378
Short name T1243
Test name
Test status
Simulation time 1147482466 ps
CPU time 3.14 seconds
Started Mar 28 12:59:31 PM PDT 24
Finished Mar 28 12:59:34 PM PDT 24
Peak memory 246984 kb
Host smart-054615a4-49eb-411e-9016-0474fa94bd1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461730378 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.otp_ctrl_csr_mem_rw_with_rand_reset.3461730378
Directory /workspace/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.389765656
Short name T1247
Test name
Test status
Simulation time 153217302 ps
CPU time 1.55 seconds
Started Mar 28 12:59:17 PM PDT 24
Finished Mar 28 12:59:20 PM PDT 24
Peak memory 241272 kb
Host smart-739fae66-7689-441b-8a10-e9e220de72fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389765656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.389765656
Directory /workspace/4.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.895114831
Short name T1299
Test name
Test status
Simulation time 539832950 ps
CPU time 1.39 seconds
Started Mar 28 12:59:18 PM PDT 24
Finished Mar 28 12:59:19 PM PDT 24
Peak memory 230776 kb
Host smart-cad94dcc-3635-4499-9a53-1eea38fe05f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895114831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.895114831
Directory /workspace/4.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.1832786051
Short name T1238
Test name
Test status
Simulation time 114962435 ps
CPU time 1.38 seconds
Started Mar 28 12:59:17 PM PDT 24
Finished Mar 28 12:59:19 PM PDT 24
Peak memory 230496 kb
Host smart-fc75d060-7fd8-4be7-aa87-daab7dc7fb18
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832786051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctr
l_mem_partial_access.1832786051
Directory /workspace/4.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.3292248622
Short name T1231
Test name
Test status
Simulation time 48038486 ps
CPU time 1.35 seconds
Started Mar 28 12:59:19 PM PDT 24
Finished Mar 28 12:59:21 PM PDT 24
Peak memory 230724 kb
Host smart-75a5bdd5-d172-42ef-b4ed-12908616db2e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292248622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk
.3292248622
Directory /workspace/4.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.245587688
Short name T1307
Test name
Test status
Simulation time 136042340 ps
CPU time 2.24 seconds
Started Mar 28 12:59:32 PM PDT 24
Finished Mar 28 12:59:35 PM PDT 24
Peak memory 239132 kb
Host smart-906d3605-905f-42a0-8859-ad93373b553c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245587688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ct
rl_same_csr_outstanding.245587688
Directory /workspace/4.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.2777098842
Short name T1200
Test name
Test status
Simulation time 87486006 ps
CPU time 3.19 seconds
Started Mar 28 12:59:18 PM PDT 24
Finished Mar 28 12:59:21 PM PDT 24
Peak memory 239176 kb
Host smart-6a3c57f4-ea5b-4f48-adef-006231abac07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777098842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.2777098842
Directory /workspace/4.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.280559044
Short name T1268
Test name
Test status
Simulation time 74486694 ps
CPU time 1.43 seconds
Started Mar 28 01:00:07 PM PDT 24
Finished Mar 28 01:00:09 PM PDT 24
Peak memory 230828 kb
Host smart-235209ef-5afb-4ad6-b183-6190ae3dedac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280559044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.280559044
Directory /workspace/40.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.2680714600
Short name T1199
Test name
Test status
Simulation time 38508313 ps
CPU time 1.4 seconds
Started Mar 28 01:00:15 PM PDT 24
Finished Mar 28 01:00:16 PM PDT 24
Peak memory 230712 kb
Host smart-710f3358-1c93-4424-bb5f-c2aeaf526b5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680714600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.2680714600
Directory /workspace/41.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.1878021501
Short name T1265
Test name
Test status
Simulation time 107105677 ps
CPU time 1.5 seconds
Started Mar 28 01:00:11 PM PDT 24
Finished Mar 28 01:00:13 PM PDT 24
Peak memory 230812 kb
Host smart-3d2a4280-b2c5-4295-b6a9-1f19c4362e7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878021501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.1878021501
Directory /workspace/42.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.3343934355
Short name T1230
Test name
Test status
Simulation time 42775837 ps
CPU time 1.42 seconds
Started Mar 28 01:00:08 PM PDT 24
Finished Mar 28 01:00:10 PM PDT 24
Peak memory 229448 kb
Host smart-835ad264-1106-4c53-bf21-8b20169f04c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343934355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.3343934355
Directory /workspace/43.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.3982481550
Short name T1279
Test name
Test status
Simulation time 559758973 ps
CPU time 1.69 seconds
Started Mar 28 01:00:25 PM PDT 24
Finished Mar 28 01:00:27 PM PDT 24
Peak memory 230656 kb
Host smart-fa8b4fdf-bf6d-4822-91bb-b27299c75ee2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982481550 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.3982481550
Directory /workspace/44.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.889264890
Short name T1210
Test name
Test status
Simulation time 143337135 ps
CPU time 1.51 seconds
Started Mar 28 01:00:24 PM PDT 24
Finished Mar 28 01:00:26 PM PDT 24
Peak memory 230628 kb
Host smart-32434e76-8bf0-44ad-9d2d-5e3dab2aaef4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889264890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.889264890
Directory /workspace/45.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.2407327629
Short name T1246
Test name
Test status
Simulation time 39508516 ps
CPU time 1.48 seconds
Started Mar 28 01:00:23 PM PDT 24
Finished Mar 28 01:00:24 PM PDT 24
Peak memory 230884 kb
Host smart-947d7d60-ecc1-4004-9a84-6f5c2040b634
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407327629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.2407327629
Directory /workspace/46.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.1372364558
Short name T1311
Test name
Test status
Simulation time 133761728 ps
CPU time 1.46 seconds
Started Mar 28 01:00:23 PM PDT 24
Finished Mar 28 01:00:24 PM PDT 24
Peak memory 230828 kb
Host smart-be0d8d6b-81c6-4f7a-96bb-c7b1ed4f7429
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372364558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.1372364558
Directory /workspace/47.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.3816877564
Short name T1227
Test name
Test status
Simulation time 36555785 ps
CPU time 1.36 seconds
Started Mar 28 01:00:20 PM PDT 24
Finished Mar 28 01:00:21 PM PDT 24
Peak memory 230892 kb
Host smart-da746d66-c0af-4387-a989-531052943ef8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816877564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.3816877564
Directory /workspace/48.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.3261115534
Short name T1208
Test name
Test status
Simulation time 565490016 ps
CPU time 2.05 seconds
Started Mar 28 01:00:22 PM PDT 24
Finished Mar 28 01:00:25 PM PDT 24
Peak memory 230672 kb
Host smart-a8fe7c5d-1555-444f-b4d0-7e5366c023e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261115534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.3261115534
Directory /workspace/49.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.575925135
Short name T1292
Test name
Test status
Simulation time 136150114 ps
CPU time 2.08 seconds
Started Mar 28 12:59:30 PM PDT 24
Finished Mar 28 12:59:33 PM PDT 24
Peak memory 238884 kb
Host smart-c2e61b6d-3747-48e6-888d-e88b3b9456c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575925135 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.otp_ctrl_csr_mem_rw_with_rand_reset.575925135
Directory /workspace/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.235738049
Short name T1218
Test name
Test status
Simulation time 175001623 ps
CPU time 1.85 seconds
Started Mar 28 12:59:35 PM PDT 24
Finished Mar 28 12:59:37 PM PDT 24
Peak memory 240024 kb
Host smart-db20e704-5c6d-4e72-81ae-9c80182dc636
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235738049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.235738049
Directory /workspace/5.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.2413032629
Short name T1233
Test name
Test status
Simulation time 543193089 ps
CPU time 1.57 seconds
Started Mar 28 12:59:35 PM PDT 24
Finished Mar 28 12:59:37 PM PDT 24
Peak memory 229480 kb
Host smart-7813be8b-da5d-4760-9a6f-2ae89a46ab1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413032629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.2413032629
Directory /workspace/5.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.4039319024
Short name T336
Test name
Test status
Simulation time 48589090 ps
CPU time 1.97 seconds
Started Mar 28 12:59:34 PM PDT 24
Finished Mar 28 12:59:36 PM PDT 24
Peak memory 238036 kb
Host smart-19ec17fc-333d-4145-b815-4fc2eab92dc4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039319024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_c
trl_same_csr_outstanding.4039319024
Directory /workspace/5.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.468863796
Short name T1212
Test name
Test status
Simulation time 363551861 ps
CPU time 7.21 seconds
Started Mar 28 12:59:32 PM PDT 24
Finished Mar 28 12:59:39 PM PDT 24
Peak memory 247052 kb
Host smart-e9d5a7dd-032a-44eb-abd6-4abf2a6a2ddf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468863796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.468863796
Directory /workspace/5.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.3418186606
Short name T372
Test name
Test status
Simulation time 20240349722 ps
CPU time 30.05 seconds
Started Mar 28 12:59:34 PM PDT 24
Finished Mar 28 01:00:04 PM PDT 24
Peak memory 246284 kb
Host smart-042d0e23-f795-46ce-a569-e933142d448e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418186606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_in
tg_err.3418186606
Directory /workspace/5.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.1102442614
Short name T1197
Test name
Test status
Simulation time 1124962852 ps
CPU time 4 seconds
Started Mar 28 12:59:35 PM PDT 24
Finished Mar 28 12:59:39 PM PDT 24
Peak memory 247404 kb
Host smart-ce889efc-5b3e-48a6-ae26-dfe76d2f9fff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102442614 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.otp_ctrl_csr_mem_rw_with_rand_reset.1102442614
Directory /workspace/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.1887753453
Short name T1272
Test name
Test status
Simulation time 48902381 ps
CPU time 1.33 seconds
Started Mar 28 12:59:34 PM PDT 24
Finished Mar 28 12:59:36 PM PDT 24
Peak memory 230772 kb
Host smart-da9d8643-2df0-44ac-ace6-52f00a1ec9d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887753453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.1887753453
Directory /workspace/6.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.4239887556
Short name T338
Test name
Test status
Simulation time 1062764087 ps
CPU time 2.59 seconds
Started Mar 28 12:59:31 PM PDT 24
Finished Mar 28 12:59:34 PM PDT 24
Peak memory 239040 kb
Host smart-f9d39a9e-a702-4073-9fbf-be70835380bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239887556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_c
trl_same_csr_outstanding.4239887556
Directory /workspace/6.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.2410950263
Short name T1236
Test name
Test status
Simulation time 113863500 ps
CPU time 3.3 seconds
Started Mar 28 12:59:31 PM PDT 24
Finished Mar 28 12:59:35 PM PDT 24
Peak memory 246756 kb
Host smart-cafd0d3c-3a74-43ef-8bc1-c7ae03573289
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410950263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.2410950263
Directory /workspace/6.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.675269398
Short name T1286
Test name
Test status
Simulation time 103783946 ps
CPU time 2.61 seconds
Started Mar 28 12:59:32 PM PDT 24
Finished Mar 28 12:59:35 PM PDT 24
Peak memory 247336 kb
Host smart-7c080b7e-486d-44ea-ae21-233107ee967f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675269398 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.otp_ctrl_csr_mem_rw_with_rand_reset.675269398
Directory /workspace/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.3450738656
Short name T326
Test name
Test status
Simulation time 73597375 ps
CPU time 1.59 seconds
Started Mar 28 01:00:35 PM PDT 24
Finished Mar 28 01:00:37 PM PDT 24
Peak memory 237964 kb
Host smart-2ea7c91a-105f-4838-bb09-b35e3487f70c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450738656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.3450738656
Directory /workspace/7.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.1436991849
Short name T1282
Test name
Test status
Simulation time 129272569 ps
CPU time 1.39 seconds
Started Mar 28 12:59:31 PM PDT 24
Finished Mar 28 12:59:32 PM PDT 24
Peak memory 230900 kb
Host smart-205ab2b1-bdcc-41d7-90ee-2552d1d85d2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436991849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.1436991849
Directory /workspace/7.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.3025839573
Short name T1322
Test name
Test status
Simulation time 93066618 ps
CPU time 2.37 seconds
Started Mar 28 12:59:31 PM PDT 24
Finished Mar 28 12:59:33 PM PDT 24
Peak memory 237932 kb
Host smart-2952bbce-7ceb-4a45-a7f1-1ae6e231a22e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025839573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_c
trl_same_csr_outstanding.3025839573
Directory /workspace/7.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.3256263402
Short name T1209
Test name
Test status
Simulation time 346745695 ps
CPU time 7.29 seconds
Started Mar 28 12:59:30 PM PDT 24
Finished Mar 28 12:59:38 PM PDT 24
Peak memory 246048 kb
Host smart-c85eb4f4-1ac3-46e8-85d2-f88229b62d3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256263402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.3256263402
Directory /workspace/7.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.459022303
Short name T1314
Test name
Test status
Simulation time 3507667224 ps
CPU time 20.84 seconds
Started Mar 28 12:59:30 PM PDT 24
Finished Mar 28 12:59:51 PM PDT 24
Peak memory 239284 kb
Host smart-20d46833-3269-4209-b4d6-9f81d51b74d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459022303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_int
g_err.459022303
Directory /workspace/7.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.2039112721
Short name T1196
Test name
Test status
Simulation time 103270364 ps
CPU time 2.76 seconds
Started Mar 28 12:59:33 PM PDT 24
Finished Mar 28 12:59:37 PM PDT 24
Peak memory 239276 kb
Host smart-7c0be901-1d5f-4a9b-9391-67058f13a019
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039112721 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.otp_ctrl_csr_mem_rw_with_rand_reset.2039112721
Directory /workspace/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.1683811906
Short name T317
Test name
Test status
Simulation time 46199580 ps
CPU time 1.64 seconds
Started Mar 28 12:59:30 PM PDT 24
Finished Mar 28 12:59:32 PM PDT 24
Peak memory 240408 kb
Host smart-a6146e6b-e4b0-4eb5-94ca-c44de84988f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683811906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.1683811906
Directory /workspace/8.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.3531727585
Short name T1195
Test name
Test status
Simulation time 47528636 ps
CPU time 1.43 seconds
Started Mar 28 12:59:31 PM PDT 24
Finished Mar 28 12:59:32 PM PDT 24
Peak memory 230496 kb
Host smart-dc46da71-f69e-4fd8-b8c9-61e6ed2ae91a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531727585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.3531727585
Directory /workspace/8.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.934031608
Short name T1251
Test name
Test status
Simulation time 123402818 ps
CPU time 2.33 seconds
Started Mar 28 12:59:31 PM PDT 24
Finished Mar 28 12:59:34 PM PDT 24
Peak memory 239024 kb
Host smart-1bee86c0-c322-40d7-a0cf-2ff2b4e845ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934031608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ct
rl_same_csr_outstanding.934031608
Directory /workspace/8.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.2852716825
Short name T1293
Test name
Test status
Simulation time 108194530 ps
CPU time 3.5 seconds
Started Mar 28 12:59:31 PM PDT 24
Finished Mar 28 12:59:34 PM PDT 24
Peak memory 239128 kb
Host smart-bd2b34be-f0b9-4d76-8064-f3613034c3c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852716825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.2852716825
Directory /workspace/8.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.2026577121
Short name T375
Test name
Test status
Simulation time 783040500 ps
CPU time 10.99 seconds
Started Mar 28 12:59:30 PM PDT 24
Finished Mar 28 12:59:41 PM PDT 24
Peak memory 243340 kb
Host smart-a4f7943c-9e01-4635-8523-65bcb9393188
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026577121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_in
tg_err.2026577121
Directory /workspace/8.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.1171568255
Short name T1194
Test name
Test status
Simulation time 106255609 ps
CPU time 3.85 seconds
Started Mar 28 12:59:43 PM PDT 24
Finished Mar 28 12:59:47 PM PDT 24
Peak memory 247280 kb
Host smart-209768e3-e628-4899-90f0-8b06182cb6cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171568255 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.otp_ctrl_csr_mem_rw_with_rand_reset.1171568255
Directory /workspace/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.2277377808
Short name T330
Test name
Test status
Simulation time 40757031 ps
CPU time 1.5 seconds
Started Mar 28 12:59:42 PM PDT 24
Finished Mar 28 12:59:44 PM PDT 24
Peak memory 240896 kb
Host smart-8cb5f0f7-ec71-43ac-bcfe-4353c3b804de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277377808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.2277377808
Directory /workspace/9.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.424403491
Short name T1278
Test name
Test status
Simulation time 37958542 ps
CPU time 1.4 seconds
Started Mar 28 12:59:45 PM PDT 24
Finished Mar 28 12:59:46 PM PDT 24
Peak memory 230832 kb
Host smart-60a1a9bf-56d2-4b42-8cc7-fd3cc5363635
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424403491 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.424403491
Directory /workspace/9.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.3649419615
Short name T1239
Test name
Test status
Simulation time 146612951 ps
CPU time 2.96 seconds
Started Mar 28 12:59:43 PM PDT 24
Finished Mar 28 12:59:46 PM PDT 24
Peak memory 239128 kb
Host smart-a1f9178b-2cd7-42eb-827c-6a89f00bdd83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649419615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_c
trl_same_csr_outstanding.3649419615
Directory /workspace/9.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.2695947225
Short name T1222
Test name
Test status
Simulation time 55560864 ps
CPU time 2.62 seconds
Started Mar 28 12:59:32 PM PDT 24
Finished Mar 28 12:59:35 PM PDT 24
Peak memory 239188 kb
Host smart-6c94ba5f-a953-4d9a-9332-83a0bd292e57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695947225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.2695947225
Directory /workspace/9.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.4055509798
Short name T373
Test name
Test status
Simulation time 1373441639 ps
CPU time 9.71 seconds
Started Mar 28 12:59:44 PM PDT 24
Finished Mar 28 12:59:54 PM PDT 24
Peak memory 244224 kb
Host smart-143be33d-0900-47ef-8660-1a59a0912e14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055509798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_in
tg_err.4055509798
Directory /workspace/9.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.otp_ctrl_alert_test.3206134844
Short name T994
Test name
Test status
Simulation time 238409264 ps
CPU time 2.13 seconds
Started Mar 28 03:30:58 PM PDT 24
Finished Mar 28 03:31:01 PM PDT 24
Peak memory 240088 kb
Host smart-97f9839d-51ff-4f70-84ae-8879041a7760
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206134844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.3206134844
Directory /workspace/0.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.otp_ctrl_background_chks.1789592523
Short name T1109
Test name
Test status
Simulation time 1012603706 ps
CPU time 9.07 seconds
Started Mar 28 03:31:00 PM PDT 24
Finished Mar 28 03:31:09 PM PDT 24
Peak memory 242144 kb
Host smart-f249e7de-d2ea-444f-8d9c-14c86f970549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789592523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.1789592523
Directory /workspace/0.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/0.otp_ctrl_check_fail.2845499562
Short name T1043
Test name
Test status
Simulation time 4478219192 ps
CPU time 35.02 seconds
Started Mar 28 03:31:01 PM PDT 24
Finished Mar 28 03:31:36 PM PDT 24
Peak memory 248716 kb
Host smart-17869afe-0006-4363-872f-d5ad510f5aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845499562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.2845499562
Directory /workspace/0.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_errs.4281631905
Short name T741
Test name
Test status
Simulation time 9563128503 ps
CPU time 23.76 seconds
Started Mar 28 03:31:02 PM PDT 24
Finished Mar 28 03:31:26 PM PDT 24
Peak memory 242176 kb
Host smart-ac8800d9-6781-4ac4-bde5-5a6d2228864f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281631905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.4281631905
Directory /workspace/0.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_lock.142734272
Short name T1083
Test name
Test status
Simulation time 2543773599 ps
CPU time 18.35 seconds
Started Mar 28 03:30:59 PM PDT 24
Finished Mar 28 03:31:17 PM PDT 24
Peak memory 241856 kb
Host smart-ed70affa-183f-4403-96fa-53aaa8f40a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142734272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.142734272
Directory /workspace/0.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/0.otp_ctrl_init_fail.284625998
Short name T626
Test name
Test status
Simulation time 284570813 ps
CPU time 4.15 seconds
Started Mar 28 03:31:02 PM PDT 24
Finished Mar 28 03:31:07 PM PDT 24
Peak memory 241860 kb
Host smart-bc61b2f9-385a-4806-8f00-caa67da4c1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284625998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.284625998
Directory /workspace/0.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_low_freq_read.2790461886
Short name T643
Test name
Test status
Simulation time 7553619664 ps
CPU time 14.22 seconds
Started Mar 28 03:30:56 PM PDT 24
Finished Mar 28 03:31:10 PM PDT 24
Peak memory 241308 kb
Host smart-2bd7d028-1f6f-4e2a-9a93-ab9c106f7af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790461886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.2790461886
Directory /workspace/0.otp_ctrl_low_freq_read/latest

Test location /workspace/coverage/default/0.otp_ctrl_macro_errs.3556158091
Short name T1066
Test name
Test status
Simulation time 352083204 ps
CPU time 11.88 seconds
Started Mar 28 03:31:03 PM PDT 24
Finished Mar 28 03:31:15 PM PDT 24
Peak memory 241972 kb
Host smart-61bbb1ae-b368-42e9-abe2-f05f2c1205f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556158091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.3556158091
Directory /workspace/0.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_key_req.445596546
Short name T997
Test name
Test status
Simulation time 3699398872 ps
CPU time 28.23 seconds
Started Mar 28 03:30:58 PM PDT 24
Finished Mar 28 03:31:27 PM PDT 24
Peak memory 241908 kb
Host smart-5d93b3bc-e48b-4605-ae94-61f9252c14f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445596546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.445596546
Directory /workspace/0.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_esc.2943409780
Short name T120
Test name
Test status
Simulation time 264288802 ps
CPU time 8.33 seconds
Started Mar 28 03:31:02 PM PDT 24
Finished Mar 28 03:31:10 PM PDT 24
Peak memory 241892 kb
Host smart-1a10cf9f-41fc-4b21-a3de-a2e4b7a68453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943409780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.2943409780
Directory /workspace/0.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_req.2170393424
Short name T628
Test name
Test status
Simulation time 584732275 ps
CPU time 18.6 seconds
Started Mar 28 03:31:03 PM PDT 24
Finished Mar 28 03:31:22 PM PDT 24
Peak memory 241612 kb
Host smart-aee5e8ab-d4c5-4094-8e2b-1c261e9cf541
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2170393424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.2170393424
Directory /workspace/0.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_partition_walk.2267244056
Short name T678
Test name
Test status
Simulation time 3224144665 ps
CPU time 27.96 seconds
Started Mar 28 03:30:57 PM PDT 24
Finished Mar 28 03:31:26 PM PDT 24
Peak memory 241408 kb
Host smart-f8441e3d-c373-45cf-b629-76dafadbbd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267244056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.2267244056
Directory /workspace/0.otp_ctrl_partition_walk/latest

Test location /workspace/coverage/default/0.otp_ctrl_sec_cm.1398094733
Short name T17
Test name
Test status
Simulation time 28578643406 ps
CPU time 195.25 seconds
Started Mar 28 03:30:56 PM PDT 24
Finished Mar 28 03:34:12 PM PDT 24
Peak memory 267820 kb
Host smart-a44e846e-2a6b-4d5c-91fa-01f5faf87d52
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398094733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.1398094733
Directory /workspace/0.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.otp_ctrl_smoke.342968532
Short name T717
Test name
Test status
Simulation time 1049610292 ps
CPU time 11.69 seconds
Started Mar 28 03:30:56 PM PDT 24
Finished Mar 28 03:31:08 PM PDT 24
Peak memory 241772 kb
Host smart-4b5d5c31-c6c0-4ce9-af78-c3f8848c554c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342968532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.342968532
Directory /workspace/0.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all.3470118987
Short name T764
Test name
Test status
Simulation time 27069797834 ps
CPU time 215.63 seconds
Started Mar 28 03:30:58 PM PDT 24
Finished Mar 28 03:34:34 PM PDT 24
Peak memory 273288 kb
Host smart-e3b01266-3b01-4edd-91f8-7ddfa4434b3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470118987 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all.
3470118987
Directory /workspace/0.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all_with_rand_reset.2730819754
Short name T486
Test name
Test status
Simulation time 46460274092 ps
CPU time 674.67 seconds
Started Mar 28 03:30:58 PM PDT 24
Finished Mar 28 03:42:14 PM PDT 24
Peak memory 258456 kb
Host smart-1a5a1ff0-95ed-4a9d-8b43-6bba0e69369d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730819754 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all_with_rand_reset.2730819754
Directory /workspace/0.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.otp_ctrl_test_access.3044581071
Short name T641
Test name
Test status
Simulation time 2069943025 ps
CPU time 38.13 seconds
Started Mar 28 03:30:59 PM PDT 24
Finished Mar 28 03:31:37 PM PDT 24
Peak memory 242400 kb
Host smart-87e926e3-2bd8-4cf7-a74e-989a29b405ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044581071 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.3044581071
Directory /workspace/0.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/0.otp_ctrl_wake_up.2376909951
Short name T425
Test name
Test status
Simulation time 816153885 ps
CPU time 1.96 seconds
Started Mar 28 03:31:12 PM PDT 24
Finished Mar 28 03:31:14 PM PDT 24
Peak memory 240248 kb
Host smart-a9d1b66f-f791-482b-844c-d18b8dbceca8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2376909951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.2376909951
Directory /workspace/0.otp_ctrl_wake_up/latest

Test location /workspace/coverage/default/1.otp_ctrl_background_chks.744517412
Short name T494
Test name
Test status
Simulation time 1916651277 ps
CPU time 31.11 seconds
Started Mar 28 03:31:00 PM PDT 24
Finished Mar 28 03:31:31 PM PDT 24
Peak memory 242044 kb
Host smart-726180a5-c69d-4895-a5e7-a37230b5ba9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744517412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.744517412
Directory /workspace/1.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/1.otp_ctrl_check_fail.1526281771
Short name T111
Test name
Test status
Simulation time 8166987072 ps
CPU time 38.35 seconds
Started Mar 28 03:31:03 PM PDT 24
Finished Mar 28 03:31:41 PM PDT 24
Peak memory 243720 kb
Host smart-4401dde2-44e2-47c0-bda6-97dc9fa8611a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526281771 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.1526281771
Directory /workspace/1.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_errs.2531867514
Short name T1065
Test name
Test status
Simulation time 6078204909 ps
CPU time 36 seconds
Started Mar 28 03:30:58 PM PDT 24
Finished Mar 28 03:31:35 PM PDT 24
Peak memory 241888 kb
Host smart-cfb70ac4-330c-49f1-9ae3-b3bd6e85b935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531867514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.2531867514
Directory /workspace/1.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_lock.3873389425
Short name T32
Test name
Test status
Simulation time 1550296001 ps
CPU time 24.63 seconds
Started Mar 28 03:31:01 PM PDT 24
Finished Mar 28 03:31:25 PM PDT 24
Peak memory 241816 kb
Host smart-7289705d-4463-428f-8d97-7ad5b226d4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873389425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.3873389425
Directory /workspace/1.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/1.otp_ctrl_init_fail.371700145
Short name T794
Test name
Test status
Simulation time 302404092 ps
CPU time 5.13 seconds
Started Mar 28 03:30:56 PM PDT 24
Finished Mar 28 03:31:02 PM PDT 24
Peak memory 241740 kb
Host smart-fb58c848-eb3b-464a-9e58-e05c35c097bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371700145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.371700145
Directory /workspace/1.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_macro_errs.3314470039
Short name T969
Test name
Test status
Simulation time 1333548427 ps
CPU time 37.47 seconds
Started Mar 28 03:31:02 PM PDT 24
Finished Mar 28 03:31:39 PM PDT 24
Peak memory 244596 kb
Host smart-c41fb5db-8e5c-4c9a-8ced-f4c500fd2f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314470039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.3314470039
Directory /workspace/1.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_key_req.785174306
Short name T539
Test name
Test status
Simulation time 3187724030 ps
CPU time 46.14 seconds
Started Mar 28 03:31:03 PM PDT 24
Finished Mar 28 03:31:49 PM PDT 24
Peak memory 242204 kb
Host smart-af7963e1-f7ce-45da-954b-2705e5d66469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785174306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.785174306
Directory /workspace/1.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_esc.1585050563
Short name T728
Test name
Test status
Simulation time 194982171 ps
CPU time 4.92 seconds
Started Mar 28 03:31:01 PM PDT 24
Finished Mar 28 03:31:06 PM PDT 24
Peak memory 241700 kb
Host smart-c33bb5d8-17cd-437d-b3e6-df367f466ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585050563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.1585050563
Directory /workspace/1.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_req.4062511215
Short name T755
Test name
Test status
Simulation time 1765677351 ps
CPU time 14.72 seconds
Started Mar 28 03:30:58 PM PDT 24
Finished Mar 28 03:31:14 PM PDT 24
Peak memory 240972 kb
Host smart-d2594f66-8faa-417b-acda-942cc7401751
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4062511215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.4062511215
Directory /workspace/1.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_regwen.4285251547
Short name T390
Test name
Test status
Simulation time 562243843 ps
CPU time 5.65 seconds
Started Mar 28 03:31:02 PM PDT 24
Finished Mar 28 03:31:07 PM PDT 24
Peak memory 242040 kb
Host smart-210cf1b4-f729-4c7b-a094-54aff34e4402
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4285251547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.4285251547
Directory /workspace/1.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/1.otp_ctrl_smoke.2446421571
Short name T10
Test name
Test status
Simulation time 222306008 ps
CPU time 6.32 seconds
Started Mar 28 03:31:02 PM PDT 24
Finished Mar 28 03:31:09 PM PDT 24
Peak memory 241744 kb
Host smart-2565265b-d7a7-4f71-bf09-30287c68333b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446421571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.2446421571
Directory /workspace/1.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all.3472841470
Short name T812
Test name
Test status
Simulation time 7223538434 ps
CPU time 169.12 seconds
Started Mar 28 03:31:02 PM PDT 24
Finished Mar 28 03:33:51 PM PDT 24
Peak memory 256976 kb
Host smart-b983bab9-e551-48d4-bcb5-b39cb431b36d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472841470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all.
3472841470
Directory /workspace/1.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all_with_rand_reset.1066105721
Short name T224
Test name
Test status
Simulation time 35025104472 ps
CPU time 319.43 seconds
Started Mar 28 03:31:03 PM PDT 24
Finished Mar 28 03:36:22 PM PDT 24
Peak memory 257032 kb
Host smart-6008ae25-75d5-4a56-9bff-886b88005b34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066105721 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all_with_rand_reset.1066105721
Directory /workspace/1.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.otp_ctrl_test_access.3543242485
Short name T1100
Test name
Test status
Simulation time 866776518 ps
CPU time 25.01 seconds
Started Mar 28 03:30:59 PM PDT 24
Finished Mar 28 03:31:24 PM PDT 24
Peak memory 242052 kb
Host smart-f14ae2dc-67d1-4a6b-b730-efc78eb28f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543242485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.3543242485
Directory /workspace/1.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/10.otp_ctrl_alert_test.2159296697
Short name T427
Test name
Test status
Simulation time 91582628 ps
CPU time 1.7 seconds
Started Mar 28 03:31:33 PM PDT 24
Finished Mar 28 03:31:35 PM PDT 24
Peak memory 240256 kb
Host smart-3fe8669a-780c-49b7-bbdb-b6eb27f705be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159296697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.2159296697
Directory /workspace/10.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_errs.2517052147
Short name T1003
Test name
Test status
Simulation time 8843493791 ps
CPU time 22.5 seconds
Started Mar 28 03:31:40 PM PDT 24
Finished Mar 28 03:32:03 PM PDT 24
Peak memory 241632 kb
Host smart-adf693f5-d440-4e6a-9653-7797c9b24e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517052147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.2517052147
Directory /workspace/10.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_lock.4004393282
Short name T1038
Test name
Test status
Simulation time 41146031305 ps
CPU time 47.23 seconds
Started Mar 28 03:31:38 PM PDT 24
Finished Mar 28 03:32:26 PM PDT 24
Peak memory 242656 kb
Host smart-4d962309-e327-4896-a9b9-3c8dcfbc43ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004393282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.4004393282
Directory /workspace/10.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/10.otp_ctrl_macro_errs.576159124
Short name T1177
Test name
Test status
Simulation time 2796644775 ps
CPU time 8.08 seconds
Started Mar 28 03:31:35 PM PDT 24
Finished Mar 28 03:31:43 PM PDT 24
Peak memory 241864 kb
Host smart-dc5ba664-528c-4afb-9f5a-02afe728c07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576159124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.576159124
Directory /workspace/10.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_key_req.127969811
Short name T435
Test name
Test status
Simulation time 645205131 ps
CPU time 8.8 seconds
Started Mar 28 03:31:37 PM PDT 24
Finished Mar 28 03:31:46 PM PDT 24
Peak memory 241976 kb
Host smart-ca286bea-cbe5-43d6-a049-0901487488e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127969811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.127969811
Directory /workspace/10.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_req.475268363
Short name T548
Test name
Test status
Simulation time 655159869 ps
CPU time 6.98 seconds
Started Mar 28 03:31:35 PM PDT 24
Finished Mar 28 03:31:42 PM PDT 24
Peak memory 241868 kb
Host smart-979010f2-43b6-4e18-bef8-01975985d6ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=475268363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.475268363
Directory /workspace/10.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_regwen.1082615331
Short name T385
Test name
Test status
Simulation time 2562527635 ps
CPU time 7.03 seconds
Started Mar 28 03:31:35 PM PDT 24
Finished Mar 28 03:31:42 PM PDT 24
Peak memory 241760 kb
Host smart-27fe576b-10b2-4f2c-bd3e-f1251837bcff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1082615331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.1082615331
Directory /workspace/10.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/10.otp_ctrl_smoke.1514396335
Short name T768
Test name
Test status
Simulation time 196464768 ps
CPU time 5.81 seconds
Started Mar 28 03:31:33 PM PDT 24
Finished Mar 28 03:31:40 PM PDT 24
Peak memory 241856 kb
Host smart-f1ae95bc-8e8f-48ba-88b7-c6fcb1e21884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514396335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.1514396335
Directory /workspace/10.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all.2121292022
Short name T368
Test name
Test status
Simulation time 310937887 ps
CPU time 12.24 seconds
Started Mar 28 03:31:35 PM PDT 24
Finished Mar 28 03:31:47 PM PDT 24
Peak memory 248640 kb
Host smart-47006d74-ea28-4d23-8fc6-5a739cac6846
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121292022 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all
.2121292022
Directory /workspace/10.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all_with_rand_reset.1575745309
Short name T350
Test name
Test status
Simulation time 192010918002 ps
CPU time 4041.96 seconds
Started Mar 28 03:31:41 PM PDT 24
Finished Mar 28 04:39:04 PM PDT 24
Peak memory 606312 kb
Host smart-ba40b281-1b03-45f0-a8d7-3411b99928b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575745309 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all_with_rand_reset.1575745309
Directory /workspace/10.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.otp_ctrl_test_access.4207393988
Short name T402
Test name
Test status
Simulation time 732755395 ps
CPU time 25.33 seconds
Started Mar 28 03:31:39 PM PDT 24
Finished Mar 28 03:32:05 PM PDT 24
Peak memory 242288 kb
Host smart-03020863-0d27-4d5f-9f0e-2745539a7264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207393988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.4207393988
Directory /workspace/10.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/100.otp_ctrl_init_fail.1903192107
Short name T842
Test name
Test status
Simulation time 189749972 ps
CPU time 4.28 seconds
Started Mar 28 03:34:21 PM PDT 24
Finished Mar 28 03:34:25 PM PDT 24
Peak memory 241736 kb
Host smart-77f379e6-692c-483d-af81-83f028c07b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903192107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.1903192107
Directory /workspace/100.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/100.otp_ctrl_parallel_lc_esc.1192938827
Short name T982
Test name
Test status
Simulation time 451135080 ps
CPU time 14.19 seconds
Started Mar 28 03:34:18 PM PDT 24
Finished Mar 28 03:34:33 PM PDT 24
Peak memory 241952 kb
Host smart-de864485-83df-45f0-b998-a98261eabda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192938827 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.1192938827
Directory /workspace/100.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/101.otp_ctrl_parallel_lc_esc.613364241
Short name T360
Test name
Test status
Simulation time 1697683476 ps
CPU time 4.69 seconds
Started Mar 28 03:34:19 PM PDT 24
Finished Mar 28 03:34:24 PM PDT 24
Peak memory 241704 kb
Host smart-b81c606d-f72a-40b4-8286-0fc1e50aafef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613364241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.613364241
Directory /workspace/101.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/102.otp_ctrl_init_fail.3519264525
Short name T1034
Test name
Test status
Simulation time 91536506 ps
CPU time 3.49 seconds
Started Mar 28 03:34:19 PM PDT 24
Finished Mar 28 03:34:23 PM PDT 24
Peak memory 241960 kb
Host smart-486cc2d6-ca8b-4868-9109-6e3cbd3c8bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519264525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.3519264525
Directory /workspace/102.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/102.otp_ctrl_parallel_lc_esc.1966303696
Short name T1080
Test name
Test status
Simulation time 1121524817 ps
CPU time 8.71 seconds
Started Mar 28 03:34:20 PM PDT 24
Finished Mar 28 03:34:29 PM PDT 24
Peak memory 241840 kb
Host smart-ab5a3ff4-d3a2-4ae8-b20e-4ba08dd27e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966303696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.1966303696
Directory /workspace/102.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/103.otp_ctrl_init_fail.854983361
Short name T897
Test name
Test status
Simulation time 206960833 ps
CPU time 4.42 seconds
Started Mar 28 03:34:18 PM PDT 24
Finished Mar 28 03:34:23 PM PDT 24
Peak memory 241732 kb
Host smart-18143237-5e3d-4985-8956-d00ad9ad8107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854983361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.854983361
Directory /workspace/103.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/103.otp_ctrl_parallel_lc_esc.286018425
Short name T168
Test name
Test status
Simulation time 80677591 ps
CPU time 2.7 seconds
Started Mar 28 03:34:22 PM PDT 24
Finished Mar 28 03:34:25 PM PDT 24
Peak memory 241616 kb
Host smart-bd8b4277-1a97-41ed-b5d0-bb224be49d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286018425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.286018425
Directory /workspace/103.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/104.otp_ctrl_init_fail.1441077856
Short name T961
Test name
Test status
Simulation time 140189055 ps
CPU time 4.7 seconds
Started Mar 28 03:34:20 PM PDT 24
Finished Mar 28 03:34:25 PM PDT 24
Peak memory 241712 kb
Host smart-20beaf00-a1bb-441d-b1cf-53d327713a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441077856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.1441077856
Directory /workspace/104.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/104.otp_ctrl_parallel_lc_esc.35861173
Short name T273
Test name
Test status
Simulation time 153411621 ps
CPU time 5.14 seconds
Started Mar 28 03:34:19 PM PDT 24
Finished Mar 28 03:34:25 PM PDT 24
Peak memory 241608 kb
Host smart-72fd9599-f515-402f-b578-3b3ebd1c7641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35861173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.35861173
Directory /workspace/104.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/105.otp_ctrl_init_fail.3915972002
Short name T777
Test name
Test status
Simulation time 324598084 ps
CPU time 3.88 seconds
Started Mar 28 03:34:20 PM PDT 24
Finished Mar 28 03:34:24 PM PDT 24
Peak memory 241936 kb
Host smart-e40fdf26-209a-4e6a-99c9-d27e3f83bd8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915972002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.3915972002
Directory /workspace/105.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/105.otp_ctrl_parallel_lc_esc.3562043322
Short name T650
Test name
Test status
Simulation time 854179614 ps
CPU time 12.67 seconds
Started Mar 28 03:34:20 PM PDT 24
Finished Mar 28 03:34:33 PM PDT 24
Peak memory 241708 kb
Host smart-67794437-d116-42a8-9d78-3eb86d80189c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562043322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.3562043322
Directory /workspace/105.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/106.otp_ctrl_init_fail.3949102755
Short name T899
Test name
Test status
Simulation time 147301780 ps
CPU time 3.95 seconds
Started Mar 28 03:34:19 PM PDT 24
Finished Mar 28 03:34:23 PM PDT 24
Peak memory 241776 kb
Host smart-a696bd93-7aaa-4c26-a443-bc250ac9ec49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949102755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.3949102755
Directory /workspace/106.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/106.otp_ctrl_parallel_lc_esc.2923121363
Short name T463
Test name
Test status
Simulation time 1102336497 ps
CPU time 9.72 seconds
Started Mar 28 03:34:19 PM PDT 24
Finished Mar 28 03:34:29 PM PDT 24
Peak memory 241772 kb
Host smart-4e34739e-9ce8-4bb0-a462-be624b63d476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923121363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.2923121363
Directory /workspace/106.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/107.otp_ctrl_parallel_lc_esc.3832022795
Short name T841
Test name
Test status
Simulation time 1078815531 ps
CPU time 8.1 seconds
Started Mar 28 03:34:18 PM PDT 24
Finished Mar 28 03:34:26 PM PDT 24
Peak memory 241652 kb
Host smart-c8113a09-b143-4791-92b2-a14e2a7befe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832022795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.3832022795
Directory /workspace/107.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/108.otp_ctrl_init_fail.2637742991
Short name T1175
Test name
Test status
Simulation time 118617770 ps
CPU time 4.78 seconds
Started Mar 28 03:34:20 PM PDT 24
Finished Mar 28 03:34:25 PM PDT 24
Peak memory 241736 kb
Host smart-a8004940-b1c9-4cc3-a444-497535b83305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637742991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.2637742991
Directory /workspace/108.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/108.otp_ctrl_parallel_lc_esc.2435818277
Short name T409
Test name
Test status
Simulation time 2300721027 ps
CPU time 16.66 seconds
Started Mar 28 03:34:17 PM PDT 24
Finished Mar 28 03:34:34 PM PDT 24
Peak memory 242152 kb
Host smart-de555439-08c7-4996-94d4-1982744c6eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435818277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.2435818277
Directory /workspace/108.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/109.otp_ctrl_init_fail.486474650
Short name T1042
Test name
Test status
Simulation time 262443459 ps
CPU time 4.18 seconds
Started Mar 28 03:34:20 PM PDT 24
Finished Mar 28 03:34:24 PM PDT 24
Peak memory 242120 kb
Host smart-37e4a6d4-ab81-4879-8760-c8f067599429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486474650 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.486474650
Directory /workspace/109.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/109.otp_ctrl_parallel_lc_esc.4151102849
Short name T660
Test name
Test status
Simulation time 472026330 ps
CPU time 13.49 seconds
Started Mar 28 03:34:22 PM PDT 24
Finished Mar 28 03:34:35 PM PDT 24
Peak memory 241736 kb
Host smart-66e36753-8763-4951-92c6-925e9ef4b3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151102849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.4151102849
Directory /workspace/109.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_alert_test.360897093
Short name T949
Test name
Test status
Simulation time 214903482 ps
CPU time 2.02 seconds
Started Mar 28 03:31:36 PM PDT 24
Finished Mar 28 03:31:39 PM PDT 24
Peak memory 240204 kb
Host smart-c371a3ee-6030-4e26-a6ec-5517bef8c55c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360897093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.360897093
Directory /workspace/11.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.otp_ctrl_check_fail.725180102
Short name T1145
Test name
Test status
Simulation time 384947716 ps
CPU time 6.5 seconds
Started Mar 28 03:31:36 PM PDT 24
Finished Mar 28 03:31:43 PM PDT 24
Peak memory 242120 kb
Host smart-07d11723-fcea-4b27-b12b-5330c4d95ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725180102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.725180102
Directory /workspace/11.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_errs.2798858793
Short name T564
Test name
Test status
Simulation time 1386625146 ps
CPU time 35.68 seconds
Started Mar 28 03:31:41 PM PDT 24
Finished Mar 28 03:32:16 PM PDT 24
Peak memory 247120 kb
Host smart-3fc72283-19b2-4899-8abc-d47cc15d4b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798858793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.2798858793
Directory /workspace/11.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_lock.3403542481
Short name T229
Test name
Test status
Simulation time 396587296 ps
CPU time 5.01 seconds
Started Mar 28 03:31:33 PM PDT 24
Finished Mar 28 03:31:38 PM PDT 24
Peak memory 241612 kb
Host smart-1d1977f9-da62-49c9-a083-1d874b1c0134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403542481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.3403542481
Directory /workspace/11.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/11.otp_ctrl_init_fail.1728994149
Short name T1138
Test name
Test status
Simulation time 154135953 ps
CPU time 4.35 seconds
Started Mar 28 03:31:33 PM PDT 24
Finished Mar 28 03:31:38 PM PDT 24
Peak memory 241772 kb
Host smart-aa6779dc-0273-4da3-aa41-61ef05b56f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728994149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.1728994149
Directory /workspace/11.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_macro_errs.1464968171
Short name T515
Test name
Test status
Simulation time 4352180465 ps
CPU time 21.29 seconds
Started Mar 28 03:31:44 PM PDT 24
Finished Mar 28 03:32:05 PM PDT 24
Peak memory 248668 kb
Host smart-4f6e72e2-b8af-4b3b-a879-ae5ecd9ca6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464968171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.1464968171
Directory /workspace/11.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_key_req.1053078121
Short name T737
Test name
Test status
Simulation time 21082109782 ps
CPU time 46.57 seconds
Started Mar 28 03:31:37 PM PDT 24
Finished Mar 28 03:32:24 PM PDT 24
Peak memory 243448 kb
Host smart-73e375e3-cf3c-43e3-a7df-7f78d1477a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053078121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.1053078121
Directory /workspace/11.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_esc.3087270502
Short name T499
Test name
Test status
Simulation time 110570889 ps
CPU time 5.04 seconds
Started Mar 28 03:31:37 PM PDT 24
Finished Mar 28 03:31:43 PM PDT 24
Peak memory 241972 kb
Host smart-b61acebd-89cb-4822-84e9-fba901173204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087270502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.3087270502
Directory /workspace/11.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_req.1300070526
Short name T209
Test name
Test status
Simulation time 1879650229 ps
CPU time 21.44 seconds
Started Mar 28 03:31:34 PM PDT 24
Finished Mar 28 03:31:55 PM PDT 24
Peak memory 241796 kb
Host smart-b10283bc-fef3-44f4-a99f-eea9f26e011d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1300070526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.1300070526
Directory /workspace/11.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_regwen.3685871971
Short name T860
Test name
Test status
Simulation time 2075747124 ps
CPU time 4.8 seconds
Started Mar 28 03:31:37 PM PDT 24
Finished Mar 28 03:31:42 PM PDT 24
Peak memory 241832 kb
Host smart-7804d87e-c7b2-4ce1-9c20-2787d95b0187
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3685871971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.3685871971
Directory /workspace/11.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/11.otp_ctrl_smoke.2537330612
Short name T649
Test name
Test status
Simulation time 944534220 ps
CPU time 11.15 seconds
Started Mar 28 03:31:37 PM PDT 24
Finished Mar 28 03:31:49 PM PDT 24
Peak memory 241828 kb
Host smart-2e5325d7-cfc9-41d6-b65f-3426ff41fd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537330612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.2537330612
Directory /workspace/11.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all.3435352478
Short name T945
Test name
Test status
Simulation time 29283737335 ps
CPU time 172 seconds
Started Mar 28 03:31:38 PM PDT 24
Finished Mar 28 03:34:30 PM PDT 24
Peak memory 265108 kb
Host smart-a769511d-ed96-4c26-aae4-333defd5d9a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435352478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all
.3435352478
Directory /workspace/11.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all_with_rand_reset.330974860
Short name T1158
Test name
Test status
Simulation time 163593512075 ps
CPU time 2393.27 seconds
Started Mar 28 03:31:45 PM PDT 24
Finished Mar 28 04:11:39 PM PDT 24
Peak memory 563732 kb
Host smart-6e91c1b4-27ac-4097-9ceb-8e0e820e0e33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330974860 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all_with_rand_reset.330974860
Directory /workspace/11.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.otp_ctrl_test_access.2444996613
Short name T1127
Test name
Test status
Simulation time 1730383661 ps
CPU time 40.1 seconds
Started Mar 28 03:31:32 PM PDT 24
Finished Mar 28 03:32:12 PM PDT 24
Peak memory 241744 kb
Host smart-ec9283aa-a7e1-4f05-b13f-92205cd26463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444996613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.2444996613
Directory /workspace/11.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/110.otp_ctrl_init_fail.218538743
Short name T798
Test name
Test status
Simulation time 502676574 ps
CPU time 3.56 seconds
Started Mar 28 03:34:18 PM PDT 24
Finished Mar 28 03:34:22 PM PDT 24
Peak memory 242020 kb
Host smart-724a476f-26a2-4f4b-a564-362cd4713450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218538743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.218538743
Directory /workspace/110.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/110.otp_ctrl_parallel_lc_esc.3962217552
Short name T790
Test name
Test status
Simulation time 447366663 ps
CPU time 13.42 seconds
Started Mar 28 03:34:20 PM PDT 24
Finished Mar 28 03:34:34 PM PDT 24
Peak memory 241764 kb
Host smart-6d6605fd-a70b-405c-aa50-6a4c14573850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962217552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.3962217552
Directory /workspace/110.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/111.otp_ctrl_init_fail.3410705054
Short name T30
Test name
Test status
Simulation time 2170012359 ps
CPU time 7.13 seconds
Started Mar 28 03:34:20 PM PDT 24
Finished Mar 28 03:34:27 PM PDT 24
Peak memory 241780 kb
Host smart-5c51bccd-7146-42ad-bc10-bd82d186e86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410705054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.3410705054
Directory /workspace/111.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/111.otp_ctrl_parallel_lc_esc.1398568008
Short name T808
Test name
Test status
Simulation time 1948476617 ps
CPU time 6.27 seconds
Started Mar 28 03:34:21 PM PDT 24
Finished Mar 28 03:34:27 PM PDT 24
Peak memory 241620 kb
Host smart-7602a349-9c2e-460a-8868-e9d5e30ff0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398568008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.1398568008
Directory /workspace/111.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/112.otp_ctrl_init_fail.3033988061
Short name T542
Test name
Test status
Simulation time 407544072 ps
CPU time 4.1 seconds
Started Mar 28 03:34:22 PM PDT 24
Finished Mar 28 03:34:26 PM PDT 24
Peak memory 241844 kb
Host smart-24b01ffd-125f-48c9-a5cb-5d311f398ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033988061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.3033988061
Directory /workspace/112.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/112.otp_ctrl_parallel_lc_esc.2065282746
Short name T1010
Test name
Test status
Simulation time 4471101571 ps
CPU time 19.97 seconds
Started Mar 28 03:34:19 PM PDT 24
Finished Mar 28 03:34:39 PM PDT 24
Peak memory 241640 kb
Host smart-a2e58750-0b27-47f2-b27e-dab058cac966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065282746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.2065282746
Directory /workspace/112.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/113.otp_ctrl_init_fail.3767354332
Short name T67
Test name
Test status
Simulation time 385341891 ps
CPU time 4.56 seconds
Started Mar 28 03:34:21 PM PDT 24
Finished Mar 28 03:34:25 PM PDT 24
Peak memory 242088 kb
Host smart-55e14db2-9022-4065-a795-8a3467dd71f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767354332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.3767354332
Directory /workspace/113.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/113.otp_ctrl_parallel_lc_esc.2163515417
Short name T479
Test name
Test status
Simulation time 159212731 ps
CPU time 4.74 seconds
Started Mar 28 03:34:20 PM PDT 24
Finished Mar 28 03:34:24 PM PDT 24
Peak memory 242032 kb
Host smart-b210d57e-600d-403a-acb5-f9198218f327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163515417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.2163515417
Directory /workspace/113.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/114.otp_ctrl_init_fail.3315214862
Short name T1074
Test name
Test status
Simulation time 293104167 ps
CPU time 3.72 seconds
Started Mar 28 03:34:23 PM PDT 24
Finished Mar 28 03:34:28 PM PDT 24
Peak memory 242060 kb
Host smart-3f8d95a7-f66a-4605-9540-051c9c90591a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315214862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.3315214862
Directory /workspace/114.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/114.otp_ctrl_parallel_lc_esc.2586235599
Short name T353
Test name
Test status
Simulation time 1215375319 ps
CPU time 3.29 seconds
Started Mar 28 03:34:19 PM PDT 24
Finished Mar 28 03:34:23 PM PDT 24
Peak memory 242092 kb
Host smart-3480b257-dd30-40f9-9726-bfa8807bd93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586235599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.2586235599
Directory /workspace/114.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/115.otp_ctrl_parallel_lc_esc.3914543835
Short name T1086
Test name
Test status
Simulation time 708654463 ps
CPU time 7.02 seconds
Started Mar 28 03:34:22 PM PDT 24
Finished Mar 28 03:34:29 PM PDT 24
Peak memory 241768 kb
Host smart-70bfcafd-d899-438a-ab3b-5cef76d26d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914543835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.3914543835
Directory /workspace/115.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/116.otp_ctrl_parallel_lc_esc.78396426
Short name T676
Test name
Test status
Simulation time 3523300662 ps
CPU time 17.39 seconds
Started Mar 28 03:34:18 PM PDT 24
Finished Mar 28 03:34:36 PM PDT 24
Peak memory 241808 kb
Host smart-d861fe43-fac2-46d2-957e-64da76045026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78396426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.78396426
Directory /workspace/116.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/117.otp_ctrl_init_fail.1730670575
Short name T760
Test name
Test status
Simulation time 245939052 ps
CPU time 3.53 seconds
Started Mar 28 03:34:20 PM PDT 24
Finished Mar 28 03:34:24 PM PDT 24
Peak memory 241828 kb
Host smart-f8afbae5-ca98-4a67-8444-b0076f0f0270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730670575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.1730670575
Directory /workspace/117.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/117.otp_ctrl_parallel_lc_esc.157457927
Short name T1006
Test name
Test status
Simulation time 846268598 ps
CPU time 7.39 seconds
Started Mar 28 03:34:21 PM PDT 24
Finished Mar 28 03:34:29 PM PDT 24
Peak memory 241748 kb
Host smart-89da19f8-b2a4-493b-addd-0a82f239d7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157457927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.157457927
Directory /workspace/117.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/118.otp_ctrl_init_fail.429527464
Short name T1137
Test name
Test status
Simulation time 458634551 ps
CPU time 4.77 seconds
Started Mar 28 03:34:21 PM PDT 24
Finished Mar 28 03:34:27 PM PDT 24
Peak memory 241752 kb
Host smart-c0868a47-0e09-43a8-aae3-730f81f7b8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429527464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.429527464
Directory /workspace/118.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/118.otp_ctrl_parallel_lc_esc.199739366
Short name T765
Test name
Test status
Simulation time 132482708 ps
CPU time 5.48 seconds
Started Mar 28 03:34:20 PM PDT 24
Finished Mar 28 03:34:26 PM PDT 24
Peak memory 241512 kb
Host smart-057d73a9-34b5-4151-945a-e0d7f331acf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199739366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.199739366
Directory /workspace/118.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/119.otp_ctrl_init_fail.832997257
Short name T715
Test name
Test status
Simulation time 151967334 ps
CPU time 3.25 seconds
Started Mar 28 03:34:21 PM PDT 24
Finished Mar 28 03:34:25 PM PDT 24
Peak memory 241748 kb
Host smart-09f372b4-85a9-4661-922c-08ab2beaa864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832997257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.832997257
Directory /workspace/119.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/119.otp_ctrl_parallel_lc_esc.1332751683
Short name T545
Test name
Test status
Simulation time 1755943848 ps
CPU time 13.74 seconds
Started Mar 28 03:34:25 PM PDT 24
Finished Mar 28 03:34:39 PM PDT 24
Peak memory 241656 kb
Host smart-354d485c-3c62-461c-91e0-5d86b6a2957a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332751683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.1332751683
Directory /workspace/119.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_alert_test.1188449847
Short name T632
Test name
Test status
Simulation time 64019555 ps
CPU time 2 seconds
Started Mar 28 03:31:41 PM PDT 24
Finished Mar 28 03:31:43 PM PDT 24
Peak memory 239972 kb
Host smart-74c12043-a421-482d-af3b-0591e2fbc930
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188449847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.1188449847
Directory /workspace/12.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.otp_ctrl_check_fail.4164645195
Short name T54
Test name
Test status
Simulation time 2284930546 ps
CPU time 12 seconds
Started Mar 28 03:31:39 PM PDT 24
Finished Mar 28 03:31:52 PM PDT 24
Peak memory 242356 kb
Host smart-baf39450-0c66-4c82-95b3-fcbb352290ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164645195 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.4164645195
Directory /workspace/12.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_errs.1865223026
Short name T933
Test name
Test status
Simulation time 10845479977 ps
CPU time 29.11 seconds
Started Mar 28 03:31:37 PM PDT 24
Finished Mar 28 03:32:07 PM PDT 24
Peak memory 241072 kb
Host smart-edaca07f-dfae-4834-be7a-1050e653afcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865223026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.1865223026
Directory /workspace/12.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_lock.833670968
Short name T575
Test name
Test status
Simulation time 1051610295 ps
CPU time 19.07 seconds
Started Mar 28 03:31:36 PM PDT 24
Finished Mar 28 03:31:55 PM PDT 24
Peak memory 242244 kb
Host smart-d5dcaa74-63cf-47e5-88bf-0cffde0f7266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833670968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.833670968
Directory /workspace/12.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/12.otp_ctrl_init_fail.3032856361
Short name T911
Test name
Test status
Simulation time 270418295 ps
CPU time 3.41 seconds
Started Mar 28 03:31:38 PM PDT 24
Finished Mar 28 03:31:42 PM PDT 24
Peak memory 241744 kb
Host smart-c4291383-0b3b-4df6-9783-78f09b7088c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032856361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.3032856361
Directory /workspace/12.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_macro_errs.4233437434
Short name T813
Test name
Test status
Simulation time 240285059 ps
CPU time 6.04 seconds
Started Mar 28 03:31:35 PM PDT 24
Finished Mar 28 03:31:41 PM PDT 24
Peak memory 241784 kb
Host smart-eaf58903-9fce-4925-ab09-c021027d0ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233437434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.4233437434
Directory /workspace/12.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_key_req.640472713
Short name T319
Test name
Test status
Simulation time 2162300559 ps
CPU time 24.05 seconds
Started Mar 28 03:31:37 PM PDT 24
Finished Mar 28 03:32:02 PM PDT 24
Peak memory 240884 kb
Host smart-9273e3e2-ae1c-4f2d-8e2b-58c720f78006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640472713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.640472713
Directory /workspace/12.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_esc.2460327372
Short name T827
Test name
Test status
Simulation time 650428864 ps
CPU time 11.39 seconds
Started Mar 28 03:31:40 PM PDT 24
Finished Mar 28 03:31:52 PM PDT 24
Peak memory 241692 kb
Host smart-9b21d811-d748-4c27-be53-74bcd7d68208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460327372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.2460327372
Directory /workspace/12.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_req.2350559117
Short name T1166
Test name
Test status
Simulation time 393465248 ps
CPU time 8.71 seconds
Started Mar 28 03:31:39 PM PDT 24
Finished Mar 28 03:31:49 PM PDT 24
Peak memory 241588 kb
Host smart-e3ca9047-274a-4938-80be-61dd969dcfaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2350559117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.2350559117
Directory /workspace/12.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_regwen.2997212917
Short name T386
Test name
Test status
Simulation time 221321995 ps
CPU time 6.31 seconds
Started Mar 28 03:31:38 PM PDT 24
Finished Mar 28 03:31:44 PM PDT 24
Peak memory 241788 kb
Host smart-a833b1b5-4bb1-45c7-b626-5d8d537ce0f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2997212917 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.2997212917
Directory /workspace/12.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/12.otp_ctrl_smoke.2687153851
Short name T942
Test name
Test status
Simulation time 272551643 ps
CPU time 5.8 seconds
Started Mar 28 03:31:35 PM PDT 24
Finished Mar 28 03:31:41 PM PDT 24
Peak memory 241808 kb
Host smart-228f6cf8-6422-4aa6-be31-5c458f63a7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687153851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.2687153851
Directory /workspace/12.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all.2681614757
Short name T139
Test name
Test status
Simulation time 5101736887 ps
CPU time 70.65 seconds
Started Mar 28 03:31:36 PM PDT 24
Finished Mar 28 03:32:47 PM PDT 24
Peak memory 246368 kb
Host smart-28527ea7-665f-4930-ae53-e92cbff670e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681614757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all
.2681614757
Directory /workspace/12.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all_with_rand_reset.1448762000
Short name T365
Test name
Test status
Simulation time 60360694912 ps
CPU time 147.64 seconds
Started Mar 28 03:31:38 PM PDT 24
Finished Mar 28 03:34:06 PM PDT 24
Peak memory 272088 kb
Host smart-29713ba4-e087-49ef-9153-919cd774925c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448762000 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all_with_rand_reset.1448762000
Directory /workspace/12.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.otp_ctrl_test_access.438525541
Short name T1001
Test name
Test status
Simulation time 754648595 ps
CPU time 9.2 seconds
Started Mar 28 03:31:38 PM PDT 24
Finished Mar 28 03:31:47 PM PDT 24
Peak memory 241692 kb
Host smart-91c65bea-f49c-43b0-abc3-99708c541238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438525541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.438525541
Directory /workspace/12.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/120.otp_ctrl_init_fail.3250760720
Short name T1063
Test name
Test status
Simulation time 503982653 ps
CPU time 3.59 seconds
Started Mar 28 03:34:21 PM PDT 24
Finished Mar 28 03:34:25 PM PDT 24
Peak memory 242084 kb
Host smart-e66ac5ff-8d8f-4836-9428-4ab1d891bd39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250760720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.3250760720
Directory /workspace/120.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/120.otp_ctrl_parallel_lc_esc.2294962161
Short name T527
Test name
Test status
Simulation time 403210473 ps
CPU time 11.53 seconds
Started Mar 28 03:34:20 PM PDT 24
Finished Mar 28 03:34:32 PM PDT 24
Peak memory 241720 kb
Host smart-fc75a5dd-6d25-4cb9-8489-47a2acfa3e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294962161 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.2294962161
Directory /workspace/120.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/121.otp_ctrl_init_fail.1330421425
Short name T749
Test name
Test status
Simulation time 87108078 ps
CPU time 3.63 seconds
Started Mar 28 03:34:25 PM PDT 24
Finished Mar 28 03:34:29 PM PDT 24
Peak memory 241684 kb
Host smart-6f86e6a6-f669-44ab-ba1f-b3fa19748a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330421425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.1330421425
Directory /workspace/121.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/121.otp_ctrl_parallel_lc_esc.232901785
Short name T557
Test name
Test status
Simulation time 219806784 ps
CPU time 5.85 seconds
Started Mar 28 03:34:20 PM PDT 24
Finished Mar 28 03:34:26 PM PDT 24
Peak memory 241400 kb
Host smart-e3c829a2-0879-4498-83c7-235f891609b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232901785 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.232901785
Directory /workspace/121.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/122.otp_ctrl_init_fail.1316965701
Short name T204
Test name
Test status
Simulation time 410405176 ps
CPU time 3.53 seconds
Started Mar 28 03:34:24 PM PDT 24
Finished Mar 28 03:34:28 PM PDT 24
Peak memory 241752 kb
Host smart-064d5bc7-76f1-473f-ac49-b5f6b2e164c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316965701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.1316965701
Directory /workspace/122.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/123.otp_ctrl_init_fail.1284079263
Short name T553
Test name
Test status
Simulation time 262302660 ps
CPU time 4.33 seconds
Started Mar 28 03:34:25 PM PDT 24
Finished Mar 28 03:34:29 PM PDT 24
Peak memory 241788 kb
Host smart-a78d20d6-0358-43dc-8732-c5aba9459b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284079263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.1284079263
Directory /workspace/123.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/123.otp_ctrl_parallel_lc_esc.3914943726
Short name T227
Test name
Test status
Simulation time 619641256 ps
CPU time 17.89 seconds
Started Mar 28 03:34:20 PM PDT 24
Finished Mar 28 03:34:38 PM PDT 24
Peak memory 241784 kb
Host smart-ca63bffb-b3e1-4438-ad4f-e7b6bb4b8c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914943726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.3914943726
Directory /workspace/123.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/124.otp_ctrl_init_fail.2857086314
Short name T898
Test name
Test status
Simulation time 253423632 ps
CPU time 3.85 seconds
Started Mar 28 03:34:21 PM PDT 24
Finished Mar 28 03:34:25 PM PDT 24
Peak memory 242036 kb
Host smart-e5362381-b214-40a7-9541-350983f822f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857086314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.2857086314
Directory /workspace/124.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/124.otp_ctrl_parallel_lc_esc.473441519
Short name T861
Test name
Test status
Simulation time 144623247 ps
CPU time 4.24 seconds
Started Mar 28 03:34:24 PM PDT 24
Finished Mar 28 03:34:29 PM PDT 24
Peak memory 241496 kb
Host smart-ffa23825-c3df-48f9-a7f8-3475074ba402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473441519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.473441519
Directory /workspace/124.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/125.otp_ctrl_init_fail.723179961
Short name T748
Test name
Test status
Simulation time 122293345 ps
CPU time 5.58 seconds
Started Mar 28 03:34:22 PM PDT 24
Finished Mar 28 03:34:28 PM PDT 24
Peak memory 241764 kb
Host smart-88276b15-c951-4083-b6a7-175134881da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723179961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.723179961
Directory /workspace/125.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/125.otp_ctrl_parallel_lc_esc.2853221951
Short name T505
Test name
Test status
Simulation time 146565739 ps
CPU time 4.63 seconds
Started Mar 28 03:34:21 PM PDT 24
Finished Mar 28 03:34:26 PM PDT 24
Peak memory 241612 kb
Host smart-9fb76669-bb12-42a8-8a1d-98f147790d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853221951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.2853221951
Directory /workspace/125.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/126.otp_ctrl_init_fail.2595154437
Short name T496
Test name
Test status
Simulation time 2470944505 ps
CPU time 5.12 seconds
Started Mar 28 03:34:22 PM PDT 24
Finished Mar 28 03:34:27 PM PDT 24
Peak memory 241872 kb
Host smart-03335966-e259-4f9c-8ea0-5acf9bc1c982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595154437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.2595154437
Directory /workspace/126.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/126.otp_ctrl_parallel_lc_esc.749227245
Short name T846
Test name
Test status
Simulation time 871036635 ps
CPU time 10.02 seconds
Started Mar 28 03:34:24 PM PDT 24
Finished Mar 28 03:34:34 PM PDT 24
Peak memory 241900 kb
Host smart-2362599a-449a-4a08-a203-788bb1c7246e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749227245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.749227245
Directory /workspace/126.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/127.otp_ctrl_init_fail.2699488828
Short name T782
Test name
Test status
Simulation time 109142076 ps
CPU time 4.13 seconds
Started Mar 28 03:34:22 PM PDT 24
Finished Mar 28 03:34:26 PM PDT 24
Peak memory 241708 kb
Host smart-bb2b7fea-05b1-4a80-b11b-9f550d2fa826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699488828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.2699488828
Directory /workspace/127.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/127.otp_ctrl_parallel_lc_esc.2517586634
Short name T910
Test name
Test status
Simulation time 1344552603 ps
CPU time 17.87 seconds
Started Mar 28 03:34:23 PM PDT 24
Finished Mar 28 03:34:41 PM PDT 24
Peak memory 241544 kb
Host smart-ce802110-0a1b-43c7-9108-385c06fb4624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517586634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.2517586634
Directory /workspace/127.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/128.otp_ctrl_init_fail.416188701
Short name T645
Test name
Test status
Simulation time 1310519855 ps
CPU time 4.67 seconds
Started Mar 28 03:34:54 PM PDT 24
Finished Mar 28 03:34:59 PM PDT 24
Peak memory 241704 kb
Host smart-fa5688ba-df44-4aa7-9188-c7a30d6fc709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416188701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.416188701
Directory /workspace/128.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/128.otp_ctrl_parallel_lc_esc.2823942437
Short name T853
Test name
Test status
Simulation time 189720264 ps
CPU time 9.96 seconds
Started Mar 28 03:34:25 PM PDT 24
Finished Mar 28 03:34:35 PM PDT 24
Peak memory 242024 kb
Host smart-8109d281-dc87-4ac5-9f5d-17257a9b7470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823942437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.2823942437
Directory /workspace/128.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/129.otp_ctrl_init_fail.3426748390
Short name T538
Test name
Test status
Simulation time 551221619 ps
CPU time 4.1 seconds
Started Mar 28 03:34:21 PM PDT 24
Finished Mar 28 03:34:25 PM PDT 24
Peak memory 241744 kb
Host smart-9f992183-4cae-4774-a76b-b1d6f75599f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426748390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.3426748390
Directory /workspace/129.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/129.otp_ctrl_parallel_lc_esc.3284444511
Short name T1106
Test name
Test status
Simulation time 235176612 ps
CPU time 5.78 seconds
Started Mar 28 03:34:25 PM PDT 24
Finished Mar 28 03:34:31 PM PDT 24
Peak memory 241616 kb
Host smart-39fdac98-6a86-483b-81b2-b0f697de0c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284444511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.3284444511
Directory /workspace/129.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_alert_test.3928620390
Short name T572
Test name
Test status
Simulation time 133689963 ps
CPU time 1.86 seconds
Started Mar 28 03:31:37 PM PDT 24
Finished Mar 28 03:31:39 PM PDT 24
Peak memory 240204 kb
Host smart-183a6220-bd11-452e-ad39-f15671f20a88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928620390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.3928620390
Directory /workspace/13.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.otp_ctrl_check_fail.4268853893
Short name T795
Test name
Test status
Simulation time 886708661 ps
CPU time 6.92 seconds
Started Mar 28 03:31:38 PM PDT 24
Finished Mar 28 03:31:45 PM PDT 24
Peak memory 242044 kb
Host smart-c9295d6c-5110-482f-93bf-7c8e957f754b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268853893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.4268853893
Directory /workspace/13.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_lock.118651393
Short name T1055
Test name
Test status
Simulation time 4658894135 ps
CPU time 15.63 seconds
Started Mar 28 03:31:37 PM PDT 24
Finished Mar 28 03:31:53 PM PDT 24
Peak memory 242440 kb
Host smart-cd01058e-78f7-4e6f-a51a-9207719bda39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118651393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.118651393
Directory /workspace/13.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/13.otp_ctrl_init_fail.223007460
Short name T588
Test name
Test status
Simulation time 193087324 ps
CPU time 3.83 seconds
Started Mar 28 03:31:36 PM PDT 24
Finished Mar 28 03:31:40 PM PDT 24
Peak memory 241800 kb
Host smart-a488af75-df79-41d4-9fd9-4badbce366ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223007460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.223007460
Directory /workspace/13.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_macro_errs.132337621
Short name T771
Test name
Test status
Simulation time 873777577 ps
CPU time 7.96 seconds
Started Mar 28 03:31:38 PM PDT 24
Finished Mar 28 03:31:46 PM PDT 24
Peak memory 241780 kb
Host smart-e0fc6d0a-5d54-4d2e-a792-e58f30ac7e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132337621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.132337621
Directory /workspace/13.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_key_req.678254910
Short name T1140
Test name
Test status
Simulation time 496063601 ps
CPU time 12.95 seconds
Started Mar 28 03:31:36 PM PDT 24
Finished Mar 28 03:31:49 PM PDT 24
Peak memory 242228 kb
Host smart-8cd35c90-4b69-461c-8175-4136e27d7793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678254910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.678254910
Directory /workspace/13.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_esc.2813755511
Short name T701
Test name
Test status
Simulation time 2223794101 ps
CPU time 8.61 seconds
Started Mar 28 03:31:37 PM PDT 24
Finished Mar 28 03:31:46 PM PDT 24
Peak memory 241660 kb
Host smart-47e4d419-aafd-49cf-bc6a-c64a6b244852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813755511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.2813755511
Directory /workspace/13.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_req.1373504738
Short name T848
Test name
Test status
Simulation time 484621316 ps
CPU time 14.96 seconds
Started Mar 28 03:31:41 PM PDT 24
Finished Mar 28 03:31:56 PM PDT 24
Peak memory 248456 kb
Host smart-2f2be0ef-1f66-47ce-8dc5-0d8fcbe12483
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1373504738 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.1373504738
Directory /workspace/13.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_regwen.2004049637
Short name T1020
Test name
Test status
Simulation time 433704805 ps
CPU time 7.36 seconds
Started Mar 28 03:31:46 PM PDT 24
Finished Mar 28 03:31:53 PM PDT 24
Peak memory 241980 kb
Host smart-d063ba5d-84f6-4fab-8467-df621102709f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2004049637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.2004049637
Directory /workspace/13.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/13.otp_ctrl_smoke.2998586310
Short name T598
Test name
Test status
Simulation time 2553070775 ps
CPU time 9.14 seconds
Started Mar 28 03:31:38 PM PDT 24
Finished Mar 28 03:31:48 PM PDT 24
Peak memory 241832 kb
Host smart-d881281e-3daf-4800-ba13-47d41fe62ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998586310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.2998586310
Directory /workspace/13.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all.3135303484
Short name T404
Test name
Test status
Simulation time 33993050445 ps
CPU time 77.86 seconds
Started Mar 28 03:31:45 PM PDT 24
Finished Mar 28 03:33:03 PM PDT 24
Peak memory 244344 kb
Host smart-81c0bebf-d397-46f6-826b-fb59edeffccf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135303484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all
.3135303484
Directory /workspace/13.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.otp_ctrl_test_access.3734316937
Short name T1149
Test name
Test status
Simulation time 493766368 ps
CPU time 9.91 seconds
Started Mar 28 03:31:46 PM PDT 24
Finished Mar 28 03:31:56 PM PDT 24
Peak memory 241936 kb
Host smart-2c336ded-5c0c-48eb-bba8-12022bad6cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734316937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.3734316937
Directory /workspace/13.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/130.otp_ctrl_init_fail.1787599786
Short name T490
Test name
Test status
Simulation time 538583504 ps
CPU time 4.8 seconds
Started Mar 28 03:34:25 PM PDT 24
Finished Mar 28 03:34:30 PM PDT 24
Peak memory 242052 kb
Host smart-1abc1c7a-34b6-4da6-aef6-08ca7d2391dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787599786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.1787599786
Directory /workspace/130.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/130.otp_ctrl_parallel_lc_esc.2537997861
Short name T565
Test name
Test status
Simulation time 1139637612 ps
CPU time 18.14 seconds
Started Mar 28 03:34:25 PM PDT 24
Finished Mar 28 03:34:44 PM PDT 24
Peak memory 241952 kb
Host smart-e6f9a4fa-f91f-42ef-98a4-8f29eeb4a660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537997861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.2537997861
Directory /workspace/130.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/131.otp_ctrl_init_fail.416836835
Short name T546
Test name
Test status
Simulation time 675329066 ps
CPU time 4.89 seconds
Started Mar 28 03:34:23 PM PDT 24
Finished Mar 28 03:34:28 PM PDT 24
Peak memory 242048 kb
Host smart-9ebffb5f-3245-4928-a590-2a1f8c5b6b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416836835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.416836835
Directory /workspace/131.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/131.otp_ctrl_parallel_lc_esc.3601422681
Short name T1090
Test name
Test status
Simulation time 551760116 ps
CPU time 6.82 seconds
Started Mar 28 03:34:27 PM PDT 24
Finished Mar 28 03:34:34 PM PDT 24
Peak memory 241612 kb
Host smart-8169fcc6-7b75-45e8-8f19-7d9eeee0873a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601422681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.3601422681
Directory /workspace/131.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/132.otp_ctrl_init_fail.325974689
Short name T931
Test name
Test status
Simulation time 123833384 ps
CPU time 3.98 seconds
Started Mar 28 03:34:27 PM PDT 24
Finished Mar 28 03:34:31 PM PDT 24
Peak memory 241780 kb
Host smart-c0a765eb-9233-40ba-bbba-65c16646c0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325974689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.325974689
Directory /workspace/132.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/132.otp_ctrl_parallel_lc_esc.3446799276
Short name T1045
Test name
Test status
Simulation time 164795273 ps
CPU time 6.54 seconds
Started Mar 28 03:34:23 PM PDT 24
Finished Mar 28 03:34:30 PM PDT 24
Peak memory 241580 kb
Host smart-6e9ddea0-6daa-4c0a-adfa-c76dac69fcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446799276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.3446799276
Directory /workspace/132.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/133.otp_ctrl_init_fail.1413923181
Short name T743
Test name
Test status
Simulation time 171931776 ps
CPU time 4.73 seconds
Started Mar 28 03:34:22 PM PDT 24
Finished Mar 28 03:34:27 PM PDT 24
Peak memory 242008 kb
Host smart-6c52e3db-8a7a-4759-a927-2b5d78e95e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413923181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.1413923181
Directory /workspace/133.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/133.otp_ctrl_parallel_lc_esc.940472783
Short name T489
Test name
Test status
Simulation time 1735122693 ps
CPU time 12.69 seconds
Started Mar 28 03:34:22 PM PDT 24
Finished Mar 28 03:34:35 PM PDT 24
Peak memory 241632 kb
Host smart-9b6de85f-a11d-4b60-9e38-23d717a9bc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940472783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.940472783
Directory /workspace/133.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/134.otp_ctrl_init_fail.564833735
Short name T1102
Test name
Test status
Simulation time 451467128 ps
CPU time 4.45 seconds
Started Mar 28 03:34:23 PM PDT 24
Finished Mar 28 03:34:27 PM PDT 24
Peak memory 241704 kb
Host smart-022fab70-a6d2-4dfb-b82a-26eebecd1fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564833735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.564833735
Directory /workspace/134.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/135.otp_ctrl_init_fail.3893927227
Short name T550
Test name
Test status
Simulation time 599851774 ps
CPU time 4.54 seconds
Started Mar 28 03:34:27 PM PDT 24
Finished Mar 28 03:34:32 PM PDT 24
Peak memory 242056 kb
Host smart-f52fd63a-9d90-4dbc-b4bf-21f1852866d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893927227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.3893927227
Directory /workspace/135.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/135.otp_ctrl_parallel_lc_esc.3577151947
Short name T269
Test name
Test status
Simulation time 279334583 ps
CPU time 8.36 seconds
Started Mar 28 03:34:21 PM PDT 24
Finished Mar 28 03:34:29 PM PDT 24
Peak memory 241704 kb
Host smart-abec965d-f21e-4b75-ae16-269d33fc5c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577151947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.3577151947
Directory /workspace/135.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/136.otp_ctrl_init_fail.3967042628
Short name T1115
Test name
Test status
Simulation time 148465158 ps
CPU time 4.5 seconds
Started Mar 28 03:34:27 PM PDT 24
Finished Mar 28 03:34:32 PM PDT 24
Peak memory 241992 kb
Host smart-fcdc698b-160f-4951-8895-42e58306d5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967042628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.3967042628
Directory /workspace/136.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/136.otp_ctrl_parallel_lc_esc.2496878734
Short name T234
Test name
Test status
Simulation time 609542948 ps
CPU time 5.67 seconds
Started Mar 28 03:34:26 PM PDT 24
Finished Mar 28 03:34:32 PM PDT 24
Peak memory 241732 kb
Host smart-a6476dbc-007f-4236-874c-485c9ef5d78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496878734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.2496878734
Directory /workspace/136.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/137.otp_ctrl_init_fail.3483676150
Short name T231
Test name
Test status
Simulation time 408743033 ps
CPU time 3.76 seconds
Started Mar 28 03:34:24 PM PDT 24
Finished Mar 28 03:34:28 PM PDT 24
Peak memory 242084 kb
Host smart-04dfa09b-131e-40ec-b250-d6483deffdd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483676150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.3483676150
Directory /workspace/137.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/137.otp_ctrl_parallel_lc_esc.796910989
Short name T155
Test name
Test status
Simulation time 513811996 ps
CPU time 11.31 seconds
Started Mar 28 03:34:25 PM PDT 24
Finished Mar 28 03:34:37 PM PDT 24
Peak memory 241900 kb
Host smart-babd7a31-97b6-4dad-b34b-844f14e4cb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796910989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.796910989
Directory /workspace/137.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/138.otp_ctrl_init_fail.3486954438
Short name T887
Test name
Test status
Simulation time 1362435668 ps
CPU time 4.27 seconds
Started Mar 28 03:34:24 PM PDT 24
Finished Mar 28 03:34:29 PM PDT 24
Peak memory 242036 kb
Host smart-3e1dcafe-3f37-4d93-95aa-735a8137202f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486954438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.3486954438
Directory /workspace/138.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/138.otp_ctrl_parallel_lc_esc.1822265938
Short name T522
Test name
Test status
Simulation time 20507146349 ps
CPU time 44.97 seconds
Started Mar 28 03:34:25 PM PDT 24
Finished Mar 28 03:35:10 PM PDT 24
Peak memory 243308 kb
Host smart-0ec707b1-7f30-4db0-9e49-43f08d140a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822265938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.1822265938
Directory /workspace/138.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/139.otp_ctrl_init_fail.2574354601
Short name T720
Test name
Test status
Simulation time 540206473 ps
CPU time 3.99 seconds
Started Mar 28 03:34:22 PM PDT 24
Finished Mar 28 03:34:26 PM PDT 24
Peak memory 241840 kb
Host smart-4dab51b6-1b25-4c7a-a92b-a2ab89b65dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574354601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.2574354601
Directory /workspace/139.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/139.otp_ctrl_parallel_lc_esc.4027059230
Short name T1061
Test name
Test status
Simulation time 350370529 ps
CPU time 3.57 seconds
Started Mar 28 03:34:22 PM PDT 24
Finished Mar 28 03:34:26 PM PDT 24
Peak memory 241668 kb
Host smart-55a8157f-d26e-456e-bc58-158fa60ff289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027059230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.4027059230
Directory /workspace/139.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_alert_test.169842845
Short name T1033
Test name
Test status
Simulation time 725755307 ps
CPU time 1.6 seconds
Started Mar 28 03:31:35 PM PDT 24
Finished Mar 28 03:31:38 PM PDT 24
Peak memory 240028 kb
Host smart-93225eab-d09f-4aa5-990e-383fb2f7a058
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169842845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.169842845
Directory /workspace/14.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.otp_ctrl_check_fail.963356152
Short name T77
Test name
Test status
Simulation time 7493303135 ps
CPU time 12.08 seconds
Started Mar 28 03:31:46 PM PDT 24
Finished Mar 28 03:31:58 PM PDT 24
Peak memory 245292 kb
Host smart-53a72d97-98e1-4774-aad9-10355ad56987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963356152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.963356152
Directory /workspace/14.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_errs.1621819337
Short name T778
Test name
Test status
Simulation time 1881976161 ps
CPU time 12.41 seconds
Started Mar 28 03:31:41 PM PDT 24
Finished Mar 28 03:31:53 PM PDT 24
Peak memory 241676 kb
Host smart-5463d245-97a6-4fda-b308-7eeb4feff5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621819337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.1621819337
Directory /workspace/14.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_lock.2524644312
Short name T107
Test name
Test status
Simulation time 305983631 ps
CPU time 4.68 seconds
Started Mar 28 03:31:40 PM PDT 24
Finished Mar 28 03:31:45 PM PDT 24
Peak memory 241692 kb
Host smart-0d39bcbd-9ba0-4202-8185-8de6e8bb1f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524644312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.2524644312
Directory /workspace/14.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/14.otp_ctrl_init_fail.970467839
Short name T549
Test name
Test status
Simulation time 612724810 ps
CPU time 4.38 seconds
Started Mar 28 03:31:40 PM PDT 24
Finished Mar 28 03:31:45 PM PDT 24
Peak memory 241696 kb
Host smart-c59df42b-55df-49dd-8c12-38b17ca0c399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970467839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.970467839
Directory /workspace/14.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_macro_errs.1741110262
Short name T1076
Test name
Test status
Simulation time 1024180081 ps
CPU time 33.06 seconds
Started Mar 28 03:31:46 PM PDT 24
Finished Mar 28 03:32:19 PM PDT 24
Peak memory 243884 kb
Host smart-c416e0ca-15f7-4af1-b968-d2b85f1b2329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741110262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_macro_errs.1741110262
Directory /workspace/14.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_key_req.1484746950
Short name T103
Test name
Test status
Simulation time 2601297060 ps
CPU time 36.93 seconds
Started Mar 28 03:31:39 PM PDT 24
Finished Mar 28 03:32:16 PM PDT 24
Peak memory 241780 kb
Host smart-b44c95a7-1b01-4e63-80af-721c9d4fd44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484746950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.1484746950
Directory /workspace/14.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_esc.2150680766
Short name T1128
Test name
Test status
Simulation time 79358778 ps
CPU time 2.54 seconds
Started Mar 28 03:31:40 PM PDT 24
Finished Mar 28 03:31:43 PM PDT 24
Peak memory 241616 kb
Host smart-561c159b-dddf-422d-a26c-b091cb396bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150680766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.2150680766
Directory /workspace/14.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_req.3533501698
Short name T93
Test name
Test status
Simulation time 11356761685 ps
CPU time 32.87 seconds
Started Mar 28 03:31:37 PM PDT 24
Finished Mar 28 03:32:11 PM PDT 24
Peak memory 241736 kb
Host smart-1f471dd6-e6b5-43f1-81d2-3b050b41454e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3533501698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.3533501698
Directory /workspace/14.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_regwen.285753148
Short name T1000
Test name
Test status
Simulation time 434952457 ps
CPU time 8.96 seconds
Started Mar 28 03:31:35 PM PDT 24
Finished Mar 28 03:31:44 PM PDT 24
Peak memory 241716 kb
Host smart-5940542b-cc6b-48fc-8eb9-9ed28e0af3d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=285753148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.285753148
Directory /workspace/14.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/14.otp_ctrl_smoke.2676943718
Short name T1150
Test name
Test status
Simulation time 6398621690 ps
CPU time 14.2 seconds
Started Mar 28 03:31:37 PM PDT 24
Finished Mar 28 03:31:52 PM PDT 24
Peak memory 242368 kb
Host smart-0b6f8a95-4415-4220-bfd6-2ea81f187635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676943718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.2676943718
Directory /workspace/14.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all.4238336673
Short name T972
Test name
Test status
Simulation time 29144805695 ps
CPU time 303.18 seconds
Started Mar 28 03:31:37 PM PDT 24
Finished Mar 28 03:36:40 PM PDT 24
Peak memory 273288 kb
Host smart-a937379a-6eae-4f27-8119-41f3e1f15456
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238336673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all
.4238336673
Directory /workspace/14.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all_with_rand_reset.690643250
Short name T265
Test name
Test status
Simulation time 58389312407 ps
CPU time 619.78 seconds
Started Mar 28 03:31:39 PM PDT 24
Finished Mar 28 03:42:00 PM PDT 24
Peak memory 330500 kb
Host smart-4c3f1dbf-5728-472a-bf65-24832efc11f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690643250 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all_with_rand_reset.690643250
Directory /workspace/14.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.otp_ctrl_test_access.2460826389
Short name T325
Test name
Test status
Simulation time 13087330689 ps
CPU time 15.95 seconds
Started Mar 28 03:31:40 PM PDT 24
Finished Mar 28 03:31:57 PM PDT 24
Peak memory 242608 kb
Host smart-5b9c50c4-7ec5-4a88-a086-113b2ce30bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460826389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.2460826389
Directory /workspace/14.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/140.otp_ctrl_init_fail.131893813
Short name T207
Test name
Test status
Simulation time 145499094 ps
CPU time 3.62 seconds
Started Mar 28 03:34:19 PM PDT 24
Finished Mar 28 03:34:23 PM PDT 24
Peak memory 241728 kb
Host smart-fcd67536-ae83-492f-a8e1-7fea40567b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131893813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.131893813
Directory /workspace/140.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/140.otp_ctrl_parallel_lc_esc.3445576614
Short name T230
Test name
Test status
Simulation time 223029761 ps
CPU time 5.29 seconds
Started Mar 28 03:34:24 PM PDT 24
Finished Mar 28 03:34:30 PM PDT 24
Peak memory 241548 kb
Host smart-8883b7b6-d36e-4620-ba64-11c5b9d71793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445576614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.3445576614
Directory /workspace/140.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/141.otp_ctrl_init_fail.3052330590
Short name T238
Test name
Test status
Simulation time 178259817 ps
CPU time 3.6 seconds
Started Mar 28 03:34:21 PM PDT 24
Finished Mar 28 03:34:25 PM PDT 24
Peak memory 241808 kb
Host smart-15b27b41-25a4-4ed7-b3da-105b47f8e170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052330590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.3052330590
Directory /workspace/141.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/141.otp_ctrl_parallel_lc_esc.1984540023
Short name T1117
Test name
Test status
Simulation time 263525037 ps
CPU time 5.76 seconds
Started Mar 28 03:34:23 PM PDT 24
Finished Mar 28 03:34:29 PM PDT 24
Peak memory 242032 kb
Host smart-287787ee-ef6d-42ab-b524-67962ad3df69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984540023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.1984540023
Directory /workspace/141.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/142.otp_ctrl_parallel_lc_esc.667977435
Short name T571
Test name
Test status
Simulation time 281269859 ps
CPU time 8.68 seconds
Started Mar 28 03:34:39 PM PDT 24
Finished Mar 28 03:34:49 PM PDT 24
Peak memory 241780 kb
Host smart-8c9e0916-e624-4cc8-ae74-5e0d17962fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667977435 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.667977435
Directory /workspace/142.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/143.otp_ctrl_init_fail.584813583
Short name T1170
Test name
Test status
Simulation time 285591024 ps
CPU time 5.38 seconds
Started Mar 28 03:34:51 PM PDT 24
Finished Mar 28 03:34:57 PM PDT 24
Peak memory 241652 kb
Host smart-e2226084-2092-48b6-870e-8417e254f219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584813583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.584813583
Directory /workspace/143.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/143.otp_ctrl_parallel_lc_esc.3173973705
Short name T167
Test name
Test status
Simulation time 773644801 ps
CPU time 6.42 seconds
Started Mar 28 03:34:39 PM PDT 24
Finished Mar 28 03:34:46 PM PDT 24
Peak memory 241624 kb
Host smart-e32a98be-f128-4edd-b70c-7ec95e0a07ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173973705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.3173973705
Directory /workspace/143.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/144.otp_ctrl_init_fail.1568904298
Short name T583
Test name
Test status
Simulation time 271877085 ps
CPU time 4.75 seconds
Started Mar 28 03:34:43 PM PDT 24
Finished Mar 28 03:34:51 PM PDT 24
Peak memory 241932 kb
Host smart-ce4f8723-e5cf-4d11-8da7-be872df40b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568904298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.1568904298
Directory /workspace/144.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/144.otp_ctrl_parallel_lc_esc.1253118661
Short name T920
Test name
Test status
Simulation time 234655657 ps
CPU time 7.16 seconds
Started Mar 28 03:34:40 PM PDT 24
Finished Mar 28 03:34:50 PM PDT 24
Peak memory 241548 kb
Host smart-306c8fb1-5d47-4fff-8bbc-c032f30afd52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253118661 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.1253118661
Directory /workspace/144.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/145.otp_ctrl_init_fail.33699418
Short name T27
Test name
Test status
Simulation time 622535997 ps
CPU time 4.92 seconds
Started Mar 28 03:34:37 PM PDT 24
Finished Mar 28 03:34:43 PM PDT 24
Peak memory 241988 kb
Host smart-5cecc694-b92e-4542-b8d1-78e076a2a23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33699418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.33699418
Directory /workspace/145.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/145.otp_ctrl_parallel_lc_esc.4250642826
Short name T633
Test name
Test status
Simulation time 1131401447 ps
CPU time 8.28 seconds
Started Mar 28 03:34:43 PM PDT 24
Finished Mar 28 03:34:54 PM PDT 24
Peak memory 241672 kb
Host smart-3de88218-9157-4456-a42f-69f9bc41ae7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250642826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.4250642826
Directory /workspace/145.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/146.otp_ctrl_init_fail.2739830596
Short name T201
Test name
Test status
Simulation time 107634045 ps
CPU time 3.86 seconds
Started Mar 28 03:34:36 PM PDT 24
Finished Mar 28 03:34:40 PM PDT 24
Peak memory 242080 kb
Host smart-d5a659fd-0177-494e-a23d-3e304f72ff1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739830596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.2739830596
Directory /workspace/146.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/146.otp_ctrl_parallel_lc_esc.2863930669
Short name T455
Test name
Test status
Simulation time 711432157 ps
CPU time 10.16 seconds
Started Mar 28 03:34:37 PM PDT 24
Finished Mar 28 03:34:47 PM PDT 24
Peak memory 241564 kb
Host smart-0421a489-e3d4-441b-8bfe-d1bdd88fe679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863930669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.2863930669
Directory /workspace/146.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/147.otp_ctrl_init_fail.3390766742
Short name T520
Test name
Test status
Simulation time 1505771199 ps
CPU time 5.54 seconds
Started Mar 28 03:34:39 PM PDT 24
Finished Mar 28 03:34:46 PM PDT 24
Peak memory 242032 kb
Host smart-30c94db3-26c0-42b5-82fc-eee82228c783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390766742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.3390766742
Directory /workspace/147.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/147.otp_ctrl_parallel_lc_esc.3275880528
Short name T927
Test name
Test status
Simulation time 1397351575 ps
CPU time 4.57 seconds
Started Mar 28 03:34:39 PM PDT 24
Finished Mar 28 03:34:44 PM PDT 24
Peak memory 241620 kb
Host smart-3f83a457-6da6-4e1c-aab0-b14a814ef998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275880528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.3275880528
Directory /workspace/147.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/148.otp_ctrl_init_fail.3315357287
Short name T29
Test name
Test status
Simulation time 601660733 ps
CPU time 4.37 seconds
Started Mar 28 03:34:36 PM PDT 24
Finished Mar 28 03:34:41 PM PDT 24
Peak memory 241736 kb
Host smart-6bdd72d0-09d8-4801-acd6-c2a848dc5bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315357287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.3315357287
Directory /workspace/148.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/148.otp_ctrl_parallel_lc_esc.2078658040
Short name T629
Test name
Test status
Simulation time 354408923 ps
CPU time 8.35 seconds
Started Mar 28 03:34:37 PM PDT 24
Finished Mar 28 03:34:45 PM PDT 24
Peak memory 241688 kb
Host smart-4a1d8baa-04ab-4b97-ade7-4d8273017da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078658040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.2078658040
Directory /workspace/148.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/149.otp_ctrl_init_fail.673189154
Short name T627
Test name
Test status
Simulation time 207028296 ps
CPU time 4.14 seconds
Started Mar 28 03:34:37 PM PDT 24
Finished Mar 28 03:34:42 PM PDT 24
Peak memory 241656 kb
Host smart-7ebd96c3-f27a-4f12-a4a2-d9e7093f97cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673189154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.673189154
Directory /workspace/149.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/149.otp_ctrl_parallel_lc_esc.1995280627
Short name T458
Test name
Test status
Simulation time 151590411 ps
CPU time 6.47 seconds
Started Mar 28 03:34:44 PM PDT 24
Finished Mar 28 03:34:52 PM PDT 24
Peak memory 241508 kb
Host smart-cc7ac374-c293-499b-befa-38f6f8a7b786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995280627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.1995280627
Directory /workspace/149.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_alert_test.1339442721
Short name T684
Test name
Test status
Simulation time 155149235 ps
CPU time 1.8 seconds
Started Mar 28 03:31:54 PM PDT 24
Finished Mar 28 03:31:59 PM PDT 24
Peak memory 240260 kb
Host smart-01eb30f3-78eb-4a62-ba76-cdd24ff3b0d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339442721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.1339442721
Directory /workspace/15.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_errs.4134233751
Short name T88
Test name
Test status
Simulation time 481523050 ps
CPU time 24.19 seconds
Started Mar 28 03:31:53 PM PDT 24
Finished Mar 28 03:32:20 PM PDT 24
Peak memory 241640 kb
Host smart-48b03482-bd14-4bc4-9aae-8e418573f5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134233751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.4134233751
Directory /workspace/15.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_lock.3330726864
Short name T593
Test name
Test status
Simulation time 223227833 ps
CPU time 4.04 seconds
Started Mar 28 03:31:53 PM PDT 24
Finished Mar 28 03:31:59 PM PDT 24
Peak memory 242032 kb
Host smart-23219b8f-811b-4d8c-8054-07d8d4e37bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330726864 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.3330726864
Directory /workspace/15.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/15.otp_ctrl_init_fail.430729796
Short name T666
Test name
Test status
Simulation time 134507696 ps
CPU time 4.29 seconds
Started Mar 28 03:32:00 PM PDT 24
Finished Mar 28 03:32:05 PM PDT 24
Peak memory 242092 kb
Host smart-f7f735e9-93ea-4fb9-80fc-2490b3969a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430729796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.430729796
Directory /workspace/15.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_macro_errs.919154790
Short name T1157
Test name
Test status
Simulation time 12174496555 ps
CPU time 36.01 seconds
Started Mar 28 03:31:54 PM PDT 24
Finished Mar 28 03:32:32 PM PDT 24
Peak memory 248660 kb
Host smart-b05239ef-fb4a-48d4-80f6-5d14e0970007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919154790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.919154790
Directory /workspace/15.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_key_req.1170335408
Short name T631
Test name
Test status
Simulation time 1000441249 ps
CPU time 6.53 seconds
Started Mar 28 03:31:55 PM PDT 24
Finished Mar 28 03:32:03 PM PDT 24
Peak memory 241668 kb
Host smart-7cc2819f-3517-484c-aba4-366de14ffe58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170335408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.1170335408
Directory /workspace/15.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_esc.858805555
Short name T530
Test name
Test status
Simulation time 115996181 ps
CPU time 4.83 seconds
Started Mar 28 03:31:54 PM PDT 24
Finished Mar 28 03:32:02 PM PDT 24
Peak memory 241628 kb
Host smart-c2f52a26-25d5-4293-b2d8-44efb46566d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858805555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.858805555
Directory /workspace/15.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_req.3245713781
Short name T531
Test name
Test status
Simulation time 1679252909 ps
CPU time 12.45 seconds
Started Mar 28 03:31:54 PM PDT 24
Finished Mar 28 03:32:09 PM PDT 24
Peak memory 241624 kb
Host smart-31d40496-ddb8-4f50-b988-c9a0065211f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3245713781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.3245713781
Directory /workspace/15.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_regwen.2665464571
Short name T288
Test name
Test status
Simulation time 308718101 ps
CPU time 5.81 seconds
Started Mar 28 03:31:53 PM PDT 24
Finished Mar 28 03:32:01 PM PDT 24
Peak memory 241844 kb
Host smart-082c74d7-1329-4bea-ae5e-6a312b09280a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2665464571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.2665464571
Directory /workspace/15.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/15.otp_ctrl_smoke.3305867436
Short name T769
Test name
Test status
Simulation time 2029471571 ps
CPU time 5.81 seconds
Started Mar 28 03:31:53 PM PDT 24
Finished Mar 28 03:32:00 PM PDT 24
Peak memory 241680 kb
Host smart-7258dcaf-6211-4e30-ad9c-2d0a0a88af35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305867436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.3305867436
Directory /workspace/15.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/15.otp_ctrl_stress_all.1141956805
Short name T938
Test name
Test status
Simulation time 5731942763 ps
CPU time 111.51 seconds
Started Mar 28 03:31:53 PM PDT 24
Finished Mar 28 03:33:47 PM PDT 24
Peak memory 248768 kb
Host smart-e2cf4335-487b-401d-903e-d6381f6ceb13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141956805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all
.1141956805
Directory /workspace/15.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.otp_ctrl_stress_all_with_rand_reset.2723384471
Short name T939
Test name
Test status
Simulation time 87035753541 ps
CPU time 1228.09 seconds
Started Mar 28 03:31:53 PM PDT 24
Finished Mar 28 03:52:24 PM PDT 24
Peak memory 291860 kb
Host smart-42cb58d9-9431-4ddf-a45d-2e909b855557
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723384471 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all_with_rand_reset.2723384471
Directory /workspace/15.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.otp_ctrl_test_access.3195356537
Short name T607
Test name
Test status
Simulation time 3133315539 ps
CPU time 23.29 seconds
Started Mar 28 03:31:54 PM PDT 24
Finished Mar 28 03:32:20 PM PDT 24
Peak memory 242076 kb
Host smart-020414da-0f35-4b30-b163-e6228a8f9568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195356537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.3195356537
Directory /workspace/15.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/150.otp_ctrl_init_fail.1703903148
Short name T758
Test name
Test status
Simulation time 222181941 ps
CPU time 3.35 seconds
Started Mar 28 03:34:40 PM PDT 24
Finished Mar 28 03:34:46 PM PDT 24
Peak memory 241664 kb
Host smart-f0337ace-bd53-4ae9-8dab-f08823f9918e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703903148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.1703903148
Directory /workspace/150.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/150.otp_ctrl_parallel_lc_esc.1690443064
Short name T719
Test name
Test status
Simulation time 2922856713 ps
CPU time 7.24 seconds
Started Mar 28 03:34:39 PM PDT 24
Finished Mar 28 03:34:47 PM PDT 24
Peak memory 241896 kb
Host smart-90628fbc-9585-41d1-adf0-a8de548e2481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690443064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.1690443064
Directory /workspace/150.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/151.otp_ctrl_init_fail.3358893405
Short name T937
Test name
Test status
Simulation time 214516389 ps
CPU time 4.22 seconds
Started Mar 28 03:34:36 PM PDT 24
Finished Mar 28 03:34:41 PM PDT 24
Peak memory 241976 kb
Host smart-a9a72641-a992-4217-a27a-ede065082a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358893405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.3358893405
Directory /workspace/151.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/151.otp_ctrl_parallel_lc_esc.3479071653
Short name T595
Test name
Test status
Simulation time 2457430922 ps
CPU time 8.2 seconds
Started Mar 28 03:34:41 PM PDT 24
Finished Mar 28 03:34:53 PM PDT 24
Peak memory 242072 kb
Host smart-91867f8c-a623-4312-8aec-da8496b702cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479071653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.3479071653
Directory /workspace/151.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/152.otp_ctrl_init_fail.755724767
Short name T883
Test name
Test status
Simulation time 2277126872 ps
CPU time 4.02 seconds
Started Mar 28 03:34:38 PM PDT 24
Finished Mar 28 03:34:43 PM PDT 24
Peak memory 242124 kb
Host smart-1181f424-4991-4d47-b96a-adf3267befc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755724767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.755724767
Directory /workspace/152.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/152.otp_ctrl_parallel_lc_esc.4147651919
Short name T917
Test name
Test status
Simulation time 972062247 ps
CPU time 24.37 seconds
Started Mar 28 03:34:37 PM PDT 24
Finished Mar 28 03:35:02 PM PDT 24
Peak memory 241532 kb
Host smart-fb09dbaf-1b7e-48ea-9d55-b9b1c6014790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147651919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.4147651919
Directory /workspace/152.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/153.otp_ctrl_init_fail.1257527046
Short name T21
Test name
Test status
Simulation time 124494910 ps
CPU time 3.72 seconds
Started Mar 28 03:34:42 PM PDT 24
Finished Mar 28 03:34:50 PM PDT 24
Peak memory 241112 kb
Host smart-6bd311e8-6266-4730-9628-91a1e1b051d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257527046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.1257527046
Directory /workspace/153.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/153.otp_ctrl_parallel_lc_esc.1234899258
Short name T591
Test name
Test status
Simulation time 604175122 ps
CPU time 5.75 seconds
Started Mar 28 03:34:38 PM PDT 24
Finished Mar 28 03:34:45 PM PDT 24
Peak memory 241756 kb
Host smart-6052ac21-7c95-453b-96ef-ea1bee1bf485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234899258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.1234899258
Directory /workspace/153.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/154.otp_ctrl_init_fail.1173015673
Short name T475
Test name
Test status
Simulation time 303531028 ps
CPU time 4.33 seconds
Started Mar 28 03:34:41 PM PDT 24
Finished Mar 28 03:34:50 PM PDT 24
Peak memory 241760 kb
Host smart-e35deccb-8dd4-45f6-b213-aa221b405f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173015673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.1173015673
Directory /workspace/154.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/154.otp_ctrl_parallel_lc_esc.1368115243
Short name T431
Test name
Test status
Simulation time 271040614 ps
CPU time 7.83 seconds
Started Mar 28 03:34:41 PM PDT 24
Finished Mar 28 03:34:54 PM PDT 24
Peak memory 241684 kb
Host smart-8650e7e8-0f5c-4dff-a104-cf0cbe5e9d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368115243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.1368115243
Directory /workspace/154.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/155.otp_ctrl_init_fail.1662669999
Short name T1143
Test name
Test status
Simulation time 284303786 ps
CPU time 4.32 seconds
Started Mar 28 03:34:37 PM PDT 24
Finished Mar 28 03:34:41 PM PDT 24
Peak memory 241736 kb
Host smart-a8fd3e37-441a-43c6-8547-280a945c2529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662669999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.1662669999
Directory /workspace/155.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/155.otp_ctrl_parallel_lc_esc.2441239305
Short name T148
Test name
Test status
Simulation time 382088459 ps
CPU time 8.82 seconds
Started Mar 28 03:34:42 PM PDT 24
Finished Mar 28 03:34:55 PM PDT 24
Peak memory 241628 kb
Host smart-5c0b36a6-f52d-4777-999c-4027bc3c4909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441239305 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.2441239305
Directory /workspace/155.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/156.otp_ctrl_init_fail.1018431742
Short name T995
Test name
Test status
Simulation time 171452938 ps
CPU time 4.33 seconds
Started Mar 28 03:34:40 PM PDT 24
Finished Mar 28 03:34:47 PM PDT 24
Peak memory 241096 kb
Host smart-d2c2fc05-09cf-4435-af6b-774f9d2bc6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018431742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.1018431742
Directory /workspace/156.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/157.otp_ctrl_init_fail.2564012079
Short name T962
Test name
Test status
Simulation time 275235675 ps
CPU time 4.47 seconds
Started Mar 28 03:34:36 PM PDT 24
Finished Mar 28 03:34:41 PM PDT 24
Peak memory 241812 kb
Host smart-9649a936-671d-488a-a266-559c05fdd0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564012079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.2564012079
Directory /workspace/157.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/157.otp_ctrl_parallel_lc_esc.2815360045
Short name T1052
Test name
Test status
Simulation time 284475491 ps
CPU time 4.22 seconds
Started Mar 28 03:34:39 PM PDT 24
Finished Mar 28 03:34:45 PM PDT 24
Peak memory 241744 kb
Host smart-f5b3606e-3777-4a9d-8283-cf76d341328f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815360045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.2815360045
Directory /workspace/157.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/158.otp_ctrl_init_fail.669015795
Short name T1051
Test name
Test status
Simulation time 266602394 ps
CPU time 3.92 seconds
Started Mar 28 03:34:39 PM PDT 24
Finished Mar 28 03:34:44 PM PDT 24
Peak memory 241416 kb
Host smart-8035111b-30e2-45cc-aef4-8df36827d607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669015795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.669015795
Directory /workspace/158.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/158.otp_ctrl_parallel_lc_esc.3641625136
Short name T909
Test name
Test status
Simulation time 537504140 ps
CPU time 16.04 seconds
Started Mar 28 03:34:40 PM PDT 24
Finished Mar 28 03:34:59 PM PDT 24
Peak memory 241604 kb
Host smart-1dc350af-0dd9-4f74-a618-64f35bf145dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641625136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.3641625136
Directory /workspace/158.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/159.otp_ctrl_init_fail.3059139319
Short name T874
Test name
Test status
Simulation time 265925688 ps
CPU time 3.95 seconds
Started Mar 28 03:34:37 PM PDT 24
Finished Mar 28 03:34:41 PM PDT 24
Peak memory 242012 kb
Host smart-ce2bfbe5-5b07-4733-82b8-f1ec1e15383a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059139319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.3059139319
Directory /workspace/159.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/159.otp_ctrl_parallel_lc_esc.4137971409
Short name T744
Test name
Test status
Simulation time 5143151173 ps
CPU time 8.73 seconds
Started Mar 28 03:34:42 PM PDT 24
Finished Mar 28 03:34:53 PM PDT 24
Peak memory 241816 kb
Host smart-f716d46e-5f82-480d-848f-75a48502bb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137971409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.4137971409
Directory /workspace/159.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_alert_test.164729555
Short name T712
Test name
Test status
Simulation time 723363427 ps
CPU time 2.03 seconds
Started Mar 28 03:31:53 PM PDT 24
Finished Mar 28 03:31:58 PM PDT 24
Peak memory 240296 kb
Host smart-547ee275-82a3-4312-b83a-f1d07c985977
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164729555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.164729555
Directory /workspace/16.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_errs.675700979
Short name T1032
Test name
Test status
Simulation time 1373505554 ps
CPU time 23 seconds
Started Mar 28 03:31:52 PM PDT 24
Finished Mar 28 03:32:17 PM PDT 24
Peak memory 241832 kb
Host smart-42f622ff-a9e5-49b7-a29f-59ab444eaea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675700979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.675700979
Directory /workspace/16.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_lock.2753433161
Short name T580
Test name
Test status
Simulation time 3814818797 ps
CPU time 39.32 seconds
Started Mar 28 03:31:52 PM PDT 24
Finished Mar 28 03:32:33 PM PDT 24
Peak memory 241780 kb
Host smart-95d8f9a5-7bad-4c1a-87c7-4b5aa9d48467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753433161 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.2753433161
Directory /workspace/16.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/16.otp_ctrl_init_fail.2701482336
Short name T708
Test name
Test status
Simulation time 202077618 ps
CPU time 3.6 seconds
Started Mar 28 03:31:54 PM PDT 24
Finished Mar 28 03:32:00 PM PDT 24
Peak memory 241752 kb
Host smart-8dd9a26d-ef45-4abb-bba1-c2b193fcd14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701482336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.2701482336
Directory /workspace/16.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_macro_errs.3775620229
Short name T340
Test name
Test status
Simulation time 1135151731 ps
CPU time 24.59 seconds
Started Mar 28 03:31:54 PM PDT 24
Finished Mar 28 03:32:21 PM PDT 24
Peak memory 242468 kb
Host smart-3ebfcdfd-3068-4389-a38d-7f3a106bf4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775620229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.3775620229
Directory /workspace/16.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_key_req.2373671839
Short name T1169
Test name
Test status
Simulation time 8409961349 ps
CPU time 31.01 seconds
Started Mar 28 03:31:57 PM PDT 24
Finished Mar 28 03:32:29 PM PDT 24
Peak memory 242676 kb
Host smart-b307606b-6fe6-4fcf-a96e-17044798b6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373671839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.2373671839
Directory /workspace/16.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_esc.2888537485
Short name T587
Test name
Test status
Simulation time 716606368 ps
CPU time 10.07 seconds
Started Mar 28 03:31:53 PM PDT 24
Finished Mar 28 03:32:05 PM PDT 24
Peak memory 241816 kb
Host smart-8613919d-6867-4b06-a89c-cf3b4d26df87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888537485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.2888537485
Directory /workspace/16.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_req.551799603
Short name T993
Test name
Test status
Simulation time 250344280 ps
CPU time 5.66 seconds
Started Mar 28 03:31:55 PM PDT 24
Finished Mar 28 03:32:02 PM PDT 24
Peak memory 241592 kb
Host smart-727b6630-f301-426e-8ba7-44898be1d36b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=551799603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_req.551799603
Directory /workspace/16.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_regwen.3393542137
Short name T393
Test name
Test status
Simulation time 2720550236 ps
CPU time 9.4 seconds
Started Mar 28 03:31:54 PM PDT 24
Finished Mar 28 03:32:05 PM PDT 24
Peak memory 241724 kb
Host smart-d18f016a-b0b3-44e3-af19-2e3d900d5c03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3393542137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.3393542137
Directory /workspace/16.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/16.otp_ctrl_smoke.2021241708
Short name T955
Test name
Test status
Simulation time 619884312 ps
CPU time 8.18 seconds
Started Mar 28 03:31:53 PM PDT 24
Finished Mar 28 03:32:03 PM PDT 24
Peak memory 242044 kb
Host smart-4b7d6f5d-6a90-4d84-867d-c685d6e328b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021241708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_smoke.2021241708
Directory /workspace/16.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all.3560025631
Short name T915
Test name
Test status
Simulation time 62968552708 ps
CPU time 107.84 seconds
Started Mar 28 03:31:57 PM PDT 24
Finished Mar 28 03:33:47 PM PDT 24
Peak memory 247520 kb
Host smart-7f843b34-42e9-4a8f-8fed-d4d56479a9c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560025631 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all
.3560025631
Directory /workspace/16.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.otp_ctrl_test_access.3978086599
Short name T226
Test name
Test status
Simulation time 14860793755 ps
CPU time 23.6 seconds
Started Mar 28 03:31:56 PM PDT 24
Finished Mar 28 03:32:21 PM PDT 24
Peak memory 243144 kb
Host smart-252d057e-299f-47f1-a9f3-1d55d83aad2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978086599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.3978086599
Directory /workspace/16.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/160.otp_ctrl_init_fail.3957842020
Short name T323
Test name
Test status
Simulation time 209319535 ps
CPU time 4.29 seconds
Started Mar 28 03:34:39 PM PDT 24
Finished Mar 28 03:34:44 PM PDT 24
Peak memory 241816 kb
Host smart-e8944c64-64f0-4ad5-bbdd-a8c5c20ab11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957842020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.3957842020
Directory /workspace/160.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/160.otp_ctrl_parallel_lc_esc.914330319
Short name T422
Test name
Test status
Simulation time 747741493 ps
CPU time 10.3 seconds
Started Mar 28 03:34:40 PM PDT 24
Finished Mar 28 03:34:53 PM PDT 24
Peak memory 241712 kb
Host smart-8942c0d7-89d4-44fd-81b3-a06a9f44724f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914330319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.914330319
Directory /workspace/160.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/161.otp_ctrl_init_fail.1476188058
Short name T1153
Test name
Test status
Simulation time 384939698 ps
CPU time 3.73 seconds
Started Mar 28 03:34:39 PM PDT 24
Finished Mar 28 03:34:44 PM PDT 24
Peak memory 241792 kb
Host smart-18c53c60-7478-4843-9e82-0dd13ddfef5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476188058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.1476188058
Directory /workspace/161.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/161.otp_ctrl_parallel_lc_esc.2912429204
Short name T936
Test name
Test status
Simulation time 435341261 ps
CPU time 4.99 seconds
Started Mar 28 03:34:39 PM PDT 24
Finished Mar 28 03:34:45 PM PDT 24
Peak memory 241704 kb
Host smart-fa469718-409e-425f-b5bf-190c5c15f1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912429204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.2912429204
Directory /workspace/161.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/162.otp_ctrl_init_fail.3341584772
Short name T1188
Test name
Test status
Simulation time 425176175 ps
CPU time 3.85 seconds
Started Mar 28 03:34:38 PM PDT 24
Finished Mar 28 03:34:43 PM PDT 24
Peak memory 242000 kb
Host smart-ad6700a3-d521-47ea-a2af-29d46c8e4254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341584772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.3341584772
Directory /workspace/162.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/162.otp_ctrl_parallel_lc_esc.3763345679
Short name T83
Test name
Test status
Simulation time 895740057 ps
CPU time 18.16 seconds
Started Mar 28 03:34:39 PM PDT 24
Finished Mar 28 03:34:58 PM PDT 24
Peak memory 241772 kb
Host smart-f34e32c3-cf43-4bbf-bdb5-ee8248ab27c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763345679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.3763345679
Directory /workspace/162.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/163.otp_ctrl_init_fail.2650344721
Short name T1007
Test name
Test status
Simulation time 348968887 ps
CPU time 4.47 seconds
Started Mar 28 03:34:42 PM PDT 24
Finished Mar 28 03:34:50 PM PDT 24
Peak memory 241684 kb
Host smart-71a480f6-7e10-44e6-beca-b05226a7ecf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650344721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.2650344721
Directory /workspace/163.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/164.otp_ctrl_init_fail.1918728672
Short name T260
Test name
Test status
Simulation time 196744229 ps
CPU time 4.49 seconds
Started Mar 28 03:34:41 PM PDT 24
Finished Mar 28 03:34:49 PM PDT 24
Peak memory 241644 kb
Host smart-a55c9bbb-2a12-4729-ba76-e2e8406623c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918728672 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.1918728672
Directory /workspace/164.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/164.otp_ctrl_parallel_lc_esc.4203553239
Short name T1062
Test name
Test status
Simulation time 3523982446 ps
CPU time 23.46 seconds
Started Mar 28 03:34:38 PM PDT 24
Finished Mar 28 03:35:01 PM PDT 24
Peak memory 241944 kb
Host smart-1f8fc70a-97e1-4e94-bdde-6b53abd2db69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203553239 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.4203553239
Directory /workspace/164.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/165.otp_ctrl_init_fail.2349489004
Short name T601
Test name
Test status
Simulation time 116477845 ps
CPU time 4.17 seconds
Started Mar 28 03:34:39 PM PDT 24
Finished Mar 28 03:34:44 PM PDT 24
Peak memory 241672 kb
Host smart-b3d60c8a-c269-4abf-96a7-4800eef39cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349489004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.2349489004
Directory /workspace/165.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/165.otp_ctrl_parallel_lc_esc.3112961561
Short name T973
Test name
Test status
Simulation time 189102743 ps
CPU time 4.61 seconds
Started Mar 28 03:34:37 PM PDT 24
Finished Mar 28 03:34:41 PM PDT 24
Peak memory 241968 kb
Host smart-80770c75-73bd-4620-84c5-af0095f6f63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112961561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.3112961561
Directory /workspace/165.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/166.otp_ctrl_parallel_lc_esc.3461089748
Short name T105
Test name
Test status
Simulation time 219693744 ps
CPU time 6.31 seconds
Started Mar 28 03:34:41 PM PDT 24
Finished Mar 28 03:34:51 PM PDT 24
Peak memory 241564 kb
Host smart-9f92bb57-e9b6-4293-b252-87311df1f8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461089748 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.3461089748
Directory /workspace/166.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/167.otp_ctrl_init_fail.294654809
Short name T805
Test name
Test status
Simulation time 153980178 ps
CPU time 5.69 seconds
Started Mar 28 03:34:40 PM PDT 24
Finished Mar 28 03:34:48 PM PDT 24
Peak memory 241624 kb
Host smart-3c51ffaa-5ac7-4942-84fa-14edc102a82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294654809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.294654809
Directory /workspace/167.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/167.otp_ctrl_parallel_lc_esc.1648893153
Short name T157
Test name
Test status
Simulation time 503852537 ps
CPU time 7.1 seconds
Started Mar 28 03:34:42 PM PDT 24
Finished Mar 28 03:34:53 PM PDT 24
Peak memory 241924 kb
Host smart-d6faa66a-0602-42e3-b9b0-695fe9167a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648893153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.1648893153
Directory /workspace/167.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/168.otp_ctrl_init_fail.4203031850
Short name T727
Test name
Test status
Simulation time 191868340 ps
CPU time 4.53 seconds
Started Mar 28 03:34:39 PM PDT 24
Finished Mar 28 03:34:45 PM PDT 24
Peak memory 241704 kb
Host smart-cf292283-5834-455c-8d44-9f3d435a944a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203031850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.4203031850
Directory /workspace/168.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/168.otp_ctrl_parallel_lc_esc.1448710648
Short name T485
Test name
Test status
Simulation time 263266942 ps
CPU time 3.37 seconds
Started Mar 28 03:34:39 PM PDT 24
Finished Mar 28 03:34:43 PM PDT 24
Peak memory 241744 kb
Host smart-fd834b0a-b67b-465e-af81-cbe63a30eeb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448710648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.1448710648
Directory /workspace/168.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/169.otp_ctrl_init_fail.492560389
Short name T1187
Test name
Test status
Simulation time 2517487326 ps
CPU time 5.2 seconds
Started Mar 28 03:34:39 PM PDT 24
Finished Mar 28 03:34:45 PM PDT 24
Peak memory 241868 kb
Host smart-c394df4d-f63b-4d82-b9f0-637c728ddbfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492560389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.492560389
Directory /workspace/169.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/169.otp_ctrl_parallel_lc_esc.2499718106
Short name T1041
Test name
Test status
Simulation time 1808822997 ps
CPU time 27.91 seconds
Started Mar 28 03:34:38 PM PDT 24
Finished Mar 28 03:35:06 PM PDT 24
Peak memory 241888 kb
Host smart-7c500cf0-b549-42ae-b561-b48dec09af03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499718106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.2499718106
Directory /workspace/169.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_alert_test.4123577466
Short name T866
Test name
Test status
Simulation time 217025168 ps
CPU time 2.3 seconds
Started Mar 28 03:32:00 PM PDT 24
Finished Mar 28 03:32:05 PM PDT 24
Peak memory 240160 kb
Host smart-1abf37c8-3e0d-48e0-8b3c-9ce43fa096b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123577466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.4123577466
Directory /workspace/17.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.otp_ctrl_check_fail.1511606685
Short name T567
Test name
Test status
Simulation time 40275908704 ps
CPU time 88.48 seconds
Started Mar 28 03:31:57 PM PDT 24
Finished Mar 28 03:33:27 PM PDT 24
Peak memory 243052 kb
Host smart-39da1be6-da40-4c50-a9db-7d5184a2315b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511606685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.1511606685
Directory /workspace/17.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_errs.1791109089
Short name T1050
Test name
Test status
Simulation time 2203566549 ps
CPU time 28.79 seconds
Started Mar 28 03:31:57 PM PDT 24
Finished Mar 28 03:32:27 PM PDT 24
Peak memory 242192 kb
Host smart-c3e7dc03-20fe-44c1-bc92-19b369746c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791109089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.1791109089
Directory /workspace/17.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_lock.1137973394
Short name T400
Test name
Test status
Simulation time 2690923373 ps
CPU time 17.07 seconds
Started Mar 28 03:31:59 PM PDT 24
Finished Mar 28 03:32:18 PM PDT 24
Peak memory 241764 kb
Host smart-14e10eb8-9ae8-44b0-a362-a94f3b610914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137973394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.1137973394
Directory /workspace/17.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/17.otp_ctrl_init_fail.3626946522
Short name T638
Test name
Test status
Simulation time 1453693413 ps
CPU time 4.61 seconds
Started Mar 28 03:31:57 PM PDT 24
Finished Mar 28 03:32:03 PM PDT 24
Peak memory 241988 kb
Host smart-a8a49738-51ce-4ee7-a37d-135a97269659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626946522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.3626946522
Directory /workspace/17.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_macro_errs.1475587859
Short name T865
Test name
Test status
Simulation time 2075656929 ps
CPU time 11.06 seconds
Started Mar 28 03:31:58 PM PDT 24
Finished Mar 28 03:32:10 PM PDT 24
Peak memory 241856 kb
Host smart-f3f7611d-bf5c-4100-8a94-1af78e8f052b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475587859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.1475587859
Directory /workspace/17.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_key_req.1563391464
Short name T663
Test name
Test status
Simulation time 655561137 ps
CPU time 27.04 seconds
Started Mar 28 03:31:55 PM PDT 24
Finished Mar 28 03:32:24 PM PDT 24
Peak memory 241724 kb
Host smart-2afe8d48-15e0-4962-af9f-14e511d257d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563391464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.1563391464
Directory /workspace/17.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_esc.1134587275
Short name T979
Test name
Test status
Simulation time 756835181 ps
CPU time 8.39 seconds
Started Mar 28 03:31:54 PM PDT 24
Finished Mar 28 03:32:04 PM PDT 24
Peak memory 242020 kb
Host smart-927f2c5e-bb3f-43d8-a51e-6a492ad3ea4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134587275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.1134587275
Directory /workspace/17.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_regwen.1062933374
Short name T397
Test name
Test status
Simulation time 238725853 ps
CPU time 5.4 seconds
Started Mar 28 03:31:56 PM PDT 24
Finished Mar 28 03:32:03 PM PDT 24
Peak memory 241744 kb
Host smart-34fd74c7-2d1e-47b7-9698-95957e48e86d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1062933374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.1062933374
Directory /workspace/17.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/17.otp_ctrl_smoke.398015976
Short name T444
Test name
Test status
Simulation time 139070576 ps
CPU time 5.74 seconds
Started Mar 28 03:31:53 PM PDT 24
Finished Mar 28 03:32:02 PM PDT 24
Peak memory 241808 kb
Host smart-f9af6a1c-707f-49c7-b662-a5868f111537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398015976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.398015976
Directory /workspace/17.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all_with_rand_reset.421558091
Short name T965
Test name
Test status
Simulation time 808743068754 ps
CPU time 1964.68 seconds
Started Mar 28 03:31:56 PM PDT 24
Finished Mar 28 04:04:42 PM PDT 24
Peak memory 280520 kb
Host smart-8404c3f9-db01-4b4d-b7e1-faf39115a3c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421558091 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all_with_rand_reset.421558091
Directory /workspace/17.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.otp_ctrl_init_fail.1609720635
Short name T1116
Test name
Test status
Simulation time 129634481 ps
CPU time 3.89 seconds
Started Mar 28 03:34:41 PM PDT 24
Finished Mar 28 03:34:48 PM PDT 24
Peak memory 241820 kb
Host smart-6b6192f6-10d9-4cfc-b310-37b2befecda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609720635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.1609720635
Directory /workspace/170.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/170.otp_ctrl_parallel_lc_esc.215626064
Short name T1120
Test name
Test status
Simulation time 337587624 ps
CPU time 8.88 seconds
Started Mar 28 03:34:40 PM PDT 24
Finished Mar 28 03:34:51 PM PDT 24
Peak memory 241760 kb
Host smart-b27dd72f-8120-4086-8e28-8d587ef568e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215626064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.215626064
Directory /workspace/170.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/171.otp_ctrl_parallel_lc_esc.2481549323
Short name T254
Test name
Test status
Simulation time 126530982 ps
CPU time 5.08 seconds
Started Mar 28 03:34:37 PM PDT 24
Finished Mar 28 03:34:42 PM PDT 24
Peak memory 241564 kb
Host smart-f296f71a-bad6-4811-aaff-bb4af1cb546a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481549323 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.2481549323
Directory /workspace/171.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/172.otp_ctrl_init_fail.3128566247
Short name T1036
Test name
Test status
Simulation time 241429336 ps
CPU time 4.7 seconds
Started Mar 28 03:34:42 PM PDT 24
Finished Mar 28 03:34:51 PM PDT 24
Peak memory 242112 kb
Host smart-8d8d6cfd-afdb-4143-853e-d373ce5ae450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128566247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.3128566247
Directory /workspace/172.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/172.otp_ctrl_parallel_lc_esc.566514576
Short name T266
Test name
Test status
Simulation time 433641949 ps
CPU time 10.44 seconds
Started Mar 28 03:34:39 PM PDT 24
Finished Mar 28 03:34:50 PM PDT 24
Peak memory 241660 kb
Host smart-2fd4fd49-9a59-402f-a9ef-0be362452e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566514576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.566514576
Directory /workspace/172.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/173.otp_ctrl_init_fail.4039264742
Short name T622
Test name
Test status
Simulation time 94691207 ps
CPU time 3.36 seconds
Started Mar 28 03:34:41 PM PDT 24
Finished Mar 28 03:34:48 PM PDT 24
Peak memory 241984 kb
Host smart-b9fabaf5-beda-48d2-9262-62905f15d60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039264742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.4039264742
Directory /workspace/173.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/173.otp_ctrl_parallel_lc_esc.3467403828
Short name T721
Test name
Test status
Simulation time 308103325 ps
CPU time 7.65 seconds
Started Mar 28 03:34:38 PM PDT 24
Finished Mar 28 03:34:45 PM PDT 24
Peak memory 241660 kb
Host smart-524dedef-f989-4410-b155-8a11eececa19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467403828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.3467403828
Directory /workspace/173.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/174.otp_ctrl_init_fail.750147699
Short name T20
Test name
Test status
Simulation time 290064821 ps
CPU time 3.35 seconds
Started Mar 28 03:34:39 PM PDT 24
Finished Mar 28 03:34:43 PM PDT 24
Peak memory 241824 kb
Host smart-a5429c27-4d12-407e-a21f-ab11e38a791b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750147699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.750147699
Directory /workspace/174.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/174.otp_ctrl_parallel_lc_esc.4172270076
Short name T214
Test name
Test status
Simulation time 199380703 ps
CPU time 7.5 seconds
Started Mar 28 03:34:40 PM PDT 24
Finished Mar 28 03:34:50 PM PDT 24
Peak memory 241164 kb
Host smart-0a2ac6da-207a-4d53-a760-617398e7f3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172270076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.4172270076
Directory /workspace/174.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/175.otp_ctrl_init_fail.1810254227
Short name T66
Test name
Test status
Simulation time 2382192697 ps
CPU time 5.58 seconds
Started Mar 28 03:34:40 PM PDT 24
Finished Mar 28 03:34:48 PM PDT 24
Peak memory 242136 kb
Host smart-8538056c-0f97-4b20-be64-bfe79d6b5c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810254227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.1810254227
Directory /workspace/175.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/175.otp_ctrl_parallel_lc_esc.2172473127
Short name T183
Test name
Test status
Simulation time 3755180961 ps
CPU time 12.61 seconds
Started Mar 28 03:34:41 PM PDT 24
Finished Mar 28 03:34:57 PM PDT 24
Peak memory 241948 kb
Host smart-28d941ea-a398-44b2-b181-ad6e53b2d49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172473127 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.2172473127
Directory /workspace/175.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/176.otp_ctrl_init_fail.3997138457
Short name T662
Test name
Test status
Simulation time 356491004 ps
CPU time 3.39 seconds
Started Mar 28 03:34:38 PM PDT 24
Finished Mar 28 03:34:43 PM PDT 24
Peak memory 242048 kb
Host smart-37fb2a09-eb59-4db3-b96d-8132f5a20e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997138457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.3997138457
Directory /workspace/176.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/176.otp_ctrl_parallel_lc_esc.4205024832
Short name T216
Test name
Test status
Simulation time 917722544 ps
CPU time 10.44 seconds
Started Mar 28 03:34:39 PM PDT 24
Finished Mar 28 03:34:52 PM PDT 24
Peak memory 241764 kb
Host smart-60b9047b-69f7-4de7-860b-89c217b73dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205024832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.4205024832
Directory /workspace/176.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/177.otp_ctrl_init_fail.3539498634
Short name T1162
Test name
Test status
Simulation time 200628913 ps
CPU time 4.24 seconds
Started Mar 28 03:34:38 PM PDT 24
Finished Mar 28 03:34:44 PM PDT 24
Peak memory 241664 kb
Host smart-30a8cc89-a011-484e-b82c-48c8c21caff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539498634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.3539498634
Directory /workspace/177.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/177.otp_ctrl_parallel_lc_esc.1949805081
Short name T958
Test name
Test status
Simulation time 355886364 ps
CPU time 6.29 seconds
Started Mar 28 03:34:39 PM PDT 24
Finished Mar 28 03:34:46 PM PDT 24
Peak memory 241704 kb
Host smart-fbb51eda-b0e5-4287-b477-baeb15af6404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949805081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.1949805081
Directory /workspace/177.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/178.otp_ctrl_init_fail.495329225
Short name T324
Test name
Test status
Simulation time 1611324669 ps
CPU time 4.38 seconds
Started Mar 28 03:34:40 PM PDT 24
Finished Mar 28 03:34:47 PM PDT 24
Peak memory 241952 kb
Host smart-044fee17-0bb9-4c22-a486-04ebbee0c35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495329225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.495329225
Directory /workspace/178.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/178.otp_ctrl_parallel_lc_esc.1120865661
Short name T543
Test name
Test status
Simulation time 708043781 ps
CPU time 16.04 seconds
Started Mar 28 03:34:42 PM PDT 24
Finished Mar 28 03:35:02 PM PDT 24
Peak memory 242072 kb
Host smart-c2f22268-4946-4f3e-8e36-4a549f528f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120865661 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.1120865661
Directory /workspace/178.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/179.otp_ctrl_init_fail.533970103
Short name T1078
Test name
Test status
Simulation time 108163880 ps
CPU time 3.45 seconds
Started Mar 28 03:34:40 PM PDT 24
Finished Mar 28 03:34:48 PM PDT 24
Peak memory 241676 kb
Host smart-6f399256-9755-4c94-939d-e282d2f12902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533970103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.533970103
Directory /workspace/179.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/179.otp_ctrl_parallel_lc_esc.2763469626
Short name T164
Test name
Test status
Simulation time 228333927 ps
CPU time 5.23 seconds
Started Mar 28 03:34:42 PM PDT 24
Finished Mar 28 03:34:51 PM PDT 24
Peak memory 241680 kb
Host smart-7cc8cbc6-ea17-40d7-8755-ae02b36fade5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763469626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.2763469626
Directory /workspace/179.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_alert_test.3275237251
Short name T754
Test name
Test status
Simulation time 177161228 ps
CPU time 1.88 seconds
Started Mar 28 03:31:57 PM PDT 24
Finished Mar 28 03:32:00 PM PDT 24
Peak memory 240108 kb
Host smart-57a86f22-c225-4491-8a0c-991f85e61344
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275237251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.3275237251
Directory /workspace/18.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.otp_ctrl_check_fail.1775462575
Short name T62
Test name
Test status
Simulation time 743336629 ps
CPU time 11.98 seconds
Started Mar 28 03:32:02 PM PDT 24
Finished Mar 28 03:32:15 PM PDT 24
Peak memory 241836 kb
Host smart-159f8ba4-ce99-4ced-a33c-0522080f8e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775462575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.1775462575
Directory /workspace/18.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_errs.1749735326
Short name T1071
Test name
Test status
Simulation time 1297863700 ps
CPU time 9.38 seconds
Started Mar 28 03:32:02 PM PDT 24
Finished Mar 28 03:32:12 PM PDT 24
Peak memory 241960 kb
Host smart-5debe9d2-e5f4-447e-ac28-ed2c9877744f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749735326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.1749735326
Directory /workspace/18.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_lock.2970916118
Short name T551
Test name
Test status
Simulation time 515025312 ps
CPU time 7.84 seconds
Started Mar 28 03:32:02 PM PDT 24
Finished Mar 28 03:32:11 PM PDT 24
Peak memory 242036 kb
Host smart-81269ae2-6ce4-47df-8a43-cb16d48e4686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970916118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.2970916118
Directory /workspace/18.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/18.otp_ctrl_init_fail.1927162575
Short name T906
Test name
Test status
Simulation time 1698323376 ps
CPU time 4.71 seconds
Started Mar 28 03:31:56 PM PDT 24
Finished Mar 28 03:32:02 PM PDT 24
Peak memory 241728 kb
Host smart-abdea6c6-eca6-400f-b13e-250350404373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927162575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.1927162575
Directory /workspace/18.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_macro_errs.685629121
Short name T428
Test name
Test status
Simulation time 591506828 ps
CPU time 9.13 seconds
Started Mar 28 03:31:59 PM PDT 24
Finished Mar 28 03:32:11 PM PDT 24
Peak memory 241784 kb
Host smart-a86e7aed-9c9c-4fa4-955e-75f64f6b6253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685629121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.685629121
Directory /workspace/18.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_key_req.3065365255
Short name T829
Test name
Test status
Simulation time 981449363 ps
CPU time 24.8 seconds
Started Mar 28 03:31:59 PM PDT 24
Finished Mar 28 03:32:26 PM PDT 24
Peak memory 242148 kb
Host smart-f812412e-80b0-458c-b189-14cafe9b0c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065365255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.3065365255
Directory /workspace/18.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_esc.542045682
Short name T181
Test name
Test status
Simulation time 404827514 ps
CPU time 3.11 seconds
Started Mar 28 03:31:56 PM PDT 24
Finished Mar 28 03:32:01 PM PDT 24
Peak memory 241692 kb
Host smart-5e35834b-8900-486f-b3a5-31844547d635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542045682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.542045682
Directory /workspace/18.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_req.3134154600
Short name T713
Test name
Test status
Simulation time 666469803 ps
CPU time 5.52 seconds
Started Mar 28 03:31:59 PM PDT 24
Finished Mar 28 03:32:07 PM PDT 24
Peak memory 241844 kb
Host smart-18d52bdd-f81b-45ab-8933-cf5464cea240
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3134154600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.3134154600
Directory /workspace/18.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_smoke.3439820731
Short name T457
Test name
Test status
Simulation time 3555987113 ps
CPU time 8.09 seconds
Started Mar 28 03:31:56 PM PDT 24
Finished Mar 28 03:32:06 PM PDT 24
Peak memory 241984 kb
Host smart-8e44a263-8675-419a-acd1-5dc537f53336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439820731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.3439820731
Directory /workspace/18.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all.1458770802
Short name T1101
Test name
Test status
Simulation time 9455385901 ps
CPU time 58.94 seconds
Started Mar 28 03:32:00 PM PDT 24
Finished Mar 28 03:33:00 PM PDT 24
Peak memory 242692 kb
Host smart-d267fbaf-ccb0-44e7-adb0-c4259434c4d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458770802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all
.1458770802
Directory /workspace/18.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all_with_rand_reset.454815692
Short name T624
Test name
Test status
Simulation time 116621413594 ps
CPU time 432.43 seconds
Started Mar 28 03:31:59 PM PDT 24
Finished Mar 28 03:39:14 PM PDT 24
Peak memory 278156 kb
Host smart-c7cd7f14-0c7c-4002-aff8-50fa7d319252
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454815692 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all_with_rand_reset.454815692
Directory /workspace/18.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.otp_ctrl_test_access.1550844175
Short name T992
Test name
Test status
Simulation time 1739022553 ps
CPU time 21.47 seconds
Started Mar 28 03:32:01 PM PDT 24
Finished Mar 28 03:32:24 PM PDT 24
Peak memory 241656 kb
Host smart-56f08a6a-3b3e-471e-ba6d-86296fe7fe20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550844175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.1550844175
Directory /workspace/18.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/180.otp_ctrl_parallel_lc_esc.3269896133
Short name T1097
Test name
Test status
Simulation time 436599995 ps
CPU time 6.16 seconds
Started Mar 28 03:34:42 PM PDT 24
Finished Mar 28 03:34:52 PM PDT 24
Peak memory 241616 kb
Host smart-9ae2fdfb-d4fd-402f-a01e-df465251e512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269896133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.3269896133
Directory /workspace/180.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/181.otp_ctrl_init_fail.3302610814
Short name T115
Test name
Test status
Simulation time 307066223 ps
CPU time 4.54 seconds
Started Mar 28 03:34:42 PM PDT 24
Finished Mar 28 03:34:50 PM PDT 24
Peak memory 241764 kb
Host smart-3680c929-622c-41e9-8112-46dd9f3452f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302610814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.3302610814
Directory /workspace/181.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/181.otp_ctrl_parallel_lc_esc.3560666846
Short name T903
Test name
Test status
Simulation time 3040249960 ps
CPU time 12.99 seconds
Started Mar 28 03:34:42 PM PDT 24
Finished Mar 28 03:34:59 PM PDT 24
Peak memory 241660 kb
Host smart-9e73f6c4-8427-4d6d-8b6d-811153c1df49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560666846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.3560666846
Directory /workspace/181.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/182.otp_ctrl_init_fail.847502368
Short name T1152
Test name
Test status
Simulation time 1580502518 ps
CPU time 4.53 seconds
Started Mar 28 03:34:51 PM PDT 24
Finished Mar 28 03:34:56 PM PDT 24
Peak memory 242016 kb
Host smart-92e45866-f594-430b-9eba-c8fa5ed131f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847502368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.847502368
Directory /workspace/182.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/182.otp_ctrl_parallel_lc_esc.3506528942
Short name T740
Test name
Test status
Simulation time 169134595 ps
CPU time 6.73 seconds
Started Mar 28 03:34:45 PM PDT 24
Finished Mar 28 03:34:53 PM PDT 24
Peak memory 241668 kb
Host smart-e5632407-1534-4ed6-ba7e-b3ee70e14aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506528942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.3506528942
Directory /workspace/182.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/183.otp_ctrl_init_fail.2871317944
Short name T854
Test name
Test status
Simulation time 171212184 ps
CPU time 4.42 seconds
Started Mar 28 03:34:44 PM PDT 24
Finished Mar 28 03:34:50 PM PDT 24
Peak memory 241696 kb
Host smart-39e2a2af-1cfc-42c4-bdc2-32b4fffe73b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871317944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.2871317944
Directory /workspace/183.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/183.otp_ctrl_parallel_lc_esc.4113384395
Short name T1092
Test name
Test status
Simulation time 516060349 ps
CPU time 7.35 seconds
Started Mar 28 03:34:44 PM PDT 24
Finished Mar 28 03:34:53 PM PDT 24
Peak memory 241592 kb
Host smart-4f7ca597-9c57-4faa-8444-141a020d87fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113384395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.4113384395
Directory /workspace/183.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/184.otp_ctrl_init_fail.416708133
Short name T606
Test name
Test status
Simulation time 372758269 ps
CPU time 4.34 seconds
Started Mar 28 03:34:44 PM PDT 24
Finished Mar 28 03:34:50 PM PDT 24
Peak memory 241792 kb
Host smart-5a1ae37f-0916-4e38-92d5-8308ea088f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416708133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.416708133
Directory /workspace/184.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/184.otp_ctrl_parallel_lc_esc.3921034747
Short name T659
Test name
Test status
Simulation time 2580263010 ps
CPU time 22.58 seconds
Started Mar 28 03:34:44 PM PDT 24
Finished Mar 28 03:35:09 PM PDT 24
Peak memory 241720 kb
Host smart-c6d4cfc4-cadb-4bfd-b206-0be02a1f69da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921034747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.3921034747
Directory /workspace/184.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/185.otp_ctrl_init_fail.3215818066
Short name T131
Test name
Test status
Simulation time 412001981 ps
CPU time 3.55 seconds
Started Mar 28 03:34:51 PM PDT 24
Finished Mar 28 03:34:55 PM PDT 24
Peak memory 241784 kb
Host smart-6b566045-77f1-4925-b684-9b19dbc683d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215818066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.3215818066
Directory /workspace/185.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/185.otp_ctrl_parallel_lc_esc.42514631
Short name T878
Test name
Test status
Simulation time 1010545456 ps
CPU time 14.42 seconds
Started Mar 28 03:34:37 PM PDT 24
Finished Mar 28 03:34:52 PM PDT 24
Peak memory 241640 kb
Host smart-abb7fa16-dd0e-41ce-8d0d-f6f42f8c4415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42514631 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.42514631
Directory /workspace/185.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/186.otp_ctrl_init_fail.3519852848
Short name T596
Test name
Test status
Simulation time 154323462 ps
CPU time 4.14 seconds
Started Mar 28 03:34:50 PM PDT 24
Finished Mar 28 03:34:56 PM PDT 24
Peak memory 241704 kb
Host smart-97f69925-884e-4264-9cf4-af60b05bb1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519852848 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.3519852848
Directory /workspace/186.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/186.otp_ctrl_parallel_lc_esc.4042113357
Short name T504
Test name
Test status
Simulation time 475364565 ps
CPU time 6.35 seconds
Started Mar 28 03:34:44 PM PDT 24
Finished Mar 28 03:34:52 PM PDT 24
Peak memory 241736 kb
Host smart-e7470ffc-fe75-4646-b9ff-c25526488bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042113357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.4042113357
Directory /workspace/186.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/187.otp_ctrl_init_fail.3742420677
Short name T1044
Test name
Test status
Simulation time 190397623 ps
CPU time 4.67 seconds
Started Mar 28 03:34:51 PM PDT 24
Finished Mar 28 03:34:56 PM PDT 24
Peak memory 241672 kb
Host smart-ccba9838-0444-49a7-950f-a0f53bc028bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742420677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.3742420677
Directory /workspace/187.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/187.otp_ctrl_parallel_lc_esc.261369352
Short name T914
Test name
Test status
Simulation time 1248435073 ps
CPU time 4.47 seconds
Started Mar 28 03:34:52 PM PDT 24
Finished Mar 28 03:34:57 PM PDT 24
Peak memory 241700 kb
Host smart-ba614787-7a6d-4e3f-a573-44260825d48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261369352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.261369352
Directory /workspace/187.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/188.otp_ctrl_init_fail.4281653395
Short name T880
Test name
Test status
Simulation time 574313304 ps
CPU time 4.81 seconds
Started Mar 28 03:34:41 PM PDT 24
Finished Mar 28 03:34:51 PM PDT 24
Peak memory 241796 kb
Host smart-cacbabd2-ffc4-416b-acd7-760589d9307e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281653395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.4281653395
Directory /workspace/188.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/188.otp_ctrl_parallel_lc_esc.3282313509
Short name T594
Test name
Test status
Simulation time 313070695 ps
CPU time 4.59 seconds
Started Mar 28 03:34:42 PM PDT 24
Finished Mar 28 03:34:49 PM PDT 24
Peak memory 241684 kb
Host smart-d0b56cf5-0b72-417d-8bd4-bac50a311d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282313509 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.3282313509
Directory /workspace/188.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/189.otp_ctrl_init_fail.2724411619
Short name T963
Test name
Test status
Simulation time 1677664125 ps
CPU time 5.71 seconds
Started Mar 28 03:34:50 PM PDT 24
Finished Mar 28 03:34:57 PM PDT 24
Peak memory 241640 kb
Host smart-58878524-6815-40c3-8be5-0aa60e66e0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724411619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.2724411619
Directory /workspace/189.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_alert_test.1766235426
Short name T442
Test name
Test status
Simulation time 169810739 ps
CPU time 1.73 seconds
Started Mar 28 03:31:56 PM PDT 24
Finished Mar 28 03:31:59 PM PDT 24
Peak memory 240304 kb
Host smart-66266909-53c1-4046-8e14-82a4c2c1a4e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766235426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.1766235426
Directory /workspace/19.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.otp_ctrl_check_fail.3476926840
Short name T421
Test name
Test status
Simulation time 753154504 ps
CPU time 7.99 seconds
Started Mar 28 03:32:00 PM PDT 24
Finished Mar 28 03:32:09 PM PDT 24
Peak memory 241832 kb
Host smart-2227c632-5b60-4cf5-9781-f28ed7562901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476926840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.3476926840
Directory /workspace/19.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_errs.3419087987
Short name T1151
Test name
Test status
Simulation time 295095763 ps
CPU time 17.69 seconds
Started Mar 28 03:32:03 PM PDT 24
Finished Mar 28 03:32:21 PM PDT 24
Peak memory 241772 kb
Host smart-e69310d5-e564-4ec6-adb6-68f73582db13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419087987 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.3419087987
Directory /workspace/19.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_lock.681112512
Short name T745
Test name
Test status
Simulation time 1040006043 ps
CPU time 22.44 seconds
Started Mar 28 03:32:00 PM PDT 24
Finished Mar 28 03:32:24 PM PDT 24
Peak memory 241612 kb
Host smart-ac668204-6e03-4a49-b3d7-2333505285f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681112512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.681112512
Directory /workspace/19.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/19.otp_ctrl_init_fail.2122290015
Short name T8
Test name
Test status
Simulation time 301194772 ps
CPU time 4.28 seconds
Started Mar 28 03:32:02 PM PDT 24
Finished Mar 28 03:32:07 PM PDT 24
Peak memory 241860 kb
Host smart-5978f309-f1a3-4aa6-85fc-2970394af54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122290015 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.2122290015
Directory /workspace/19.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_macro_errs.1269805155
Short name T225
Test name
Test status
Simulation time 3793412536 ps
CPU time 43.42 seconds
Started Mar 28 03:32:20 PM PDT 24
Finished Mar 28 03:33:04 PM PDT 24
Peak memory 241972 kb
Host smart-c0026e94-0d70-45cb-b047-badd0cd2da42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269805155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.1269805155
Directory /workspace/19.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_key_req.3104604277
Short name T420
Test name
Test status
Simulation time 433707170 ps
CPU time 5.32 seconds
Started Mar 28 03:31:55 PM PDT 24
Finished Mar 28 03:32:02 PM PDT 24
Peak memory 241652 kb
Host smart-742f1124-2483-4dd6-a86a-eeba30e57f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104604277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_key_req.3104604277
Directory /workspace/19.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_esc.608799159
Short name T483
Test name
Test status
Simulation time 788961339 ps
CPU time 18.12 seconds
Started Mar 28 03:32:00 PM PDT 24
Finished Mar 28 03:32:18 PM PDT 24
Peak memory 241584 kb
Host smart-43be9eb3-8426-4b98-ac36-23548b030813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608799159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.608799159
Directory /workspace/19.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_req.78906187
Short name T1093
Test name
Test status
Simulation time 971494226 ps
CPU time 7.97 seconds
Started Mar 28 03:31:57 PM PDT 24
Finished Mar 28 03:32:07 PM PDT 24
Peak memory 241896 kb
Host smart-ca2e89e0-eadb-4c43-a90f-cf9578d45498
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=78906187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_req.78906187
Directory /workspace/19.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_regwen.601436496
Short name T953
Test name
Test status
Simulation time 157275802 ps
CPU time 4.13 seconds
Started Mar 28 03:32:01 PM PDT 24
Finished Mar 28 03:32:07 PM PDT 24
Peak memory 241968 kb
Host smart-b6634e5a-ccab-4bd3-bcd1-4278f36eae01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=601436496 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.601436496
Directory /workspace/19.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/19.otp_ctrl_smoke.1054358776
Short name T1121
Test name
Test status
Simulation time 813165317 ps
CPU time 6.36 seconds
Started Mar 28 03:31:58 PM PDT 24
Finished Mar 28 03:32:05 PM PDT 24
Peak memory 241780 kb
Host smart-ab350067-566d-42ed-8e5e-e2daf2a7d01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054358776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.1054358776
Directory /workspace/19.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all_with_rand_reset.3177012305
Short name T304
Test name
Test status
Simulation time 111336140112 ps
CPU time 1254.8 seconds
Started Mar 28 03:32:01 PM PDT 24
Finished Mar 28 03:52:58 PM PDT 24
Peak memory 314628 kb
Host smart-a06416ac-724f-4559-8eea-5fdaae90a495
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177012305 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all_with_rand_reset.3177012305
Directory /workspace/19.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.otp_ctrl_test_access.1929009349
Short name T616
Test name
Test status
Simulation time 204232964 ps
CPU time 5.54 seconds
Started Mar 28 03:32:02 PM PDT 24
Finished Mar 28 03:32:08 PM PDT 24
Peak memory 241708 kb
Host smart-0c6131f5-3b52-43fd-b414-f40809539090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929009349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.1929009349
Directory /workspace/19.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/190.otp_ctrl_init_fail.1368891744
Short name T137
Test name
Test status
Simulation time 217919460 ps
CPU time 3.76 seconds
Started Mar 28 03:34:44 PM PDT 24
Finished Mar 28 03:34:50 PM PDT 24
Peak memory 241804 kb
Host smart-717c2aa7-633c-48cb-8fe9-4476153a317f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368891744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.1368891744
Directory /workspace/190.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/190.otp_ctrl_parallel_lc_esc.703371764
Short name T1171
Test name
Test status
Simulation time 799326693 ps
CPU time 9.83 seconds
Started Mar 28 03:34:44 PM PDT 24
Finished Mar 28 03:34:56 PM PDT 24
Peak memory 242088 kb
Host smart-eea2692f-3257-47da-b9bf-4970a9ec457e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703371764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.703371764
Directory /workspace/190.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/191.otp_ctrl_parallel_lc_esc.783056446
Short name T146
Test name
Test status
Simulation time 1021352423 ps
CPU time 7.75 seconds
Started Mar 28 03:34:51 PM PDT 24
Finished Mar 28 03:34:59 PM PDT 24
Peak memory 241792 kb
Host smart-03482453-9110-4200-bf8b-ce02486e7c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783056446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.783056446
Directory /workspace/191.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/192.otp_ctrl_init_fail.3566960956
Short name T669
Test name
Test status
Simulation time 653946973 ps
CPU time 4.19 seconds
Started Mar 28 03:34:38 PM PDT 24
Finished Mar 28 03:34:44 PM PDT 24
Peak memory 241796 kb
Host smart-3d7c7061-b78e-4c48-893e-74d725b527ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566960956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.3566960956
Directory /workspace/192.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/192.otp_ctrl_parallel_lc_esc.3001701521
Short name T497
Test name
Test status
Simulation time 743991143 ps
CPU time 13.58 seconds
Started Mar 28 03:34:50 PM PDT 24
Finished Mar 28 03:35:05 PM PDT 24
Peak memory 241508 kb
Host smart-61394c17-2483-4030-8117-52c512bfccbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001701521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.3001701521
Directory /workspace/192.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/193.otp_ctrl_init_fail.107045854
Short name T38
Test name
Test status
Simulation time 427045092 ps
CPU time 4.17 seconds
Started Mar 28 03:34:51 PM PDT 24
Finished Mar 28 03:34:56 PM PDT 24
Peak memory 242084 kb
Host smart-a3bde750-da5a-4262-9da2-211d77ac67ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107045854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.107045854
Directory /workspace/193.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/193.otp_ctrl_parallel_lc_esc.4065154878
Short name T694
Test name
Test status
Simulation time 310951862 ps
CPU time 10.36 seconds
Started Mar 28 03:34:49 PM PDT 24
Finished Mar 28 03:34:59 PM PDT 24
Peak memory 241676 kb
Host smart-cca92ba0-03a4-4917-8a89-bb78d7adecd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065154878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.4065154878
Directory /workspace/193.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/194.otp_ctrl_init_fail.1282126793
Short name T680
Test name
Test status
Simulation time 1716518100 ps
CPU time 6.89 seconds
Started Mar 28 03:34:49 PM PDT 24
Finished Mar 28 03:34:56 PM PDT 24
Peak memory 241756 kb
Host smart-6f356d0c-ea38-49d5-9325-8bcbfdcf8119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282126793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.1282126793
Directory /workspace/194.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/194.otp_ctrl_parallel_lc_esc.699483977
Short name T820
Test name
Test status
Simulation time 163543345 ps
CPU time 7.09 seconds
Started Mar 28 03:34:40 PM PDT 24
Finished Mar 28 03:34:50 PM PDT 24
Peak memory 241704 kb
Host smart-1a4734ed-2b0f-4af2-bda0-e2dc6094be07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699483977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.699483977
Directory /workspace/194.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/195.otp_ctrl_init_fail.3827334232
Short name T730
Test name
Test status
Simulation time 190943310 ps
CPU time 5.03 seconds
Started Mar 28 03:34:40 PM PDT 24
Finished Mar 28 03:34:48 PM PDT 24
Peak memory 241932 kb
Host smart-ef722f00-42a9-4ed4-bac9-d9f0f038c1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827334232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.3827334232
Directory /workspace/195.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/195.otp_ctrl_parallel_lc_esc.818889823
Short name T165
Test name
Test status
Simulation time 1436713631 ps
CPU time 23.38 seconds
Started Mar 28 03:34:41 PM PDT 24
Finished Mar 28 03:35:08 PM PDT 24
Peak memory 242068 kb
Host smart-9186ed78-6854-4e79-bff9-6d595126365d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818889823 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.818889823
Directory /workspace/195.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/196.otp_ctrl_init_fail.2126510866
Short name T459
Test name
Test status
Simulation time 228253860 ps
CPU time 4.49 seconds
Started Mar 28 03:34:44 PM PDT 24
Finished Mar 28 03:34:50 PM PDT 24
Peak memory 241748 kb
Host smart-18f846ef-fb41-4da9-8bdf-41b566a220ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126510866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.2126510866
Directory /workspace/196.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/196.otp_ctrl_parallel_lc_esc.2167980430
Short name T268
Test name
Test status
Simulation time 1837468388 ps
CPU time 16.39 seconds
Started Mar 28 03:34:54 PM PDT 24
Finished Mar 28 03:35:11 PM PDT 24
Peak memory 241628 kb
Host smart-b80b4afb-cb4f-47ef-a147-928a109695e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167980430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.2167980430
Directory /workspace/196.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/197.otp_ctrl_init_fail.236652958
Short name T970
Test name
Test status
Simulation time 235359135 ps
CPU time 3.66 seconds
Started Mar 28 03:34:54 PM PDT 24
Finished Mar 28 03:34:58 PM PDT 24
Peak memory 242044 kb
Host smart-706e6e50-ef55-496f-ba12-8659434afa12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236652958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.236652958
Directory /workspace/197.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/197.otp_ctrl_parallel_lc_esc.1469747850
Short name T322
Test name
Test status
Simulation time 250567651 ps
CPU time 5.13 seconds
Started Mar 28 03:35:10 PM PDT 24
Finished Mar 28 03:35:15 PM PDT 24
Peak memory 242044 kb
Host smart-9f8a4507-c567-4f6f-99e5-6cfc906a6ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469747850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.1469747850
Directory /workspace/197.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/198.otp_ctrl_init_fail.1721642973
Short name T968
Test name
Test status
Simulation time 281648648 ps
CPU time 3.48 seconds
Started Mar 28 03:34:51 PM PDT 24
Finished Mar 28 03:34:55 PM PDT 24
Peak memory 241732 kb
Host smart-6d1c9677-be64-45e4-b5b0-bd7c6007e99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721642973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.1721642973
Directory /workspace/198.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/198.otp_ctrl_parallel_lc_esc.1662928586
Short name T108
Test name
Test status
Simulation time 172278661 ps
CPU time 8.84 seconds
Started Mar 28 03:34:51 PM PDT 24
Finished Mar 28 03:35:01 PM PDT 24
Peak memory 241704 kb
Host smart-c4e42135-7bcd-41d4-a976-fa6cfc030f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662928586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.1662928586
Directory /workspace/198.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/199.otp_ctrl_init_fail.2483710012
Short name T493
Test name
Test status
Simulation time 157764653 ps
CPU time 3.44 seconds
Started Mar 28 03:34:52 PM PDT 24
Finished Mar 28 03:34:55 PM PDT 24
Peak memory 241696 kb
Host smart-91cfa46d-d660-4aac-b067-5751e7554e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483710012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.2483710012
Directory /workspace/199.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/199.otp_ctrl_parallel_lc_esc.450965293
Short name T802
Test name
Test status
Simulation time 295408015 ps
CPU time 6.87 seconds
Started Mar 28 03:34:55 PM PDT 24
Finished Mar 28 03:35:03 PM PDT 24
Peak memory 241456 kb
Host smart-b461f8c7-2139-436f-975a-e05f792ddaf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450965293 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.450965293
Directory /workspace/199.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_alert_test.836441415
Short name T464
Test name
Test status
Simulation time 63436694 ps
CPU time 1.97 seconds
Started Mar 28 03:31:09 PM PDT 24
Finished Mar 28 03:31:12 PM PDT 24
Peak memory 240040 kb
Host smart-2dbcdbaf-c54c-437e-a06a-7618f658c8a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836441415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.836441415
Directory /workspace/2.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.otp_ctrl_background_chks.3564294914
Short name T597
Test name
Test status
Simulation time 6774029891 ps
CPU time 11.51 seconds
Started Mar 28 03:30:59 PM PDT 24
Finished Mar 28 03:31:11 PM PDT 24
Peak memory 242348 kb
Host smart-32be60d3-8708-4506-89ad-0204ade32eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564294914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.3564294914
Directory /workspace/2.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/2.otp_ctrl_check_fail.3980448745
Short name T465
Test name
Test status
Simulation time 426535769 ps
CPU time 7.51 seconds
Started Mar 28 03:31:10 PM PDT 24
Finished Mar 28 03:31:18 PM PDT 24
Peak memory 242064 kb
Host smart-8a8512d8-d745-4880-8c65-4c230d5a8414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980448745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.3980448745
Directory /workspace/2.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_errs.755234799
Short name T175
Test name
Test status
Simulation time 1953375125 ps
CPU time 31.7 seconds
Started Mar 28 03:31:03 PM PDT 24
Finished Mar 28 03:31:35 PM PDT 24
Peak memory 241976 kb
Host smart-98ed86ac-8ed6-4a38-b79a-c79272ce8a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755234799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.755234799
Directory /workspace/2.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_lock.1612836713
Short name T984
Test name
Test status
Simulation time 3702305822 ps
CPU time 11.18 seconds
Started Mar 28 03:31:10 PM PDT 24
Finished Mar 28 03:31:21 PM PDT 24
Peak memory 242816 kb
Host smart-331f6e06-5ad4-4fa2-9f4e-7fe45b73968c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612836713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.1612836713
Directory /workspace/2.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/2.otp_ctrl_init_fail.579218582
Short name T206
Test name
Test status
Simulation time 205569346 ps
CPU time 3.91 seconds
Started Mar 28 03:31:03 PM PDT 24
Finished Mar 28 03:31:07 PM PDT 24
Peak memory 242004 kb
Host smart-f9ffafdf-b07e-4e6e-85b9-52f68f8becf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579218582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.579218582
Directory /workspace/2.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_macro_errs.2106133512
Short name T847
Test name
Test status
Simulation time 1912432240 ps
CPU time 28.91 seconds
Started Mar 28 03:31:02 PM PDT 24
Finished Mar 28 03:31:31 PM PDT 24
Peak memory 245292 kb
Host smart-723d9512-cef1-404c-b7a2-d21801e5a83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106133512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.2106133512
Directory /workspace/2.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_key_req.682825366
Short name T735
Test name
Test status
Simulation time 1254184747 ps
CPU time 18.11 seconds
Started Mar 28 03:31:02 PM PDT 24
Finished Mar 28 03:31:21 PM PDT 24
Peak memory 242040 kb
Host smart-fdf08107-0d08-487c-919e-b4951c294f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682825366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.682825366
Directory /workspace/2.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_esc.2848912173
Short name T162
Test name
Test status
Simulation time 263015036 ps
CPU time 10.12 seconds
Started Mar 28 03:30:57 PM PDT 24
Finished Mar 28 03:31:08 PM PDT 24
Peak memory 241580 kb
Host smart-2ba44c3b-f209-474b-a3ba-8844a94e64b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848912173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.2848912173
Directory /workspace/2.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_req.1769965060
Short name T929
Test name
Test status
Simulation time 292485388 ps
CPU time 5.81 seconds
Started Mar 28 03:31:42 PM PDT 24
Finished Mar 28 03:31:48 PM PDT 24
Peak memory 241968 kb
Host smart-e54b16ef-4a51-42f6-b908-88743d97183e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1769965060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.1769965060
Directory /workspace/2.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_regwen.3216764733
Short name T396
Test name
Test status
Simulation time 309232218 ps
CPU time 8.44 seconds
Started Mar 28 03:31:02 PM PDT 24
Finished Mar 28 03:31:11 PM PDT 24
Peak memory 241844 kb
Host smart-012a180c-c6a6-4e3b-b013-9852ed5824eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3216764733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.3216764733
Directory /workspace/2.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/2.otp_ctrl_sec_cm.2634650545
Short name T248
Test name
Test status
Simulation time 40198162189 ps
CPU time 207.65 seconds
Started Mar 28 03:31:10 PM PDT 24
Finished Mar 28 03:34:38 PM PDT 24
Peak memory 270664 kb
Host smart-b659a419-ed5b-4cde-933b-969cd491b40e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634650545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.2634650545
Directory /workspace/2.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.otp_ctrl_smoke.3956791155
Short name T835
Test name
Test status
Simulation time 3346819811 ps
CPU time 5.76 seconds
Started Mar 28 03:31:03 PM PDT 24
Finished Mar 28 03:31:09 PM PDT 24
Peak memory 241736 kb
Host smart-9dc5d4a0-e74d-4661-af61-7e70f8ed3d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956791155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.3956791155
Directory /workspace/2.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all.353800206
Short name T1148
Test name
Test status
Simulation time 21184913122 ps
CPU time 159.41 seconds
Started Mar 28 03:31:10 PM PDT 24
Finished Mar 28 03:33:49 PM PDT 24
Peak memory 248704 kb
Host smart-e700d4a0-e779-4239-8466-76fbb396ff8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353800206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all.353800206
Directory /workspace/2.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all_with_rand_reset.1969825576
Short name T692
Test name
Test status
Simulation time 27473438388 ps
CPU time 786.13 seconds
Started Mar 28 03:31:10 PM PDT 24
Finished Mar 28 03:44:16 PM PDT 24
Peak memory 265220 kb
Host smart-4b43ec3f-37e3-4282-a5d3-ccc2d99e8e2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969825576 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all_with_rand_reset.1969825576
Directory /workspace/2.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.otp_ctrl_test_access.2786887992
Short name T560
Test name
Test status
Simulation time 1027847331 ps
CPU time 11.13 seconds
Started Mar 28 03:31:10 PM PDT 24
Finished Mar 28 03:31:21 PM PDT 24
Peak memory 242056 kb
Host smart-3a196ad2-ce53-406f-b3e6-fc001079db8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786887992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.2786887992
Directory /workspace/2.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/20.otp_ctrl_alert_test.3974532418
Short name T959
Test name
Test status
Simulation time 93837252 ps
CPU time 2.16 seconds
Started Mar 28 03:32:17 PM PDT 24
Finished Mar 28 03:32:19 PM PDT 24
Peak memory 240048 kb
Host smart-11fd06be-b0e4-4285-a9b8-d9f70ee6613e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974532418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.3974532418
Directory /workspace/20.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.otp_ctrl_check_fail.1852786851
Short name T343
Test name
Test status
Simulation time 1538023007 ps
CPU time 12.98 seconds
Started Mar 28 03:32:13 PM PDT 24
Finished Mar 28 03:32:26 PM PDT 24
Peak memory 248636 kb
Host smart-f5d941a0-f421-410a-86e0-f8ed54756a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852786851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.1852786851
Directory /workspace/20.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_errs.3408462573
Short name T419
Test name
Test status
Simulation time 1600397701 ps
CPU time 50.39 seconds
Started Mar 28 03:31:58 PM PDT 24
Finished Mar 28 03:32:50 PM PDT 24
Peak memory 256588 kb
Host smart-c063848c-be10-4114-aba6-dcb14a7278fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408462573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.3408462573
Directory /workspace/20.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_lock.2367369565
Short name T1013
Test name
Test status
Simulation time 1208327052 ps
CPU time 27.06 seconds
Started Mar 28 03:31:59 PM PDT 24
Finished Mar 28 03:32:27 PM PDT 24
Peak memory 241680 kb
Host smart-12f125b8-8f14-4ac5-8976-af9d2da7265e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367369565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.2367369565
Directory /workspace/20.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/20.otp_ctrl_init_fail.2383412170
Short name T112
Test name
Test status
Simulation time 192329065 ps
CPU time 3.42 seconds
Started Mar 28 03:32:02 PM PDT 24
Finished Mar 28 03:32:06 PM PDT 24
Peak memory 241584 kb
Host smart-8d43d65d-c5bb-4a0e-ac85-69a35053601b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383412170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.2383412170
Directory /workspace/20.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_macro_errs.681897651
Short name T604
Test name
Test status
Simulation time 1710956846 ps
CPU time 12.93 seconds
Started Mar 28 03:32:19 PM PDT 24
Finished Mar 28 03:32:32 PM PDT 24
Peak memory 242096 kb
Host smart-dfbbeb32-4691-4757-8527-939d9a89e443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681897651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_macro_errs.681897651
Directory /workspace/20.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_key_req.2446594499
Short name T774
Test name
Test status
Simulation time 4362854179 ps
CPU time 33.17 seconds
Started Mar 28 03:32:14 PM PDT 24
Finished Mar 28 03:32:47 PM PDT 24
Peak memory 248540 kb
Host smart-e22c2385-e03d-45fc-88ca-4033ed5f6ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446594499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.2446594499
Directory /workspace/20.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_esc.385949519
Short name T1107
Test name
Test status
Simulation time 1226950942 ps
CPU time 27.92 seconds
Started Mar 28 03:31:54 PM PDT 24
Finished Mar 28 03:32:24 PM PDT 24
Peak memory 241596 kb
Host smart-3d572fe7-bd8c-47c7-a1e1-904bc637f50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385949519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.385949519
Directory /workspace/20.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_req.719570144
Short name T462
Test name
Test status
Simulation time 3230424194 ps
CPU time 10.01 seconds
Started Mar 28 03:31:56 PM PDT 24
Finished Mar 28 03:32:08 PM PDT 24
Peak memory 241580 kb
Host smart-9225c1da-3dcf-446e-bcbe-6942ef2a760b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=719570144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.719570144
Directory /workspace/20.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_regwen.1235938218
Short name T104
Test name
Test status
Simulation time 3924259713 ps
CPU time 11.93 seconds
Started Mar 28 03:32:17 PM PDT 24
Finished Mar 28 03:32:29 PM PDT 24
Peak memory 242088 kb
Host smart-5b8025cd-e5ba-484b-a2e8-759c15fa1cab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1235938218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.1235938218
Directory /workspace/20.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/20.otp_ctrl_smoke.612620995
Short name T186
Test name
Test status
Simulation time 7701730895 ps
CPU time 22.59 seconds
Started Mar 28 03:31:58 PM PDT 24
Finished Mar 28 03:32:21 PM PDT 24
Peak memory 242452 kb
Host smart-f534f8c1-7563-45ce-b901-7fd9f1c1f15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612620995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.612620995
Directory /workspace/20.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all.2294460374
Short name T72
Test name
Test status
Simulation time 5191201621 ps
CPU time 87.28 seconds
Started Mar 28 03:32:19 PM PDT 24
Finished Mar 28 03:33:46 PM PDT 24
Peak memory 245252 kb
Host smart-870de83f-8dd9-4756-8ac8-89045c32bf4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294460374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all
.2294460374
Directory /workspace/20.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all_with_rand_reset.4134152338
Short name T154
Test name
Test status
Simulation time 40022860407 ps
CPU time 1285.02 seconds
Started Mar 28 03:32:17 PM PDT 24
Finished Mar 28 03:53:42 PM PDT 24
Peak memory 332432 kb
Host smart-7124eee7-248a-4c97-9242-8b1fe89dc064
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134152338 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all_with_rand_reset.4134152338
Directory /workspace/20.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.otp_ctrl_test_access.535088523
Short name T770
Test name
Test status
Simulation time 4217180419 ps
CPU time 38.49 seconds
Started Mar 28 03:32:20 PM PDT 24
Finished Mar 28 03:32:59 PM PDT 24
Peak memory 242056 kb
Host smart-52a7d804-080f-4f7d-a3db-f595d559352c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535088523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.535088523
Directory /workspace/20.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/200.otp_ctrl_init_fail.4267992483
Short name T1069
Test name
Test status
Simulation time 169699573 ps
CPU time 3.94 seconds
Started Mar 28 03:34:54 PM PDT 24
Finished Mar 28 03:34:58 PM PDT 24
Peak memory 241804 kb
Host smart-87358c30-0f9e-4bcb-bf40-80a80045b0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267992483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.4267992483
Directory /workspace/200.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/201.otp_ctrl_init_fail.406662240
Short name T250
Test name
Test status
Simulation time 2186876835 ps
CPU time 5.73 seconds
Started Mar 28 03:34:53 PM PDT 24
Finished Mar 28 03:34:59 PM PDT 24
Peak memory 241776 kb
Host smart-38fbfbee-7409-4abd-98c1-3373d2174dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406662240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.406662240
Directory /workspace/201.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/202.otp_ctrl_init_fail.1306322361
Short name T750
Test name
Test status
Simulation time 535667791 ps
CPU time 3.82 seconds
Started Mar 28 03:34:54 PM PDT 24
Finished Mar 28 03:34:58 PM PDT 24
Peak memory 241796 kb
Host smart-33930927-5401-44fa-af23-3bf4160cf765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306322361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.1306322361
Directory /workspace/202.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/203.otp_ctrl_init_fail.1028396149
Short name T46
Test name
Test status
Simulation time 210061120 ps
CPU time 4.23 seconds
Started Mar 28 03:34:53 PM PDT 24
Finished Mar 28 03:34:57 PM PDT 24
Peak memory 241736 kb
Host smart-0655380f-acf3-4ed7-bc94-d80f8221c9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028396149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.1028396149
Directory /workspace/203.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/204.otp_ctrl_init_fail.632349238
Short name T964
Test name
Test status
Simulation time 141748038 ps
CPU time 3.72 seconds
Started Mar 28 03:34:56 PM PDT 24
Finished Mar 28 03:35:00 PM PDT 24
Peak memory 241600 kb
Host smart-ff497812-f8cb-4ae1-b478-165aa5791edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632349238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.632349238
Directory /workspace/204.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/206.otp_ctrl_init_fail.2062962013
Short name T1136
Test name
Test status
Simulation time 103871144 ps
CPU time 3.49 seconds
Started Mar 28 03:34:52 PM PDT 24
Finished Mar 28 03:34:56 PM PDT 24
Peak memory 241612 kb
Host smart-0e1a6993-73b6-4829-a598-b9a6e30bb3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062962013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.2062962013
Directory /workspace/206.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/207.otp_ctrl_init_fail.926650007
Short name T119
Test name
Test status
Simulation time 2143558728 ps
CPU time 5.86 seconds
Started Mar 28 03:34:55 PM PDT 24
Finished Mar 28 03:35:02 PM PDT 24
Peak memory 242068 kb
Host smart-5fac8968-1e64-4035-9a88-c3a18c9aa6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926650007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.926650007
Directory /workspace/207.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/208.otp_ctrl_init_fail.3372847166
Short name T37
Test name
Test status
Simulation time 312117409 ps
CPU time 5.26 seconds
Started Mar 28 03:34:57 PM PDT 24
Finished Mar 28 03:35:03 PM PDT 24
Peak memory 242020 kb
Host smart-29ed12eb-7ff9-41d2-9efb-b3e64d149f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372847166 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.3372847166
Directory /workspace/208.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/209.otp_ctrl_init_fail.2306005018
Short name T117
Test name
Test status
Simulation time 222382573 ps
CPU time 4.33 seconds
Started Mar 28 03:34:51 PM PDT 24
Finished Mar 28 03:34:56 PM PDT 24
Peak memory 241820 kb
Host smart-ac7d4183-5d3f-4ec0-bd56-d8d98f71d950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306005018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.2306005018
Directory /workspace/209.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_alert_test.871575679
Short name T106
Test name
Test status
Simulation time 81672589 ps
CPU time 2.11 seconds
Started Mar 28 03:32:18 PM PDT 24
Finished Mar 28 03:32:21 PM PDT 24
Peak memory 240132 kb
Host smart-ee5bd758-2cf8-4621-b5a7-fffc0d7e3c76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871575679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.871575679
Directory /workspace/21.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.otp_ctrl_check_fail.1189310694
Short name T673
Test name
Test status
Simulation time 2102869492 ps
CPU time 21.85 seconds
Started Mar 28 03:32:11 PM PDT 24
Finished Mar 28 03:32:33 PM PDT 24
Peak memory 242648 kb
Host smart-c91fcd45-131e-4af6-b022-f330d04f3763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189310694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.1189310694
Directory /workspace/21.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_errs.1954722529
Short name T1058
Test name
Test status
Simulation time 366453853 ps
CPU time 20.62 seconds
Started Mar 28 03:32:20 PM PDT 24
Finished Mar 28 03:32:41 PM PDT 24
Peak memory 241668 kb
Host smart-38d9b332-b70a-4f5e-ad96-3374abe5cd87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954722529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.1954722529
Directory /workspace/21.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_lock.525352970
Short name T347
Test name
Test status
Simulation time 263200583 ps
CPU time 9 seconds
Started Mar 28 03:32:16 PM PDT 24
Finished Mar 28 03:32:25 PM PDT 24
Peak memory 241968 kb
Host smart-2e214003-ff2d-482b-8c65-28b07af5dfc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525352970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.525352970
Directory /workspace/21.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/21.otp_ctrl_init_fail.966051852
Short name T1004
Test name
Test status
Simulation time 265868554 ps
CPU time 4.95 seconds
Started Mar 28 03:32:18 PM PDT 24
Finished Mar 28 03:32:23 PM PDT 24
Peak memory 241876 kb
Host smart-6d06cb07-240d-4596-9d29-1bdef83178a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966051852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.966051852
Directory /workspace/21.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_macro_errs.2730210721
Short name T817
Test name
Test status
Simulation time 3114195485 ps
CPU time 24.45 seconds
Started Mar 28 03:32:18 PM PDT 24
Finished Mar 28 03:32:43 PM PDT 24
Peak memory 242972 kb
Host smart-32e52fb6-2606-4989-b8d4-ac66ff705e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730210721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_macro_errs.2730210721
Directory /workspace/21.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_key_req.3846930554
Short name T952
Test name
Test status
Simulation time 1129760161 ps
CPU time 30.17 seconds
Started Mar 28 03:32:16 PM PDT 24
Finished Mar 28 03:32:47 PM PDT 24
Peak memory 242032 kb
Host smart-eeb82d36-39b6-4506-9684-b636ad7f6800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846930554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.3846930554
Directory /workspace/21.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_esc.12072600
Short name T1174
Test name
Test status
Simulation time 513095354 ps
CPU time 13.82 seconds
Started Mar 28 03:32:18 PM PDT 24
Finished Mar 28 03:32:31 PM PDT 24
Peak memory 241876 kb
Host smart-43c0a7dd-ca6a-49dd-8685-7166dbb03af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12072600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.12072600
Directory /workspace/21.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_req.3995068144
Short name T1123
Test name
Test status
Simulation time 994485010 ps
CPU time 17.14 seconds
Started Mar 28 03:32:16 PM PDT 24
Finished Mar 28 03:32:33 PM PDT 24
Peak memory 241888 kb
Host smart-562d504f-41de-4382-b23c-e8f0f65fba01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3995068144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_req.3995068144
Directory /workspace/21.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_regwen.1184260290
Short name T1130
Test name
Test status
Simulation time 537598092 ps
CPU time 6.83 seconds
Started Mar 28 03:32:18 PM PDT 24
Finished Mar 28 03:32:25 PM PDT 24
Peak memory 241668 kb
Host smart-514ac97d-1471-489e-a438-964e53087bbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1184260290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.1184260290
Directory /workspace/21.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/21.otp_ctrl_smoke.168917557
Short name T614
Test name
Test status
Simulation time 4784198929 ps
CPU time 15.92 seconds
Started Mar 28 03:32:16 PM PDT 24
Finished Mar 28 03:32:32 PM PDT 24
Peak memory 241780 kb
Host smart-42d290a2-4700-4831-963c-3e0808a4efdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168917557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.168917557
Directory /workspace/21.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all.1866276739
Short name T566
Test name
Test status
Simulation time 643411794 ps
CPU time 14.65 seconds
Started Mar 28 03:32:17 PM PDT 24
Finished Mar 28 03:32:32 PM PDT 24
Peak memory 241388 kb
Host smart-50a287de-71e8-4051-b6b5-c7e522eb8df3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866276739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all
.1866276739
Directory /workspace/21.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.otp_ctrl_test_access.3415551680
Short name T784
Test name
Test status
Simulation time 471493168 ps
CPU time 8.91 seconds
Started Mar 28 03:32:20 PM PDT 24
Finished Mar 28 03:32:29 PM PDT 24
Peak memory 241728 kb
Host smart-057dcf48-d4e0-45b9-bf9c-c3a9ee34a8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415551680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.3415551680
Directory /workspace/21.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/210.otp_ctrl_init_fail.1827126844
Short name T653
Test name
Test status
Simulation time 203309844 ps
CPU time 4.25 seconds
Started Mar 28 03:34:51 PM PDT 24
Finished Mar 28 03:34:56 PM PDT 24
Peak memory 241808 kb
Host smart-27c8b7c8-f3c8-4ebd-9741-e787ff43a059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827126844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.1827126844
Directory /workspace/210.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/211.otp_ctrl_init_fail.1387415528
Short name T592
Test name
Test status
Simulation time 403825166 ps
CPU time 4.63 seconds
Started Mar 28 03:34:52 PM PDT 24
Finished Mar 28 03:34:57 PM PDT 24
Peak memory 241924 kb
Host smart-0c6ba5c2-0265-45c9-b1ca-e410c4108d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387415528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.1387415528
Directory /workspace/211.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/212.otp_ctrl_init_fail.3626727639
Short name T834
Test name
Test status
Simulation time 299464324 ps
CPU time 4.21 seconds
Started Mar 28 03:34:54 PM PDT 24
Finished Mar 28 03:34:59 PM PDT 24
Peak memory 241784 kb
Host smart-8017494b-141a-4189-98cd-ca10858c49a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626727639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.3626727639
Directory /workspace/212.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/213.otp_ctrl_init_fail.3778469989
Short name T31
Test name
Test status
Simulation time 143107894 ps
CPU time 3.45 seconds
Started Mar 28 03:34:51 PM PDT 24
Finished Mar 28 03:34:55 PM PDT 24
Peak memory 241640 kb
Host smart-36817c30-af3e-41a3-b013-48c0d297e0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778469989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.3778469989
Directory /workspace/213.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/214.otp_ctrl_init_fail.845137753
Short name T807
Test name
Test status
Simulation time 355129253 ps
CPU time 4.97 seconds
Started Mar 28 03:34:52 PM PDT 24
Finished Mar 28 03:34:57 PM PDT 24
Peak memory 241796 kb
Host smart-573c8395-28f6-422b-990a-9784c366c8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845137753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.845137753
Directory /workspace/214.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/215.otp_ctrl_init_fail.547481948
Short name T1142
Test name
Test status
Simulation time 111602195 ps
CPU time 3.2 seconds
Started Mar 28 03:34:55 PM PDT 24
Finished Mar 28 03:34:59 PM PDT 24
Peak memory 242116 kb
Host smart-0e56c4e3-463b-4413-a2df-e13774893816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547481948 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.547481948
Directory /workspace/215.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/216.otp_ctrl_init_fail.1035968126
Short name T618
Test name
Test status
Simulation time 2166768026 ps
CPU time 7.32 seconds
Started Mar 28 03:34:56 PM PDT 24
Finished Mar 28 03:35:04 PM PDT 24
Peak memory 241888 kb
Host smart-656ab0e2-143c-401c-bcf1-e02be945b943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035968126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.1035968126
Directory /workspace/216.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/217.otp_ctrl_init_fail.1185346635
Short name T787
Test name
Test status
Simulation time 515459449 ps
CPU time 5.16 seconds
Started Mar 28 03:34:53 PM PDT 24
Finished Mar 28 03:34:58 PM PDT 24
Peak memory 241936 kb
Host smart-ba61e1ca-9822-4b45-b739-f6c3811e373a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185346635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.1185346635
Directory /workspace/217.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/218.otp_ctrl_init_fail.147218890
Short name T1056
Test name
Test status
Simulation time 364139114 ps
CPU time 3.23 seconds
Started Mar 28 03:34:53 PM PDT 24
Finished Mar 28 03:34:56 PM PDT 24
Peak memory 242008 kb
Host smart-6a6210b6-b173-4059-9a63-bbf07d8615b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147218890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.147218890
Directory /workspace/218.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/219.otp_ctrl_init_fail.186010296
Short name T471
Test name
Test status
Simulation time 133843653 ps
CPU time 3.94 seconds
Started Mar 28 03:34:51 PM PDT 24
Finished Mar 28 03:34:56 PM PDT 24
Peak memory 241700 kb
Host smart-86ff8f3c-bdd2-499c-bb61-ebff5fb2301d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186010296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.186010296
Directory /workspace/219.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_alert_test.2604860313
Short name T661
Test name
Test status
Simulation time 165414318 ps
CPU time 2.69 seconds
Started Mar 28 03:32:14 PM PDT 24
Finished Mar 28 03:32:17 PM PDT 24
Peak memory 240220 kb
Host smart-ce7d4584-73c8-4c88-8b56-f27e5e8f3d00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604860313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.2604860313
Directory /workspace/22.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.otp_ctrl_check_fail.2361273228
Short name T957
Test name
Test status
Simulation time 2269153088 ps
CPU time 7.85 seconds
Started Mar 28 03:32:17 PM PDT 24
Finished Mar 28 03:32:25 PM PDT 24
Peak memory 241800 kb
Host smart-59c8387f-e277-4e35-a4ea-7f580e79a0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361273228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.2361273228
Directory /workspace/22.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_errs.2534615381
Short name T364
Test name
Test status
Simulation time 342787723 ps
CPU time 19.25 seconds
Started Mar 28 03:32:18 PM PDT 24
Finished Mar 28 03:32:37 PM PDT 24
Peak memory 241816 kb
Host smart-46deb143-8499-412c-ae2b-c662c88ce2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534615381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.2534615381
Directory /workspace/22.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_lock.2488367731
Short name T637
Test name
Test status
Simulation time 1687006447 ps
CPU time 12.31 seconds
Started Mar 28 03:32:20 PM PDT 24
Finished Mar 28 03:32:32 PM PDT 24
Peak memory 241908 kb
Host smart-96e53cf2-b84d-4710-8a8c-ced5c65889a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488367731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.2488367731
Directory /workspace/22.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/22.otp_ctrl_init_fail.1428778196
Short name T815
Test name
Test status
Simulation time 112432932 ps
CPU time 3.83 seconds
Started Mar 28 03:32:17 PM PDT 24
Finished Mar 28 03:32:21 PM PDT 24
Peak memory 241660 kb
Host smart-bf749576-3e75-4385-bc19-979d31e846dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428778196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.1428778196
Directory /workspace/22.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_macro_errs.1237256592
Short name T170
Test name
Test status
Simulation time 207103780 ps
CPU time 6.91 seconds
Started Mar 28 03:32:22 PM PDT 24
Finished Mar 28 03:32:29 PM PDT 24
Peak memory 242240 kb
Host smart-a0c32f9e-d65e-47d9-bfc8-650222614aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237256592 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_macro_errs.1237256592
Directory /workspace/22.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_key_req.458681841
Short name T430
Test name
Test status
Simulation time 15609643490 ps
CPU time 39.55 seconds
Started Mar 28 03:32:19 PM PDT 24
Finished Mar 28 03:32:59 PM PDT 24
Peak memory 243236 kb
Host smart-7ae708ae-42f8-45c2-9610-5ad5cc02e933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458681841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.458681841
Directory /workspace/22.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_esc.1357371351
Short name T346
Test name
Test status
Simulation time 119395893 ps
CPU time 3.9 seconds
Started Mar 28 03:32:18 PM PDT 24
Finished Mar 28 03:32:22 PM PDT 24
Peak memory 241616 kb
Host smart-e4f5eca0-3d98-45a5-a479-0ec2479a5dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357371351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.1357371351
Directory /workspace/22.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_req.3962168404
Short name T630
Test name
Test status
Simulation time 12969252137 ps
CPU time 28.51 seconds
Started Mar 28 03:32:19 PM PDT 24
Finished Mar 28 03:32:47 PM PDT 24
Peak memory 241940 kb
Host smart-47b16fb4-0c15-4734-9a74-a74522669dd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3962168404 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_req.3962168404
Directory /workspace/22.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_regwen.2363441593
Short name T391
Test name
Test status
Simulation time 480620799 ps
CPU time 8.82 seconds
Started Mar 28 03:32:17 PM PDT 24
Finished Mar 28 03:32:26 PM PDT 24
Peak memory 241800 kb
Host smart-06b3c1ee-7ccc-41b9-bc59-e7967a4133e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2363441593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.2363441593
Directory /workspace/22.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/22.otp_ctrl_smoke.1519353265
Short name T513
Test name
Test status
Simulation time 479953790 ps
CPU time 4.52 seconds
Started Mar 28 03:32:15 PM PDT 24
Finished Mar 28 03:32:20 PM PDT 24
Peak memory 241956 kb
Host smart-60223010-bc74-44ee-bf35-fe0db2eab049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519353265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.1519353265
Directory /workspace/22.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all.306549258
Short name T123
Test name
Test status
Simulation time 6197374377 ps
CPU time 105.97 seconds
Started Mar 28 03:32:17 PM PDT 24
Finished Mar 28 03:34:03 PM PDT 24
Peak memory 246440 kb
Host smart-87faaccf-4e56-4e74-9d07-8d414b00d09d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306549258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all.
306549258
Directory /workspace/22.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.otp_ctrl_test_access.532600348
Short name T599
Test name
Test status
Simulation time 763175053 ps
CPU time 14.34 seconds
Started Mar 28 03:32:17 PM PDT 24
Finished Mar 28 03:32:32 PM PDT 24
Peak memory 241828 kb
Host smart-624f2f4a-6623-4192-8fb4-a2987ff7c51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532600348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.532600348
Directory /workspace/22.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/220.otp_ctrl_init_fail.3165624403
Short name T1183
Test name
Test status
Simulation time 383464853 ps
CPU time 3.84 seconds
Started Mar 28 03:34:52 PM PDT 24
Finished Mar 28 03:34:56 PM PDT 24
Peak memory 241784 kb
Host smart-2d06593d-366d-4a45-a083-a6ceb5de1c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165624403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.3165624403
Directory /workspace/220.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/221.otp_ctrl_init_fail.1276466834
Short name T818
Test name
Test status
Simulation time 131904358 ps
CPU time 3.82 seconds
Started Mar 28 03:34:52 PM PDT 24
Finished Mar 28 03:34:56 PM PDT 24
Peak memory 241844 kb
Host smart-dd5f2f83-cdad-4690-a77d-4010e36823e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276466834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.1276466834
Directory /workspace/221.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/222.otp_ctrl_init_fail.1158390154
Short name T1012
Test name
Test status
Simulation time 171237190 ps
CPU time 4.5 seconds
Started Mar 28 03:34:57 PM PDT 24
Finished Mar 28 03:35:03 PM PDT 24
Peak memory 241644 kb
Host smart-cd0aed96-86b0-4401-a782-0351e990297f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158390154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.1158390154
Directory /workspace/222.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/223.otp_ctrl_init_fail.1390991547
Short name T517
Test name
Test status
Simulation time 558060385 ps
CPU time 3.81 seconds
Started Mar 28 03:34:52 PM PDT 24
Finished Mar 28 03:34:56 PM PDT 24
Peak memory 242092 kb
Host smart-21859340-189d-4d57-989d-30699a80a933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390991547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.1390991547
Directory /workspace/223.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/224.otp_ctrl_init_fail.1388762157
Short name T693
Test name
Test status
Simulation time 125094472 ps
CPU time 3.83 seconds
Started Mar 28 03:34:56 PM PDT 24
Finished Mar 28 03:35:00 PM PDT 24
Peak memory 242008 kb
Host smart-789b6c01-d9cb-4cee-b7d0-1a2d917e9b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388762157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.1388762157
Directory /workspace/224.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/225.otp_ctrl_init_fail.1016118716
Short name T635
Test name
Test status
Simulation time 1730748061 ps
CPU time 4.8 seconds
Started Mar 28 03:34:51 PM PDT 24
Finished Mar 28 03:34:57 PM PDT 24
Peak memory 241748 kb
Host smart-d652f1dd-f78d-4eab-8720-dfff4eeb408f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016118716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.1016118716
Directory /workspace/225.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/226.otp_ctrl_init_fail.1649737739
Short name T990
Test name
Test status
Simulation time 227566980 ps
CPU time 4.63 seconds
Started Mar 28 03:34:54 PM PDT 24
Finished Mar 28 03:34:59 PM PDT 24
Peak memory 241748 kb
Host smart-3a267ffd-56b0-42e0-b06d-9d7004196d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649737739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.1649737739
Directory /workspace/226.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/227.otp_ctrl_init_fail.2552044951
Short name T488
Test name
Test status
Simulation time 301855303 ps
CPU time 4 seconds
Started Mar 28 03:34:53 PM PDT 24
Finished Mar 28 03:34:57 PM PDT 24
Peak memory 241780 kb
Host smart-fc5ed19c-2978-49b3-a11e-18678c9afc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552044951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.2552044951
Directory /workspace/227.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/228.otp_ctrl_init_fail.1244655853
Short name T219
Test name
Test status
Simulation time 441334322 ps
CPU time 3.7 seconds
Started Mar 28 03:34:55 PM PDT 24
Finished Mar 28 03:35:00 PM PDT 24
Peak memory 241932 kb
Host smart-852392e3-5b4b-49bd-928f-29ead837af53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244655853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.1244655853
Directory /workspace/228.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/229.otp_ctrl_init_fail.772016875
Short name T718
Test name
Test status
Simulation time 350017051 ps
CPU time 2.81 seconds
Started Mar 28 03:34:53 PM PDT 24
Finished Mar 28 03:34:56 PM PDT 24
Peak memory 241656 kb
Host smart-632e6035-d16d-428f-9737-1700eca64fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772016875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.772016875
Directory /workspace/229.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_alert_test.3508230135
Short name T716
Test name
Test status
Simulation time 44811404 ps
CPU time 1.56 seconds
Started Mar 28 03:32:17 PM PDT 24
Finished Mar 28 03:32:19 PM PDT 24
Peak memory 240060 kb
Host smart-1e69f789-b1c2-4193-ba54-c09184280fe7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508230135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.3508230135
Directory /workspace/23.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.otp_ctrl_check_fail.1665174968
Short name T40
Test name
Test status
Simulation time 3410724746 ps
CPU time 17.06 seconds
Started Mar 28 03:32:20 PM PDT 24
Finished Mar 28 03:32:37 PM PDT 24
Peak memory 242492 kb
Host smart-8ca6adf2-b3f1-4b8d-aed8-760dd91616d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665174968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.1665174968
Directory /workspace/23.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_errs.4076440122
Short name T194
Test name
Test status
Simulation time 781906801 ps
CPU time 21.65 seconds
Started Mar 28 03:32:22 PM PDT 24
Finished Mar 28 03:32:44 PM PDT 24
Peak memory 241580 kb
Host smart-6ece8756-af48-465a-b55b-f4a201c3fc74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076440122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.4076440122
Directory /workspace/23.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_lock.1457168457
Short name T697
Test name
Test status
Simulation time 5146593549 ps
CPU time 14.67 seconds
Started Mar 28 03:32:16 PM PDT 24
Finished Mar 28 03:32:31 PM PDT 24
Peak memory 242280 kb
Host smart-7073235d-62ee-4b5c-b6d9-183a559293c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457168457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.1457168457
Directory /workspace/23.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/23.otp_ctrl_init_fail.1254376988
Short name T198
Test name
Test status
Simulation time 430123632 ps
CPU time 4.89 seconds
Started Mar 28 03:32:18 PM PDT 24
Finished Mar 28 03:32:23 PM PDT 24
Peak memory 241648 kb
Host smart-1e1c08e8-d90e-499f-91b5-f2b4c34bd01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254376988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.1254376988
Directory /workspace/23.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_macro_errs.376790900
Short name T1105
Test name
Test status
Simulation time 5404581277 ps
CPU time 30.99 seconds
Started Mar 28 03:32:17 PM PDT 24
Finished Mar 28 03:32:49 PM PDT 24
Peak memory 249592 kb
Host smart-972964c4-54bd-4820-abe7-7fb429652db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376790900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.376790900
Directory /workspace/23.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_key_req.2382974582
Short name T187
Test name
Test status
Simulation time 1696008442 ps
CPU time 25.57 seconds
Started Mar 28 03:32:17 PM PDT 24
Finished Mar 28 03:32:43 PM PDT 24
Peak memory 242608 kb
Host smart-e28d413d-7f8c-4055-9750-78ed920bf188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382974582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.2382974582
Directory /workspace/23.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_esc.887379426
Short name T495
Test name
Test status
Simulation time 2555356970 ps
CPU time 8.3 seconds
Started Mar 28 03:32:19 PM PDT 24
Finished Mar 28 03:32:27 PM PDT 24
Peak memory 241956 kb
Host smart-df9ac7fe-e80d-4a21-a850-d01b1a2fb3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887379426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.887379426
Directory /workspace/23.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_req.4247015535
Short name T1085
Test name
Test status
Simulation time 1032410940 ps
CPU time 16.84 seconds
Started Mar 28 03:32:17 PM PDT 24
Finished Mar 28 03:32:34 PM PDT 24
Peak memory 241728 kb
Host smart-85b5507d-e534-47a2-8d6e-568faf992889
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4247015535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.4247015535
Directory /workspace/23.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_regwen.2982869394
Short name T816
Test name
Test status
Simulation time 902556587 ps
CPU time 7.86 seconds
Started Mar 28 03:32:15 PM PDT 24
Finished Mar 28 03:32:23 PM PDT 24
Peak memory 241704 kb
Host smart-bb94d33c-5719-4d8c-a348-dc70bbe0e06b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2982869394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.2982869394
Directory /workspace/23.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/23.otp_ctrl_smoke.4045837375
Short name T558
Test name
Test status
Simulation time 427176653 ps
CPU time 10.66 seconds
Started Mar 28 03:32:18 PM PDT 24
Finished Mar 28 03:32:29 PM PDT 24
Peak memory 241756 kb
Host smart-97852ac5-a417-4bbd-a9b9-91f56f466196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045837375 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.4045837375
Directory /workspace/23.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all.2742603261
Short name T1018
Test name
Test status
Simulation time 5101861694 ps
CPU time 64.6 seconds
Started Mar 28 03:32:18 PM PDT 24
Finished Mar 28 03:33:23 PM PDT 24
Peak memory 262848 kb
Host smart-194daf44-ce5b-4b25-9d01-e1c9413642b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742603261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all
.2742603261
Directory /workspace/23.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.otp_ctrl_test_access.2621665255
Short name T447
Test name
Test status
Simulation time 4780452826 ps
CPU time 27.38 seconds
Started Mar 28 03:32:19 PM PDT 24
Finished Mar 28 03:32:46 PM PDT 24
Peak memory 243440 kb
Host smart-92cfced1-41e7-4780-a6c9-065c6f82e7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621665255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_test_access.2621665255
Directory /workspace/23.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/230.otp_ctrl_init_fail.3894622768
Short name T197
Test name
Test status
Simulation time 272507399 ps
CPU time 4.15 seconds
Started Mar 28 03:34:52 PM PDT 24
Finished Mar 28 03:34:57 PM PDT 24
Peak memory 241708 kb
Host smart-4083c32f-d050-414a-8c93-a8b7680da0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894622768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.3894622768
Directory /workspace/230.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/231.otp_ctrl_init_fail.3593838138
Short name T537
Test name
Test status
Simulation time 242608647 ps
CPU time 4.64 seconds
Started Mar 28 03:34:56 PM PDT 24
Finished Mar 28 03:35:01 PM PDT 24
Peak memory 241604 kb
Host smart-4861f2d7-24a3-4402-b393-6a73bcd1daa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593838138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.3593838138
Directory /workspace/231.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/232.otp_ctrl_init_fail.4137706725
Short name T140
Test name
Test status
Simulation time 337333612 ps
CPU time 3.75 seconds
Started Mar 28 03:34:53 PM PDT 24
Finished Mar 28 03:34:57 PM PDT 24
Peak memory 241876 kb
Host smart-7729ae86-8190-4bb3-a04e-379b839748f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137706725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.4137706725
Directory /workspace/232.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/233.otp_ctrl_init_fail.3988981333
Short name T9
Test name
Test status
Simulation time 2120216435 ps
CPU time 5.69 seconds
Started Mar 28 03:34:57 PM PDT 24
Finished Mar 28 03:35:04 PM PDT 24
Peak memory 241784 kb
Host smart-f0e18a31-1191-49e6-8f62-c4dcbc3dc27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988981333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.3988981333
Directory /workspace/233.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/234.otp_ctrl_init_fail.364168207
Short name T924
Test name
Test status
Simulation time 315269225 ps
CPU time 4.18 seconds
Started Mar 28 03:34:52 PM PDT 24
Finished Mar 28 03:34:57 PM PDT 24
Peak memory 241696 kb
Host smart-24c83ebf-09ab-4f65-9ea8-6ba3747f2160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364168207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.364168207
Directory /workspace/234.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/235.otp_ctrl_init_fail.2710935282
Short name T574
Test name
Test status
Simulation time 260153376 ps
CPU time 4.39 seconds
Started Mar 28 03:34:56 PM PDT 24
Finished Mar 28 03:35:01 PM PDT 24
Peak memory 241772 kb
Host smart-2c9a41f9-bcc0-4348-b367-fffa90adeda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710935282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.2710935282
Directory /workspace/235.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/236.otp_ctrl_init_fail.2897247533
Short name T806
Test name
Test status
Simulation time 102343684 ps
CPU time 3.91 seconds
Started Mar 28 03:34:53 PM PDT 24
Finished Mar 28 03:34:57 PM PDT 24
Peak memory 241748 kb
Host smart-60a71e0d-2072-4986-b865-d8c6104ef197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897247533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.2897247533
Directory /workspace/236.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/237.otp_ctrl_init_fail.1311381519
Short name T44
Test name
Test status
Simulation time 244925663 ps
CPU time 5.11 seconds
Started Mar 28 03:34:55 PM PDT 24
Finished Mar 28 03:35:01 PM PDT 24
Peak memory 241856 kb
Host smart-84774a39-6ee2-4608-819b-5f900f322c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311381519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.1311381519
Directory /workspace/237.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/238.otp_ctrl_init_fail.1736186619
Short name T1134
Test name
Test status
Simulation time 467301260 ps
CPU time 3.83 seconds
Started Mar 28 03:34:53 PM PDT 24
Finished Mar 28 03:34:57 PM PDT 24
Peak memory 241656 kb
Host smart-26ddc845-59a9-4df5-acb0-fda086e8ce1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736186619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.1736186619
Directory /workspace/238.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/239.otp_ctrl_init_fail.688325292
Short name T53
Test name
Test status
Simulation time 125306597 ps
CPU time 3.31 seconds
Started Mar 28 03:34:54 PM PDT 24
Finished Mar 28 03:34:57 PM PDT 24
Peak memory 241772 kb
Host smart-8bb3d09d-0436-47b1-a8c7-93f6389eaa93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688325292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.688325292
Directory /workspace/239.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_alert_test.2299513998
Short name T585
Test name
Test status
Simulation time 114545534 ps
CPU time 2 seconds
Started Mar 28 03:32:19 PM PDT 24
Finished Mar 28 03:32:21 PM PDT 24
Peak memory 240080 kb
Host smart-b82a1246-956d-4dfd-923a-78705578ff27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299513998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.2299513998
Directory /workspace/24.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_errs.3806443262
Short name T1122
Test name
Test status
Simulation time 299107515 ps
CPU time 17.15 seconds
Started Mar 28 03:32:19 PM PDT 24
Finished Mar 28 03:32:36 PM PDT 24
Peak memory 242204 kb
Host smart-80a67344-7178-4413-8e6b-4e34bbcee39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806443262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.3806443262
Directory /workspace/24.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_lock.297598715
Short name T436
Test name
Test status
Simulation time 214747450 ps
CPU time 5.42 seconds
Started Mar 28 03:32:22 PM PDT 24
Finished Mar 28 03:32:28 PM PDT 24
Peak memory 241612 kb
Host smart-220d5526-6580-4b2b-a771-35bc73092da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297598715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.297598715
Directory /workspace/24.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/24.otp_ctrl_init_fail.2899297605
Short name T1019
Test name
Test status
Simulation time 222355498 ps
CPU time 4.57 seconds
Started Mar 28 03:32:20 PM PDT 24
Finished Mar 28 03:32:24 PM PDT 24
Peak memory 241960 kb
Host smart-11d3d697-78a9-48c8-b760-7ec389583848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899297605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.2899297605
Directory /workspace/24.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_macro_errs.3707318045
Short name T828
Test name
Test status
Simulation time 1944688836 ps
CPU time 39.16 seconds
Started Mar 28 03:32:18 PM PDT 24
Finished Mar 28 03:32:57 PM PDT 24
Peak memory 246804 kb
Host smart-89f9a8a7-5599-4321-a914-b18044e957bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707318045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.3707318045
Directory /workspace/24.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_key_req.2425854261
Short name T184
Test name
Test status
Simulation time 1654544143 ps
CPU time 9.78 seconds
Started Mar 28 03:32:20 PM PDT 24
Finished Mar 28 03:32:30 PM PDT 24
Peak memory 241708 kb
Host smart-62da2653-c243-4a74-9d56-b0f380d51102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425854261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.2425854261
Directory /workspace/24.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_esc.2187354538
Short name T1084
Test name
Test status
Simulation time 2698257194 ps
CPU time 11.11 seconds
Started Mar 28 03:32:16 PM PDT 24
Finished Mar 28 03:32:28 PM PDT 24
Peak memory 241680 kb
Host smart-18c22166-38ae-41b0-bd6d-a5d8d9ea37e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187354538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.2187354538
Directory /workspace/24.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_req.361558983
Short name T792
Test name
Test status
Simulation time 933650288 ps
CPU time 8.5 seconds
Started Mar 28 03:32:17 PM PDT 24
Finished Mar 28 03:32:26 PM PDT 24
Peak memory 241628 kb
Host smart-38a9d29c-0274-4293-b7f3-0671395ec6fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=361558983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.361558983
Directory /workspace/24.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_regwen.4138760155
Short name T612
Test name
Test status
Simulation time 279846469 ps
CPU time 8.01 seconds
Started Mar 28 03:32:18 PM PDT 24
Finished Mar 28 03:32:27 PM PDT 24
Peak memory 241784 kb
Host smart-e9cc5c2d-e13f-4215-900f-7b0a77ec0a22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4138760155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.4138760155
Directory /workspace/24.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/24.otp_ctrl_smoke.3427364334
Short name T412
Test name
Test status
Simulation time 1802058895 ps
CPU time 4.25 seconds
Started Mar 28 03:32:18 PM PDT 24
Finished Mar 28 03:32:23 PM PDT 24
Peak memory 242040 kb
Host smart-3b08eb65-05eb-409b-8acd-c76f210b81d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427364334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.3427364334
Directory /workspace/24.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/24.otp_ctrl_test_access.2450792951
Short name T507
Test name
Test status
Simulation time 17599006428 ps
CPU time 29.18 seconds
Started Mar 28 03:32:19 PM PDT 24
Finished Mar 28 03:32:48 PM PDT 24
Peak memory 242488 kb
Host smart-d4f96436-1407-4c19-ba15-c4104ee52def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450792951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_test_access.2450792951
Directory /workspace/24.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/240.otp_ctrl_init_fail.1848958308
Short name T1147
Test name
Test status
Simulation time 206271472 ps
CPU time 4.62 seconds
Started Mar 28 03:34:54 PM PDT 24
Finished Mar 28 03:34:59 PM PDT 24
Peak memory 242168 kb
Host smart-d7ede011-c9b6-4b28-8f55-6111dfe1157e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848958308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.1848958308
Directory /workspace/240.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/241.otp_ctrl_init_fail.294086658
Short name T199
Test name
Test status
Simulation time 487522543 ps
CPU time 4.6 seconds
Started Mar 28 03:34:52 PM PDT 24
Finished Mar 28 03:34:56 PM PDT 24
Peak memory 241776 kb
Host smart-c297dadf-95b1-4fdb-86b7-246131f819f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294086658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.294086658
Directory /workspace/241.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/242.otp_ctrl_init_fail.1259625838
Short name T977
Test name
Test status
Simulation time 154201358 ps
CPU time 4.07 seconds
Started Mar 28 03:34:54 PM PDT 24
Finished Mar 28 03:34:58 PM PDT 24
Peak memory 241776 kb
Host smart-8d3a5663-7f6d-4da2-a28f-495907d40812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259625838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.1259625838
Directory /workspace/242.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/243.otp_ctrl_init_fail.1841152223
Short name T258
Test name
Test status
Simulation time 697303032 ps
CPU time 5.27 seconds
Started Mar 28 03:34:52 PM PDT 24
Finished Mar 28 03:34:58 PM PDT 24
Peak memory 241740 kb
Host smart-c6ae7cf5-de8f-4983-8164-c0539805e351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841152223 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.1841152223
Directory /workspace/243.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/244.otp_ctrl_init_fail.3500602086
Short name T586
Test name
Test status
Simulation time 253138452 ps
CPU time 3.98 seconds
Started Mar 28 03:34:57 PM PDT 24
Finished Mar 28 03:35:02 PM PDT 24
Peak memory 241780 kb
Host smart-74030f75-0816-4ae7-9fc7-d3e028fe8cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500602086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.3500602086
Directory /workspace/244.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/245.otp_ctrl_init_fail.2758590576
Short name T235
Test name
Test status
Simulation time 461571549 ps
CPU time 3.82 seconds
Started Mar 28 03:35:10 PM PDT 24
Finished Mar 28 03:35:14 PM PDT 24
Peak memory 242112 kb
Host smart-5ffd7e76-53a3-4198-8833-65c797d81ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758590576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.2758590576
Directory /workspace/245.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/246.otp_ctrl_init_fail.546624536
Short name T617
Test name
Test status
Simulation time 222348122 ps
CPU time 5.17 seconds
Started Mar 28 03:35:09 PM PDT 24
Finished Mar 28 03:35:15 PM PDT 24
Peak memory 241748 kb
Host smart-e50fb0a5-a263-444a-9c16-aa220925ecfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546624536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.546624536
Directory /workspace/246.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/247.otp_ctrl_init_fail.2295291498
Short name T738
Test name
Test status
Simulation time 149569832 ps
CPU time 4.25 seconds
Started Mar 28 03:34:57 PM PDT 24
Finished Mar 28 03:35:02 PM PDT 24
Peak memory 241520 kb
Host smart-fcd8ae51-a426-4a0c-8833-c47ebebf9548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295291498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.2295291498
Directory /workspace/247.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/248.otp_ctrl_init_fail.519219346
Short name T36
Test name
Test status
Simulation time 389880307 ps
CPU time 4.83 seconds
Started Mar 28 03:34:56 PM PDT 24
Finished Mar 28 03:35:01 PM PDT 24
Peak memory 241620 kb
Host smart-55661d3c-a55d-44ee-8e38-4e9b417778f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519219346 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.519219346
Directory /workspace/248.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/249.otp_ctrl_init_fail.2380840546
Short name T1124
Test name
Test status
Simulation time 1631458888 ps
CPU time 5.04 seconds
Started Mar 28 03:34:57 PM PDT 24
Finished Mar 28 03:35:03 PM PDT 24
Peak memory 241820 kb
Host smart-1c4e7445-f814-4f98-8535-52fa1eb68544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380840546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.2380840546
Directory /workspace/249.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_alert_test.2890535743
Short name T1091
Test name
Test status
Simulation time 56757782 ps
CPU time 1.72 seconds
Started Mar 28 03:32:39 PM PDT 24
Finished Mar 28 03:32:41 PM PDT 24
Peak memory 239816 kb
Host smart-3f8089fc-d136-4aac-bc18-2855616e19cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890535743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.2890535743
Directory /workspace/25.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.otp_ctrl_check_fail.889111713
Short name T113
Test name
Test status
Simulation time 450151966 ps
CPU time 15.44 seconds
Started Mar 28 03:32:17 PM PDT 24
Finished Mar 28 03:32:33 PM PDT 24
Peak memory 242624 kb
Host smart-9d81019b-d60a-4e78-abd2-0efb980ad4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889111713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.889111713
Directory /workspace/25.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_errs.3591435323
Short name T907
Test name
Test status
Simulation time 972160059 ps
CPU time 16.68 seconds
Started Mar 28 03:32:19 PM PDT 24
Finished Mar 28 03:32:36 PM PDT 24
Peak memory 241820 kb
Host smart-85326e73-7947-4ef3-a3ca-7d5d0a02ab29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591435323 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_errs.3591435323
Directory /workspace/25.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_lock.1960042112
Short name T399
Test name
Test status
Simulation time 1125714356 ps
CPU time 17.2 seconds
Started Mar 28 03:32:18 PM PDT 24
Finished Mar 28 03:32:36 PM PDT 24
Peak memory 242016 kb
Host smart-c8462549-5183-4339-bcb9-d7ca6726dde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960042112 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.1960042112
Directory /workspace/25.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/25.otp_ctrl_macro_errs.2753888248
Short name T980
Test name
Test status
Simulation time 1135001662 ps
CPU time 24.03 seconds
Started Mar 28 03:32:18 PM PDT 24
Finished Mar 28 03:32:42 PM PDT 24
Peak memory 243368 kb
Host smart-bbc7b34b-6c88-4d88-9497-8fe01abdc552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753888248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.2753888248
Directory /workspace/25.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_key_req.3358275841
Short name T449
Test name
Test status
Simulation time 1310030605 ps
CPU time 14.58 seconds
Started Mar 28 03:32:17 PM PDT 24
Finished Mar 28 03:32:31 PM PDT 24
Peak memory 242204 kb
Host smart-eea8faf5-2d7c-4c96-95ec-2c0f2d643256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358275841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_key_req.3358275841
Directory /workspace/25.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_esc.219149815
Short name T1173
Test name
Test status
Simulation time 4180128351 ps
CPU time 20.82 seconds
Started Mar 28 03:32:18 PM PDT 24
Finished Mar 28 03:32:39 PM PDT 24
Peak memory 241780 kb
Host smart-935d83b9-f942-4d54-bdae-b096649dea13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219149815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.219149815
Directory /workspace/25.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_req.1447902776
Short name T881
Test name
Test status
Simulation time 572341153 ps
CPU time 10.72 seconds
Started Mar 28 03:32:18 PM PDT 24
Finished Mar 28 03:32:29 PM PDT 24
Peak memory 241624 kb
Host smart-5887754c-7994-4d3f-8f22-d1e48965a6f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1447902776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_req.1447902776
Directory /workspace/25.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_regwen.1999257703
Short name T1095
Test name
Test status
Simulation time 249527051 ps
CPU time 4.38 seconds
Started Mar 28 03:32:17 PM PDT 24
Finished Mar 28 03:32:21 PM PDT 24
Peak memory 241672 kb
Host smart-ec448bf6-4aea-419d-948e-beefc3e3c768
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1999257703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.1999257703
Directory /workspace/25.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/25.otp_ctrl_smoke.1876241719
Short name T753
Test name
Test status
Simulation time 273874649 ps
CPU time 6.25 seconds
Started Mar 28 03:32:21 PM PDT 24
Finished Mar 28 03:32:27 PM PDT 24
Peak memory 241928 kb
Host smart-230899ec-0392-4ba0-bb2c-130cf4b0e7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876241719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.1876241719
Directory /workspace/25.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all.2884805730
Short name T147
Test name
Test status
Simulation time 12323999144 ps
CPU time 195.37 seconds
Started Mar 28 03:32:37 PM PDT 24
Finished Mar 28 03:35:52 PM PDT 24
Peak memory 257904 kb
Host smart-9d3fd110-cea1-4f7a-be59-520fc5a45979
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884805730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all
.2884805730
Directory /workspace/25.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.otp_ctrl_test_access.1103090549
Short name T303
Test name
Test status
Simulation time 930830151 ps
CPU time 18.45 seconds
Started Mar 28 03:32:20 PM PDT 24
Finished Mar 28 03:32:39 PM PDT 24
Peak memory 241660 kb
Host smart-60812095-7fcd-46f3-b459-b5848fbc10fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103090549 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.1103090549
Directory /workspace/25.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/250.otp_ctrl_init_fail.174335828
Short name T535
Test name
Test status
Simulation time 2808703631 ps
CPU time 5.57 seconds
Started Mar 28 03:35:09 PM PDT 24
Finished Mar 28 03:35:15 PM PDT 24
Peak memory 241864 kb
Host smart-5042438f-6e1c-49dd-99e3-b8b41e79f765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174335828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.174335828
Directory /workspace/250.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/251.otp_ctrl_init_fail.2658764721
Short name T56
Test name
Test status
Simulation time 172939875 ps
CPU time 5.57 seconds
Started Mar 28 03:35:09 PM PDT 24
Finished Mar 28 03:35:16 PM PDT 24
Peak memory 241704 kb
Host smart-96359586-9b5c-45f4-8f75-6dcbf82951b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658764721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.2658764721
Directory /workspace/251.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/252.otp_ctrl_init_fail.79847522
Short name T492
Test name
Test status
Simulation time 151714575 ps
CPU time 3.33 seconds
Started Mar 28 03:34:54 PM PDT 24
Finished Mar 28 03:34:58 PM PDT 24
Peak memory 241792 kb
Host smart-8872a074-d47d-4314-b91f-d68969249bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79847522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.79847522
Directory /workspace/252.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/253.otp_ctrl_init_fail.3304486467
Short name T185
Test name
Test status
Simulation time 217655296 ps
CPU time 4.17 seconds
Started Mar 28 03:34:55 PM PDT 24
Finished Mar 28 03:35:00 PM PDT 24
Peak memory 242012 kb
Host smart-b52abd69-5e4b-443e-b786-8ffe4086f358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304486467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.3304486467
Directory /workspace/253.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/254.otp_ctrl_init_fail.3223894474
Short name T950
Test name
Test status
Simulation time 2259099176 ps
CPU time 6.98 seconds
Started Mar 28 03:34:56 PM PDT 24
Finished Mar 28 03:35:03 PM PDT 24
Peak memory 241880 kb
Host smart-71c35a6a-0a42-4522-a9e6-a63bc7aca906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223894474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.3223894474
Directory /workspace/254.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/255.otp_ctrl_init_fail.3607124976
Short name T236
Test name
Test status
Simulation time 170717480 ps
CPU time 4.56 seconds
Started Mar 28 03:35:09 PM PDT 24
Finished Mar 28 03:35:14 PM PDT 24
Peak memory 241800 kb
Host smart-53ee010d-f38c-45fe-9a74-975d445bd8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607124976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.3607124976
Directory /workspace/255.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/256.otp_ctrl_init_fail.3513724654
Short name T1070
Test name
Test status
Simulation time 2574872845 ps
CPU time 5.77 seconds
Started Mar 28 03:34:55 PM PDT 24
Finished Mar 28 03:35:02 PM PDT 24
Peak memory 242120 kb
Host smart-41ad888c-592a-46c4-a225-a7bb539e2e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513724654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.3513724654
Directory /workspace/256.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/257.otp_ctrl_init_fail.2996844483
Short name T647
Test name
Test status
Simulation time 430630059 ps
CPU time 4.23 seconds
Started Mar 28 03:35:09 PM PDT 24
Finished Mar 28 03:35:14 PM PDT 24
Peak memory 241916 kb
Host smart-136762f5-8e95-45b9-a2fa-f5c4016d7040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996844483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.2996844483
Directory /workspace/257.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/258.otp_ctrl_init_fail.3989624023
Short name T309
Test name
Test status
Simulation time 162545849 ps
CPU time 4.13 seconds
Started Mar 28 03:35:09 PM PDT 24
Finished Mar 28 03:35:13 PM PDT 24
Peak memory 241644 kb
Host smart-e10d8c5f-9fb2-4bee-87d0-99dc61e3bd2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989624023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.3989624023
Directory /workspace/258.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/259.otp_ctrl_init_fail.4109351023
Short name T1015
Test name
Test status
Simulation time 143371153 ps
CPU time 3.75 seconds
Started Mar 28 03:34:56 PM PDT 24
Finished Mar 28 03:35:00 PM PDT 24
Peak memory 241632 kb
Host smart-91261252-0b4f-4308-a8d8-c7280eea577e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109351023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.4109351023
Directory /workspace/259.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_alert_test.3080258926
Short name T417
Test name
Test status
Simulation time 50932302 ps
CPU time 1.57 seconds
Started Mar 28 03:32:37 PM PDT 24
Finished Mar 28 03:32:38 PM PDT 24
Peak memory 240028 kb
Host smart-fc97d4ff-3613-4ece-8da7-184cfe2a87e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080258926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.3080258926
Directory /workspace/26.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.otp_ctrl_check_fail.1674597052
Short name T1112
Test name
Test status
Simulation time 5089777179 ps
CPU time 34.49 seconds
Started Mar 28 03:32:34 PM PDT 24
Finished Mar 28 03:33:09 PM PDT 24
Peak memory 245696 kb
Host smart-e0f65c9e-6c87-4591-9d22-f3bdb4b3aa40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674597052 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.1674597052
Directory /workspace/26.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_errs.1456820334
Short name T844
Test name
Test status
Simulation time 588309286 ps
CPU time 17.38 seconds
Started Mar 28 03:32:38 PM PDT 24
Finished Mar 28 03:32:56 PM PDT 24
Peak memory 241764 kb
Host smart-ccb4eefa-0765-4c67-9141-9bf480931b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456820334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.1456820334
Directory /workspace/26.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_lock.581599147
Short name T1184
Test name
Test status
Simulation time 9683323260 ps
CPU time 17.22 seconds
Started Mar 28 03:32:36 PM PDT 24
Finished Mar 28 03:32:54 PM PDT 24
Peak memory 242996 kb
Host smart-9662acbb-0f33-49ee-ab80-4386fa8ea541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581599147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.581599147
Directory /workspace/26.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/26.otp_ctrl_init_fail.3948298493
Short name T667
Test name
Test status
Simulation time 312698191 ps
CPU time 3.74 seconds
Started Mar 28 03:32:36 PM PDT 24
Finished Mar 28 03:32:40 PM PDT 24
Peak memory 242076 kb
Host smart-b2f18570-3640-474a-bbfa-fc1844897a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948298493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.3948298493
Directory /workspace/26.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_macro_errs.3508090074
Short name T1079
Test name
Test status
Simulation time 2441498091 ps
CPU time 30.69 seconds
Started Mar 28 03:32:37 PM PDT 24
Finished Mar 28 03:33:08 PM PDT 24
Peak memory 248576 kb
Host smart-bbd52936-7f5f-4a13-8b3d-671ae42fd92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508090074 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.3508090074
Directory /workspace/26.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_key_req.1244341141
Short name T1132
Test name
Test status
Simulation time 951224832 ps
CPU time 18.33 seconds
Started Mar 28 03:32:40 PM PDT 24
Finished Mar 28 03:32:58 PM PDT 24
Peak memory 241896 kb
Host smart-19d98d9f-a4d7-44fc-9313-26a2c0cb6815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244341141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.1244341141
Directory /workspace/26.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_esc.4243571939
Short name T696
Test name
Test status
Simulation time 1383000061 ps
CPU time 9.36 seconds
Started Mar 28 03:32:35 PM PDT 24
Finished Mar 28 03:32:44 PM PDT 24
Peak memory 241892 kb
Host smart-2945d66e-2b4d-49fd-88e0-fe65208c33d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243571939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.4243571939
Directory /workspace/26.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_req.1140023957
Short name T503
Test name
Test status
Simulation time 347208367 ps
CPU time 14.89 seconds
Started Mar 28 03:32:40 PM PDT 24
Finished Mar 28 03:32:55 PM PDT 24
Peak memory 241968 kb
Host smart-f60d36fb-70d1-48df-8a3a-198ebcc29768
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1140023957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.1140023957
Directory /workspace/26.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_regwen.3230074654
Short name T383
Test name
Test status
Simulation time 688754488 ps
CPU time 7.29 seconds
Started Mar 28 03:32:38 PM PDT 24
Finished Mar 28 03:32:45 PM PDT 24
Peak memory 241848 kb
Host smart-c14ae92e-7a77-4653-9db6-11274a913328
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3230074654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.3230074654
Directory /workspace/26.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/26.otp_ctrl_smoke.710589312
Short name T500
Test name
Test status
Simulation time 185613959 ps
CPU time 6.21 seconds
Started Mar 28 03:32:35 PM PDT 24
Finished Mar 28 03:32:41 PM PDT 24
Peak memory 241668 kb
Host smart-e9cd68d6-3582-4aaa-be82-00a80126c19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710589312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.710589312
Directory /workspace/26.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all.3234378277
Short name T916
Test name
Test status
Simulation time 46351105724 ps
CPU time 161.38 seconds
Started Mar 28 03:32:44 PM PDT 24
Finished Mar 28 03:35:25 PM PDT 24
Peak memory 250792 kb
Host smart-550d4ca1-de5f-4f35-a9ab-2a050019f494
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234378277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all
.3234378277
Directory /workspace/26.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.otp_ctrl_test_access.2750369120
Short name T450
Test name
Test status
Simulation time 1860868079 ps
CPU time 21.98 seconds
Started Mar 28 03:32:38 PM PDT 24
Finished Mar 28 03:33:00 PM PDT 24
Peak memory 241820 kb
Host smart-71a0bb42-29eb-4fbd-a744-97eb51e46351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750369120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.2750369120
Directory /workspace/26.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/260.otp_ctrl_init_fail.2092808541
Short name T525
Test name
Test status
Simulation time 1923992352 ps
CPU time 4.87 seconds
Started Mar 28 03:34:56 PM PDT 24
Finished Mar 28 03:35:01 PM PDT 24
Peak memory 241728 kb
Host smart-cda108a7-46f9-4512-bb5e-4de798924f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092808541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.2092808541
Directory /workspace/260.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/261.otp_ctrl_init_fail.1777185284
Short name T196
Test name
Test status
Simulation time 269730563 ps
CPU time 4.74 seconds
Started Mar 28 03:34:57 PM PDT 24
Finished Mar 28 03:35:03 PM PDT 24
Peak memory 242052 kb
Host smart-3483b269-b830-4015-b890-e71efe6fbf9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777185284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.1777185284
Directory /workspace/261.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/262.otp_ctrl_init_fail.2947646418
Short name T797
Test name
Test status
Simulation time 165263121 ps
CPU time 4.46 seconds
Started Mar 28 03:34:57 PM PDT 24
Finished Mar 28 03:35:02 PM PDT 24
Peak memory 241876 kb
Host smart-e620c76c-6078-410f-bbd2-bd9d249b6378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947646418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.2947646418
Directory /workspace/262.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/263.otp_ctrl_init_fail.2197682
Short name T508
Test name
Test status
Simulation time 259743754 ps
CPU time 4.14 seconds
Started Mar 28 03:34:57 PM PDT 24
Finished Mar 28 03:35:02 PM PDT 24
Peak memory 242020 kb
Host smart-98d85e6d-2a80-43d5-b4d8-fd9351c9ce13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.2197682
Directory /workspace/263.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/264.otp_ctrl_init_fail.2481176670
Short name T541
Test name
Test status
Simulation time 127999875 ps
CPU time 3.82 seconds
Started Mar 28 03:34:57 PM PDT 24
Finished Mar 28 03:35:02 PM PDT 24
Peak memory 241684 kb
Host smart-09a4f442-78cd-469a-bd6e-f937f31cb676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481176670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.2481176670
Directory /workspace/264.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/265.otp_ctrl_init_fail.1551251247
Short name T714
Test name
Test status
Simulation time 448247632 ps
CPU time 4.1 seconds
Started Mar 28 03:34:57 PM PDT 24
Finished Mar 28 03:35:02 PM PDT 24
Peak memory 241648 kb
Host smart-119eb7aa-3669-41e5-ac28-dce0cbf8af0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551251247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.1551251247
Directory /workspace/265.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/266.otp_ctrl_init_fail.283750975
Short name T45
Test name
Test status
Simulation time 127079981 ps
CPU time 5.1 seconds
Started Mar 28 03:35:05 PM PDT 24
Finished Mar 28 03:35:10 PM PDT 24
Peak memory 241668 kb
Host smart-210acc9d-6ebd-492c-bbe8-38f8f8766cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283750975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.283750975
Directory /workspace/266.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/267.otp_ctrl_init_fail.1707952115
Short name T879
Test name
Test status
Simulation time 141854850 ps
CPU time 4.3 seconds
Started Mar 28 03:35:05 PM PDT 24
Finished Mar 28 03:35:09 PM PDT 24
Peak memory 241668 kb
Host smart-1acf6235-57a4-4a33-a808-ba9325939009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707952115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.1707952115
Directory /workspace/267.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/269.otp_ctrl_init_fail.1382428000
Short name T49
Test name
Test status
Simulation time 144323782 ps
CPU time 3.91 seconds
Started Mar 28 03:35:05 PM PDT 24
Finished Mar 28 03:35:09 PM PDT 24
Peak memory 241668 kb
Host smart-c89a1534-2f2e-4098-bf1c-0c3cf13b0128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382428000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.1382428000
Directory /workspace/269.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_alert_test.2061086874
Short name T858
Test name
Test status
Simulation time 753741838 ps
CPU time 2.57 seconds
Started Mar 28 03:32:38 PM PDT 24
Finished Mar 28 03:32:41 PM PDT 24
Peak memory 240040 kb
Host smart-ad400b6c-1a8a-433f-9d7a-c4b6d20f68ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061086874 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.2061086874
Directory /workspace/27.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_errs.2815637423
Short name T644
Test name
Test status
Simulation time 169120577 ps
CPU time 8.18 seconds
Started Mar 28 03:32:39 PM PDT 24
Finished Mar 28 03:32:47 PM PDT 24
Peak memory 241984 kb
Host smart-f943b0a0-3eb6-4e63-8cbd-1fb3a8e7f771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815637423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_errs.2815637423
Directory /workspace/27.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_lock.828123283
Short name T512
Test name
Test status
Simulation time 119279926 ps
CPU time 3.89 seconds
Started Mar 28 03:32:36 PM PDT 24
Finished Mar 28 03:32:40 PM PDT 24
Peak memory 241636 kb
Host smart-3d23a48f-63a8-4079-a5d0-986609fd4fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828123283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.828123283
Directory /workspace/27.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/27.otp_ctrl_init_fail.562745905
Short name T510
Test name
Test status
Simulation time 581016704 ps
CPU time 4.22 seconds
Started Mar 28 03:32:36 PM PDT 24
Finished Mar 28 03:32:40 PM PDT 24
Peak memory 241744 kb
Host smart-d172f973-e6a2-41ef-9a4f-9b718d7514e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562745905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.562745905
Directory /workspace/27.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_macro_errs.574591458
Short name T577
Test name
Test status
Simulation time 1630968731 ps
CPU time 17.88 seconds
Started Mar 28 03:32:36 PM PDT 24
Finished Mar 28 03:32:54 PM PDT 24
Peak memory 242224 kb
Host smart-8692bba5-c681-4005-9aa1-30e59d488620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574591458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.574591458
Directory /workspace/27.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_key_req.1649138087
Short name T923
Test name
Test status
Simulation time 667951088 ps
CPU time 24.47 seconds
Started Mar 28 03:32:37 PM PDT 24
Finished Mar 28 03:33:01 PM PDT 24
Peak memory 241516 kb
Host smart-33705c06-72c7-4029-b953-bc5c88c04d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649138087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.1649138087
Directory /workspace/27.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_esc.3616733986
Short name T445
Test name
Test status
Simulation time 326272031 ps
CPU time 19.64 seconds
Started Mar 28 03:32:41 PM PDT 24
Finished Mar 28 03:33:01 PM PDT 24
Peak memory 241608 kb
Host smart-a09bb9b8-7d7c-4ca7-9269-4735d428c8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616733986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.3616733986
Directory /workspace/27.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_req.1250724963
Short name T498
Test name
Test status
Simulation time 595687265 ps
CPU time 12.97 seconds
Started Mar 28 03:32:39 PM PDT 24
Finished Mar 28 03:32:53 PM PDT 24
Peak memory 241704 kb
Host smart-02cbfd62-b887-40a2-aa6c-3d96c128030f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1250724963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.1250724963
Directory /workspace/27.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_regwen.2809527031
Short name T943
Test name
Test status
Simulation time 850868032 ps
CPU time 8.98 seconds
Started Mar 28 03:32:36 PM PDT 24
Finished Mar 28 03:32:45 PM PDT 24
Peak memory 241984 kb
Host smart-db45f89e-bd8e-489f-b6ab-5eab2df1fb1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2809527031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.2809527031
Directory /workspace/27.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/27.otp_ctrl_smoke.2460042029
Short name T568
Test name
Test status
Simulation time 641772935 ps
CPU time 7.27 seconds
Started Mar 28 03:32:43 PM PDT 24
Finished Mar 28 03:32:50 PM PDT 24
Peak memory 241680 kb
Host smart-6db8a45c-8da0-400c-8e55-878b37dfa070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460042029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_smoke.2460042029
Directory /workspace/27.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all.695339930
Short name T408
Test name
Test status
Simulation time 30304619834 ps
CPU time 157.82 seconds
Started Mar 28 03:32:33 PM PDT 24
Finished Mar 28 03:35:11 PM PDT 24
Peak memory 245772 kb
Host smart-aec29a92-3004-4293-97b7-7ebe61247f8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695339930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all.
695339930
Directory /workspace/27.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all_with_rand_reset.1564760296
Short name T366
Test name
Test status
Simulation time 229918277285 ps
CPU time 1985.44 seconds
Started Mar 28 03:32:41 PM PDT 24
Finished Mar 28 04:05:47 PM PDT 24
Peak memory 555864 kb
Host smart-112cceb4-ca75-436d-8d55-bd0551628adc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564760296 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all_with_rand_reset.1564760296
Directory /workspace/27.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.otp_ctrl_test_access.3493823463
Short name T308
Test name
Test status
Simulation time 5626722436 ps
CPU time 60.25 seconds
Started Mar 28 03:32:36 PM PDT 24
Finished Mar 28 03:33:37 PM PDT 24
Peak memory 241804 kb
Host smart-8daedab1-846d-4b9e-a9a1-52410962f6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493823463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_test_access.3493823463
Directory /workspace/27.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/270.otp_ctrl_init_fail.2235746765
Short name T64
Test name
Test status
Simulation time 102438441 ps
CPU time 4.19 seconds
Started Mar 28 03:34:53 PM PDT 24
Finished Mar 28 03:34:57 PM PDT 24
Peak memory 241908 kb
Host smart-12718c5f-be1a-4bd0-9e74-40197c48f1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235746765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.2235746765
Directory /workspace/270.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/271.otp_ctrl_init_fail.120460745
Short name T434
Test name
Test status
Simulation time 89736588 ps
CPU time 2.79 seconds
Started Mar 28 03:35:05 PM PDT 24
Finished Mar 28 03:35:08 PM PDT 24
Peak memory 241912 kb
Host smart-82dea10e-7afa-4aca-b311-ebbe8e141f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120460745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.120460745
Directory /workspace/271.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/272.otp_ctrl_init_fail.971040116
Short name T935
Test name
Test status
Simulation time 1776519157 ps
CPU time 5.11 seconds
Started Mar 28 03:34:55 PM PDT 24
Finished Mar 28 03:35:01 PM PDT 24
Peak memory 241736 kb
Host smart-a8861f8c-bca4-4ca7-8567-394ba00faba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971040116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.971040116
Directory /workspace/272.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/273.otp_ctrl_init_fail.3370238757
Short name T892
Test name
Test status
Simulation time 261933888 ps
CPU time 3.63 seconds
Started Mar 28 03:35:05 PM PDT 24
Finished Mar 28 03:35:08 PM PDT 24
Peak memory 241704 kb
Host smart-156364bb-40cb-4a91-b923-bd2150ba3d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370238757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.3370238757
Directory /workspace/273.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/274.otp_ctrl_init_fail.323035909
Short name T222
Test name
Test status
Simulation time 117809963 ps
CPU time 3.93 seconds
Started Mar 28 03:34:56 PM PDT 24
Finished Mar 28 03:35:00 PM PDT 24
Peak memory 241680 kb
Host smart-6284705d-74e7-44d3-84e9-66ec1fd95a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323035909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.323035909
Directory /workspace/274.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/275.otp_ctrl_init_fail.2606366516
Short name T975
Test name
Test status
Simulation time 226624089 ps
CPU time 4.57 seconds
Started Mar 28 03:34:57 PM PDT 24
Finished Mar 28 03:35:03 PM PDT 24
Peak memory 241824 kb
Host smart-644c1297-8c60-4db3-b694-380152dc10c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606366516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.2606366516
Directory /workspace/275.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/276.otp_ctrl_init_fail.3852264130
Short name T934
Test name
Test status
Simulation time 583994102 ps
CPU time 5.59 seconds
Started Mar 28 03:35:28 PM PDT 24
Finished Mar 28 03:35:35 PM PDT 24
Peak memory 242172 kb
Host smart-61d4b8be-5b5f-4869-aa54-fee09b3560f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852264130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.3852264130
Directory /workspace/276.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/277.otp_ctrl_init_fail.1156010373
Short name T547
Test name
Test status
Simulation time 137791321 ps
CPU time 3.67 seconds
Started Mar 28 03:35:22 PM PDT 24
Finished Mar 28 03:35:26 PM PDT 24
Peak memory 242072 kb
Host smart-e2ce0edd-26b8-4617-8d1d-9baebee11238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156010373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.1156010373
Directory /workspace/277.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/278.otp_ctrl_init_fail.889927331
Short name T477
Test name
Test status
Simulation time 152678438 ps
CPU time 4.32 seconds
Started Mar 28 03:35:29 PM PDT 24
Finished Mar 28 03:35:34 PM PDT 24
Peak memory 241996 kb
Host smart-ad38545e-61e1-425c-868d-983783ae903b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889927331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.889927331
Directory /workspace/278.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/279.otp_ctrl_init_fail.2258953990
Short name T1030
Test name
Test status
Simulation time 1969679274 ps
CPU time 4.52 seconds
Started Mar 28 03:35:23 PM PDT 24
Finished Mar 28 03:35:28 PM PDT 24
Peak memory 241736 kb
Host smart-06fc368e-8b9c-431e-ad37-6b38f893fde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258953990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.2258953990
Directory /workspace/279.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_alert_test.3097900911
Short name T414
Test name
Test status
Simulation time 242747604 ps
CPU time 2.69 seconds
Started Mar 28 03:32:37 PM PDT 24
Finished Mar 28 03:32:40 PM PDT 24
Peak memory 239716 kb
Host smart-9a8c8509-7ef9-449d-bd3f-e6cbd3256a18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097900911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.3097900911
Directory /workspace/28.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.otp_ctrl_check_fail.1845757736
Short name T581
Test name
Test status
Simulation time 698336436 ps
CPU time 5.69 seconds
Started Mar 28 03:32:35 PM PDT 24
Finished Mar 28 03:32:41 PM PDT 24
Peak memory 242032 kb
Host smart-d340a454-1186-4889-a9e6-cffaa7731b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845757736 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.1845757736
Directory /workspace/28.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_errs.3624329957
Short name T243
Test name
Test status
Simulation time 665995957 ps
CPU time 18.14 seconds
Started Mar 28 03:32:39 PM PDT 24
Finished Mar 28 03:32:58 PM PDT 24
Peak memory 242220 kb
Host smart-bf34f060-9333-42c0-9a5b-fecebe263712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624329957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.3624329957
Directory /workspace/28.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_lock.4148815330
Short name T482
Test name
Test status
Simulation time 1850857374 ps
CPU time 20.88 seconds
Started Mar 28 03:32:36 PM PDT 24
Finished Mar 28 03:32:57 PM PDT 24
Peak memory 242004 kb
Host smart-b2340cae-5223-4c79-a652-1a95960efdd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148815330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.4148815330
Directory /workspace/28.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/28.otp_ctrl_init_fail.2768910470
Short name T532
Test name
Test status
Simulation time 172401638 ps
CPU time 3.76 seconds
Started Mar 28 03:32:41 PM PDT 24
Finished Mar 28 03:32:45 PM PDT 24
Peak memory 241756 kb
Host smart-beb2cd4e-14dd-4909-a342-e133f056cb63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768910470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.2768910470
Directory /workspace/28.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_macro_errs.3787703127
Short name T86
Test name
Test status
Simulation time 2755096694 ps
CPU time 17.37 seconds
Started Mar 28 03:32:37 PM PDT 24
Finished Mar 28 03:32:54 PM PDT 24
Peak memory 242972 kb
Host smart-f7016666-2a56-4622-9d33-8962b948772d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787703127 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.3787703127
Directory /workspace/28.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_key_req.1140836291
Short name T92
Test name
Test status
Simulation time 5938318038 ps
CPU time 42.22 seconds
Started Mar 28 03:32:36 PM PDT 24
Finished Mar 28 03:33:18 PM PDT 24
Peak memory 242060 kb
Host smart-153849aa-61f3-4da1-95cd-6ddd516f0d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140836291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.1140836291
Directory /workspace/28.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_esc.2569864429
Short name T776
Test name
Test status
Simulation time 495571253 ps
CPU time 6.7 seconds
Started Mar 28 03:32:38 PM PDT 24
Finished Mar 28 03:32:45 PM PDT 24
Peak memory 241828 kb
Host smart-4d7bed06-39ea-4897-a466-ecbebec49908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569864429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.2569864429
Directory /workspace/28.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_req.3166593759
Short name T451
Test name
Test status
Simulation time 1714484885 ps
CPU time 23.14 seconds
Started Mar 28 03:32:40 PM PDT 24
Finished Mar 28 03:33:03 PM PDT 24
Peak memory 241960 kb
Host smart-d7f4a993-18ab-4e66-bc74-791bbc0ecd66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3166593759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.3166593759
Directory /workspace/28.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_regwen.895202585
Short name T960
Test name
Test status
Simulation time 4290175947 ps
CPU time 16.6 seconds
Started Mar 28 03:32:41 PM PDT 24
Finished Mar 28 03:32:58 PM PDT 24
Peak memory 241796 kb
Host smart-4dd0b142-9811-437d-8f38-14a8abe3fc34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=895202585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.895202585
Directory /workspace/28.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/28.otp_ctrl_smoke.1378750908
Short name T1027
Test name
Test status
Simulation time 939661908 ps
CPU time 12.1 seconds
Started Mar 28 03:32:38 PM PDT 24
Finished Mar 28 03:32:50 PM PDT 24
Peak memory 241972 kb
Host smart-62e0e49b-181f-4048-931c-bba634bca888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378750908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.1378750908
Directory /workspace/28.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all_with_rand_reset.1256612463
Short name T348
Test name
Test status
Simulation time 69005353601 ps
CPU time 1900.36 seconds
Started Mar 28 03:32:37 PM PDT 24
Finished Mar 28 04:04:18 PM PDT 24
Peak memory 445024 kb
Host smart-4bcbd173-ab28-4d9b-b30c-c21afcfa86b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256612463 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all_with_rand_reset.1256612463
Directory /workspace/28.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.otp_ctrl_test_access.63400301
Short name T307
Test name
Test status
Simulation time 8424843971 ps
CPU time 15.4 seconds
Started Mar 28 03:32:38 PM PDT 24
Finished Mar 28 03:32:54 PM PDT 24
Peak memory 242704 kb
Host smart-2981f169-946b-476a-aac1-2f62aea9531e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63400301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_test_access.63400301
Directory /workspace/28.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/280.otp_ctrl_init_fail.3317715927
Short name T177
Test name
Test status
Simulation time 292354839 ps
CPU time 3.81 seconds
Started Mar 28 03:35:27 PM PDT 24
Finished Mar 28 03:35:31 PM PDT 24
Peak memory 241728 kb
Host smart-4d471214-7365-4776-81b5-ffa605cf75a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317715927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.3317715927
Directory /workspace/280.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/281.otp_ctrl_init_fail.3698794304
Short name T52
Test name
Test status
Simulation time 158784785 ps
CPU time 4.31 seconds
Started Mar 28 03:35:27 PM PDT 24
Finished Mar 28 03:35:33 PM PDT 24
Peak memory 241728 kb
Host smart-0b84faff-524a-4e64-a1b9-9d066d157ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698794304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.3698794304
Directory /workspace/281.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/282.otp_ctrl_init_fail.4186578982
Short name T203
Test name
Test status
Simulation time 475904155 ps
CPU time 3.91 seconds
Started Mar 28 03:35:25 PM PDT 24
Finished Mar 28 03:35:29 PM PDT 24
Peak memory 241952 kb
Host smart-f89a60e8-1a82-42cd-8934-1da243a15abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186578982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.4186578982
Directory /workspace/282.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/284.otp_ctrl_init_fail.3031169651
Short name T1181
Test name
Test status
Simulation time 346709462 ps
CPU time 3.52 seconds
Started Mar 28 03:35:29 PM PDT 24
Finished Mar 28 03:35:33 PM PDT 24
Peak memory 241920 kb
Host smart-3144f6e3-4b5d-42de-972c-0aabf0d6bc4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031169651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.3031169651
Directory /workspace/284.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/285.otp_ctrl_init_fail.3596508183
Short name T921
Test name
Test status
Simulation time 606080867 ps
CPU time 4.44 seconds
Started Mar 28 03:35:27 PM PDT 24
Finished Mar 28 03:35:31 PM PDT 24
Peak memory 241752 kb
Host smart-4273b4b4-8385-4ce4-bbf5-5147bc434855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596508183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.3596508183
Directory /workspace/285.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/286.otp_ctrl_init_fail.2042322648
Short name T674
Test name
Test status
Simulation time 412646795 ps
CPU time 4.74 seconds
Started Mar 28 03:35:28 PM PDT 24
Finished Mar 28 03:35:34 PM PDT 24
Peak memory 241624 kb
Host smart-2d7de9a2-3999-46b7-8dac-f8df586d075b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042322648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.2042322648
Directory /workspace/286.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/287.otp_ctrl_init_fail.1353589546
Short name T576
Test name
Test status
Simulation time 124838964 ps
CPU time 4.14 seconds
Started Mar 28 03:35:27 PM PDT 24
Finished Mar 28 03:35:33 PM PDT 24
Peak memory 241732 kb
Host smart-2dde4946-d4d4-4521-9eb9-74fa659584f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353589546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.1353589546
Directory /workspace/287.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/288.otp_ctrl_init_fail.1584798437
Short name T502
Test name
Test status
Simulation time 167961390 ps
CPU time 4.7 seconds
Started Mar 28 03:35:27 PM PDT 24
Finished Mar 28 03:35:32 PM PDT 24
Peak memory 241740 kb
Host smart-01f4d169-0d9f-48e7-846f-ca0f4f7d0e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584798437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.1584798437
Directory /workspace/288.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/289.otp_ctrl_init_fail.991740260
Short name T922
Test name
Test status
Simulation time 2104912659 ps
CPU time 8.45 seconds
Started Mar 28 03:35:29 PM PDT 24
Finished Mar 28 03:35:38 PM PDT 24
Peak memory 241920 kb
Host smart-be0d3f02-8d3d-4123-aa08-e49b497542b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991740260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.991740260
Directory /workspace/289.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_alert_test.3978664069
Short name T775
Test name
Test status
Simulation time 194914538 ps
CPU time 2.7 seconds
Started Mar 28 03:32:41 PM PDT 24
Finished Mar 28 03:32:44 PM PDT 24
Peak memory 240148 kb
Host smart-1f3010d9-b0e7-4821-873c-1236cdd17544
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978664069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.3978664069
Directory /workspace/29.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.otp_ctrl_check_fail.947089211
Short name T344
Test name
Test status
Simulation time 157470139 ps
CPU time 3.55 seconds
Started Mar 28 03:32:39 PM PDT 24
Finished Mar 28 03:32:43 PM PDT 24
Peak memory 241892 kb
Host smart-680ab3eb-9a8b-41be-9b31-2bdc61a91189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947089211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.947089211
Directory /workspace/29.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_errs.459710919
Short name T868
Test name
Test status
Simulation time 1442992883 ps
CPU time 33.75 seconds
Started Mar 28 03:32:38 PM PDT 24
Finished Mar 28 03:33:12 PM PDT 24
Peak memory 241896 kb
Host smart-2dd75669-7040-4310-9ba7-52f03844fdf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459710919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.459710919
Directory /workspace/29.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_lock.1631023572
Short name T270
Test name
Test status
Simulation time 745585127 ps
CPU time 7.95 seconds
Started Mar 28 03:32:36 PM PDT 24
Finished Mar 28 03:32:44 PM PDT 24
Peak memory 241844 kb
Host smart-583efb64-3d6d-4cf3-9d0c-c1f5743d590e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631023572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.1631023572
Directory /workspace/29.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/29.otp_ctrl_init_fail.3390541477
Short name T983
Test name
Test status
Simulation time 122661579 ps
CPU time 4.43 seconds
Started Mar 28 03:32:37 PM PDT 24
Finished Mar 28 03:32:41 PM PDT 24
Peak memory 241620 kb
Host smart-6d52d582-30bb-44a7-acb0-d04d02c303ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390541477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.3390541477
Directory /workspace/29.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_macro_errs.3381212684
Short name T172
Test name
Test status
Simulation time 1147188545 ps
CPU time 19.32 seconds
Started Mar 28 03:32:36 PM PDT 24
Finished Mar 28 03:32:56 PM PDT 24
Peak memory 241952 kb
Host smart-aa76489a-1f4d-46a9-8e0d-bf1243c625e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381212684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.3381212684
Directory /workspace/29.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_key_req.3534823746
Short name T609
Test name
Test status
Simulation time 1145176585 ps
CPU time 20.28 seconds
Started Mar 28 03:32:39 PM PDT 24
Finished Mar 28 03:33:00 PM PDT 24
Peak memory 241992 kb
Host smart-08bf83b5-8ed3-4307-9123-aad59c2253df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534823746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.3534823746
Directory /workspace/29.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_esc.3997533518
Short name T491
Test name
Test status
Simulation time 372931962 ps
CPU time 6.26 seconds
Started Mar 28 03:32:42 PM PDT 24
Finished Mar 28 03:32:48 PM PDT 24
Peak memory 242032 kb
Host smart-caceda93-1167-4c2f-ac80-89589fd18de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997533518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.3997533518
Directory /workspace/29.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_req.1315332262
Short name T986
Test name
Test status
Simulation time 5046421516 ps
CPU time 12.56 seconds
Started Mar 28 03:32:41 PM PDT 24
Finished Mar 28 03:32:54 PM PDT 24
Peak memory 241756 kb
Host smart-15bd2b0e-871d-4b11-a5c8-9b70817f4c77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1315332262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.1315332262
Directory /workspace/29.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_regwen.507179223
Short name T341
Test name
Test status
Simulation time 285238516 ps
CPU time 10.65 seconds
Started Mar 28 03:32:41 PM PDT 24
Finished Mar 28 03:32:52 PM PDT 24
Peak memory 242036 kb
Host smart-0125f941-6d6d-4c3a-9b0c-8834bd5d68d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=507179223 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.507179223
Directory /workspace/29.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/29.otp_ctrl_smoke.501348451
Short name T875
Test name
Test status
Simulation time 3058871317 ps
CPU time 7.99 seconds
Started Mar 28 03:32:36 PM PDT 24
Finished Mar 28 03:32:44 PM PDT 24
Peak memory 242088 kb
Host smart-02be65eb-406c-4664-98a2-c52cfe6126e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501348451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.501348451
Directory /workspace/29.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all.295192318
Short name T1082
Test name
Test status
Simulation time 74956999 ps
CPU time 1.96 seconds
Started Mar 28 03:32:38 PM PDT 24
Finished Mar 28 03:32:40 PM PDT 24
Peak memory 241172 kb
Host smart-09191abf-9d06-496b-87a7-2ccc7afdd289
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295192318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all.
295192318
Directory /workspace/29.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all_with_rand_reset.3250858049
Short name T867
Test name
Test status
Simulation time 37591100748 ps
CPU time 1241.78 seconds
Started Mar 28 03:32:39 PM PDT 24
Finished Mar 28 03:53:23 PM PDT 24
Peak memory 258240 kb
Host smart-7dbe7e6f-9129-4b2e-970f-5c5bf5fcbff9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250858049 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all_with_rand_reset.3250858049
Directory /workspace/29.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.otp_ctrl_test_access.954921205
Short name T1064
Test name
Test status
Simulation time 1779232567 ps
CPU time 15.98 seconds
Started Mar 28 03:32:44 PM PDT 24
Finished Mar 28 03:33:00 PM PDT 24
Peak memory 242112 kb
Host smart-41014a68-f588-4b03-996e-e8d45679ed77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954921205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.954921205
Directory /workspace/29.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/290.otp_ctrl_init_fail.2786389591
Short name T582
Test name
Test status
Simulation time 292540099 ps
CPU time 5.74 seconds
Started Mar 28 03:35:26 PM PDT 24
Finished Mar 28 03:35:32 PM PDT 24
Peak memory 241728 kb
Host smart-88a7b888-edf1-4d89-bb17-b70e61f490b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786389591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.2786389591
Directory /workspace/290.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/291.otp_ctrl_init_fail.83052371
Short name T946
Test name
Test status
Simulation time 432010225 ps
CPU time 4.21 seconds
Started Mar 28 03:35:25 PM PDT 24
Finished Mar 28 03:35:29 PM PDT 24
Peak memory 241584 kb
Host smart-32b23456-870a-4222-9e28-12a6928fc566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83052371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.83052371
Directory /workspace/291.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/292.otp_ctrl_init_fail.3455039508
Short name T474
Test name
Test status
Simulation time 414746299 ps
CPU time 4.92 seconds
Started Mar 28 03:35:22 PM PDT 24
Finished Mar 28 03:35:28 PM PDT 24
Peak memory 241724 kb
Host smart-8fabf8ec-67d8-4e2f-ad55-048145e7af66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455039508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.3455039508
Directory /workspace/292.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/293.otp_ctrl_init_fail.1379680327
Short name T966
Test name
Test status
Simulation time 102846615 ps
CPU time 3.54 seconds
Started Mar 28 03:35:27 PM PDT 24
Finished Mar 28 03:35:32 PM PDT 24
Peak memory 241764 kb
Host smart-494d5f0f-c5aa-4f79-be03-4af5bff16527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379680327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.1379680327
Directory /workspace/293.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/294.otp_ctrl_init_fail.2929521813
Short name T125
Test name
Test status
Simulation time 147411390 ps
CPU time 4.04 seconds
Started Mar 28 03:35:26 PM PDT 24
Finished Mar 28 03:35:31 PM PDT 24
Peak memory 241752 kb
Host smart-037cddbb-ae2c-4dea-9dbc-9b949aa4bc18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929521813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.2929521813
Directory /workspace/294.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/295.otp_ctrl_init_fail.3151644745
Short name T1099
Test name
Test status
Simulation time 573855151 ps
CPU time 4.93 seconds
Started Mar 28 03:35:31 PM PDT 24
Finished Mar 28 03:35:36 PM PDT 24
Peak memory 241792 kb
Host smart-10061046-be80-49a9-a33d-6aab3d367070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151644745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.3151644745
Directory /workspace/295.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/296.otp_ctrl_init_fail.2619573666
Short name T180
Test name
Test status
Simulation time 168696037 ps
CPU time 4.06 seconds
Started Mar 28 03:35:29 PM PDT 24
Finished Mar 28 03:35:34 PM PDT 24
Peak memory 241776 kb
Host smart-494d5e71-51f7-481f-87a1-4ffbc6e09d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619573666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.2619573666
Directory /workspace/296.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/297.otp_ctrl_init_fail.2900038100
Short name T561
Test name
Test status
Simulation time 100745879 ps
CPU time 3.36 seconds
Started Mar 28 03:35:25 PM PDT 24
Finished Mar 28 03:35:28 PM PDT 24
Peak memory 241668 kb
Host smart-458207bf-78d9-47b2-b9e5-9efba673ab4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900038100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.2900038100
Directory /workspace/297.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/298.otp_ctrl_init_fail.989057682
Short name T1057
Test name
Test status
Simulation time 2298331327 ps
CPU time 7.19 seconds
Started Mar 28 03:35:27 PM PDT 24
Finished Mar 28 03:35:35 PM PDT 24
Peak memory 241804 kb
Host smart-31e17cc0-bb7c-4f1a-9156-30b4a2a12321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989057682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.989057682
Directory /workspace/298.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/299.otp_ctrl_init_fail.3705376118
Short name T50
Test name
Test status
Simulation time 181456227 ps
CPU time 4.86 seconds
Started Mar 28 03:35:25 PM PDT 24
Finished Mar 28 03:35:30 PM PDT 24
Peak memory 242000 kb
Host smart-357a770c-2123-4e5f-83e4-624d9320835d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705376118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.3705376118
Directory /workspace/299.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_alert_test.3799166102
Short name T670
Test name
Test status
Simulation time 726177459 ps
CPU time 2 seconds
Started Mar 28 03:31:18 PM PDT 24
Finished Mar 28 03:31:21 PM PDT 24
Peak memory 240088 kb
Host smart-9d8f3441-255c-4405-b08a-2d940e342e90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799166102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.3799166102
Directory /workspace/3.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.otp_ctrl_background_chks.941398717
Short name T536
Test name
Test status
Simulation time 1280442271 ps
CPU time 11.5 seconds
Started Mar 28 03:30:57 PM PDT 24
Finished Mar 28 03:31:08 PM PDT 24
Peak memory 241816 kb
Host smart-718b3d1a-293c-49bf-910b-b908e808c1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941398717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.941398717
Directory /workspace/3.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_errs.1409652807
Short name T918
Test name
Test status
Simulation time 368749935 ps
CPU time 22.7 seconds
Started Mar 28 03:31:14 PM PDT 24
Finished Mar 28 03:31:37 PM PDT 24
Peak memory 241364 kb
Host smart-26f5754b-d9c9-4869-a80c-e2cc9c5c8360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409652807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.1409652807
Directory /workspace/3.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_lock.4118038910
Short name T1075
Test name
Test status
Simulation time 172588145 ps
CPU time 4.24 seconds
Started Mar 28 03:30:57 PM PDT 24
Finished Mar 28 03:31:02 PM PDT 24
Peak memory 241640 kb
Host smart-75696406-b116-467b-9265-aa122b643efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118038910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.4118038910
Directory /workspace/3.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/3.otp_ctrl_init_fail.177724189
Short name T195
Test name
Test status
Simulation time 265957239 ps
CPU time 4.13 seconds
Started Mar 28 03:31:10 PM PDT 24
Finished Mar 28 03:31:14 PM PDT 24
Peak memory 241732 kb
Host smart-3d89f724-3204-4bab-9036-88c82be8857f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177724189 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.177724189
Directory /workspace/3.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_macro_errs.2564337357
Short name T1031
Test name
Test status
Simulation time 954550434 ps
CPU time 11.32 seconds
Started Mar 28 03:31:17 PM PDT 24
Finished Mar 28 03:31:29 PM PDT 24
Peak memory 242264 kb
Host smart-9cf86d0f-2026-4186-9887-923dd1eebeaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564337357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.2564337357
Directory /workspace/3.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_key_req.1522543436
Short name T1023
Test name
Test status
Simulation time 2780412232 ps
CPU time 34.02 seconds
Started Mar 28 03:31:18 PM PDT 24
Finished Mar 28 03:31:53 PM PDT 24
Peak memory 242648 kb
Host smart-9758d44d-2e4a-4299-ae5a-17029377f765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522543436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.1522543436
Directory /workspace/3.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_esc.1540315785
Short name T363
Test name
Test status
Simulation time 2683029362 ps
CPU time 10.16 seconds
Started Mar 28 03:31:00 PM PDT 24
Finished Mar 28 03:31:10 PM PDT 24
Peak memory 241688 kb
Host smart-de074d30-1030-441f-a14e-b7ea884ffe23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540315785 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.1540315785
Directory /workspace/3.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_req.2291033289
Short name T240
Test name
Test status
Simulation time 1365637506 ps
CPU time 10.47 seconds
Started Mar 28 03:30:58 PM PDT 24
Finished Mar 28 03:31:09 PM PDT 24
Peak memory 241516 kb
Host smart-d6e848d6-ac43-40e0-abe3-d647a93a9f61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2291033289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.2291033289
Directory /workspace/3.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_smoke.1139838631
Short name T461
Test name
Test status
Simulation time 257460710 ps
CPU time 9.7 seconds
Started Mar 28 03:31:02 PM PDT 24
Finished Mar 28 03:31:12 PM PDT 24
Peak memory 242036 kb
Host smart-0aec5e93-0c4d-42a3-a793-1dda9047b706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139838631 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.1139838631
Directory /workspace/3.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all_with_rand_reset.1380261692
Short name T90
Test name
Test status
Simulation time 85317334822 ps
CPU time 1265.35 seconds
Started Mar 28 03:31:18 PM PDT 24
Finished Mar 28 03:52:25 PM PDT 24
Peak memory 370684 kb
Host smart-bb1362a5-cd72-4c43-9e2b-7bfed993759f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380261692 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all_with_rand_reset.1380261692
Directory /workspace/3.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.otp_ctrl_test_access.283999312
Short name T301
Test name
Test status
Simulation time 1113251266 ps
CPU time 8.78 seconds
Started Mar 28 03:31:16 PM PDT 24
Finished Mar 28 03:31:25 PM PDT 24
Peak memory 241700 kb
Host smart-281a7344-7db1-4376-af56-1b8ffad78503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283999312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.283999312
Directory /workspace/3.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/30.otp_ctrl_alert_test.539467305
Short name T985
Test name
Test status
Simulation time 654832443 ps
CPU time 2.19 seconds
Started Mar 28 03:32:42 PM PDT 24
Finished Mar 28 03:32:45 PM PDT 24
Peak memory 240300 kb
Host smart-fce7cf77-4af9-4825-a1a9-c45657a0ff85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539467305 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.539467305
Directory /workspace/30.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.otp_ctrl_check_fail.3749426303
Short name T358
Test name
Test status
Simulation time 439918074 ps
CPU time 7.27 seconds
Started Mar 28 03:32:41 PM PDT 24
Finished Mar 28 03:32:49 PM PDT 24
Peak memory 242236 kb
Host smart-e0743821-ffda-43a4-ad84-c061217bcd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749426303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.3749426303
Directory /workspace/30.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_errs.250924323
Short name T1104
Test name
Test status
Simulation time 351792278 ps
CPU time 15.27 seconds
Started Mar 28 03:32:40 PM PDT 24
Finished Mar 28 03:32:56 PM PDT 24
Peak memory 241536 kb
Host smart-5152280d-de2e-4899-acd1-605816e16703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250924323 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.250924323
Directory /workspace/30.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_lock.997827681
Short name T640
Test name
Test status
Simulation time 1715222228 ps
CPU time 23.63 seconds
Started Mar 28 03:32:40 PM PDT 24
Finished Mar 28 03:33:05 PM PDT 24
Peak memory 242768 kb
Host smart-6012c8a6-1ffd-401d-a068-34c8d7f231f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997827681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.997827681
Directory /workspace/30.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/30.otp_ctrl_init_fail.1077271178
Short name T884
Test name
Test status
Simulation time 103085951 ps
CPU time 3.59 seconds
Started Mar 28 03:32:38 PM PDT 24
Finished Mar 28 03:32:42 PM PDT 24
Peak memory 242016 kb
Host smart-137b779c-260f-45b7-b0ca-666df5e89c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077271178 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.1077271178
Directory /workspace/30.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_macro_errs.2316289857
Short name T342
Test name
Test status
Simulation time 1873805700 ps
CPU time 28.89 seconds
Started Mar 28 03:32:40 PM PDT 24
Finished Mar 28 03:33:10 PM PDT 24
Peak memory 246488 kb
Host smart-21dcf8b1-53bc-4b52-b7cf-8b083786c717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316289857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.2316289857
Directory /workspace/30.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_key_req.2877588438
Short name T781
Test name
Test status
Simulation time 1794489028 ps
CPU time 19.38 seconds
Started Mar 28 03:32:41 PM PDT 24
Finished Mar 28 03:33:01 PM PDT 24
Peak memory 241940 kb
Host smart-3c5b1565-fd5f-4c82-84f8-44598d069948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877588438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.2877588438
Directory /workspace/30.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_esc.1492149981
Short name T573
Test name
Test status
Simulation time 444686980 ps
CPU time 6.07 seconds
Started Mar 28 03:32:40 PM PDT 24
Finished Mar 28 03:32:47 PM PDT 24
Peak memory 241596 kb
Host smart-048b14d9-303d-4c10-8fc7-6203090e429a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492149981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.1492149981
Directory /workspace/30.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_req.1628503056
Short name T1111
Test name
Test status
Simulation time 1367267876 ps
CPU time 24.97 seconds
Started Mar 28 03:32:39 PM PDT 24
Finished Mar 28 03:33:04 PM PDT 24
Peak memory 241484 kb
Host smart-e10cd742-2979-44da-a5c9-53488020ea81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1628503056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_req.1628503056
Directory /workspace/30.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_regwen.2413979058
Short name T1178
Test name
Test status
Simulation time 290417385 ps
CPU time 11.83 seconds
Started Mar 28 03:32:39 PM PDT 24
Finished Mar 28 03:32:51 PM PDT 24
Peak memory 241856 kb
Host smart-8b3ccff7-90b4-481b-ba1d-2efaa85294fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2413979058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.2413979058
Directory /workspace/30.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/30.otp_ctrl_smoke.24470187
Short name T432
Test name
Test status
Simulation time 212227586 ps
CPU time 4.67 seconds
Started Mar 28 03:32:38 PM PDT 24
Finished Mar 28 03:32:43 PM PDT 24
Peak memory 241668 kb
Host smart-a506b595-8d6e-4080-98c1-18e2138ef064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24470187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.24470187
Directory /workspace/30.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all_with_rand_reset.946521662
Short name T356
Test name
Test status
Simulation time 48064680434 ps
CPU time 928.56 seconds
Started Mar 28 03:32:37 PM PDT 24
Finished Mar 28 03:48:06 PM PDT 24
Peak memory 259816 kb
Host smart-7df30773-aed3-4aed-b178-2b68b63c30e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946521662 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all_with_rand_reset.946521662
Directory /workspace/30.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.otp_ctrl_test_access.3123662044
Short name T193
Test name
Test status
Simulation time 2700057869 ps
CPU time 15.13 seconds
Started Mar 28 03:32:40 PM PDT 24
Finished Mar 28 03:32:56 PM PDT 24
Peak memory 248624 kb
Host smart-2e48108a-aa4b-478f-9397-de89712deb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123662044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.3123662044
Directory /workspace/30.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/31.otp_ctrl_alert_test.2110575616
Short name T429
Test name
Test status
Simulation time 189198030 ps
CPU time 2.12 seconds
Started Mar 28 03:32:39 PM PDT 24
Finished Mar 28 03:32:42 PM PDT 24
Peak memory 240404 kb
Host smart-43d0cd52-5f27-4c5a-82f9-b546cc3d0627
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110575616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.2110575616
Directory /workspace/31.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_errs.1355402241
Short name T772
Test name
Test status
Simulation time 416716941 ps
CPU time 16.71 seconds
Started Mar 28 03:32:39 PM PDT 24
Finished Mar 28 03:32:56 PM PDT 24
Peak memory 248036 kb
Host smart-243683c5-8363-4153-9629-c63ff1a8a1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355402241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_errs.1355402241
Directory /workspace/31.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_lock.3286419638
Short name T896
Test name
Test status
Simulation time 27758488699 ps
CPU time 58.73 seconds
Started Mar 28 03:32:42 PM PDT 24
Finished Mar 28 03:33:41 PM PDT 24
Peak memory 243336 kb
Host smart-5d852548-97a2-4cc2-bdfe-190778555e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286419638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.3286419638
Directory /workspace/31.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/31.otp_ctrl_init_fail.1959100538
Short name T800
Test name
Test status
Simulation time 120162251 ps
CPU time 4.37 seconds
Started Mar 28 03:32:41 PM PDT 24
Finished Mar 28 03:32:46 PM PDT 24
Peak memory 241772 kb
Host smart-18aef856-580f-4410-b757-0e5addd5d02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959100538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.1959100538
Directory /workspace/31.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_macro_errs.2883751660
Short name T98
Test name
Test status
Simulation time 4178101051 ps
CPU time 37.28 seconds
Started Mar 28 03:32:45 PM PDT 24
Finished Mar 28 03:33:22 PM PDT 24
Peak memory 256860 kb
Host smart-09224e0e-81b8-4e43-b529-63b1a6f50b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883751660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.2883751660
Directory /workspace/31.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_key_req.2336312117
Short name T524
Test name
Test status
Simulation time 2450441736 ps
CPU time 40.54 seconds
Started Mar 28 03:32:41 PM PDT 24
Finished Mar 28 03:33:22 PM PDT 24
Peak memory 242460 kb
Host smart-67b439d2-06b9-4ed1-b73d-6c55f6246afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336312117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.2336312117
Directory /workspace/31.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_esc.3770249367
Short name T1088
Test name
Test status
Simulation time 749010694 ps
CPU time 9.35 seconds
Started Mar 28 03:32:45 PM PDT 24
Finished Mar 28 03:32:55 PM PDT 24
Peak memory 241444 kb
Host smart-c370b915-96f0-4120-91d4-a882a12cd87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770249367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.3770249367
Directory /workspace/31.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_req.2027483850
Short name T1133
Test name
Test status
Simulation time 709751226 ps
CPU time 19.19 seconds
Started Mar 28 03:32:41 PM PDT 24
Finished Mar 28 03:33:00 PM PDT 24
Peak memory 241584 kb
Host smart-857b8642-755b-48a1-be79-0eeb42c119af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2027483850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_req.2027483850
Directory /workspace/31.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_regwen.1934025746
Short name T1108
Test name
Test status
Simulation time 280396439 ps
CPU time 8.21 seconds
Started Mar 28 03:32:45 PM PDT 24
Finished Mar 28 03:32:54 PM PDT 24
Peak memory 241716 kb
Host smart-118742eb-8018-4769-a690-1b73a88c60dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1934025746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.1934025746
Directory /workspace/31.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/31.otp_ctrl_smoke.3503477036
Short name T476
Test name
Test status
Simulation time 364992011 ps
CPU time 5.46 seconds
Started Mar 28 03:32:41 PM PDT 24
Finished Mar 28 03:32:47 PM PDT 24
Peak memory 241928 kb
Host smart-565e90b6-2e16-4d8f-a6d7-4f83486a7ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503477036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.3503477036
Directory /workspace/31.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all.22066520
Short name T1185
Test name
Test status
Simulation time 20236344190 ps
CPU time 205.8 seconds
Started Mar 28 03:32:40 PM PDT 24
Finished Mar 28 03:36:07 PM PDT 24
Peak memory 265896 kb
Host smart-e8f2991f-f214-466f-b00c-22f794675464
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22066520 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all.22066520
Directory /workspace/31.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.otp_ctrl_test_access.193253202
Short name T695
Test name
Test status
Simulation time 376789240 ps
CPU time 11.95 seconds
Started Mar 28 03:32:41 PM PDT 24
Finished Mar 28 03:32:53 PM PDT 24
Peak memory 242056 kb
Host smart-71f76a3b-7879-4316-839d-d2dc8d497c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193253202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.193253202
Directory /workspace/31.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/32.otp_ctrl_alert_test.1405424863
Short name T318
Test name
Test status
Simulation time 161872070 ps
CPU time 1.59 seconds
Started Mar 28 03:32:40 PM PDT 24
Finished Mar 28 03:32:43 PM PDT 24
Peak memory 240048 kb
Host smart-a80b1c05-5cf1-4d41-8f6b-10fe6c4c383b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405424863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.1405424863
Directory /workspace/32.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.otp_ctrl_check_fail.1933231764
Short name T780
Test name
Test status
Simulation time 1568193535 ps
CPU time 35.43 seconds
Started Mar 28 03:32:46 PM PDT 24
Finished Mar 28 03:33:22 PM PDT 24
Peak memory 241812 kb
Host smart-20bf8d93-dea9-4e8a-9258-d3eeaecb7ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933231764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.1933231764
Directory /workspace/32.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_errs.27838638
Short name T4
Test name
Test status
Simulation time 1652083123 ps
CPU time 44.15 seconds
Started Mar 28 03:32:46 PM PDT 24
Finished Mar 28 03:33:31 PM PDT 24
Peak memory 253224 kb
Host smart-8f6cb4fd-86a5-49e1-bd48-d26af9d670fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27838638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.27838638
Directory /workspace/32.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_lock.4065002529
Short name T468
Test name
Test status
Simulation time 1626659000 ps
CPU time 11.34 seconds
Started Mar 28 03:32:40 PM PDT 24
Finished Mar 28 03:32:52 PM PDT 24
Peak memory 241992 kb
Host smart-008fcc6c-0d32-4f56-986e-bfb56c65d863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065002529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.4065002529
Directory /workspace/32.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/32.otp_ctrl_macro_errs.1971085482
Short name T1126
Test name
Test status
Simulation time 1720272555 ps
CPU time 30.39 seconds
Started Mar 28 03:32:46 PM PDT 24
Finished Mar 28 03:33:17 PM PDT 24
Peak memory 242984 kb
Host smart-a3e8bcb8-ab71-4034-8b18-a5d6a6ac897d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971085482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_macro_errs.1971085482
Directory /workspace/32.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_key_req.3170869777
Short name T133
Test name
Test status
Simulation time 626161057 ps
CPU time 9.06 seconds
Started Mar 28 03:32:42 PM PDT 24
Finished Mar 28 03:32:51 PM PDT 24
Peak memory 242032 kb
Host smart-d67ff6c0-7919-4de3-9841-7e9b5c3ab1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170869777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.3170869777
Directory /workspace/32.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_esc.1411968918
Short name T514
Test name
Test status
Simulation time 1666064160 ps
CPU time 22.94 seconds
Started Mar 28 03:32:39 PM PDT 24
Finished Mar 28 03:33:02 PM PDT 24
Peak memory 241684 kb
Host smart-9790b274-379c-4734-938c-249efd0929e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411968918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.1411968918
Directory /workspace/32.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_req.1898291560
Short name T210
Test name
Test status
Simulation time 656477768 ps
CPU time 5.05 seconds
Started Mar 28 03:32:45 PM PDT 24
Finished Mar 28 03:32:50 PM PDT 24
Peak memory 241584 kb
Host smart-734471d4-e2e8-48b2-8533-9ef8d7b0055d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1898291560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.1898291560
Directory /workspace/32.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_smoke.1221559911
Short name T590
Test name
Test status
Simulation time 168150413 ps
CPU time 5.26 seconds
Started Mar 28 03:32:36 PM PDT 24
Finished Mar 28 03:32:42 PM PDT 24
Peak memory 241720 kb
Host smart-d657202c-d61f-45cc-8441-f7804c17be14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221559911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.1221559911
Directory /workspace/32.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all.804632278
Short name T563
Test name
Test status
Simulation time 7900933169 ps
CPU time 28.78 seconds
Started Mar 28 03:32:39 PM PDT 24
Finished Mar 28 03:33:08 PM PDT 24
Peak memory 241748 kb
Host smart-40bbff9f-7ac9-402e-90c9-4b8ad8454bcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804632278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all.
804632278
Directory /workspace/32.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all_with_rand_reset.930375035
Short name T611
Test name
Test status
Simulation time 72255320125 ps
CPU time 988.44 seconds
Started Mar 28 03:32:40 PM PDT 24
Finished Mar 28 03:49:10 PM PDT 24
Peak memory 311724 kb
Host smart-bc0a47f7-872d-420c-9f05-decaad3ca075
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930375035 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all_with_rand_reset.930375035
Directory /workspace/32.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.otp_ctrl_test_access.3956225803
Short name T305
Test name
Test status
Simulation time 1830508558 ps
CPU time 13.34 seconds
Started Mar 28 03:32:42 PM PDT 24
Finished Mar 28 03:32:56 PM PDT 24
Peak memory 241996 kb
Host smart-deaf728a-9379-42f5-9feb-feff4241da3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956225803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.3956225803
Directory /workspace/32.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/33.otp_ctrl_alert_test.67587671
Short name T242
Test name
Test status
Simulation time 703077330 ps
CPU time 2.33 seconds
Started Mar 28 03:33:00 PM PDT 24
Finished Mar 28 03:33:05 PM PDT 24
Peak memory 240052 kb
Host smart-1c06e7a6-0a18-44be-8e7e-1e9dde816e80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67587671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.67587671
Directory /workspace/33.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.otp_ctrl_check_fail.2773186897
Short name T33
Test name
Test status
Simulation time 1203051533 ps
CPU time 21.03 seconds
Started Mar 28 03:32:39 PM PDT 24
Finished Mar 28 03:33:00 PM PDT 24
Peak memory 242316 kb
Host smart-6c075bef-5c9c-41bf-b845-513ee3a93a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773186897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.2773186897
Directory /workspace/33.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_errs.1271343587
Short name T838
Test name
Test status
Simulation time 1303927314 ps
CPU time 30.74 seconds
Started Mar 28 03:32:41 PM PDT 24
Finished Mar 28 03:33:12 PM PDT 24
Peak memory 241776 kb
Host smart-a4780d2f-90e7-411d-b246-8a0e9c418e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271343587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.1271343587
Directory /workspace/33.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_lock.3301366406
Short name T855
Test name
Test status
Simulation time 2009501809 ps
CPU time 36.93 seconds
Started Mar 28 03:32:41 PM PDT 24
Finished Mar 28 03:33:18 PM PDT 24
Peak memory 241896 kb
Host smart-0c6d427a-4497-41ef-91e5-fa7064983a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301366406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_lock.3301366406
Directory /workspace/33.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/33.otp_ctrl_init_fail.2159398191
Short name T702
Test name
Test status
Simulation time 244319173 ps
CPU time 4.28 seconds
Started Mar 28 03:32:44 PM PDT 24
Finished Mar 28 03:32:48 PM PDT 24
Peak memory 241768 kb
Host smart-8fe0f9a4-a0e4-4f6e-9636-8f18fc104754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159398191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.2159398191
Directory /workspace/33.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_key_req.408876867
Short name T410
Test name
Test status
Simulation time 1079451530 ps
CPU time 26.94 seconds
Started Mar 28 03:32:39 PM PDT 24
Finished Mar 28 03:33:07 PM PDT 24
Peak memory 242252 kb
Host smart-0db01347-6a68-4767-9bb5-f4ce777a9b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408876867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_key_req.408876867
Directory /workspace/33.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_esc.2986973340
Short name T608
Test name
Test status
Simulation time 2151837630 ps
CPU time 17.64 seconds
Started Mar 28 03:32:38 PM PDT 24
Finished Mar 28 03:32:56 PM PDT 24
Peak memory 241708 kb
Host smart-50e9606f-6646-49fd-991a-7ca52f08c109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986973340 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.2986973340
Directory /workspace/33.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_req.4012325356
Short name T733
Test name
Test status
Simulation time 891036969 ps
CPU time 21.73 seconds
Started Mar 28 03:32:40 PM PDT 24
Finished Mar 28 03:33:02 PM PDT 24
Peak memory 241616 kb
Host smart-0fdfddab-9914-42ac-8916-5e201c8656a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4012325356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_req.4012325356
Directory /workspace/33.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_regwen.271983279
Short name T382
Test name
Test status
Simulation time 215701230 ps
CPU time 7.11 seconds
Started Mar 28 03:32:54 PM PDT 24
Finished Mar 28 03:33:02 PM PDT 24
Peak memory 241824 kb
Host smart-f649077f-0fcf-4f26-bdbf-8e28e3746497
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=271983279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.271983279
Directory /workspace/33.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/33.otp_ctrl_smoke.672873368
Short name T685
Test name
Test status
Simulation time 1479588717 ps
CPU time 8.27 seconds
Started Mar 28 03:32:39 PM PDT 24
Finished Mar 28 03:32:48 PM PDT 24
Peak memory 241960 kb
Host smart-63404cc4-d1e6-4c6c-86ce-e01a07017a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672873368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.672873368
Directory /workspace/33.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all.1282815644
Short name T311
Test name
Test status
Simulation time 18416735316 ps
CPU time 234.91 seconds
Started Mar 28 03:32:54 PM PDT 24
Finished Mar 28 03:36:50 PM PDT 24
Peak memory 257056 kb
Host smart-e5c6bff2-30c6-4b4c-859c-326db5473609
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282815644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all
.1282815644
Directory /workspace/33.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all_with_rand_reset.2479682663
Short name T355
Test name
Test status
Simulation time 51849414773 ps
CPU time 543.95 seconds
Started Mar 28 03:32:58 PM PDT 24
Finished Mar 28 03:42:06 PM PDT 24
Peak memory 274596 kb
Host smart-358017b5-3230-42cf-85fb-391672677d50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479682663 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all_with_rand_reset.2479682663
Directory /workspace/33.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.otp_ctrl_test_access.4046574222
Short name T1156
Test name
Test status
Simulation time 4235004736 ps
CPU time 10.46 seconds
Started Mar 28 03:32:56 PM PDT 24
Finished Mar 28 03:33:08 PM PDT 24
Peak memory 241824 kb
Host smart-3ded8abb-e208-4e5d-95f4-2b0d91bf9215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046574222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.4046574222
Directory /workspace/33.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/34.otp_ctrl_alert_test.962867663
Short name T691
Test name
Test status
Simulation time 144621134 ps
CPU time 2.02 seconds
Started Mar 28 03:32:57 PM PDT 24
Finished Mar 28 03:32:59 PM PDT 24
Peak memory 240148 kb
Host smart-3d068644-54e1-40b6-919a-0497c7d0c25e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962867663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.962867663
Directory /workspace/34.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.otp_ctrl_check_fail.48378809
Short name T110
Test name
Test status
Simulation time 946826687 ps
CPU time 17.76 seconds
Started Mar 28 03:32:54 PM PDT 24
Finished Mar 28 03:33:12 PM PDT 24
Peak memory 248568 kb
Host smart-9f9e5477-06c1-49b8-b5aa-acdc6529eb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48378809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.48378809
Directory /workspace/34.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_errs.1597226303
Short name T681
Test name
Test status
Simulation time 2905737325 ps
CPU time 40.77 seconds
Started Mar 28 03:32:58 PM PDT 24
Finished Mar 28 03:33:42 PM PDT 24
Peak memory 246640 kb
Host smart-2a1f2dc2-0768-4dc6-879f-85841a6a54d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597226303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.1597226303
Directory /workspace/34.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_lock.268868751
Short name T478
Test name
Test status
Simulation time 1754939329 ps
CPU time 34.8 seconds
Started Mar 28 03:32:57 PM PDT 24
Finished Mar 28 03:33:32 PM PDT 24
Peak memory 242392 kb
Host smart-73c7a825-4c5d-4e0b-9e46-699dfbef635c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268868751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_lock.268868751
Directory /workspace/34.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/34.otp_ctrl_init_fail.747236300
Short name T124
Test name
Test status
Simulation time 163002035 ps
CPU time 3.21 seconds
Started Mar 28 03:32:55 PM PDT 24
Finished Mar 28 03:32:59 PM PDT 24
Peak memory 241752 kb
Host smart-bc2dd440-6f54-4545-af83-c1da022ba3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747236300 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.747236300
Directory /workspace/34.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_macro_errs.4089099481
Short name T726
Test name
Test status
Simulation time 3661545513 ps
CPU time 28.18 seconds
Started Mar 28 03:32:59 PM PDT 24
Finished Mar 28 03:33:30 PM PDT 24
Peak memory 243256 kb
Host smart-5cbbebe4-be0e-4cac-a138-4a59423b79f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089099481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.4089099481
Directory /workspace/34.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_key_req.3912982549
Short name T1141
Test name
Test status
Simulation time 1655774617 ps
CPU time 22.18 seconds
Started Mar 28 03:32:59 PM PDT 24
Finished Mar 28 03:33:24 PM PDT 24
Peak memory 241832 kb
Host smart-9ad32dac-3c93-42d6-be57-2e023fce09ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912982549 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.3912982549
Directory /workspace/34.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_esc.2800518536
Short name T687
Test name
Test status
Simulation time 425800654 ps
CPU time 4.59 seconds
Started Mar 28 03:32:58 PM PDT 24
Finished Mar 28 03:33:06 PM PDT 24
Peak memory 242020 kb
Host smart-e1f51e5e-3316-4b60-a34f-d8f5baea8eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800518536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.2800518536
Directory /workspace/34.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_req.2513277105
Short name T747
Test name
Test status
Simulation time 418710599 ps
CPU time 11.63 seconds
Started Mar 28 03:32:59 PM PDT 24
Finished Mar 28 03:33:13 PM PDT 24
Peak memory 241580 kb
Host smart-9818b27d-d23e-485e-89dc-c9f9feb87a6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2513277105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.2513277105
Directory /workspace/34.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_regwen.2496667633
Short name T271
Test name
Test status
Simulation time 118595833 ps
CPU time 3.49 seconds
Started Mar 28 03:32:58 PM PDT 24
Finished Mar 28 03:33:04 PM PDT 24
Peak memory 241704 kb
Host smart-325d61bf-ab6b-47a2-a1dd-24e6c22f4fb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2496667633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.2496667633
Directory /workspace/34.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/34.otp_ctrl_smoke.4138267793
Short name T705
Test name
Test status
Simulation time 1253212678 ps
CPU time 8.87 seconds
Started Mar 28 03:33:01 PM PDT 24
Finished Mar 28 03:33:11 PM PDT 24
Peak memory 241736 kb
Host smart-f7ff289e-386b-4fa5-955f-86a7805384e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138267793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_smoke.4138267793
Directory /workspace/34.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all.1892393035
Short name T932
Test name
Test status
Simulation time 7730075629 ps
CPU time 155.81 seconds
Started Mar 28 03:33:00 PM PDT 24
Finished Mar 28 03:35:38 PM PDT 24
Peak memory 246768 kb
Host smart-9351cae7-8a13-4a19-8fb6-ce072a6e3712
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892393035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all
.1892393035
Directory /workspace/34.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.otp_ctrl_test_access.1711004554
Short name T521
Test name
Test status
Simulation time 14695919686 ps
CPU time 44.07 seconds
Started Mar 28 03:33:00 PM PDT 24
Finished Mar 28 03:33:46 PM PDT 24
Peak memory 242072 kb
Host smart-74425f7a-f73c-403e-a4dc-1ed8d2061058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711004554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_test_access.1711004554
Directory /workspace/34.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/35.otp_ctrl_alert_test.546950276
Short name T509
Test name
Test status
Simulation time 104548576 ps
CPU time 2.06 seconds
Started Mar 28 03:33:00 PM PDT 24
Finished Mar 28 03:33:04 PM PDT 24
Peak memory 240340 kb
Host smart-6d999db4-64b5-4145-a87c-8520d825dd69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546950276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.546950276
Directory /workspace/35.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.otp_ctrl_check_fail.3556087292
Short name T664
Test name
Test status
Simulation time 174625177 ps
CPU time 4.25 seconds
Started Mar 28 03:33:00 PM PDT 24
Finished Mar 28 03:33:07 PM PDT 24
Peak memory 241900 kb
Host smart-64008d9d-d42c-4f37-9c87-2ecf36e82f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556087292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.3556087292
Directory /workspace/35.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_errs.178927457
Short name T996
Test name
Test status
Simulation time 1143276804 ps
CPU time 20.27 seconds
Started Mar 28 03:32:56 PM PDT 24
Finished Mar 28 03:33:17 PM PDT 24
Peak memory 241568 kb
Host smart-b38d7f0b-f837-4ccb-8190-abe1e745c5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178927457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_errs.178927457
Directory /workspace/35.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_lock.1091778912
Short name T729
Test name
Test status
Simulation time 890196262 ps
CPU time 20.47 seconds
Started Mar 28 03:32:58 PM PDT 24
Finished Mar 28 03:33:22 PM PDT 24
Peak memory 242440 kb
Host smart-12ef1b39-e74a-448f-9fbc-4b6eb146f60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091778912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_lock.1091778912
Directory /workspace/35.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/35.otp_ctrl_init_fail.2930214603
Short name T819
Test name
Test status
Simulation time 272174028 ps
CPU time 4.95 seconds
Started Mar 28 03:32:58 PM PDT 24
Finished Mar 28 03:33:07 PM PDT 24
Peak memory 241660 kb
Host smart-5768fbdd-e0a6-476c-a1a6-46fe053709f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930214603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.2930214603
Directory /workspace/35.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_macro_errs.3075486391
Short name T679
Test name
Test status
Simulation time 3773655126 ps
CPU time 36.03 seconds
Started Mar 28 03:32:58 PM PDT 24
Finished Mar 28 03:33:38 PM PDT 24
Peak memory 249548 kb
Host smart-38e67cdf-ae95-49e5-9bf2-dac95fe0cfe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075486391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.3075486391
Directory /workspace/35.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_key_req.1147813776
Short name T850
Test name
Test status
Simulation time 3455618863 ps
CPU time 27.7 seconds
Started Mar 28 03:33:00 PM PDT 24
Finished Mar 28 03:33:30 PM PDT 24
Peak memory 242180 kb
Host smart-ac75d708-af3a-4395-9b85-f87b08049988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147813776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.1147813776
Directory /workspace/35.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_esc.1960128836
Short name T799
Test name
Test status
Simulation time 705198155 ps
CPU time 15.11 seconds
Started Mar 28 03:32:58 PM PDT 24
Finished Mar 28 03:33:17 PM PDT 24
Peak memory 242028 kb
Host smart-97e2e5f1-0140-4042-8921-348c18734b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960128836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.1960128836
Directory /workspace/35.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_req.3820804919
Short name T102
Test name
Test status
Simulation time 715918861 ps
CPU time 12.04 seconds
Started Mar 28 03:33:04 PM PDT 24
Finished Mar 28 03:33:16 PM PDT 24
Peak memory 241500 kb
Host smart-5228a47e-3fa1-40e0-99d0-c490476c12fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3820804919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.3820804919
Directory /workspace/35.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_regwen.353166324
Short name T394
Test name
Test status
Simulation time 625977509 ps
CPU time 8.96 seconds
Started Mar 28 03:32:56 PM PDT 24
Finished Mar 28 03:33:06 PM PDT 24
Peak memory 241732 kb
Host smart-3fa5f4be-4fa4-4483-a7c4-a0fea6cdb3bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=353166324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.353166324
Directory /workspace/35.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/35.otp_ctrl_smoke.1456871826
Short name T811
Test name
Test status
Simulation time 1550838091 ps
CPU time 12.86 seconds
Started Mar 28 03:32:57 PM PDT 24
Finished Mar 28 03:33:10 PM PDT 24
Peak memory 241972 kb
Host smart-648c6e66-4fdf-4931-b809-24fc8b67b4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456871826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.1456871826
Directory /workspace/35.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/35.otp_ctrl_stress_all.2107322183
Short name T357
Test name
Test status
Simulation time 25111926066 ps
CPU time 228.97 seconds
Started Mar 28 03:32:59 PM PDT 24
Finished Mar 28 03:36:51 PM PDT 24
Peak memory 273320 kb
Host smart-1e5e5ccb-4fde-4f65-86ed-80721f382cac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107322183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all
.2107322183
Directory /workspace/35.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.otp_ctrl_test_access.222360836
Short name T487
Test name
Test status
Simulation time 1104680557 ps
CPU time 13.29 seconds
Started Mar 28 03:32:59 PM PDT 24
Finished Mar 28 03:33:15 PM PDT 24
Peak memory 241844 kb
Host smart-7795487f-fcfd-4971-83d2-66633413bd7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222360836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_test_access.222360836
Directory /workspace/35.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/36.otp_ctrl_alert_test.3490118526
Short name T711
Test name
Test status
Simulation time 620355893 ps
CPU time 1.71 seconds
Started Mar 28 03:33:02 PM PDT 24
Finished Mar 28 03:33:05 PM PDT 24
Peak memory 240120 kb
Host smart-b1dce1c5-993e-403a-b03a-87dfe046e3f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490118526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.3490118526
Directory /workspace/36.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.otp_ctrl_check_fail.4252749706
Short name T114
Test name
Test status
Simulation time 627473897 ps
CPU time 21.09 seconds
Started Mar 28 03:32:59 PM PDT 24
Finished Mar 28 03:33:23 PM PDT 24
Peak memory 248672 kb
Host smart-4c3462c7-5a29-4251-bd2c-3a294c532211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252749706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.4252749706
Directory /workspace/36.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_lock.2813948183
Short name T1168
Test name
Test status
Simulation time 1551888182 ps
CPU time 11.16 seconds
Started Mar 28 03:32:58 PM PDT 24
Finished Mar 28 03:33:13 PM PDT 24
Peak memory 241736 kb
Host smart-feb03abe-5589-4ab0-b880-aff36a029c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813948183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_lock.2813948183
Directory /workspace/36.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/36.otp_ctrl_init_fail.1049888610
Short name T636
Test name
Test status
Simulation time 2153008102 ps
CPU time 5.21 seconds
Started Mar 28 03:33:00 PM PDT 24
Finished Mar 28 03:33:08 PM PDT 24
Peak memory 241904 kb
Host smart-e312be6c-2e3c-43d0-ac5b-368be070fb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049888610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.1049888610
Directory /workspace/36.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_macro_errs.4041793306
Short name T830
Test name
Test status
Simulation time 723337871 ps
CPU time 20.1 seconds
Started Mar 28 03:32:59 PM PDT 24
Finished Mar 28 03:33:22 PM PDT 24
Peak memory 242292 kb
Host smart-9d11dc45-eaa2-458d-a8d6-c2a4aa4e00cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041793306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.4041793306
Directory /workspace/36.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_key_req.1916172402
Short name T801
Test name
Test status
Simulation time 1204682107 ps
CPU time 30.73 seconds
Started Mar 28 03:32:58 PM PDT 24
Finished Mar 28 03:33:32 PM PDT 24
Peak memory 242044 kb
Host smart-b8fc036f-3d22-477b-88d2-89a30a74ea6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916172402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.1916172402
Directory /workspace/36.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_esc.3277402347
Short name T1016
Test name
Test status
Simulation time 334149208 ps
CPU time 8.41 seconds
Started Mar 28 03:33:01 PM PDT 24
Finished Mar 28 03:33:11 PM PDT 24
Peak memory 241972 kb
Host smart-8a8c01ca-37bc-4cf3-9afb-cde52fa67c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277402347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.3277402347
Directory /workspace/36.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_req.113062280
Short name T926
Test name
Test status
Simulation time 1993581715 ps
CPU time 6.88 seconds
Started Mar 28 03:33:00 PM PDT 24
Finished Mar 28 03:33:09 PM PDT 24
Peak memory 241656 kb
Host smart-eb4df2d1-cf72-4909-8b8a-2c682512b9c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=113062280 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.113062280
Directory /workspace/36.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_regwen.693141886
Short name T877
Test name
Test status
Simulation time 2623853622 ps
CPU time 7.92 seconds
Started Mar 28 03:33:00 PM PDT 24
Finished Mar 28 03:33:10 PM PDT 24
Peak memory 241808 kb
Host smart-9e29c458-c474-44ed-8214-950e795796df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=693141886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.693141886
Directory /workspace/36.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/36.otp_ctrl_smoke.3554844814
Short name T690
Test name
Test status
Simulation time 458674759 ps
CPU time 8.26 seconds
Started Mar 28 03:33:00 PM PDT 24
Finished Mar 28 03:33:11 PM PDT 24
Peak memory 241640 kb
Host smart-fabdb5e3-e8a9-4537-9cff-41db4eb28abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554844814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.3554844814
Directory /workspace/36.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all.410076231
Short name T160
Test name
Test status
Simulation time 27602161713 ps
CPU time 145.73 seconds
Started Mar 28 03:33:05 PM PDT 24
Finished Mar 28 03:35:31 PM PDT 24
Peak memory 256980 kb
Host smart-3aa89edc-a644-4b0a-a093-625fd8cd86d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410076231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all.
410076231
Directory /workspace/36.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all_with_rand_reset.2499636000
Short name T889
Test name
Test status
Simulation time 812505549359 ps
CPU time 2561.44 seconds
Started Mar 28 03:33:02 PM PDT 24
Finished Mar 28 04:15:45 PM PDT 24
Peak memory 557628 kb
Host smart-1c853f53-4299-49d6-ade8-4ebf574e37c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499636000 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all_with_rand_reset.2499636000
Directory /workspace/36.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.otp_ctrl_test_access.2773858418
Short name T639
Test name
Test status
Simulation time 539833251 ps
CPU time 12.16 seconds
Started Mar 28 03:32:58 PM PDT 24
Finished Mar 28 03:33:14 PM PDT 24
Peak memory 241780 kb
Host smart-a5e51fee-0cdc-435b-95fe-12906d6a72f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773858418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.2773858418
Directory /workspace/36.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/37.otp_ctrl_alert_test.3750314244
Short name T321
Test name
Test status
Simulation time 80111684 ps
CPU time 1.82 seconds
Started Mar 28 03:32:57 PM PDT 24
Finished Mar 28 03:32:59 PM PDT 24
Peak memory 240124 kb
Host smart-266b262f-9646-40e3-a453-2ea5370b5838
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750314244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.3750314244
Directory /workspace/37.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.otp_ctrl_check_fail.3450781945
Short name T1167
Test name
Test status
Simulation time 3565610519 ps
CPU time 42.67 seconds
Started Mar 28 03:33:03 PM PDT 24
Finished Mar 28 03:33:46 PM PDT 24
Peak memory 243292 kb
Host smart-eea07870-dc11-442a-bb67-622361ca8be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450781945 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.3450781945
Directory /workspace/37.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_errs.4243974466
Short name T518
Test name
Test status
Simulation time 585405710 ps
CPU time 8.06 seconds
Started Mar 28 03:33:03 PM PDT 24
Finished Mar 28 03:33:12 PM PDT 24
Peak memory 241508 kb
Host smart-28309662-a670-469e-b4e9-bdafa0a92a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243974466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.4243974466
Directory /workspace/37.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_lock.1120888791
Short name T742
Test name
Test status
Simulation time 817184895 ps
CPU time 11.65 seconds
Started Mar 28 03:33:00 PM PDT 24
Finished Mar 28 03:33:14 PM PDT 24
Peak memory 241632 kb
Host smart-ac0d196e-cf99-414d-9a77-b8ce571aa0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120888791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.1120888791
Directory /workspace/37.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/37.otp_ctrl_init_fail.1973851601
Short name T467
Test name
Test status
Simulation time 683906115 ps
CPU time 5.03 seconds
Started Mar 28 03:33:00 PM PDT 24
Finished Mar 28 03:33:07 PM PDT 24
Peak memory 241692 kb
Host smart-ab0cfdb0-4ca7-475b-9c11-6bcb82a03756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973851601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.1973851601
Directory /workspace/37.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_macro_errs.2497939785
Short name T1024
Test name
Test status
Simulation time 962959607 ps
CPU time 18.32 seconds
Started Mar 28 03:33:03 PM PDT 24
Finished Mar 28 03:33:22 PM PDT 24
Peak memory 242112 kb
Host smart-665870fb-8640-4102-9745-c4b55b44a07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497939785 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.2497939785
Directory /workspace/37.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_key_req.1603359784
Short name T1180
Test name
Test status
Simulation time 2626058922 ps
CPU time 19.04 seconds
Started Mar 28 03:33:02 PM PDT 24
Finished Mar 28 03:33:22 PM PDT 24
Peak memory 241584 kb
Host smart-b8646de4-313d-4c43-97bf-e081ba1651c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603359784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_key_req.1603359784
Directory /workspace/37.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_esc.1830868318
Short name T70
Test name
Test status
Simulation time 421812112 ps
CPU time 8.24 seconds
Started Mar 28 03:33:03 PM PDT 24
Finished Mar 28 03:33:12 PM PDT 24
Peak memory 241552 kb
Host smart-daa37959-a05e-4eff-b47a-6c1ecd4dcd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830868318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.1830868318
Directory /workspace/37.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_req.492365230
Short name T688
Test name
Test status
Simulation time 937508162 ps
CPU time 20.2 seconds
Started Mar 28 03:32:58 PM PDT 24
Finished Mar 28 03:33:22 PM PDT 24
Peak memory 241872 kb
Host smart-bc84c533-e338-404c-ad3b-0cbaac674f1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=492365230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.492365230
Directory /workspace/37.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_regwen.2097744777
Short name T831
Test name
Test status
Simulation time 132675191 ps
CPU time 4.97 seconds
Started Mar 28 03:33:01 PM PDT 24
Finished Mar 28 03:33:08 PM PDT 24
Peak memory 241720 kb
Host smart-c8b0ce8e-0349-408f-95ff-d36ef8196227
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2097744777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.2097744777
Directory /workspace/37.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/37.otp_ctrl_smoke.437844529
Short name T699
Test name
Test status
Simulation time 469878486 ps
CPU time 4.75 seconds
Started Mar 28 03:33:02 PM PDT 24
Finished Mar 28 03:33:08 PM PDT 24
Peak memory 241768 kb
Host smart-209cdf96-4d8b-4cd5-837d-1162d9d1f0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437844529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_smoke.437844529
Directory /workspace/37.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all.1204008784
Short name T665
Test name
Test status
Simulation time 819664584 ps
CPU time 34.08 seconds
Started Mar 28 03:32:56 PM PDT 24
Finished Mar 28 03:33:31 PM PDT 24
Peak memory 241708 kb
Host smart-119d46fa-3876-41b6-98a9-58fac324748c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204008784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all
.1204008784
Directory /workspace/37.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.otp_ctrl_test_access.1235998133
Short name T244
Test name
Test status
Simulation time 7241080847 ps
CPU time 17.52 seconds
Started Mar 28 03:33:01 PM PDT 24
Finished Mar 28 03:33:20 PM PDT 24
Peak memory 242524 kb
Host smart-f3b8bbb9-7e56-4743-bc34-e2de0a174cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235998133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.1235998133
Directory /workspace/37.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/38.otp_ctrl_alert_test.3437353031
Short name T1159
Test name
Test status
Simulation time 98846295 ps
CPU time 2.14 seconds
Started Mar 28 03:33:01 PM PDT 24
Finished Mar 28 03:33:05 PM PDT 24
Peak memory 240052 kb
Host smart-c6bd73f6-4cd5-4bbe-97f2-639043c456ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437353031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.3437353031
Directory /workspace/38.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.otp_ctrl_check_fail.3719781065
Short name T126
Test name
Test status
Simulation time 1118425772 ps
CPU time 21.26 seconds
Started Mar 28 03:33:05 PM PDT 24
Finished Mar 28 03:33:26 PM PDT 24
Peak memory 248616 kb
Host smart-6b81fd18-4a2d-436b-992d-e42b73db55b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719781065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.3719781065
Directory /workspace/38.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_errs.3684454179
Short name T141
Test name
Test status
Simulation time 994373807 ps
CPU time 16.01 seconds
Started Mar 28 03:33:04 PM PDT 24
Finished Mar 28 03:33:20 PM PDT 24
Peak memory 241768 kb
Host smart-c9da83c8-5fca-4706-ae16-482c7477bdb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684454179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_errs.3684454179
Directory /workspace/38.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_lock.3919021469
Short name T208
Test name
Test status
Simulation time 1146592366 ps
CPU time 20.26 seconds
Started Mar 28 03:33:01 PM PDT 24
Finished Mar 28 03:33:23 PM PDT 24
Peak memory 242044 kb
Host smart-3375a789-1173-4317-b2b0-0268bedc60e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919021469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_lock.3919021469
Directory /workspace/38.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/38.otp_ctrl_init_fail.253784508
Short name T569
Test name
Test status
Simulation time 111834890 ps
CPU time 3.77 seconds
Started Mar 28 03:33:01 PM PDT 24
Finished Mar 28 03:33:07 PM PDT 24
Peak memory 241696 kb
Host smart-ce6de237-7083-4663-b72e-526c463c9f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253784508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.253784508
Directory /workspace/38.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_macro_errs.922891587
Short name T904
Test name
Test status
Simulation time 444565885 ps
CPU time 5.86 seconds
Started Mar 28 03:33:03 PM PDT 24
Finished Mar 28 03:33:10 PM PDT 24
Peak memory 241708 kb
Host smart-32fc55ab-2482-435e-9b0e-bb27a8c18696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922891587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.922891587
Directory /workspace/38.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_key_req.2040411111
Short name T95
Test name
Test status
Simulation time 27700182822 ps
CPU time 78.02 seconds
Started Mar 28 03:33:05 PM PDT 24
Finished Mar 28 03:34:23 PM PDT 24
Peak memory 243032 kb
Host smart-1296b664-52fe-496f-87e7-bf9479671b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040411111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_key_req.2040411111
Directory /workspace/38.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_esc.1246472382
Short name T361
Test name
Test status
Simulation time 759981425 ps
CPU time 10.56 seconds
Started Mar 28 03:33:01 PM PDT 24
Finished Mar 28 03:33:14 PM PDT 24
Peak memory 242088 kb
Host smart-72bef793-ea6e-465d-8da1-9608e96b0e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246472382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.1246472382
Directory /workspace/38.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_req.747342268
Short name T757
Test name
Test status
Simulation time 1007802098 ps
CPU time 17.25 seconds
Started Mar 28 03:33:01 PM PDT 24
Finished Mar 28 03:33:20 PM PDT 24
Peak memory 241564 kb
Host smart-ac9824a4-9fd8-42a5-b87f-3aa04244c4ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=747342268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.747342268
Directory /workspace/38.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_regwen.3279728619
Short name T384
Test name
Test status
Simulation time 2163884548 ps
CPU time 9.39 seconds
Started Mar 28 03:32:59 PM PDT 24
Finished Mar 28 03:33:11 PM PDT 24
Peak memory 241616 kb
Host smart-4ea25a4b-8e8c-4b4c-a15c-25f738d7eee8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3279728619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.3279728619
Directory /workspace/38.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/38.otp_ctrl_smoke.886096730
Short name T87
Test name
Test status
Simulation time 2437776277 ps
CPU time 11 seconds
Started Mar 28 03:33:02 PM PDT 24
Finished Mar 28 03:33:14 PM PDT 24
Peak memory 241676 kb
Host smart-462a2aeb-1ee2-4d6f-86b2-319535b8636c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886096730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.886096730
Directory /workspace/38.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all.2770635569
Short name T369
Test name
Test status
Simulation time 7341299165 ps
CPU time 114.24 seconds
Started Mar 28 03:33:02 PM PDT 24
Finished Mar 28 03:34:57 PM PDT 24
Peak memory 248708 kb
Host smart-913fe4e9-7c37-484b-a130-88fc540aa3a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770635569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all
.2770635569
Directory /workspace/38.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all_with_rand_reset.769153943
Short name T150
Test name
Test status
Simulation time 677114294363 ps
CPU time 1506.24 seconds
Started Mar 28 03:33:05 PM PDT 24
Finished Mar 28 03:58:12 PM PDT 24
Peak memory 272952 kb
Host smart-6bc8b0c0-78ac-4968-b779-94cdd9b8aa83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769153943 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all_with_rand_reset.769153943
Directory /workspace/38.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.otp_ctrl_test_access.2569633768
Short name T788
Test name
Test status
Simulation time 311976376 ps
CPU time 4.28 seconds
Started Mar 28 03:33:05 PM PDT 24
Finished Mar 28 03:33:09 PM PDT 24
Peak memory 241984 kb
Host smart-202c08fe-071d-4752-beb2-5f8b2a33e0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569633768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.2569633768
Directory /workspace/38.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/39.otp_ctrl_alert_test.3504140739
Short name T438
Test name
Test status
Simulation time 171335305 ps
CPU time 1.66 seconds
Started Mar 28 03:33:06 PM PDT 24
Finished Mar 28 03:33:08 PM PDT 24
Peak memory 240036 kb
Host smart-10672464-91f9-48ea-95b1-af3f985f105a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504140739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.3504140739
Directory /workspace/39.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.otp_ctrl_check_fail.2274273805
Short name T821
Test name
Test status
Simulation time 8753810190 ps
CPU time 22.7 seconds
Started Mar 28 03:33:06 PM PDT 24
Finished Mar 28 03:33:29 PM PDT 24
Peak memory 244248 kb
Host smart-cd2b9d71-2edf-498d-aa77-c85220d280b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274273805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.2274273805
Directory /workspace/39.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_errs.3172971548
Short name T1046
Test name
Test status
Simulation time 1568735199 ps
CPU time 17.93 seconds
Started Mar 28 03:33:06 PM PDT 24
Finished Mar 28 03:33:24 PM PDT 24
Peak memory 241752 kb
Host smart-a9e6a801-b40e-4d5c-8543-1dd3938b466d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172971548 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.3172971548
Directory /workspace/39.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_lock.329524764
Short name T803
Test name
Test status
Simulation time 1838457875 ps
CPU time 9.6 seconds
Started Mar 28 03:33:08 PM PDT 24
Finished Mar 28 03:33:21 PM PDT 24
Peak memory 241752 kb
Host smart-95bee00b-a52f-43f0-8e4b-b57508ea80e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329524764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.329524764
Directory /workspace/39.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/39.otp_ctrl_init_fail.3351217510
Short name T191
Test name
Test status
Simulation time 274255117 ps
CPU time 3.68 seconds
Started Mar 28 03:32:59 PM PDT 24
Finished Mar 28 03:33:05 PM PDT 24
Peak memory 241864 kb
Host smart-6a82d4f3-baf6-4464-9a15-800880987148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351217510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.3351217510
Directory /workspace/39.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_macro_errs.2576518555
Short name T686
Test name
Test status
Simulation time 1771390726 ps
CPU time 5.56 seconds
Started Mar 28 03:33:10 PM PDT 24
Finished Mar 28 03:33:17 PM PDT 24
Peak memory 242252 kb
Host smart-5493c562-a536-478a-b191-2b99ad1a0c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576518555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_macro_errs.2576518555
Directory /workspace/39.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_key_req.198445508
Short name T912
Test name
Test status
Simulation time 1959002345 ps
CPU time 12.3 seconds
Started Mar 28 03:33:10 PM PDT 24
Finished Mar 28 03:33:23 PM PDT 24
Peak memory 241996 kb
Host smart-e0a169c8-80f3-4785-a0b3-8266f75e54dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198445508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.198445508
Directory /workspace/39.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_esc.3906720498
Short name T528
Test name
Test status
Simulation time 710082439 ps
CPU time 5.45 seconds
Started Mar 28 03:33:00 PM PDT 24
Finished Mar 28 03:33:08 PM PDT 24
Peak memory 242092 kb
Host smart-39084def-d009-4d82-b3f3-192ed62b3427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906720498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.3906720498
Directory /workspace/39.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_req.2962608240
Short name T1009
Test name
Test status
Simulation time 736888405 ps
CPU time 7.99 seconds
Started Mar 28 03:33:00 PM PDT 24
Finished Mar 28 03:33:10 PM PDT 24
Peak memory 241884 kb
Host smart-e5ecac28-98b1-4859-96a0-51fd36b1b105
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2962608240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.2962608240
Directory /workspace/39.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_regwen.3884773685
Short name T734
Test name
Test status
Simulation time 269149924 ps
CPU time 6.46 seconds
Started Mar 28 03:33:01 PM PDT 24
Finished Mar 28 03:33:09 PM PDT 24
Peak memory 241748 kb
Host smart-88077d43-6fb3-4f21-9836-10cef9dee342
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3884773685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.3884773685
Directory /workspace/39.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/39.otp_ctrl_smoke.1606439955
Short name T833
Test name
Test status
Simulation time 347114735 ps
CPU time 5.39 seconds
Started Mar 28 03:33:06 PM PDT 24
Finished Mar 28 03:33:11 PM PDT 24
Peak memory 241652 kb
Host smart-1fdaa2cd-c7ad-4870-92d1-c3b1040f3302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606439955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.1606439955
Directory /workspace/39.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all_with_rand_reset.3989227361
Short name T285
Test name
Test status
Simulation time 52807131448 ps
CPU time 944.83 seconds
Started Mar 28 03:33:09 PM PDT 24
Finished Mar 28 03:48:56 PM PDT 24
Peak memory 280256 kb
Host smart-10101701-25d1-426b-b253-402fbdeec953
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989227361 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all_with_rand_reset.3989227361
Directory /workspace/39.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.otp_ctrl_test_access.2372330726
Short name T526
Test name
Test status
Simulation time 10520425489 ps
CPU time 17.5 seconds
Started Mar 28 03:33:09 PM PDT 24
Finished Mar 28 03:33:29 PM PDT 24
Peak memory 241836 kb
Host smart-3e3b2603-e53e-4735-b137-ddf3c2ee7129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372330726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.2372330726
Directory /workspace/39.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/4.otp_ctrl_alert_test.3925740365
Short name T698
Test name
Test status
Simulation time 217945547 ps
CPU time 2.14 seconds
Started Mar 28 03:31:18 PM PDT 24
Finished Mar 28 03:31:20 PM PDT 24
Peak memory 240020 kb
Host smart-e98f16d1-a491-4ab6-ae91-d4483fcf8423
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925740365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.3925740365
Directory /workspace/4.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.otp_ctrl_background_chks.666277834
Short name T473
Test name
Test status
Simulation time 619469442 ps
CPU time 6.21 seconds
Started Mar 28 03:31:17 PM PDT 24
Finished Mar 28 03:31:23 PM PDT 24
Peak memory 241904 kb
Host smart-d9734cbf-cde9-442f-acab-48aa5c32dbc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666277834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.666277834
Directory /workspace/4.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/4.otp_ctrl_check_fail.944221999
Short name T57
Test name
Test status
Simulation time 4682195532 ps
CPU time 36.72 seconds
Started Mar 28 03:31:17 PM PDT 24
Finished Mar 28 03:31:54 PM PDT 24
Peak memory 243308 kb
Host smart-6db6c7a5-c52a-4a25-a0d8-1c63f1c0e21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944221999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.944221999
Directory /workspace/4.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_errs.2103431573
Short name T173
Test name
Test status
Simulation time 642357595 ps
CPU time 8.41 seconds
Started Mar 28 03:31:16 PM PDT 24
Finished Mar 28 03:31:24 PM PDT 24
Peak memory 242088 kb
Host smart-e17d2964-4c3f-40e9-84af-79d7833130fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103431573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.2103431573
Directory /workspace/4.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_lock.1242080219
Short name T446
Test name
Test status
Simulation time 1351039105 ps
CPU time 15.04 seconds
Started Mar 28 03:31:17 PM PDT 24
Finished Mar 28 03:31:33 PM PDT 24
Peak memory 241756 kb
Host smart-554e4ffb-287d-4856-af91-6cf0e803d514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242080219 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.1242080219
Directory /workspace/4.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/4.otp_ctrl_init_fail.927555252
Short name T237
Test name
Test status
Simulation time 2044706166 ps
CPU time 6.56 seconds
Started Mar 28 03:31:16 PM PDT 24
Finished Mar 28 03:31:23 PM PDT 24
Peak memory 242084 kb
Host smart-17fecb01-3c11-4b02-9a04-ddb243fc7400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927555252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.927555252
Directory /workspace/4.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_macro_errs.983897087
Short name T739
Test name
Test status
Simulation time 558544624 ps
CPU time 18.9 seconds
Started Mar 28 03:31:19 PM PDT 24
Finished Mar 28 03:31:39 PM PDT 24
Peak memory 242312 kb
Host smart-81671406-3237-43d8-a550-5b7666711f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983897087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.983897087
Directory /workspace/4.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_key_req.729056035
Short name T704
Test name
Test status
Simulation time 3177363138 ps
CPU time 32.21 seconds
Started Mar 28 03:31:17 PM PDT 24
Finished Mar 28 03:31:50 PM PDT 24
Peak memory 241944 kb
Host smart-dd9c09d9-7802-476f-a133-f10c2f8ce684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729056035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.729056035
Directory /workspace/4.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_esc.2366571472
Short name T967
Test name
Test status
Simulation time 161080082 ps
CPU time 4.01 seconds
Started Mar 28 03:31:15 PM PDT 24
Finished Mar 28 03:31:19 PM PDT 24
Peak memory 241824 kb
Host smart-997ebf54-d946-44dd-88e2-0cdcfce1af85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366571472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.2366571472
Directory /workspace/4.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_req.4233012895
Short name T619
Test name
Test status
Simulation time 985072655 ps
CPU time 17.57 seconds
Started Mar 28 03:31:17 PM PDT 24
Finished Mar 28 03:31:35 PM PDT 24
Peak memory 241700 kb
Host smart-67806804-f436-47b1-a028-1dd75f106de1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4233012895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.4233012895
Directory /workspace/4.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_regwen.3786391422
Short name T759
Test name
Test status
Simulation time 750673289 ps
CPU time 12.72 seconds
Started Mar 28 03:31:14 PM PDT 24
Finished Mar 28 03:31:27 PM PDT 24
Peak memory 241856 kb
Host smart-a295f11c-e8d8-4a47-9284-5ba54e047574
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3786391422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.3786391422
Directory /workspace/4.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/4.otp_ctrl_sec_cm.3073116291
Short name T247
Test name
Test status
Simulation time 24243427070 ps
CPU time 237.92 seconds
Started Mar 28 03:31:18 PM PDT 24
Finished Mar 28 03:35:17 PM PDT 24
Peak memory 279520 kb
Host smart-2a2c00aa-831f-4535-b7c0-76df4046e98c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073116291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.3073116291
Directory /workspace/4.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.otp_ctrl_smoke.1583100116
Short name T1048
Test name
Test status
Simulation time 1130512481 ps
CPU time 15.6 seconds
Started Mar 28 03:31:18 PM PDT 24
Finished Mar 28 03:31:35 PM PDT 24
Peak memory 241968 kb
Host smart-0bddc540-bc63-4151-9669-8eb6a98309df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583100116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.1583100116
Directory /workspace/4.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all.2461605329
Short name T233
Test name
Test status
Simulation time 16338621593 ps
CPU time 143.39 seconds
Started Mar 28 03:31:15 PM PDT 24
Finished Mar 28 03:33:38 PM PDT 24
Peak memory 259212 kb
Host smart-bab26278-141e-48be-811d-01c0ea2d2a02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461605329 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all.
2461605329
Directory /workspace/4.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.otp_ctrl_test_access.71897839
Short name T469
Test name
Test status
Simulation time 2263782210 ps
CPU time 18.81 seconds
Started Mar 28 03:31:18 PM PDT 24
Finished Mar 28 03:31:37 PM PDT 24
Peak memory 241800 kb
Host smart-5b75f241-708b-4513-aa92-ff7c1d8313d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71897839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.71897839
Directory /workspace/4.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/40.otp_ctrl_alert_test.2353660896
Short name T516
Test name
Test status
Simulation time 1008368615 ps
CPU time 2.6 seconds
Started Mar 28 03:33:18 PM PDT 24
Finished Mar 28 03:33:21 PM PDT 24
Peak memory 240056 kb
Host smart-50441aa4-e62e-4465-8cdd-fa46c3ca637f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353660896 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.2353660896
Directory /workspace/40.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.otp_ctrl_check_fail.3848437501
Short name T127
Test name
Test status
Simulation time 19579556400 ps
CPU time 29.27 seconds
Started Mar 28 03:32:59 PM PDT 24
Finished Mar 28 03:33:31 PM PDT 24
Peak memory 242192 kb
Host smart-0297387d-d880-4e17-bc9c-45713f0b0e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848437501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.3848437501
Directory /workspace/40.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_errs.3721743501
Short name T1179
Test name
Test status
Simulation time 186005205 ps
CPU time 10.18 seconds
Started Mar 28 03:33:05 PM PDT 24
Finished Mar 28 03:33:15 PM PDT 24
Peak memory 241420 kb
Host smart-9f2e8f7b-b468-4c6a-952d-296f97b623aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721743501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_errs.3721743501
Directory /workspace/40.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_lock.1023390673
Short name T24
Test name
Test status
Simulation time 889684581 ps
CPU time 23.2 seconds
Started Mar 28 03:32:58 PM PDT 24
Finished Mar 28 03:33:25 PM PDT 24
Peak memory 242024 kb
Host smart-ae3c4e02-8415-4171-8b31-f5cff3b80e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023390673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.1023390673
Directory /workspace/40.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/40.otp_ctrl_macro_errs.32345037
Short name T3
Test name
Test status
Simulation time 939556610 ps
CPU time 34.06 seconds
Started Mar 28 03:33:02 PM PDT 24
Finished Mar 28 03:33:38 PM PDT 24
Peak memory 246180 kb
Host smart-9aa7eb68-e357-4174-b02f-0cff51e394ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32345037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.32345037
Directory /workspace/40.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_key_req.1668608728
Short name T1113
Test name
Test status
Simulation time 843472575 ps
CPU time 22.59 seconds
Started Mar 28 03:32:59 PM PDT 24
Finished Mar 28 03:33:25 PM PDT 24
Peak memory 241772 kb
Host smart-d98106a8-e7ca-4587-aeb2-f8d58ae994fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668608728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_key_req.1668608728
Directory /workspace/40.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_esc.3384245227
Short name T440
Test name
Test status
Simulation time 154915042 ps
CPU time 4.58 seconds
Started Mar 28 03:32:58 PM PDT 24
Finished Mar 28 03:33:06 PM PDT 24
Peak memory 241644 kb
Host smart-096bf72b-9f57-47ee-ab9d-48f929755b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384245227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.3384245227
Directory /workspace/40.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_req.363988321
Short name T589
Test name
Test status
Simulation time 959479667 ps
CPU time 7.56 seconds
Started Mar 28 03:33:01 PM PDT 24
Finished Mar 28 03:33:10 PM PDT 24
Peak memory 241704 kb
Host smart-8b5c16ab-150f-40e6-a235-56e0228b1922
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=363988321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.363988321
Directory /workspace/40.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_regwen.3276005036
Short name T395
Test name
Test status
Simulation time 3753443762 ps
CPU time 10.33 seconds
Started Mar 28 03:33:00 PM PDT 24
Finished Mar 28 03:33:13 PM PDT 24
Peak memory 241960 kb
Host smart-553305e7-490f-488a-97c2-de583b96d373
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3276005036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.3276005036
Directory /workspace/40.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/40.otp_ctrl_smoke.530588613
Short name T413
Test name
Test status
Simulation time 453169996 ps
CPU time 4.4 seconds
Started Mar 28 03:32:59 PM PDT 24
Finished Mar 28 03:33:07 PM PDT 24
Peak memory 241892 kb
Host smart-6de1c125-33fd-4d32-86cc-c23c0a3be53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530588613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_smoke.530588613
Directory /workspace/40.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all.2919563073
Short name T232
Test name
Test status
Simulation time 51864565830 ps
CPU time 242.55 seconds
Started Mar 28 03:33:21 PM PDT 24
Finished Mar 28 03:37:26 PM PDT 24
Peak memory 297944 kb
Host smart-28121b5c-d519-4c99-831b-3ad69f7858e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919563073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all
.2919563073
Directory /workspace/40.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all_with_rand_reset.3502410837
Short name T857
Test name
Test status
Simulation time 100431030471 ps
CPU time 365.68 seconds
Started Mar 28 03:33:16 PM PDT 24
Finished Mar 28 03:39:22 PM PDT 24
Peak memory 277236 kb
Host smart-b5f7267e-7a18-43a9-ac5c-0739384ab45c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502410837 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all_with_rand_reset.3502410837
Directory /workspace/40.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.otp_ctrl_test_access.3415821752
Short name T981
Test name
Test status
Simulation time 1058565194 ps
CPU time 17.48 seconds
Started Mar 28 03:33:17 PM PDT 24
Finished Mar 28 03:33:34 PM PDT 24
Peak memory 241988 kb
Host smart-735d236d-935b-4b1f-8f1a-3d6ae0c9767e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415821752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.3415821752
Directory /workspace/40.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/41.otp_ctrl_alert_test.4003617596
Short name T710
Test name
Test status
Simulation time 161333729 ps
CPU time 1.89 seconds
Started Mar 28 03:33:20 PM PDT 24
Finished Mar 28 03:33:22 PM PDT 24
Peak memory 240092 kb
Host smart-65f86194-f052-4300-94f9-e20a4153f274
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003617596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.4003617596
Directory /workspace/41.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.otp_ctrl_check_fail.3241081061
Short name T59
Test name
Test status
Simulation time 2476864851 ps
CPU time 30.11 seconds
Started Mar 28 03:33:19 PM PDT 24
Finished Mar 28 03:33:49 PM PDT 24
Peak memory 242380 kb
Host smart-ac4af76c-0e2c-471b-b0bb-05d3a1cca8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241081061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.3241081061
Directory /workspace/41.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_errs.3235642490
Short name T174
Test name
Test status
Simulation time 428673424 ps
CPU time 21.56 seconds
Started Mar 28 03:33:22 PM PDT 24
Finished Mar 28 03:33:45 PM PDT 24
Peak memory 242128 kb
Host smart-fb1e1490-2a9e-47df-9245-9e2f18a1a28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235642490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_errs.3235642490
Directory /workspace/41.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_lock.2086349172
Short name T634
Test name
Test status
Simulation time 1751507034 ps
CPU time 11.68 seconds
Started Mar 28 03:33:22 PM PDT 24
Finished Mar 28 03:33:35 PM PDT 24
Peak memory 241620 kb
Host smart-12d0dc32-fb39-49d2-a6b5-f24978e34fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086349172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.2086349172
Directory /workspace/41.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/41.otp_ctrl_macro_errs.2369222340
Short name T971
Test name
Test status
Simulation time 11113670669 ps
CPU time 24.29 seconds
Started Mar 28 03:33:19 PM PDT 24
Finished Mar 28 03:33:43 PM PDT 24
Peak memory 245668 kb
Host smart-07103f56-0973-4795-858a-f81277433536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369222340 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.2369222340
Directory /workspace/41.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_key_req.102421943
Short name T1176
Test name
Test status
Simulation time 22443773233 ps
CPU time 56.42 seconds
Started Mar 28 03:33:20 PM PDT 24
Finished Mar 28 03:34:17 PM PDT 24
Peak memory 243244 kb
Host smart-82d3001a-50c9-45fb-b6dc-41812a85d43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102421943 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_key_req.102421943
Directory /workspace/41.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_esc.633972283
Short name T672
Test name
Test status
Simulation time 415054786 ps
CPU time 10.68 seconds
Started Mar 28 03:33:24 PM PDT 24
Finished Mar 28 03:33:35 PM PDT 24
Peak memory 241676 kb
Host smart-7b1b5d26-2c99-455e-b003-ded6b499b5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633972283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.633972283
Directory /workspace/41.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_req.408726033
Short name T407
Test name
Test status
Simulation time 10628189861 ps
CPU time 21.96 seconds
Started Mar 28 03:33:21 PM PDT 24
Finished Mar 28 03:33:46 PM PDT 24
Peak memory 242032 kb
Host smart-4d9f2454-64b6-4d8a-97f8-839938d0a760
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=408726033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.408726033
Directory /workspace/41.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_regwen.2469044411
Short name T724
Test name
Test status
Simulation time 243472762 ps
CPU time 3.32 seconds
Started Mar 28 03:33:21 PM PDT 24
Finished Mar 28 03:33:27 PM PDT 24
Peak memory 241828 kb
Host smart-b7b40ab0-fdcc-4e93-88fd-2fcc2c1170f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2469044411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.2469044411
Directory /workspace/41.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/41.otp_ctrl_smoke.1249897005
Short name T885
Test name
Test status
Simulation time 769051584 ps
CPU time 6.06 seconds
Started Mar 28 03:33:17 PM PDT 24
Finished Mar 28 03:33:23 PM PDT 24
Peak memory 241772 kb
Host smart-68cf6385-4974-428b-964f-3384a8514bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249897005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.1249897005
Directory /workspace/41.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/41.otp_ctrl_stress_all.2372600018
Short name T559
Test name
Test status
Simulation time 6489393447 ps
CPU time 23.06 seconds
Started Mar 28 03:33:22 PM PDT 24
Finished Mar 28 03:33:47 PM PDT 24
Peak memory 242612 kb
Host smart-2879e980-fa6a-4efd-9321-c12df0ace514
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372600018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all
.2372600018
Directory /workspace/41.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.otp_ctrl_stress_all_with_rand_reset.2934192326
Short name T411
Test name
Test status
Simulation time 158090135476 ps
CPU time 1443.25 seconds
Started Mar 28 03:33:22 PM PDT 24
Finished Mar 28 03:57:27 PM PDT 24
Peak memory 320044 kb
Host smart-4ab47566-1ae1-497e-beb4-b86d00a2af79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934192326 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all_with_rand_reset.2934192326
Directory /workspace/41.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.otp_ctrl_test_access.4235120226
Short name T116
Test name
Test status
Simulation time 1256952650 ps
CPU time 11.08 seconds
Started Mar 28 03:33:20 PM PDT 24
Finished Mar 28 03:33:31 PM PDT 24
Peak memory 241948 kb
Host smart-8884fdd0-8349-4092-a07e-8dbd1d9c11d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235120226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.4235120226
Directory /workspace/41.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/42.otp_ctrl_alert_test.1167904944
Short name T1053
Test name
Test status
Simulation time 48934403 ps
CPU time 1.62 seconds
Started Mar 28 03:33:18 PM PDT 24
Finished Mar 28 03:33:20 PM PDT 24
Peak memory 240044 kb
Host smart-e12b8f4e-c053-4f5d-b1cb-a6e765d15a66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167904944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.1167904944
Directory /workspace/42.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.otp_ctrl_check_fail.2830292352
Short name T1017
Test name
Test status
Simulation time 1177097958 ps
CPU time 16.87 seconds
Started Mar 28 03:33:21 PM PDT 24
Finished Mar 28 03:33:41 PM PDT 24
Peak memory 242036 kb
Host smart-20dd9112-55f8-4b67-8945-ee2222d17591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830292352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.2830292352
Directory /workspace/42.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_errs.1812786111
Short name T1161
Test name
Test status
Simulation time 382286594 ps
CPU time 9.04 seconds
Started Mar 28 03:33:20 PM PDT 24
Finished Mar 28 03:33:29 PM PDT 24
Peak memory 241412 kb
Host smart-a2704e92-8480-4747-b678-d1427e903d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812786111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_errs.1812786111
Directory /workspace/42.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_lock.1772498153
Short name T245
Test name
Test status
Simulation time 2148089971 ps
CPU time 29.88 seconds
Started Mar 28 03:33:20 PM PDT 24
Finished Mar 28 03:33:50 PM PDT 24
Peak memory 242288 kb
Host smart-168c2af2-a187-4cb0-8919-5124985a16a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772498153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.1772498153
Directory /workspace/42.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/42.otp_ctrl_init_fail.3481076788
Short name T1039
Test name
Test status
Simulation time 2217860988 ps
CPU time 6.68 seconds
Started Mar 28 03:33:18 PM PDT 24
Finished Mar 28 03:33:25 PM PDT 24
Peak memory 242084 kb
Host smart-ecfef276-428a-4a53-9baa-d0fdfa4e8906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481076788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.3481076788
Directory /workspace/42.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_macro_errs.2033743026
Short name T891
Test name
Test status
Simulation time 2267586235 ps
CPU time 28.3 seconds
Started Mar 28 03:33:19 PM PDT 24
Finished Mar 28 03:33:48 PM PDT 24
Peak memory 241776 kb
Host smart-253b1d90-c74c-4cd5-9628-ae57f18d850e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033743026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_macro_errs.2033743026
Directory /workspace/42.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_key_req.552732854
Short name T96
Test name
Test status
Simulation time 1964574528 ps
CPU time 41.25 seconds
Started Mar 28 03:33:20 PM PDT 24
Finished Mar 28 03:34:02 PM PDT 24
Peak memory 241908 kb
Host smart-0d04b36a-8c6f-405b-9aa9-7a631b16d450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552732854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.552732854
Directory /workspace/42.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_esc.2020559308
Short name T362
Test name
Test status
Simulation time 149810334 ps
CPU time 6.01 seconds
Started Mar 28 03:33:21 PM PDT 24
Finished Mar 28 03:33:30 PM PDT 24
Peak memory 241688 kb
Host smart-dddc50fd-99f6-49d8-bc60-30b255f9be56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020559308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.2020559308
Directory /workspace/42.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_req.3532509300
Short name T837
Test name
Test status
Simulation time 373029734 ps
CPU time 10.77 seconds
Started Mar 28 03:33:22 PM PDT 24
Finished Mar 28 03:33:35 PM PDT 24
Peak memory 241620 kb
Host smart-6449721d-2122-40b1-ac7a-4a06e74604af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3532509300 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.3532509300
Directory /workspace/42.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_regwen.895022378
Short name T1008
Test name
Test status
Simulation time 328640545 ps
CPU time 5.76 seconds
Started Mar 28 03:33:21 PM PDT 24
Finished Mar 28 03:33:30 PM PDT 24
Peak memory 242108 kb
Host smart-5e8b992c-a995-44ed-81a4-89f16df74356
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=895022378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.895022378
Directory /workspace/42.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/42.otp_ctrl_smoke.2017663621
Short name T783
Test name
Test status
Simulation time 4870175340 ps
CPU time 15.61 seconds
Started Mar 28 03:33:20 PM PDT 24
Finished Mar 28 03:33:36 PM PDT 24
Peak memory 241740 kb
Host smart-bd874afd-973c-4798-b4eb-47b5509ef781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017663621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_smoke.2017663621
Directory /workspace/42.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all.556402082
Short name T287
Test name
Test status
Simulation time 6026389330 ps
CPU time 21.31 seconds
Started Mar 28 03:33:18 PM PDT 24
Finished Mar 28 03:33:40 PM PDT 24
Peak memory 243060 kb
Host smart-f268e0ac-eccd-483b-9d94-1c168bf63e61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556402082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all.
556402082
Directory /workspace/42.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all_with_rand_reset.2316979508
Short name T1186
Test name
Test status
Simulation time 73721562830 ps
CPU time 1264.43 seconds
Started Mar 28 03:33:26 PM PDT 24
Finished Mar 28 03:54:31 PM PDT 24
Peak memory 359732 kb
Host smart-460fcce8-fcb3-4865-ba8f-ceca538be45d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316979508 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all_with_rand_reset.2316979508
Directory /workspace/42.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.otp_ctrl_test_access.2324369577
Short name T252
Test name
Test status
Simulation time 459581952 ps
CPU time 10.44 seconds
Started Mar 28 03:33:21 PM PDT 24
Finished Mar 28 03:33:34 PM PDT 24
Peak memory 248580 kb
Host smart-a9186bc0-5efb-496a-b2b4-73404602383e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324369577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.2324369577
Directory /workspace/42.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/43.otp_ctrl_alert_test.526363820
Short name T948
Test name
Test status
Simulation time 159903349 ps
CPU time 1.94 seconds
Started Mar 28 03:33:22 PM PDT 24
Finished Mar 28 03:33:26 PM PDT 24
Peak memory 240076 kb
Host smart-81364a8d-bbdc-43d6-a6f0-b9980c9ddf90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526363820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.526363820
Directory /workspace/43.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_errs.1675831737
Short name T756
Test name
Test status
Simulation time 1826289232 ps
CPU time 31.3 seconds
Started Mar 28 03:33:20 PM PDT 24
Finished Mar 28 03:33:51 PM PDT 24
Peak memory 244048 kb
Host smart-eb3f6022-2519-449f-853a-9524f440f372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675831737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.1675831737
Directory /workspace/43.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_lock.3472012136
Short name T441
Test name
Test status
Simulation time 18997087443 ps
CPU time 53.17 seconds
Started Mar 28 03:33:20 PM PDT 24
Finished Mar 28 03:34:13 PM PDT 24
Peak memory 243260 kb
Host smart-c57fccb9-7be6-4d43-96e8-52e2246f5a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472012136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_lock.3472012136
Directory /workspace/43.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/43.otp_ctrl_init_fail.4108487583
Short name T1026
Test name
Test status
Simulation time 387490973 ps
CPU time 4.23 seconds
Started Mar 28 03:33:20 PM PDT 24
Finished Mar 28 03:33:24 PM PDT 24
Peak memory 241600 kb
Host smart-6dd1a4d1-e772-42ad-8517-d5f8355947d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108487583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.4108487583
Directory /workspace/43.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_macro_errs.1340574437
Short name T1014
Test name
Test status
Simulation time 496178837 ps
CPU time 10.32 seconds
Started Mar 28 03:33:20 PM PDT 24
Finished Mar 28 03:33:31 PM PDT 24
Peak memory 241848 kb
Host smart-065ee0b8-4357-4cc2-9530-0be9ab6a331a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340574437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.1340574437
Directory /workspace/43.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_key_req.3550031066
Short name T766
Test name
Test status
Simulation time 2060939843 ps
CPU time 28.79 seconds
Started Mar 28 03:33:22 PM PDT 24
Finished Mar 28 03:33:53 PM PDT 24
Peak memory 242020 kb
Host smart-32d8ce31-2e41-495d-8ac2-242a596a3183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550031066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_key_req.3550031066
Directory /workspace/43.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_esc.1677433240
Short name T709
Test name
Test status
Simulation time 127581945 ps
CPU time 5.03 seconds
Started Mar 28 03:33:20 PM PDT 24
Finished Mar 28 03:33:25 PM PDT 24
Peak memory 241748 kb
Host smart-a712a9da-e92b-4943-b2be-e6ade43be7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677433240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.1677433240
Directory /workspace/43.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_req.2268424804
Short name T851
Test name
Test status
Simulation time 1480717682 ps
CPU time 17.8 seconds
Started Mar 28 03:33:21 PM PDT 24
Finished Mar 28 03:33:42 PM PDT 24
Peak memory 241900 kb
Host smart-3f28ff1f-f71f-48fc-aae8-3616f3dfbe3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2268424804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.2268424804
Directory /workspace/43.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_regwen.1844239660
Short name T1144
Test name
Test status
Simulation time 338687471 ps
CPU time 6.35 seconds
Started Mar 28 03:33:20 PM PDT 24
Finished Mar 28 03:33:27 PM PDT 24
Peak memory 241840 kb
Host smart-3e8f4a32-dff4-4025-9e82-0982cb6b0c6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1844239660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.1844239660
Directory /workspace/43.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/43.otp_ctrl_smoke.1182093639
Short name T448
Test name
Test status
Simulation time 473836656 ps
CPU time 9.76 seconds
Started Mar 28 03:33:18 PM PDT 24
Finished Mar 28 03:33:28 PM PDT 24
Peak memory 241904 kb
Host smart-efe0073b-2f6f-40d6-8c2b-91dcce11cd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182093639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_smoke.1182093639
Directory /workspace/43.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all_with_rand_reset.186230784
Short name T351
Test name
Test status
Simulation time 153390270265 ps
CPU time 1368.16 seconds
Started Mar 28 03:33:21 PM PDT 24
Finished Mar 28 03:56:12 PM PDT 24
Peak memory 315720 kb
Host smart-afd8cbdf-7b94-4bf1-a25d-c7324f67f0bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186230784 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all_with_rand_reset.186230784
Directory /workspace/43.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.otp_ctrl_test_access.1986241109
Short name T785
Test name
Test status
Simulation time 2020435990 ps
CPU time 24.9 seconds
Started Mar 28 03:33:19 PM PDT 24
Finished Mar 28 03:33:45 PM PDT 24
Peak memory 242164 kb
Host smart-2baa3b8f-ca2b-4a0e-b388-aea45ac720cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986241109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.1986241109
Directory /workspace/43.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/44.otp_ctrl_alert_test.888409895
Short name T615
Test name
Test status
Simulation time 843832326 ps
CPU time 2.27 seconds
Started Mar 28 03:33:18 PM PDT 24
Finished Mar 28 03:33:21 PM PDT 24
Peak memory 240164 kb
Host smart-6177fa07-081b-4745-858b-26231be81b9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888409895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.888409895
Directory /workspace/44.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.otp_ctrl_check_fail.780741743
Short name T239
Test name
Test status
Simulation time 2603452324 ps
CPU time 21.36 seconds
Started Mar 28 03:33:19 PM PDT 24
Finished Mar 28 03:33:41 PM PDT 24
Peak memory 242584 kb
Host smart-395f9b5d-2264-4a22-b3f3-e71c773b05e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780741743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_check_fail.780741743
Directory /workspace/44.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_errs.429476070
Short name T876
Test name
Test status
Simulation time 313822443 ps
CPU time 15.57 seconds
Started Mar 28 03:33:22 PM PDT 24
Finished Mar 28 03:33:39 PM PDT 24
Peak memory 241468 kb
Host smart-a22ab286-3251-4bd5-b39e-c9128216feea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429476070 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_errs.429476070
Directory /workspace/44.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_lock.3267240084
Short name T2
Test name
Test status
Simulation time 1637832555 ps
CPU time 21.77 seconds
Started Mar 28 03:33:19 PM PDT 24
Finished Mar 28 03:33:41 PM PDT 24
Peak memory 242532 kb
Host smart-5f951b63-c798-4e5c-9fd2-b119e11bdff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267240084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_lock.3267240084
Directory /workspace/44.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/44.otp_ctrl_init_fail.2279534329
Short name T956
Test name
Test status
Simulation time 122113038 ps
CPU time 3.82 seconds
Started Mar 28 03:33:20 PM PDT 24
Finished Mar 28 03:33:24 PM PDT 24
Peak memory 241808 kb
Host smart-315b5d10-8851-4f18-bb58-90bd79007ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279534329 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.2279534329
Directory /workspace/44.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_key_req.351459671
Short name T1021
Test name
Test status
Simulation time 161066867 ps
CPU time 7.1 seconds
Started Mar 28 03:33:24 PM PDT 24
Finished Mar 28 03:33:33 PM PDT 24
Peak memory 241640 kb
Host smart-ddeaf5ab-dc82-45e0-960a-9b71d9e2fda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351459671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.351459671
Directory /workspace/44.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_esc.3653588170
Short name T1165
Test name
Test status
Simulation time 12730612493 ps
CPU time 39.46 seconds
Started Mar 28 03:33:21 PM PDT 24
Finished Mar 28 03:34:03 PM PDT 24
Peak memory 241764 kb
Host smart-ca4ef86a-790d-492b-b559-70399c635ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653588170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.3653588170
Directory /workspace/44.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_req.2626417130
Short name T529
Test name
Test status
Simulation time 564792532 ps
CPU time 4.66 seconds
Started Mar 28 03:33:19 PM PDT 24
Finished Mar 28 03:33:24 PM PDT 24
Peak memory 241952 kb
Host smart-486d57da-6c7c-4627-9bb8-fccd419e007c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2626417130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.2626417130
Directory /workspace/44.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_regwen.1658999301
Short name T773
Test name
Test status
Simulation time 117877966 ps
CPU time 5.31 seconds
Started Mar 28 03:33:21 PM PDT 24
Finished Mar 28 03:33:29 PM PDT 24
Peak memory 241924 kb
Host smart-471480be-c104-471b-be26-77e56f22f411
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1658999301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.1658999301
Directory /workspace/44.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/44.otp_ctrl_smoke.1608916478
Short name T416
Test name
Test status
Simulation time 539095465 ps
CPU time 6.07 seconds
Started Mar 28 03:33:20 PM PDT 24
Finished Mar 28 03:33:26 PM PDT 24
Peak memory 242012 kb
Host smart-2c73ba7a-4305-4fc4-bad5-e0c8c09ca6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608916478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.1608916478
Directory /workspace/44.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all_with_rand_reset.2896260579
Short name T1135
Test name
Test status
Simulation time 320282958473 ps
CPU time 802.47 seconds
Started Mar 28 03:33:22 PM PDT 24
Finished Mar 28 03:46:47 PM PDT 24
Peak memory 256864 kb
Host smart-1cab34d9-66b9-4c00-97bc-df1db26baf7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896260579 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all_with_rand_reset.2896260579
Directory /workspace/44.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.otp_ctrl_test_access.3965356734
Short name T625
Test name
Test status
Simulation time 836461128 ps
CPU time 13.16 seconds
Started Mar 28 03:33:21 PM PDT 24
Finished Mar 28 03:33:37 PM PDT 24
Peak memory 241824 kb
Host smart-1ed73412-e097-4dab-a245-61454fa6623a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965356734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.3965356734
Directory /workspace/44.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/45.otp_ctrl_alert_test.3589777687
Short name T188
Test name
Test status
Simulation time 879053217 ps
CPU time 1.73 seconds
Started Mar 28 03:33:23 PM PDT 24
Finished Mar 28 03:33:26 PM PDT 24
Peak memory 240228 kb
Host smart-564008a2-9507-426e-a9cd-4d6c0fd834bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589777687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.3589777687
Directory /workspace/45.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.otp_ctrl_check_fail.1572838487
Short name T99
Test name
Test status
Simulation time 284871826 ps
CPU time 7.51 seconds
Started Mar 28 03:33:26 PM PDT 24
Finished Mar 28 03:33:33 PM PDT 24
Peak memory 242036 kb
Host smart-55614158-a989-4032-9fa1-3ee22fb0d607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572838487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.1572838487
Directory /workspace/45.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_errs.4011035068
Short name T470
Test name
Test status
Simulation time 494117029 ps
CPU time 17.61 seconds
Started Mar 28 03:33:26 PM PDT 24
Finished Mar 28 03:33:43 PM PDT 24
Peak memory 241924 kb
Host smart-e9627520-4edd-4fba-9457-0b0229098bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011035068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_errs.4011035068
Directory /workspace/45.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_lock.1928658078
Short name T345
Test name
Test status
Simulation time 1186503743 ps
CPU time 21.17 seconds
Started Mar 28 03:33:21 PM PDT 24
Finished Mar 28 03:33:45 PM PDT 24
Peak memory 241796 kb
Host smart-2cfc62e1-4989-4610-83b4-58224e2619b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928658078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.1928658078
Directory /workspace/45.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/45.otp_ctrl_init_fail.1845784277
Short name T1087
Test name
Test status
Simulation time 145038706 ps
CPU time 5.27 seconds
Started Mar 28 03:33:21 PM PDT 24
Finished Mar 28 03:33:29 PM PDT 24
Peak memory 241664 kb
Host smart-e1c7711e-8c9f-41f7-9da5-56ddae2cca55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845784277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.1845784277
Directory /workspace/45.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_macro_errs.2439352793
Short name T534
Test name
Test status
Simulation time 1527859106 ps
CPU time 26.57 seconds
Started Mar 28 03:33:24 PM PDT 24
Finished Mar 28 03:33:52 PM PDT 24
Peak memory 243192 kb
Host smart-445d6e34-c123-4fc6-b7b1-fcf8e4d3f7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439352793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.2439352793
Directory /workspace/45.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_key_req.3941044356
Short name T501
Test name
Test status
Simulation time 401202726 ps
CPU time 14.85 seconds
Started Mar 28 03:33:25 PM PDT 24
Finished Mar 28 03:33:41 PM PDT 24
Peak memory 241772 kb
Host smart-244e9205-e88a-431a-91f2-a860bd856b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941044356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_key_req.3941044356
Directory /workspace/45.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_esc.4108768108
Short name T152
Test name
Test status
Simulation time 534735497 ps
CPU time 12.88 seconds
Started Mar 28 03:33:24 PM PDT 24
Finished Mar 28 03:33:37 PM PDT 24
Peak memory 241760 kb
Host smart-4d4aeb2c-f8a9-472e-8c5e-86e98cee20c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108768108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.4108768108
Directory /workspace/45.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_req.1989193037
Short name T902
Test name
Test status
Simulation time 8408581901 ps
CPU time 19.28 seconds
Started Mar 28 03:33:26 PM PDT 24
Finished Mar 28 03:33:45 PM PDT 24
Peak memory 241876 kb
Host smart-bf41ca48-f838-41e3-9586-938fa45267b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1989193037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.1989193037
Directory /workspace/45.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_regwen.1665790933
Short name T954
Test name
Test status
Simulation time 191646714 ps
CPU time 6.93 seconds
Started Mar 28 03:33:21 PM PDT 24
Finished Mar 28 03:33:31 PM PDT 24
Peak memory 241800 kb
Host smart-319a3c29-d96b-4651-9b04-fd0196d5d4f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1665790933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.1665790933
Directory /workspace/45.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/45.otp_ctrl_smoke.2529585004
Short name T443
Test name
Test status
Simulation time 420376535 ps
CPU time 5.02 seconds
Started Mar 28 03:33:23 PM PDT 24
Finished Mar 28 03:33:29 PM PDT 24
Peak memory 241496 kb
Host smart-d1d0e40b-eb34-4574-8e85-fa988cbc8ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529585004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_smoke.2529585004
Directory /workspace/45.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all.3799720551
Short name T991
Test name
Test status
Simulation time 3930820283 ps
CPU time 141.93 seconds
Started Mar 28 03:33:22 PM PDT 24
Finished Mar 28 03:35:46 PM PDT 24
Peak memory 258088 kb
Host smart-7ef0a72e-d58e-40b1-9530-bd4291f60611
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799720551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all
.3799720551
Directory /workspace/45.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all_with_rand_reset.1653758762
Short name T1125
Test name
Test status
Simulation time 52719466480 ps
CPU time 532.53 seconds
Started Mar 28 03:33:24 PM PDT 24
Finished Mar 28 03:42:17 PM PDT 24
Peak memory 256896 kb
Host smart-746b5f53-64df-49b0-bcd9-a0cf544ca093
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653758762 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all_with_rand_reset.1653758762
Directory /workspace/45.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.otp_ctrl_test_access.4124914380
Short name T882
Test name
Test status
Simulation time 6022993737 ps
CPU time 42.88 seconds
Started Mar 28 03:33:19 PM PDT 24
Finished Mar 28 03:34:02 PM PDT 24
Peak memory 242028 kb
Host smart-fc87c220-13f0-43f1-a0b1-035f9f44675d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124914380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.4124914380
Directory /workspace/45.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/46.otp_ctrl_alert_test.2675455843
Short name T725
Test name
Test status
Simulation time 55207964 ps
CPU time 1.85 seconds
Started Mar 28 03:33:23 PM PDT 24
Finished Mar 28 03:33:26 PM PDT 24
Peak memory 240036 kb
Host smart-21df6afb-4ed1-49b7-a3d7-13523c76ac1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675455843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.2675455843
Directory /workspace/46.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.otp_ctrl_check_fail.1664767488
Short name T76
Test name
Test status
Simulation time 14906964116 ps
CPU time 35.78 seconds
Started Mar 28 03:33:25 PM PDT 24
Finished Mar 28 03:34:02 PM PDT 24
Peak memory 242252 kb
Host smart-16796563-d743-4bbe-991e-29a4c3dff4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664767488 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.1664767488
Directory /workspace/46.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_errs.2730156076
Short name T192
Test name
Test status
Simulation time 313670718 ps
CPU time 16.5 seconds
Started Mar 28 03:33:24 PM PDT 24
Finished Mar 28 03:33:42 PM PDT 24
Peak memory 241640 kb
Host smart-7494fe2b-1343-4fbb-8cea-a26f20c0bb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730156076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.2730156076
Directory /workspace/46.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_lock.796064786
Short name T401
Test name
Test status
Simulation time 570077705 ps
CPU time 15.85 seconds
Started Mar 28 03:33:21 PM PDT 24
Finished Mar 28 03:33:39 PM PDT 24
Peak memory 241688 kb
Host smart-3eff7012-ccc9-4e5d-bb5e-5fa8aee84c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796064786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.796064786
Directory /workspace/46.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/46.otp_ctrl_init_fail.693031249
Short name T940
Test name
Test status
Simulation time 161584917 ps
CPU time 4.57 seconds
Started Mar 28 03:33:24 PM PDT 24
Finished Mar 28 03:33:30 PM PDT 24
Peak memory 241744 kb
Host smart-b7785e03-43f5-4f03-b1dd-a24c3af31a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693031249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.693031249
Directory /workspace/46.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_macro_errs.1930332028
Short name T213
Test name
Test status
Simulation time 20500392029 ps
CPU time 93.7 seconds
Started Mar 28 03:33:21 PM PDT 24
Finished Mar 28 03:34:58 PM PDT 24
Peak memory 265156 kb
Host smart-9fa07515-489f-4eac-8fff-3031001e7c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930332028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_macro_errs.1930332028
Directory /workspace/46.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_key_req.4176658035
Short name T657
Test name
Test status
Simulation time 1152244916 ps
CPU time 23.42 seconds
Started Mar 28 03:33:22 PM PDT 24
Finished Mar 28 03:33:47 PM PDT 24
Peak memory 241848 kb
Host smart-30404395-d69c-484c-be10-19327616a0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176658035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_key_req.4176658035
Directory /workspace/46.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_esc.2564107397
Short name T555
Test name
Test status
Simulation time 235907348 ps
CPU time 5.48 seconds
Started Mar 28 03:33:23 PM PDT 24
Finished Mar 28 03:33:29 PM PDT 24
Peak memory 241548 kb
Host smart-765664d5-5796-4d2a-acfd-75c842dc25c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564107397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.2564107397
Directory /workspace/46.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/46.otp_ctrl_regwen.2704593877
Short name T389
Test name
Test status
Simulation time 190591048 ps
CPU time 5.93 seconds
Started Mar 28 03:33:23 PM PDT 24
Finished Mar 28 03:33:30 PM PDT 24
Peak memory 241696 kb
Host smart-f0492702-ca18-4fba-813a-b813d9d26696
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2704593877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.2704593877
Directory /workspace/46.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/46.otp_ctrl_smoke.1234262185
Short name T675
Test name
Test status
Simulation time 283949059 ps
CPU time 7.12 seconds
Started Mar 28 03:33:23 PM PDT 24
Finished Mar 28 03:33:31 PM PDT 24
Peak memory 241660 kb
Host smart-865e897d-f90d-42e5-aae9-d902f8d5877f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234262185 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_smoke.1234262185
Directory /workspace/46.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all.3139721227
Short name T1160
Test name
Test status
Simulation time 4613554001 ps
CPU time 165.42 seconds
Started Mar 28 03:33:22 PM PDT 24
Finished Mar 28 03:36:09 PM PDT 24
Peak memory 256916 kb
Host smart-719facf2-f692-4305-8ce5-059a73dbe7ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139721227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all
.3139721227
Directory /workspace/46.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all_with_rand_reset.3248667588
Short name T284
Test name
Test status
Simulation time 332535027030 ps
CPU time 1460.48 seconds
Started Mar 28 03:33:20 PM PDT 24
Finished Mar 28 03:57:41 PM PDT 24
Peak memory 332420 kb
Host smart-f65c0637-cef6-4f83-9ed5-49a9f0990a03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248667588 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all_with_rand_reset.3248667588
Directory /workspace/46.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.otp_ctrl_test_access.4026833203
Short name T1110
Test name
Test status
Simulation time 452897734 ps
CPU time 18.81 seconds
Started Mar 28 03:33:24 PM PDT 24
Finished Mar 28 03:33:45 PM PDT 24
Peak memory 241808 kb
Host smart-cf31be94-e4cd-41cd-a856-8034f202cf03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026833203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.4026833203
Directory /workspace/46.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/47.otp_ctrl_alert_test.1409200803
Short name T85
Test name
Test status
Simulation time 117549228 ps
CPU time 2.02 seconds
Started Mar 28 03:33:36 PM PDT 24
Finished Mar 28 03:33:38 PM PDT 24
Peak memory 240236 kb
Host smart-46e5c56c-320a-4610-80b7-34dff16afc6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409200803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.1409200803
Directory /workspace/47.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.otp_ctrl_check_fail.3871645654
Short name T652
Test name
Test status
Simulation time 1017972320 ps
CPU time 17.33 seconds
Started Mar 28 03:33:41 PM PDT 24
Finished Mar 28 03:33:58 PM PDT 24
Peak memory 242492 kb
Host smart-f6378a8f-39be-4e0e-9d7d-92496768d091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871645654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_check_fail.3871645654
Directory /workspace/47.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_errs.459377088
Short name T1029
Test name
Test status
Simulation time 24286255707 ps
CPU time 59.89 seconds
Started Mar 28 03:33:16 PM PDT 24
Finished Mar 28 03:34:16 PM PDT 24
Peak memory 256332 kb
Host smart-f7ae989a-26dd-48ff-86e3-cba0d6e5f0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459377088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_errs.459377088
Directory /workspace/47.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_lock.3584746318
Short name T456
Test name
Test status
Simulation time 1712915956 ps
CPU time 25.23 seconds
Started Mar 28 03:33:20 PM PDT 24
Finished Mar 28 03:33:46 PM PDT 24
Peak memory 242468 kb
Host smart-7709f31e-bf84-4e25-8673-c4dea66ddad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584746318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_lock.3584746318
Directory /workspace/47.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/47.otp_ctrl_init_fail.3756881832
Short name T849
Test name
Test status
Simulation time 128953088 ps
CPU time 4.32 seconds
Started Mar 28 03:33:22 PM PDT 24
Finished Mar 28 03:33:28 PM PDT 24
Peak memory 242044 kb
Host smart-e495ecc0-5af4-47cf-a9f4-8bc145cf7359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756881832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.3756881832
Directory /workspace/47.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_macro_errs.3319673408
Short name T822
Test name
Test status
Simulation time 834540873 ps
CPU time 8.97 seconds
Started Mar 28 03:33:37 PM PDT 24
Finished Mar 28 03:33:47 PM PDT 24
Peak memory 242144 kb
Host smart-2246524f-2e43-4d88-81ce-9192da0c3b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319673408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_macro_errs.3319673408
Directory /workspace/47.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_key_req.318968245
Short name T190
Test name
Test status
Simulation time 8034748899 ps
CPU time 22.17 seconds
Started Mar 28 03:33:40 PM PDT 24
Finished Mar 28 03:34:03 PM PDT 24
Peak memory 241756 kb
Host smart-fa2db6a2-e243-4655-bfa8-327279052731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318968245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.318968245
Directory /workspace/47.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_esc.2002171497
Short name T1011
Test name
Test status
Simulation time 7900616144 ps
CPU time 23.42 seconds
Started Mar 28 03:33:19 PM PDT 24
Finished Mar 28 03:33:43 PM PDT 24
Peak memory 241832 kb
Host smart-7e58c90e-c106-45a2-9ec9-f454fccb66e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002171497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.2002171497
Directory /workspace/47.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_req.3163057528
Short name T257
Test name
Test status
Simulation time 306027833 ps
CPU time 8.83 seconds
Started Mar 28 03:33:22 PM PDT 24
Finished Mar 28 03:33:33 PM PDT 24
Peak memory 241596 kb
Host smart-73bfa41a-077f-49c0-939c-5d98738b0df5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3163057528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.3163057528
Directory /workspace/47.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_regwen.203325837
Short name T387
Test name
Test status
Simulation time 213673404 ps
CPU time 7.64 seconds
Started Mar 28 03:33:39 PM PDT 24
Finished Mar 28 03:33:47 PM PDT 24
Peak memory 241960 kb
Host smart-f3ef376d-84f2-4504-8be1-61849e0a3a12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=203325837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.203325837
Directory /workspace/47.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/47.otp_ctrl_smoke.1129364199
Short name T1089
Test name
Test status
Simulation time 2751779879 ps
CPU time 5.79 seconds
Started Mar 28 03:33:19 PM PDT 24
Finished Mar 28 03:33:25 PM PDT 24
Peak memory 241848 kb
Host smart-5cfa0169-4fd1-4c30-88e8-b902aa51b2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129364199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_smoke.1129364199
Directory /workspace/47.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all.612646011
Short name T289
Test name
Test status
Simulation time 11254101879 ps
CPU time 72.28 seconds
Started Mar 28 03:33:41 PM PDT 24
Finished Mar 28 03:34:53 PM PDT 24
Peak memory 246312 kb
Host smart-69b2f5c5-14cc-498b-80da-7797bf141883
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612646011 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all.
612646011
Directory /workspace/47.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.otp_ctrl_test_access.1451983298
Short name T584
Test name
Test status
Simulation time 455367767 ps
CPU time 3.53 seconds
Started Mar 28 03:33:39 PM PDT 24
Finished Mar 28 03:33:43 PM PDT 24
Peak memory 241712 kb
Host smart-4629de52-676d-42d5-9ff8-c2da1f77120b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451983298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_test_access.1451983298
Directory /workspace/47.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/48.otp_ctrl_alert_test.975226839
Short name T839
Test name
Test status
Simulation time 225766795 ps
CPU time 3.29 seconds
Started Mar 28 03:33:41 PM PDT 24
Finished Mar 28 03:33:44 PM PDT 24
Peak memory 240208 kb
Host smart-dc89c557-b432-487a-9f9a-75c6852f3fd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975226839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.975226839
Directory /workspace/48.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_errs.3593895467
Short name T454
Test name
Test status
Simulation time 13616706797 ps
CPU time 32.45 seconds
Started Mar 28 03:33:38 PM PDT 24
Finished Mar 28 03:34:11 PM PDT 24
Peak memory 242452 kb
Host smart-6fc84a91-91a9-441a-b8da-a5058ceb344e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593895467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.3593895467
Directory /workspace/48.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_lock.27770667
Short name T791
Test name
Test status
Simulation time 15462387191 ps
CPU time 25.89 seconds
Started Mar 28 03:33:40 PM PDT 24
Finished Mar 28 03:34:06 PM PDT 24
Peak memory 242760 kb
Host smart-4b462397-e068-4293-b0fb-f3af3f044a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27770667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.27770667
Directory /workspace/48.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/48.otp_ctrl_init_fail.356687064
Short name T941
Test name
Test status
Simulation time 567632802 ps
CPU time 3.95 seconds
Started Mar 28 03:33:40 PM PDT 24
Finished Mar 28 03:33:44 PM PDT 24
Peak memory 242016 kb
Host smart-9c7865ed-e5b1-473a-9a34-3ebb574b2bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356687064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.356687064
Directory /workspace/48.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_macro_errs.1696946227
Short name T845
Test name
Test status
Simulation time 6504474181 ps
CPU time 84.48 seconds
Started Mar 28 03:33:37 PM PDT 24
Finished Mar 28 03:35:02 PM PDT 24
Peak memory 251704 kb
Host smart-72fe82a4-ba83-4f47-8b19-353b523a9389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696946227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_macro_errs.1696946227
Directory /workspace/48.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_key_req.268322980
Short name T452
Test name
Test status
Simulation time 1718642781 ps
CPU time 16.99 seconds
Started Mar 28 03:33:39 PM PDT 24
Finished Mar 28 03:33:57 PM PDT 24
Peak memory 241936 kb
Host smart-845aae24-61bf-42df-97be-c609f64ad767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268322980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_key_req.268322980
Directory /workspace/48.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_esc.437730805
Short name T843
Test name
Test status
Simulation time 843459842 ps
CPU time 11.74 seconds
Started Mar 28 03:33:36 PM PDT 24
Finished Mar 28 03:33:48 PM PDT 24
Peak memory 241680 kb
Host smart-55a74442-c111-49fb-85fd-48732abbcf1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437730805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.437730805
Directory /workspace/48.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_req.1245511439
Short name T484
Test name
Test status
Simulation time 2521821827 ps
CPU time 5.62 seconds
Started Mar 28 03:33:35 PM PDT 24
Finished Mar 28 03:33:41 PM PDT 24
Peak memory 241684 kb
Host smart-22cd07ae-27bb-45ca-8dcc-805d1113aa15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1245511439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.1245511439
Directory /workspace/48.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_regwen.1067935569
Short name T1059
Test name
Test status
Simulation time 203937907 ps
CPU time 4.02 seconds
Started Mar 28 03:33:40 PM PDT 24
Finished Mar 28 03:33:45 PM PDT 24
Peak memory 241704 kb
Host smart-acf589ae-f1a0-4cb1-a94f-dcdd0d0aa78f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1067935569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.1067935569
Directory /workspace/48.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/48.otp_ctrl_smoke.4181760978
Short name T825
Test name
Test status
Simulation time 571737247 ps
CPU time 10.33 seconds
Started Mar 28 03:33:38 PM PDT 24
Finished Mar 28 03:33:49 PM PDT 24
Peak memory 241628 kb
Host smart-758d78ef-3e11-4097-878b-fd620cbc4d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181760978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_smoke.4181760978
Directory /workspace/48.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all_with_rand_reset.2681852066
Short name T306
Test name
Test status
Simulation time 36045431769 ps
CPU time 1087 seconds
Started Mar 28 03:33:39 PM PDT 24
Finished Mar 28 03:51:46 PM PDT 24
Peak memory 260652 kb
Host smart-257fb62a-7e39-432e-b5d1-ea9048300944
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681852066 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all_with_rand_reset.2681852066
Directory /workspace/48.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.otp_ctrl_test_access.1242466828
Short name T403
Test name
Test status
Simulation time 2072612318 ps
CPU time 31.49 seconds
Started Mar 28 03:33:37 PM PDT 24
Finished Mar 28 03:34:09 PM PDT 24
Peak memory 242328 kb
Host smart-493e3aef-27fe-47c2-bc44-9b94fb3920ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242466828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_test_access.1242466828
Directory /workspace/48.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/49.otp_ctrl_alert_test.1885709110
Short name T869
Test name
Test status
Simulation time 221721522 ps
CPU time 1.9 seconds
Started Mar 28 03:33:39 PM PDT 24
Finished Mar 28 03:33:41 PM PDT 24
Peak memory 240128 kb
Host smart-e842e313-f068-4a95-9d02-fc86fbe758d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885709110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.1885709110
Directory /workspace/49.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.otp_ctrl_check_fail.2759436265
Short name T41
Test name
Test status
Simulation time 1275370324 ps
CPU time 19.02 seconds
Started Mar 28 03:33:41 PM PDT 24
Finished Mar 28 03:34:00 PM PDT 24
Peak memory 241972 kb
Host smart-05beb33e-da05-43fd-97b0-8180722500ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759436265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.2759436265
Directory /workspace/49.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_errs.1650296729
Short name T736
Test name
Test status
Simulation time 17759467689 ps
CPU time 39.81 seconds
Started Mar 28 03:33:40 PM PDT 24
Finished Mar 28 03:34:20 PM PDT 24
Peak memory 248100 kb
Host smart-04bf5f2c-c304-49ea-b6ce-9fa6129858a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650296729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_errs.1650296729
Directory /workspace/49.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_lock.3650585700
Short name T796
Test name
Test status
Simulation time 292656737 ps
CPU time 3.99 seconds
Started Mar 28 03:33:38 PM PDT 24
Finished Mar 28 03:33:43 PM PDT 24
Peak memory 241760 kb
Host smart-46d4dee3-9ebc-467c-8b9a-0644859ba74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650585700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_lock.3650585700
Directory /workspace/49.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/49.otp_ctrl_init_fail.555442598
Short name T648
Test name
Test status
Simulation time 2462619989 ps
CPU time 5.69 seconds
Started Mar 28 03:33:38 PM PDT 24
Finished Mar 28 03:33:45 PM PDT 24
Peak memory 241736 kb
Host smart-4e40b243-b818-41f1-a1a0-0c3a148bcbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555442598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.555442598
Directory /workspace/49.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_key_req.814298175
Short name T651
Test name
Test status
Simulation time 667436625 ps
CPU time 18.58 seconds
Started Mar 28 03:33:43 PM PDT 24
Finished Mar 28 03:34:02 PM PDT 24
Peak memory 241988 kb
Host smart-2b4d2d30-7d09-43ec-ac2a-532b939cbe77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814298175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.814298175
Directory /workspace/49.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_esc.219418635
Short name T746
Test name
Test status
Simulation time 331958047 ps
CPU time 7.97 seconds
Started Mar 28 03:33:39 PM PDT 24
Finished Mar 28 03:33:47 PM PDT 24
Peak memory 241708 kb
Host smart-e60d4a1d-212b-4f6a-83e1-1408ba9124f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219418635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.219418635
Directory /workspace/49.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_req.723328228
Short name T1025
Test name
Test status
Simulation time 5769075005 ps
CPU time 13.98 seconds
Started Mar 28 03:33:38 PM PDT 24
Finished Mar 28 03:33:53 PM PDT 24
Peak memory 241884 kb
Host smart-8c28b929-a04a-450a-9657-2bbbe13d3d82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=723328228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_req.723328228
Directory /workspace/49.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_regwen.2970809094
Short name T930
Test name
Test status
Simulation time 220055176 ps
CPU time 7.05 seconds
Started Mar 28 03:33:40 PM PDT 24
Finished Mar 28 03:33:48 PM PDT 24
Peak memory 242024 kb
Host smart-27ec2e58-53c9-45fd-9a2d-9cb69b4e9cf4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2970809094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.2970809094
Directory /workspace/49.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/49.otp_ctrl_smoke.1005242711
Short name T109
Test name
Test status
Simulation time 4417239157 ps
CPU time 11.24 seconds
Started Mar 28 03:33:43 PM PDT 24
Finished Mar 28 03:33:54 PM PDT 24
Peak memory 241848 kb
Host smart-18b7cc8f-2244-4ce9-a045-d5a9b72ac264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005242711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.1005242711
Directory /workspace/49.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all_with_rand_reset.3122575802
Short name T1155
Test name
Test status
Simulation time 7934019458 ps
CPU time 216.39 seconds
Started Mar 28 03:33:42 PM PDT 24
Finished Mar 28 03:37:19 PM PDT 24
Peak memory 256760 kb
Host smart-a8d4ac10-27b1-4dcc-ac49-c91e4ac012cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122575802 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all_with_rand_reset.3122575802
Directory /workspace/49.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.otp_ctrl_test_access.1222876811
Short name T1022
Test name
Test status
Simulation time 1455047776 ps
CPU time 14.19 seconds
Started Mar 28 03:33:42 PM PDT 24
Finished Mar 28 03:33:56 PM PDT 24
Peak memory 241712 kb
Host smart-b23b25e7-9e97-40e3-b3fb-ac2a6dc6c0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222876811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_test_access.1222876811
Directory /workspace/49.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/5.otp_ctrl_alert_test.2747159418
Short name T862
Test name
Test status
Simulation time 66998248 ps
CPU time 1.98 seconds
Started Mar 28 03:31:20 PM PDT 24
Finished Mar 28 03:31:23 PM PDT 24
Peak memory 240020 kb
Host smart-e266127f-1cf7-48f6-a144-4e54dd1a078c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747159418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.2747159418
Directory /workspace/5.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.otp_ctrl_background_chks.2144862582
Short name T863
Test name
Test status
Simulation time 1694340154 ps
CPU time 13.8 seconds
Started Mar 28 03:31:22 PM PDT 24
Finished Mar 28 03:31:37 PM PDT 24
Peak memory 242048 kb
Host smart-90de522f-7590-4c29-8752-8653e1894afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144862582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.2144862582
Directory /workspace/5.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/5.otp_ctrl_check_fail.325476293
Short name T132
Test name
Test status
Simulation time 818082931 ps
CPU time 20.27 seconds
Started Mar 28 03:31:15 PM PDT 24
Finished Mar 28 03:31:36 PM PDT 24
Peak memory 242744 kb
Host smart-66d37471-376f-4ba9-8e8f-b7501676439a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325476293 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.325476293
Directory /workspace/5.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_errs.4231465347
Short name T602
Test name
Test status
Simulation time 2508254082 ps
CPU time 8.9 seconds
Started Mar 28 03:31:19 PM PDT 24
Finished Mar 28 03:31:29 PM PDT 24
Peak memory 241864 kb
Host smart-d4ada6e2-15fa-4103-84cd-048f2ae8191f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231465347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.4231465347
Directory /workspace/5.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_lock.2617404311
Short name T836
Test name
Test status
Simulation time 6396096155 ps
CPU time 18.12 seconds
Started Mar 28 03:31:15 PM PDT 24
Finished Mar 28 03:31:33 PM PDT 24
Peak memory 248632 kb
Host smart-a5cc370d-874c-449b-9ee2-752cd35e6056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617404311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.2617404311
Directory /workspace/5.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/5.otp_ctrl_init_fail.638509121
Short name T824
Test name
Test status
Simulation time 424278289 ps
CPU time 4.66 seconds
Started Mar 28 03:31:17 PM PDT 24
Finished Mar 28 03:31:22 PM PDT 24
Peak memory 241824 kb
Host smart-5f334920-523d-4358-afdf-afc42cd1bfda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638509121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.638509121
Directory /workspace/5.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_macro_errs.2994302949
Short name T1035
Test name
Test status
Simulation time 2261792019 ps
CPU time 5.49 seconds
Started Mar 28 03:31:15 PM PDT 24
Finished Mar 28 03:31:21 PM PDT 24
Peak memory 241752 kb
Host smart-ba9f4f20-609b-4600-83f8-703850c25f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994302949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.2994302949
Directory /workspace/5.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_key_req.979758417
Short name T466
Test name
Test status
Simulation time 1693199884 ps
CPU time 12.27 seconds
Started Mar 28 03:31:18 PM PDT 24
Finished Mar 28 03:31:32 PM PDT 24
Peak memory 248536 kb
Host smart-f70f188e-6658-4643-868c-7402514777e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979758417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.979758417
Directory /workspace/5.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_esc.3447721874
Short name T944
Test name
Test status
Simulation time 186079488 ps
CPU time 7.01 seconds
Started Mar 28 03:31:17 PM PDT 24
Finished Mar 28 03:31:24 PM PDT 24
Peak memory 241708 kb
Host smart-55be8256-6577-466c-953e-81c940ce306b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447721874 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.3447721874
Directory /workspace/5.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_req.3440494028
Short name T1002
Test name
Test status
Simulation time 4282985362 ps
CPU time 9.17 seconds
Started Mar 28 03:31:16 PM PDT 24
Finished Mar 28 03:31:25 PM PDT 24
Peak memory 241860 kb
Host smart-58efc9b6-aa6d-46c0-b455-a659eec61394
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3440494028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.3440494028
Directory /workspace/5.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_regwen.3946565466
Short name T1154
Test name
Test status
Simulation time 527805598 ps
CPU time 5.02 seconds
Started Mar 28 03:31:19 PM PDT 24
Finished Mar 28 03:31:25 PM PDT 24
Peak memory 241848 kb
Host smart-34f90946-8b99-471c-bb77-14a1d7c13f50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3946565466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.3946565466
Directory /workspace/5.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/5.otp_ctrl_smoke.902374536
Short name T511
Test name
Test status
Simulation time 782394917 ps
CPU time 5.67 seconds
Started Mar 28 03:31:17 PM PDT 24
Finished Mar 28 03:31:22 PM PDT 24
Peak memory 241704 kb
Host smart-00644148-56c3-456b-92d9-834323db2c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902374536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.902374536
Directory /workspace/5.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all.3767193660
Short name T159
Test name
Test status
Simulation time 1149565552 ps
CPU time 19.46 seconds
Started Mar 28 03:31:17 PM PDT 24
Finished Mar 28 03:31:37 PM PDT 24
Peak memory 241832 kb
Host smart-3239288f-dfd9-4f9d-b4da-db86a4de84b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767193660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all.
3767193660
Directory /workspace/5.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all_with_rand_reset.1383873673
Short name T951
Test name
Test status
Simulation time 1106631162373 ps
CPU time 3896.47 seconds
Started Mar 28 03:31:18 PM PDT 24
Finished Mar 28 04:36:16 PM PDT 24
Peak memory 560100 kb
Host smart-56a495dc-299f-46a7-b64e-650259de9fc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383873673 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all_with_rand_reset.1383873673
Directory /workspace/5.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.otp_ctrl_test_access.2690951069
Short name T433
Test name
Test status
Simulation time 2093440436 ps
CPU time 22.81 seconds
Started Mar 28 03:31:14 PM PDT 24
Finished Mar 28 03:31:37 PM PDT 24
Peak memory 242036 kb
Host smart-71a6ef88-2e1a-48c7-9087-f80e86d9af85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690951069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.2690951069
Directory /workspace/5.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/50.otp_ctrl_init_fail.2460000459
Short name T1139
Test name
Test status
Simulation time 429677534 ps
CPU time 4.62 seconds
Started Mar 28 03:33:39 PM PDT 24
Finished Mar 28 03:33:44 PM PDT 24
Peak memory 241772 kb
Host smart-ecd2bf2e-b671-4ddc-9d74-eb783e965e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460000459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.2460000459
Directory /workspace/50.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/50.otp_ctrl_parallel_lc_esc.1501130194
Short name T274
Test name
Test status
Simulation time 117327841 ps
CPU time 5.53 seconds
Started Mar 28 03:33:40 PM PDT 24
Finished Mar 28 03:33:46 PM PDT 24
Peak memory 241512 kb
Host smart-62aa6266-db76-49c2-b7c5-62d9ba1dc903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501130194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.1501130194
Directory /workspace/50.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/50.otp_ctrl_stress_all_with_rand_reset.1557824127
Short name T682
Test name
Test status
Simulation time 72510425411 ps
CPU time 2100.84 seconds
Started Mar 28 03:33:40 PM PDT 24
Finished Mar 28 04:08:42 PM PDT 24
Peak memory 281732 kb
Host smart-5cd324e2-215f-43c5-b4ae-fc1e7755d270
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557824127 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_stress_all_with_rand_reset.1557824127
Directory /workspace/50.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.otp_ctrl_init_fail.2197679163
Short name T1054
Test name
Test status
Simulation time 613101054 ps
CPU time 5.24 seconds
Started Mar 28 03:33:43 PM PDT 24
Finished Mar 28 03:33:48 PM PDT 24
Peak memory 242076 kb
Host smart-d774ef3d-8b32-4f3a-a329-b0be9ba34ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197679163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.2197679163
Directory /workspace/51.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/51.otp_ctrl_parallel_lc_esc.1215860719
Short name T552
Test name
Test status
Simulation time 16425237690 ps
CPU time 42.74 seconds
Started Mar 28 03:33:39 PM PDT 24
Finished Mar 28 03:34:22 PM PDT 24
Peak memory 242104 kb
Host smart-164604a4-d34a-4e5a-97fe-7c87c884eec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215860719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.1215860719
Directory /workspace/51.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/51.otp_ctrl_stress_all_with_rand_reset.273940105
Short name T453
Test name
Test status
Simulation time 162218924537 ps
CPU time 1479.69 seconds
Started Mar 28 03:33:42 PM PDT 24
Finished Mar 28 03:58:21 PM PDT 24
Peak memory 484048 kb
Host smart-0f5c04ff-fc0e-49fe-a745-8c905b495f73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273940105 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_stress_all_with_rand_reset.273940105
Directory /workspace/51.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.otp_ctrl_init_fail.3990340840
Short name T578
Test name
Test status
Simulation time 122517503 ps
CPU time 4.63 seconds
Started Mar 28 03:33:43 PM PDT 24
Finished Mar 28 03:33:48 PM PDT 24
Peak memory 242020 kb
Host smart-70cd54e5-0bdc-4bef-977b-4a46ed19b1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990340840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.3990340840
Directory /workspace/52.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/52.otp_ctrl_parallel_lc_esc.2148122283
Short name T320
Test name
Test status
Simulation time 594812819 ps
CPU time 7.28 seconds
Started Mar 28 03:33:38 PM PDT 24
Finished Mar 28 03:33:46 PM PDT 24
Peak memory 241020 kb
Host smart-71f2a2dd-efc3-435f-8e50-495ecc2fe01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148122283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.2148122283
Directory /workspace/52.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/52.otp_ctrl_stress_all_with_rand_reset.2424190178
Short name T1129
Test name
Test status
Simulation time 176213787285 ps
CPU time 764.36 seconds
Started Mar 28 03:33:42 PM PDT 24
Finished Mar 28 03:46:27 PM PDT 24
Peak memory 273124 kb
Host smart-e6b6f475-946a-4ecd-9873-c69b1639e5c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424190178 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_stress_all_with_rand_reset.2424190178
Directory /workspace/52.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.otp_ctrl_init_fail.2320427463
Short name T723
Test name
Test status
Simulation time 449358516 ps
CPU time 4.98 seconds
Started Mar 28 03:33:41 PM PDT 24
Finished Mar 28 03:33:46 PM PDT 24
Peak memory 241648 kb
Host smart-6b46db7d-84ef-49bf-a8a8-ec1ed40d01fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320427463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.2320427463
Directory /workspace/53.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/53.otp_ctrl_parallel_lc_esc.2381237142
Short name T683
Test name
Test status
Simulation time 664828795 ps
CPU time 7.86 seconds
Started Mar 28 03:33:41 PM PDT 24
Finished Mar 28 03:33:49 PM PDT 24
Peak memory 241704 kb
Host smart-8d9d9464-2973-4d01-bd37-2750a98412c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381237142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.2381237142
Directory /workspace/53.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/54.otp_ctrl_init_fail.54910127
Short name T218
Test name
Test status
Simulation time 539394955 ps
CPU time 4.39 seconds
Started Mar 28 03:33:38 PM PDT 24
Finished Mar 28 03:33:43 PM PDT 24
Peak memory 240984 kb
Host smart-3933fa73-5b0e-413a-afc9-dd8078f09574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54910127 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.54910127
Directory /workspace/54.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/54.otp_ctrl_parallel_lc_esc.2981491897
Short name T988
Test name
Test status
Simulation time 3719890224 ps
CPU time 8.3 seconds
Started Mar 28 03:33:41 PM PDT 24
Finished Mar 28 03:33:49 PM PDT 24
Peak memory 241888 kb
Host smart-116b1510-8bf6-4fe1-9d54-b0bd5151ca61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981491897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.2981491897
Directory /workspace/54.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/54.otp_ctrl_stress_all_with_rand_reset.2930325206
Short name T299
Test name
Test status
Simulation time 252002734315 ps
CPU time 1543.1 seconds
Started Mar 28 03:33:50 PM PDT 24
Finished Mar 28 03:59:34 PM PDT 24
Peak memory 330756 kb
Host smart-a1768295-e2fa-42d8-a22b-9cc5ab7dd892
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930325206 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_stress_all_with_rand_reset.2930325206
Directory /workspace/54.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.otp_ctrl_init_fail.3393268875
Short name T809
Test name
Test status
Simulation time 1639946429 ps
CPU time 4.12 seconds
Started Mar 28 03:33:40 PM PDT 24
Finished Mar 28 03:33:45 PM PDT 24
Peak memory 242056 kb
Host smart-3d230a38-c175-47c9-9f97-44e959186333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393268875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.3393268875
Directory /workspace/55.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/55.otp_ctrl_parallel_lc_esc.1255185200
Short name T646
Test name
Test status
Simulation time 922339345 ps
CPU time 7.76 seconds
Started Mar 28 03:33:41 PM PDT 24
Finished Mar 28 03:33:49 PM PDT 24
Peak memory 241896 kb
Host smart-72e63007-4819-4265-b8a9-573b8abbccf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255185200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.1255185200
Directory /workspace/55.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/55.otp_ctrl_stress_all_with_rand_reset.3558329204
Short name T339
Test name
Test status
Simulation time 16866989034 ps
CPU time 281.61 seconds
Started Mar 28 03:33:42 PM PDT 24
Finished Mar 28 03:38:25 PM PDT 24
Peak memory 256812 kb
Host smart-dad6eb86-0cfd-4156-ba4c-5184a38ba69a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558329204 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_stress_all_with_rand_reset.3558329204
Directory /workspace/55.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.otp_ctrl_init_fail.803455481
Short name T1131
Test name
Test status
Simulation time 285281401 ps
CPU time 4.19 seconds
Started Mar 28 03:33:38 PM PDT 24
Finished Mar 28 03:33:43 PM PDT 24
Peak memory 241940 kb
Host smart-2d09edc5-0d04-4542-8f5e-ef175adb8ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803455481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.803455481
Directory /workspace/56.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/56.otp_ctrl_parallel_lc_esc.2415331061
Short name T779
Test name
Test status
Simulation time 4428076235 ps
CPU time 30.08 seconds
Started Mar 28 03:33:42 PM PDT 24
Finished Mar 28 03:34:12 PM PDT 24
Peak memory 242244 kb
Host smart-80adf066-2129-42cb-8502-a35d45005745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415331061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.2415331061
Directory /workspace/56.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/57.otp_ctrl_init_fail.2135449884
Short name T1096
Test name
Test status
Simulation time 85810222 ps
CPU time 3.44 seconds
Started Mar 28 03:33:37 PM PDT 24
Finished Mar 28 03:33:41 PM PDT 24
Peak memory 241608 kb
Host smart-3329958e-29d0-4c63-93db-24861d048f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135449884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.2135449884
Directory /workspace/57.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/57.otp_ctrl_parallel_lc_esc.380087703
Short name T182
Test name
Test status
Simulation time 301134746 ps
CPU time 8.28 seconds
Started Mar 28 03:33:40 PM PDT 24
Finished Mar 28 03:33:49 PM PDT 24
Peak memory 241756 kb
Host smart-f4237d36-1106-49c4-96b4-cd000be81509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380087703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.380087703
Directory /workspace/57.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/58.otp_ctrl_init_fail.2833566398
Short name T220
Test name
Test status
Simulation time 159471166 ps
CPU time 3.73 seconds
Started Mar 28 03:33:43 PM PDT 24
Finished Mar 28 03:33:47 PM PDT 24
Peak memory 242064 kb
Host smart-7fadfcf9-c26f-47f0-82b4-5c63563ebe56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833566398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.2833566398
Directory /workspace/58.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/58.otp_ctrl_parallel_lc_esc.2570957304
Short name T913
Test name
Test status
Simulation time 136470454 ps
CPU time 3.82 seconds
Started Mar 28 03:33:46 PM PDT 24
Finished Mar 28 03:33:50 PM PDT 24
Peak memory 241668 kb
Host smart-0aa49b03-636f-4ae9-9a3c-112b6936560d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570957304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.2570957304
Directory /workspace/58.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/58.otp_ctrl_stress_all_with_rand_reset.3219266765
Short name T677
Test name
Test status
Simulation time 158411110244 ps
CPU time 3318.8 seconds
Started Mar 28 03:33:46 PM PDT 24
Finished Mar 28 04:29:06 PM PDT 24
Peak memory 604732 kb
Host smart-8cf3862b-9e81-41d3-8f19-251f935f866e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219266765 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_stress_all_with_rand_reset.3219266765
Directory /workspace/58.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.otp_ctrl_init_fail.3207398933
Short name T832
Test name
Test status
Simulation time 460458922 ps
CPU time 4.77 seconds
Started Mar 28 03:33:37 PM PDT 24
Finished Mar 28 03:33:42 PM PDT 24
Peak memory 241992 kb
Host smart-4cc0cb36-1637-4983-9c49-fbac866972d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207398933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.3207398933
Directory /workspace/59.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/59.otp_ctrl_parallel_lc_esc.1588949427
Short name T562
Test name
Test status
Simulation time 2535395060 ps
CPU time 10.15 seconds
Started Mar 28 03:33:38 PM PDT 24
Finished Mar 28 03:33:49 PM PDT 24
Peak memory 241604 kb
Host smart-303725e3-ac99-47b0-bc24-2535e28af081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588949427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.1588949427
Directory /workspace/59.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/59.otp_ctrl_stress_all_with_rand_reset.3634622208
Short name T406
Test name
Test status
Simulation time 69253656538 ps
CPU time 565.84 seconds
Started Mar 28 03:33:41 PM PDT 24
Finished Mar 28 03:43:07 PM PDT 24
Peak memory 258436 kb
Host smart-dca8c680-b34b-4047-81e6-8b8204731809
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634622208 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_stress_all_with_rand_reset.3634622208
Directory /workspace/59.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.otp_ctrl_alert_test.2012041933
Short name T415
Test name
Test status
Simulation time 63469459 ps
CPU time 1.86 seconds
Started Mar 28 03:31:22 PM PDT 24
Finished Mar 28 03:31:26 PM PDT 24
Peak memory 240108 kb
Host smart-226c4c89-48a2-48c1-a453-ee67b9720b3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012041933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.2012041933
Directory /workspace/6.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.otp_ctrl_background_chks.2068268805
Short name T804
Test name
Test status
Simulation time 2699049141 ps
CPU time 19.66 seconds
Started Mar 28 03:31:17 PM PDT 24
Finished Mar 28 03:31:37 PM PDT 24
Peak memory 242704 kb
Host smart-03a6632b-3ac6-4efe-8cd6-7db375f0f545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068268805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.2068268805
Directory /workspace/6.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/6.otp_ctrl_check_fail.4018011269
Short name T25
Test name
Test status
Simulation time 1487828473 ps
CPU time 27.34 seconds
Started Mar 28 03:31:16 PM PDT 24
Finished Mar 28 03:31:43 PM PDT 24
Peak memory 245072 kb
Host smart-cee495a8-28f3-427c-9f0c-5efeec488c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018011269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.4018011269
Directory /workspace/6.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_errs.4034109766
Short name T751
Test name
Test status
Simulation time 3662101805 ps
CPU time 20.04 seconds
Started Mar 28 03:31:19 PM PDT 24
Finished Mar 28 03:31:40 PM PDT 24
Peak memory 241980 kb
Host smart-5230fcee-766b-4115-81dc-311a922c0c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034109766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.4034109766
Directory /workspace/6.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_lock.2757527389
Short name T732
Test name
Test status
Simulation time 5548775318 ps
CPU time 15 seconds
Started Mar 28 03:31:19 PM PDT 24
Finished Mar 28 03:31:35 PM PDT 24
Peak memory 241704 kb
Host smart-4ee98e92-8abd-4a1c-b4ac-0652188c82d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757527389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.2757527389
Directory /workspace/6.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/6.otp_ctrl_macro_errs.1234291779
Short name T215
Test name
Test status
Simulation time 3881770717 ps
CPU time 32.54 seconds
Started Mar 28 03:31:22 PM PDT 24
Finished Mar 28 03:31:56 PM PDT 24
Peak memory 248080 kb
Host smart-54bd80c9-9b75-4a08-8405-f274bdae60b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234291779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.1234291779
Directory /workspace/6.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_key_req.2945997549
Short name T947
Test name
Test status
Simulation time 3404424519 ps
CPU time 44.87 seconds
Started Mar 28 03:31:21 PM PDT 24
Finished Mar 28 03:32:08 PM PDT 24
Peak memory 241860 kb
Host smart-bb496d71-d1fd-4bec-ac25-5197523883b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945997549 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.2945997549
Directory /workspace/6.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_esc.194341252
Short name T122
Test name
Test status
Simulation time 394701234 ps
CPU time 9.9 seconds
Started Mar 28 03:31:20 PM PDT 24
Finished Mar 28 03:31:30 PM PDT 24
Peak memory 241816 kb
Host smart-ec61984c-f62f-4ab2-8d3a-18dcb292ba3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194341252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.194341252
Directory /workspace/6.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_req.3390858244
Short name T859
Test name
Test status
Simulation time 10208863414 ps
CPU time 24.1 seconds
Started Mar 28 03:31:17 PM PDT 24
Finished Mar 28 03:31:41 PM PDT 24
Peak memory 241712 kb
Host smart-8fcc04c2-73e2-4a5e-833a-8b717da6713d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3390858244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.3390858244
Directory /workspace/6.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_regwen.3893009263
Short name T852
Test name
Test status
Simulation time 3042398297 ps
CPU time 9.42 seconds
Started Mar 28 03:31:16 PM PDT 24
Finished Mar 28 03:31:26 PM PDT 24
Peak memory 242004 kb
Host smart-97b71b51-842e-45ee-982e-4dab07fcdc12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3893009263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.3893009263
Directory /workspace/6.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/6.otp_ctrl_smoke.2746945416
Short name T424
Test name
Test status
Simulation time 545246905 ps
CPU time 7.32 seconds
Started Mar 28 03:31:17 PM PDT 24
Finished Mar 28 03:31:24 PM PDT 24
Peak memory 248476 kb
Host smart-418596fd-27e9-4f3e-88a0-87cab9daec78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746945416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.2746945416
Directory /workspace/6.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all.2596980953
Short name T570
Test name
Test status
Simulation time 28953016054 ps
CPU time 217.66 seconds
Started Mar 28 03:31:18 PM PDT 24
Finished Mar 28 03:34:56 PM PDT 24
Peak memory 266876 kb
Host smart-5f62a9d5-0af6-4008-8d03-edc88595eb34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596980953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all.
2596980953
Directory /workspace/6.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all_with_rand_reset.437719866
Short name T703
Test name
Test status
Simulation time 624203178627 ps
CPU time 1337.96 seconds
Started Mar 28 03:31:16 PM PDT 24
Finished Mar 28 03:53:34 PM PDT 24
Peak memory 365012 kb
Host smart-d208a757-4837-437a-a515-41a019c78b74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437719866 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all_with_rand_reset.437719866
Directory /workspace/6.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.otp_ctrl_test_access.2702595305
Short name T439
Test name
Test status
Simulation time 8724802287 ps
CPU time 34.97 seconds
Started Mar 28 03:31:20 PM PDT 24
Finished Mar 28 03:31:57 PM PDT 24
Peak memory 243036 kb
Host smart-00e057e7-dc6e-402e-a7df-edae2c3317a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702595305 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.2702595305
Directory /workspace/6.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/60.otp_ctrl_init_fail.4173063971
Short name T506
Test name
Test status
Simulation time 143211453 ps
CPU time 4.89 seconds
Started Mar 28 03:33:42 PM PDT 24
Finished Mar 28 03:33:48 PM PDT 24
Peak memory 241680 kb
Host smart-ff68f058-e4b2-49af-a335-072d0687f898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173063971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.4173063971
Directory /workspace/60.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/60.otp_ctrl_stress_all_with_rand_reset.448760757
Short name T291
Test name
Test status
Simulation time 28574577511 ps
CPU time 779.44 seconds
Started Mar 28 03:33:42 PM PDT 24
Finished Mar 28 03:46:42 PM PDT 24
Peak memory 248780 kb
Host smart-100cf77a-dd7a-4e30-bb51-a722ee812859
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448760757 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_stress_all_with_rand_reset.448760757
Directory /workspace/60.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.otp_ctrl_init_fail.3411826078
Short name T1164
Test name
Test status
Simulation time 142794953 ps
CPU time 4.74 seconds
Started Mar 28 03:33:42 PM PDT 24
Finished Mar 28 03:33:47 PM PDT 24
Peak memory 242004 kb
Host smart-6162ec3e-925a-46dc-a98d-72dbfc2d047b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411826078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.3411826078
Directory /workspace/61.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/61.otp_ctrl_parallel_lc_esc.4071010212
Short name T1172
Test name
Test status
Simulation time 786803015 ps
CPU time 11.08 seconds
Started Mar 28 03:33:47 PM PDT 24
Finished Mar 28 03:33:58 PM PDT 24
Peak memory 241700 kb
Host smart-ff785509-2c98-413f-922b-78dc65a697cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071010212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.4071010212
Directory /workspace/61.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/61.otp_ctrl_stress_all_with_rand_reset.4051574984
Short name T298
Test name
Test status
Simulation time 987269637567 ps
CPU time 1881.73 seconds
Started Mar 28 03:33:41 PM PDT 24
Finished Mar 28 04:05:03 PM PDT 24
Peak memory 256884 kb
Host smart-ef52fc5e-fcc8-4836-ac1e-703bffc9743f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051574984 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_stress_all_with_rand_reset.4051574984
Directory /workspace/61.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.otp_ctrl_init_fail.3075062837
Short name T655
Test name
Test status
Simulation time 167376752 ps
CPU time 4.1 seconds
Started Mar 28 03:33:41 PM PDT 24
Finished Mar 28 03:33:45 PM PDT 24
Peak memory 241724 kb
Host smart-ef6e5e6d-73fa-448b-8bf3-b41fbbafeec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075062837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.3075062837
Directory /workspace/62.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/62.otp_ctrl_stress_all_with_rand_reset.3645340873
Short name T654
Test name
Test status
Simulation time 332518770886 ps
CPU time 2073.28 seconds
Started Mar 28 03:33:42 PM PDT 24
Finished Mar 28 04:08:16 PM PDT 24
Peak memory 298480 kb
Host smart-d43a9b0d-5638-40eb-8d09-1974876cb9e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645340873 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_stress_all_with_rand_reset.3645340873
Directory /workspace/62.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.otp_ctrl_init_fail.2091644281
Short name T1005
Test name
Test status
Simulation time 518576408 ps
CPU time 4.34 seconds
Started Mar 28 03:33:37 PM PDT 24
Finished Mar 28 03:33:42 PM PDT 24
Peak memory 242076 kb
Host smart-215076ff-0dbc-4abe-a0d6-b94fe22abfa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091644281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.2091644281
Directory /workspace/63.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/63.otp_ctrl_parallel_lc_esc.2314596816
Short name T1073
Test name
Test status
Simulation time 772556440 ps
CPU time 6.4 seconds
Started Mar 28 03:33:40 PM PDT 24
Finished Mar 28 03:33:47 PM PDT 24
Peak memory 241644 kb
Host smart-0e4534c6-5817-4817-ba08-850166297252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314596816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.2314596816
Directory /workspace/63.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/64.otp_ctrl_init_fail.4189089346
Short name T999
Test name
Test status
Simulation time 518944614 ps
CPU time 3.91 seconds
Started Mar 28 03:33:47 PM PDT 24
Finished Mar 28 03:33:51 PM PDT 24
Peak memory 241800 kb
Host smart-ae5f6ce5-01e0-4cb7-81c4-6d2f0eab77da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189089346 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.4189089346
Directory /workspace/64.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/64.otp_ctrl_parallel_lc_esc.1993192788
Short name T603
Test name
Test status
Simulation time 813032962 ps
CPU time 11.84 seconds
Started Mar 28 03:33:42 PM PDT 24
Finished Mar 28 03:33:54 PM PDT 24
Peak memory 241552 kb
Host smart-ef8d8fae-0369-4a88-86ea-6ebb907f4276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993192788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.1993192788
Directory /workspace/64.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/65.otp_ctrl_init_fail.2014351710
Short name T978
Test name
Test status
Simulation time 1830434366 ps
CPU time 4.84 seconds
Started Mar 28 03:33:47 PM PDT 24
Finished Mar 28 03:33:52 PM PDT 24
Peak memory 241796 kb
Host smart-574f6c1e-81ad-4a52-b167-d2712ace4368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014351710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.2014351710
Directory /workspace/65.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/65.otp_ctrl_parallel_lc_esc.2752396456
Short name T610
Test name
Test status
Simulation time 2080918048 ps
CPU time 16.86 seconds
Started Mar 28 03:33:42 PM PDT 24
Finished Mar 28 03:33:59 PM PDT 24
Peak memory 241644 kb
Host smart-5c514709-57f4-4aed-85bd-3c33fa2adf39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752396456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.2752396456
Directory /workspace/65.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.1587692199
Short name T6
Test name
Test status
Simulation time 42472394253 ps
CPU time 1141.89 seconds
Started Mar 28 03:33:47 PM PDT 24
Finished Mar 28 03:52:49 PM PDT 24
Peak memory 336864 kb
Host smart-2a03caf2-3c28-4f94-8f65-321bbfdca88d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587692199 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_stress_all_with_rand_reset.1587692199
Directory /workspace/65.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.otp_ctrl_init_fail.1330042611
Short name T919
Test name
Test status
Simulation time 393117582 ps
CPU time 4.39 seconds
Started Mar 28 03:33:42 PM PDT 24
Finished Mar 28 03:33:47 PM PDT 24
Peak memory 241744 kb
Host smart-0bab1006-9736-45b8-8218-92537eaf68b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330042611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.1330042611
Directory /workspace/66.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/66.otp_ctrl_parallel_lc_esc.3431965177
Short name T263
Test name
Test status
Simulation time 1497041734 ps
CPU time 22.06 seconds
Started Mar 28 03:33:47 PM PDT 24
Finished Mar 28 03:34:09 PM PDT 24
Peak memory 241880 kb
Host smart-98d2fa20-8ed2-4325-b213-a8a4fc46972a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431965177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.3431965177
Directory /workspace/66.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/67.otp_ctrl_init_fail.344609899
Short name T205
Test name
Test status
Simulation time 551121420 ps
CPU time 4.79 seconds
Started Mar 28 03:33:41 PM PDT 24
Finished Mar 28 03:33:46 PM PDT 24
Peak memory 241916 kb
Host smart-4f3e3ba4-c7f1-4097-877c-f22d1cf10484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344609899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.344609899
Directory /workspace/67.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/67.otp_ctrl_parallel_lc_esc.3174914647
Short name T136
Test name
Test status
Simulation time 266862929 ps
CPU time 7.49 seconds
Started Mar 28 03:33:39 PM PDT 24
Finished Mar 28 03:33:47 PM PDT 24
Peak memory 241620 kb
Host smart-b4c02d7f-df91-453c-acca-5110bee54bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174914647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.3174914647
Directory /workspace/67.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/67.otp_ctrl_stress_all_with_rand_reset.2947142204
Short name T354
Test name
Test status
Simulation time 333892852719 ps
CPU time 634.39 seconds
Started Mar 28 03:33:41 PM PDT 24
Finished Mar 28 03:44:15 PM PDT 24
Peak memory 273536 kb
Host smart-731c6faf-c85d-45c9-a370-ccf993dc10f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947142204 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_stress_all_with_rand_reset.2947142204
Directory /workspace/67.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.otp_ctrl_init_fail.3208199922
Short name T1
Test name
Test status
Simulation time 2338384367 ps
CPU time 5.05 seconds
Started Mar 28 03:33:40 PM PDT 24
Finished Mar 28 03:33:45 PM PDT 24
Peak memory 241772 kb
Host smart-37c00429-fb03-4ef7-8830-2ad90702b606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208199922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.3208199922
Directory /workspace/68.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/68.otp_ctrl_parallel_lc_esc.367296869
Short name T987
Test name
Test status
Simulation time 105312274 ps
CPU time 3.97 seconds
Started Mar 28 03:33:40 PM PDT 24
Finished Mar 28 03:33:44 PM PDT 24
Peak memory 241532 kb
Host smart-355d7230-36b8-401d-8a5c-ec7436f8951f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367296869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.367296869
Directory /workspace/68.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/68.otp_ctrl_stress_all_with_rand_reset.3018590162
Short name T290
Test name
Test status
Simulation time 461841203618 ps
CPU time 2874.05 seconds
Started Mar 28 03:33:58 PM PDT 24
Finished Mar 28 04:21:52 PM PDT 24
Peak memory 515880 kb
Host smart-33055736-58e4-43c9-b416-44a8af067b5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018590162 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_stress_all_with_rand_reset.3018590162
Directory /workspace/68.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.otp_ctrl_init_fail.1699417117
Short name T202
Test name
Test status
Simulation time 216608670 ps
CPU time 4.02 seconds
Started Mar 28 03:33:59 PM PDT 24
Finished Mar 28 03:34:03 PM PDT 24
Peak memory 242000 kb
Host smart-58fced21-6cae-42bc-acf7-799151bbe340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699417117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.1699417117
Directory /workspace/69.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/69.otp_ctrl_parallel_lc_esc.2430278018
Short name T423
Test name
Test status
Simulation time 193552672 ps
CPU time 4.91 seconds
Started Mar 28 03:33:58 PM PDT 24
Finished Mar 28 03:34:03 PM PDT 24
Peak memory 241652 kb
Host smart-04d2efe3-14d2-44bf-897b-9fabac7a77bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430278018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.2430278018
Directory /workspace/69.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/69.otp_ctrl_stress_all_with_rand_reset.3997130496
Short name T158
Test name
Test status
Simulation time 81896300508 ps
CPU time 1267.38 seconds
Started Mar 28 03:33:58 PM PDT 24
Finished Mar 28 03:55:06 PM PDT 24
Peak memory 323528 kb
Host smart-bed888c8-b83b-499f-a668-8107a0e29974
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997130496 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_stress_all_with_rand_reset.3997130496
Directory /workspace/69.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.otp_ctrl_alert_test.1042280398
Short name T1049
Test name
Test status
Simulation time 182143184 ps
CPU time 2.12 seconds
Started Mar 28 03:31:18 PM PDT 24
Finished Mar 28 03:31:20 PM PDT 24
Peak memory 240112 kb
Host smart-6998611e-eafe-418b-b1f7-3f8fc089f55e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042280398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.1042280398
Directory /workspace/7.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.otp_ctrl_background_chks.3544575270
Short name T989
Test name
Test status
Simulation time 1329142528 ps
CPU time 20.08 seconds
Started Mar 28 03:31:18 PM PDT 24
Finished Mar 28 03:31:39 PM PDT 24
Peak memory 242108 kb
Host smart-bb8a232b-c52a-4112-b1c9-2730e0a1fb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544575270 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.3544575270
Directory /workspace/7.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/7.otp_ctrl_check_fail.872022794
Short name T55
Test name
Test status
Simulation time 1011284942 ps
CPU time 16.75 seconds
Started Mar 28 03:31:18 PM PDT 24
Finished Mar 28 03:31:36 PM PDT 24
Peak memory 241964 kb
Host smart-b2f1ef20-8150-4e6d-8391-213c65779a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872022794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.872022794
Directory /workspace/7.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_errs.636315887
Short name T621
Test name
Test status
Simulation time 24919742218 ps
CPU time 79.98 seconds
Started Mar 28 03:31:20 PM PDT 24
Finished Mar 28 03:32:41 PM PDT 24
Peak memory 256056 kb
Host smart-ecd11ace-33e1-42ee-96cf-76600d67265f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636315887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.636315887
Directory /workspace/7.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_lock.1965464368
Short name T533
Test name
Test status
Simulation time 179397454 ps
CPU time 4.75 seconds
Started Mar 28 03:31:18 PM PDT 24
Finished Mar 28 03:31:23 PM PDT 24
Peak memory 241628 kb
Host smart-31c8df25-b7d7-486e-b9d4-bc2e811bb70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965464368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.1965464368
Directory /workspace/7.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/7.otp_ctrl_init_fail.1726993850
Short name T840
Test name
Test status
Simulation time 164236512 ps
CPU time 4.1 seconds
Started Mar 28 03:31:22 PM PDT 24
Finished Mar 28 03:31:28 PM PDT 24
Peak memory 242048 kb
Host smart-50d7b8ee-76e8-425a-bff7-bf656f94fb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726993850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.1726993850
Directory /workspace/7.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_macro_errs.2298428092
Short name T370
Test name
Test status
Simulation time 2532725681 ps
CPU time 16.16 seconds
Started Mar 28 03:31:20 PM PDT 24
Finished Mar 28 03:31:38 PM PDT 24
Peak memory 244060 kb
Host smart-165ad346-abfa-4984-b3e7-d9422eaebfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298428092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.2298428092
Directory /workspace/7.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_key_req.2811888099
Short name T246
Test name
Test status
Simulation time 378587389 ps
CPU time 8.45 seconds
Started Mar 28 03:31:18 PM PDT 24
Finished Mar 28 03:31:27 PM PDT 24
Peak memory 241820 kb
Host smart-23e9a0cc-a3e2-44e3-908b-fef540eb70dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811888099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.2811888099
Directory /workspace/7.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_esc.3936837373
Short name T761
Test name
Test status
Simulation time 214214011 ps
CPU time 10.84 seconds
Started Mar 28 03:31:16 PM PDT 24
Finished Mar 28 03:31:27 PM PDT 24
Peak memory 241708 kb
Host smart-e76a43c0-a330-45c3-b829-9e6c5f0d0ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936837373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.3936837373
Directory /workspace/7.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_req.2697980514
Short name T623
Test name
Test status
Simulation time 10978789287 ps
CPU time 23.61 seconds
Started Mar 28 03:31:18 PM PDT 24
Finished Mar 28 03:31:43 PM PDT 24
Peak memory 241760 kb
Host smart-4cb6ff07-110f-451f-b4b1-39f7b97f30a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2697980514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.2697980514
Directory /workspace/7.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_regwen.2480081094
Short name T826
Test name
Test status
Simulation time 225697794 ps
CPU time 6.49 seconds
Started Mar 28 03:31:22 PM PDT 24
Finished Mar 28 03:31:30 PM PDT 24
Peak memory 241896 kb
Host smart-13fab539-766c-4a93-aef6-5a2fd0a4e667
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2480081094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.2480081094
Directory /workspace/7.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/7.otp_ctrl_smoke.1317263130
Short name T900
Test name
Test status
Simulation time 1921181271 ps
CPU time 4.6 seconds
Started Mar 28 03:31:18 PM PDT 24
Finished Mar 28 03:31:23 PM PDT 24
Peak memory 241896 kb
Host smart-5e559b66-0eb5-46f7-9df6-537676a9d5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317263130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.1317263130
Directory /workspace/7.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all.1675671314
Short name T579
Test name
Test status
Simulation time 21392613735 ps
CPU time 188.28 seconds
Started Mar 28 03:31:18 PM PDT 24
Finished Mar 28 03:34:27 PM PDT 24
Peak memory 249304 kb
Host smart-287938a9-ffff-4d90-b8f6-261f54672d98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675671314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all.
1675671314
Directory /workspace/7.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all_with_rand_reset.1722922899
Short name T789
Test name
Test status
Simulation time 14681144296 ps
CPU time 338.32 seconds
Started Mar 28 03:31:18 PM PDT 24
Finished Mar 28 03:36:57 PM PDT 24
Peak memory 265184 kb
Host smart-d1678649-9cf5-4a9f-a2f0-658671e6f048
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722922899 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all_with_rand_reset.1722922899
Directory /workspace/7.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.otp_ctrl_test_access.2690660449
Short name T786
Test name
Test status
Simulation time 1706768523 ps
CPU time 32.66 seconds
Started Mar 28 03:31:23 PM PDT 24
Finished Mar 28 03:31:58 PM PDT 24
Peak memory 242272 kb
Host smart-efeadf0a-5087-43c5-aa06-1914f073244b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690660449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.2690660449
Directory /workspace/7.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/70.otp_ctrl_init_fail.3884402180
Short name T540
Test name
Test status
Simulation time 2715549777 ps
CPU time 5.35 seconds
Started Mar 28 03:33:59 PM PDT 24
Finished Mar 28 03:34:05 PM PDT 24
Peak memory 241808 kb
Host smart-4c428c5a-7641-482d-98bf-a929486cc4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884402180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.3884402180
Directory /workspace/70.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/70.otp_ctrl_parallel_lc_esc.439299076
Short name T153
Test name
Test status
Simulation time 314082251 ps
CPU time 4.46 seconds
Started Mar 28 03:34:00 PM PDT 24
Finished Mar 28 03:34:04 PM PDT 24
Peak memory 240972 kb
Host smart-d45b4a85-c7ce-4266-bde5-12f7404a41dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439299076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.439299076
Directory /workspace/70.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/70.otp_ctrl_stress_all_with_rand_reset.1671322774
Short name T262
Test name
Test status
Simulation time 362803509592 ps
CPU time 2488.36 seconds
Started Mar 28 03:34:05 PM PDT 24
Finished Mar 28 04:15:34 PM PDT 24
Peak memory 502372 kb
Host smart-78c404f5-32bc-456d-888e-b52b51d75e57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671322774 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_stress_all_with_rand_reset.1671322774
Directory /workspace/70.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.otp_ctrl_init_fail.4037431879
Short name T60
Test name
Test status
Simulation time 144506665 ps
CPU time 5.24 seconds
Started Mar 28 03:33:57 PM PDT 24
Finished Mar 28 03:34:02 PM PDT 24
Peak memory 241732 kb
Host smart-2bdd662a-b417-4f16-95b5-b065698a7bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037431879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.4037431879
Directory /workspace/71.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/71.otp_ctrl_parallel_lc_esc.2469828516
Short name T169
Test name
Test status
Simulation time 530313785 ps
CPU time 7.91 seconds
Started Mar 28 03:33:58 PM PDT 24
Finished Mar 28 03:34:06 PM PDT 24
Peak memory 241500 kb
Host smart-b56a5744-8837-493d-a672-80ce63a3e2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469828516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.2469828516
Directory /workspace/71.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/72.otp_ctrl_parallel_lc_esc.1522703733
Short name T823
Test name
Test status
Simulation time 280458610 ps
CPU time 7.57 seconds
Started Mar 28 03:34:00 PM PDT 24
Finished Mar 28 03:34:08 PM PDT 24
Peak memory 241472 kb
Host smart-df60db66-0108-4967-b72f-20bf8c6d8226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522703733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.1522703733
Directory /workspace/72.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/72.otp_ctrl_stress_all_with_rand_reset.3789680418
Short name T523
Test name
Test status
Simulation time 208193300442 ps
CPU time 1653.42 seconds
Started Mar 28 03:33:56 PM PDT 24
Finished Mar 28 04:01:30 PM PDT 24
Peak memory 297984 kb
Host smart-dd0bc07b-cef2-4187-af27-a4498e448d5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789680418 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_stress_all_with_rand_reset.3789680418
Directory /workspace/72.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.otp_ctrl_init_fail.3315101770
Short name T80
Test name
Test status
Simulation time 213898892 ps
CPU time 4.46 seconds
Started Mar 28 03:33:59 PM PDT 24
Finished Mar 28 03:34:03 PM PDT 24
Peak memory 241708 kb
Host smart-7e974d01-f0d8-4dd2-94ba-69a7770ee8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315101770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.3315101770
Directory /workspace/73.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/73.otp_ctrl_parallel_lc_esc.3025770002
Short name T1103
Test name
Test status
Simulation time 283393348 ps
CPU time 4.81 seconds
Started Mar 28 03:33:59 PM PDT 24
Finished Mar 28 03:34:04 PM PDT 24
Peak memory 241972 kb
Host smart-9169cbc6-bf94-4016-a9d4-00a0790d1472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025770002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.3025770002
Directory /workspace/73.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/74.otp_ctrl_init_fail.820057605
Short name T100
Test name
Test status
Simulation time 142944820 ps
CPU time 4.17 seconds
Started Mar 28 03:33:59 PM PDT 24
Finished Mar 28 03:34:03 PM PDT 24
Peak memory 241728 kb
Host smart-126d7faa-5870-4ab7-943c-6ddfa615e563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820057605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.820057605
Directory /workspace/74.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/74.otp_ctrl_parallel_lc_esc.4286382951
Short name T253
Test name
Test status
Simulation time 181517402 ps
CPU time 8.7 seconds
Started Mar 28 03:33:58 PM PDT 24
Finished Mar 28 03:34:07 PM PDT 24
Peak memory 241808 kb
Host smart-752057da-8ce2-4217-9f52-5491d8d8e547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286382951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.4286382951
Directory /workspace/74.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/74.otp_ctrl_stress_all_with_rand_reset.2454339567
Short name T144
Test name
Test status
Simulation time 604835297765 ps
CPU time 2432.11 seconds
Started Mar 28 03:33:59 PM PDT 24
Finished Mar 28 04:14:31 PM PDT 24
Peak memory 460680 kb
Host smart-fe59073b-b844-4002-8e30-50e931aa419a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454339567 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_stress_all_with_rand_reset.2454339567
Directory /workspace/74.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.otp_ctrl_init_fail.91124760
Short name T179
Test name
Test status
Simulation time 632908629 ps
CPU time 4.84 seconds
Started Mar 28 03:33:57 PM PDT 24
Finished Mar 28 03:34:02 PM PDT 24
Peak memory 241912 kb
Host smart-a9ae7c58-f37a-4a9a-af0a-106d6f055027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91124760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.91124760
Directory /workspace/75.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/75.otp_ctrl_parallel_lc_esc.586977559
Short name T1067
Test name
Test status
Simulation time 131692363 ps
CPU time 5.55 seconds
Started Mar 28 03:34:03 PM PDT 24
Finished Mar 28 03:34:09 PM PDT 24
Peak memory 241880 kb
Host smart-84e8ef14-3e1d-4445-be38-ffd35ea34e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586977559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.586977559
Directory /workspace/75.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/75.otp_ctrl_stress_all_with_rand_reset.987769375
Short name T297
Test name
Test status
Simulation time 138076919697 ps
CPU time 2178.37 seconds
Started Mar 28 03:33:59 PM PDT 24
Finished Mar 28 04:10:18 PM PDT 24
Peak memory 265100 kb
Host smart-3cce5168-401b-43a2-bd5a-c6a0e9ffec01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987769375 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_stress_all_with_rand_reset.987769375
Directory /workspace/75.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.otp_ctrl_init_fail.1246356164
Short name T894
Test name
Test status
Simulation time 155126213 ps
CPU time 4.12 seconds
Started Mar 28 03:33:59 PM PDT 24
Finished Mar 28 03:34:03 PM PDT 24
Peak memory 242044 kb
Host smart-8c5593df-5425-478a-98aa-c3e6923f446a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246356164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.1246356164
Directory /workspace/76.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/76.otp_ctrl_parallel_lc_esc.3961513451
Short name T272
Test name
Test status
Simulation time 3196017492 ps
CPU time 25.82 seconds
Started Mar 28 03:33:56 PM PDT 24
Finished Mar 28 03:34:22 PM PDT 24
Peak memory 242028 kb
Host smart-db6e21c4-285f-4dab-ab4a-4a502502746f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961513451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.3961513451
Directory /workspace/76.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/76.otp_ctrl_stress_all_with_rand_reset.2443159269
Short name T928
Test name
Test status
Simulation time 68164432684 ps
CPU time 975.6 seconds
Started Mar 28 03:34:00 PM PDT 24
Finished Mar 28 03:50:16 PM PDT 24
Peak memory 260920 kb
Host smart-4d8cf0f3-7a15-4501-a2a9-88f3cc1a819c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443159269 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_stress_all_with_rand_reset.2443159269
Directory /workspace/76.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.otp_ctrl_parallel_lc_esc.197645716
Short name T925
Test name
Test status
Simulation time 214703001 ps
CPU time 5.53 seconds
Started Mar 28 03:33:58 PM PDT 24
Finished Mar 28 03:34:04 PM PDT 24
Peak memory 241700 kb
Host smart-af51582d-a482-4608-896a-edceb9e40b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197645716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.197645716
Directory /workspace/77.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/77.otp_ctrl_stress_all_with_rand_reset.2479079500
Short name T367
Test name
Test status
Simulation time 38790185231 ps
CPU time 421.38 seconds
Started Mar 28 03:33:59 PM PDT 24
Finished Mar 28 03:41:00 PM PDT 24
Peak memory 259652 kb
Host smart-9388679a-de04-4281-a9c4-bee2cdd6ef95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479079500 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_stress_all_with_rand_reset.2479079500
Directory /workspace/77.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.otp_ctrl_init_fail.2675698739
Short name T161
Test name
Test status
Simulation time 113020016 ps
CPU time 3.26 seconds
Started Mar 28 03:34:00 PM PDT 24
Finished Mar 28 03:34:04 PM PDT 24
Peak memory 241684 kb
Host smart-cedf5c7e-64e6-49ed-9302-5e68cae573bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675698739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.2675698739
Directory /workspace/78.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/78.otp_ctrl_parallel_lc_esc.1426633948
Short name T706
Test name
Test status
Simulation time 136121187 ps
CPU time 5.44 seconds
Started Mar 28 03:33:56 PM PDT 24
Finished Mar 28 03:34:01 PM PDT 24
Peak memory 241564 kb
Host smart-a09bf8bc-da0f-43d5-a85f-0109dcdef926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426633948 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.1426633948
Directory /workspace/78.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/79.otp_ctrl_init_fail.687009762
Short name T221
Test name
Test status
Simulation time 1954277990 ps
CPU time 5.81 seconds
Started Mar 28 03:33:59 PM PDT 24
Finished Mar 28 03:34:05 PM PDT 24
Peak memory 242108 kb
Host smart-14354a9c-e9de-429a-bbf5-9063c8fe2d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687009762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.687009762
Directory /workspace/79.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/79.otp_ctrl_parallel_lc_esc.49675709
Short name T212
Test name
Test status
Simulation time 155352285 ps
CPU time 6.84 seconds
Started Mar 28 03:34:00 PM PDT 24
Finished Mar 28 03:34:07 PM PDT 24
Peak memory 241704 kb
Host smart-35395eaf-0f0e-4620-9a67-d6d57b9508fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49675709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.49675709
Directory /workspace/79.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/8.otp_ctrl_alert_test.1408352044
Short name T418
Test name
Test status
Simulation time 677709401 ps
CPU time 2.41 seconds
Started Mar 28 03:31:39 PM PDT 24
Finished Mar 28 03:31:42 PM PDT 24
Peak memory 240104 kb
Host smart-e630caf1-27c2-4131-a347-b19567bdddff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408352044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.1408352044
Directory /workspace/8.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.otp_ctrl_background_chks.1779796450
Short name T1114
Test name
Test status
Simulation time 16461303308 ps
CPU time 34.91 seconds
Started Mar 28 03:31:17 PM PDT 24
Finished Mar 28 03:31:53 PM PDT 24
Peak memory 242224 kb
Host smart-e9b92a47-1f8a-4e6f-b305-c6d55d6ad3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779796450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.1779796450
Directory /workspace/8.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/8.otp_ctrl_check_fail.3028395037
Short name T642
Test name
Test status
Simulation time 11158906239 ps
CPU time 17.1 seconds
Started Mar 28 03:31:18 PM PDT 24
Finished Mar 28 03:31:36 PM PDT 24
Peak memory 242704 kb
Host smart-1932c803-6617-4dde-b4f9-b146ee00df7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028395037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.3028395037
Directory /workspace/8.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_errs.3426199793
Short name T142
Test name
Test status
Simulation time 10590698349 ps
CPU time 33.45 seconds
Started Mar 28 03:31:18 PM PDT 24
Finished Mar 28 03:31:53 PM PDT 24
Peak memory 243120 kb
Host smart-ef3582c5-2e41-4cdb-9c05-cbc5aefa22f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426199793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.3426199793
Directory /workspace/8.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_lock.3420293661
Short name T1081
Test name
Test status
Simulation time 6188057377 ps
CPU time 11.73 seconds
Started Mar 28 03:31:19 PM PDT 24
Finished Mar 28 03:31:32 PM PDT 24
Peak memory 242864 kb
Host smart-c0d2a47f-d568-4161-b2af-dc7d85f0fc65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420293661 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.3420293661
Directory /workspace/8.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/8.otp_ctrl_init_fail.4282772175
Short name T700
Test name
Test status
Simulation time 605778284 ps
CPU time 4.79 seconds
Started Mar 28 03:31:23 PM PDT 24
Finished Mar 28 03:31:29 PM PDT 24
Peak memory 241728 kb
Host smart-83d60353-c2fc-4ffe-88b2-7d2f881f6d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282772175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.4282772175
Directory /workspace/8.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_macro_errs.2975901582
Short name T437
Test name
Test status
Simulation time 7959703591 ps
CPU time 19.6 seconds
Started Mar 28 03:31:26 PM PDT 24
Finished Mar 28 03:31:46 PM PDT 24
Peak memory 242132 kb
Host smart-4d5795f5-8253-483f-bebb-b2b344bf3cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975901582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.2975901582
Directory /workspace/8.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_key_req.542720157
Short name T974
Test name
Test status
Simulation time 1614509294 ps
CPU time 44.98 seconds
Started Mar 28 03:31:16 PM PDT 24
Finished Mar 28 03:32:01 PM PDT 24
Peak memory 242316 kb
Host smart-298eade7-9061-42f4-808a-727990f27746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542720157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.542720157
Directory /workspace/8.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_esc.695801952
Short name T998
Test name
Test status
Simulation time 445134365 ps
CPU time 5.86 seconds
Started Mar 28 03:31:23 PM PDT 24
Finished Mar 28 03:31:31 PM PDT 24
Peak memory 241492 kb
Host smart-1262cb89-2a6d-474f-a285-f42f8bc53134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695801952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.695801952
Directory /workspace/8.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_req.2267717903
Short name T814
Test name
Test status
Simulation time 1640887152 ps
CPU time 16.55 seconds
Started Mar 28 03:31:18 PM PDT 24
Finished Mar 28 03:31:36 PM PDT 24
Peak memory 241616 kb
Host smart-574b1a20-4317-4a6e-99c2-a7cfbc08a2cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2267717903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.2267717903
Directory /workspace/8.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_regwen.3475703276
Short name T722
Test name
Test status
Simulation time 113409616 ps
CPU time 4.23 seconds
Started Mar 28 03:31:26 PM PDT 24
Finished Mar 28 03:31:30 PM PDT 24
Peak memory 241684 kb
Host smart-cc6b665d-99ba-4135-9f1a-0f4ce448ac93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3475703276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.3475703276
Directory /workspace/8.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/8.otp_ctrl_smoke.583362078
Short name T613
Test name
Test status
Simulation time 207330221 ps
CPU time 4.88 seconds
Started Mar 28 03:31:23 PM PDT 24
Finished Mar 28 03:31:29 PM PDT 24
Peak memory 241532 kb
Host smart-4f91752e-143d-4ec1-b6d6-02a04dec481f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583362078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.583362078
Directory /workspace/8.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/8.otp_ctrl_test_access.274078961
Short name T251
Test name
Test status
Simulation time 1883415682 ps
CPU time 3.74 seconds
Started Mar 28 03:31:19 PM PDT 24
Finished Mar 28 03:31:23 PM PDT 24
Peak memory 241644 kb
Host smart-08681cd1-59b7-4255-bd71-545c25d93a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274078961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.274078961
Directory /workspace/8.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/80.otp_ctrl_init_fail.1354122617
Short name T1182
Test name
Test status
Simulation time 337028336 ps
CPU time 4.06 seconds
Started Mar 28 03:33:59 PM PDT 24
Finished Mar 28 03:34:03 PM PDT 24
Peak memory 241816 kb
Host smart-c4db4a84-5ff5-4cee-8ea1-2d98f543e56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354122617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.1354122617
Directory /workspace/80.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/80.otp_ctrl_parallel_lc_esc.207270658
Short name T888
Test name
Test status
Simulation time 3660466859 ps
CPU time 23.12 seconds
Started Mar 28 03:33:58 PM PDT 24
Finished Mar 28 03:34:21 PM PDT 24
Peak memory 241812 kb
Host smart-157a5d79-a18f-4c6e-9de2-2178c8ff1b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207270658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.207270658
Directory /workspace/80.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/81.otp_ctrl_init_fail.3262425160
Short name T1094
Test name
Test status
Simulation time 451347669 ps
CPU time 3.94 seconds
Started Mar 28 03:34:00 PM PDT 24
Finished Mar 28 03:34:04 PM PDT 24
Peak memory 241816 kb
Host smart-3d3b0b17-0db5-46ea-a352-f5274d995fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262425160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.3262425160
Directory /workspace/81.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/81.otp_ctrl_parallel_lc_esc.985268092
Short name T426
Test name
Test status
Simulation time 635763673 ps
CPU time 11.29 seconds
Started Mar 28 03:33:59 PM PDT 24
Finished Mar 28 03:34:10 PM PDT 24
Peak memory 241700 kb
Host smart-b824caa9-161b-410b-9d78-5a866e6952cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985268092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.985268092
Directory /workspace/81.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/81.otp_ctrl_stress_all_with_rand_reset.3474039437
Short name T295
Test name
Test status
Simulation time 209700401125 ps
CPU time 1983.72 seconds
Started Mar 28 03:33:56 PM PDT 24
Finished Mar 28 04:07:01 PM PDT 24
Peak memory 294664 kb
Host smart-51db441a-b654-4994-8626-6295bac83a2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474039437 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_stress_all_with_rand_reset.3474039437
Directory /workspace/81.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.otp_ctrl_init_fail.1446016369
Short name T1047
Test name
Test status
Simulation time 321315727 ps
CPU time 3.76 seconds
Started Mar 28 03:34:01 PM PDT 24
Finished Mar 28 03:34:05 PM PDT 24
Peak memory 241660 kb
Host smart-83f23da9-1c1f-4c32-af8d-a81bb16c8eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446016369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.1446016369
Directory /workspace/82.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/82.otp_ctrl_parallel_lc_esc.4239096949
Short name T600
Test name
Test status
Simulation time 2534488972 ps
CPU time 9.87 seconds
Started Mar 28 03:34:03 PM PDT 24
Finished Mar 28 03:34:13 PM PDT 24
Peak memory 242092 kb
Host smart-593740f7-2830-4977-bdbb-75419bac7438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239096949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.4239096949
Directory /workspace/82.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/83.otp_ctrl_parallel_lc_esc.928163412
Short name T481
Test name
Test status
Simulation time 97910415 ps
CPU time 2.51 seconds
Started Mar 28 03:33:59 PM PDT 24
Finished Mar 28 03:34:02 PM PDT 24
Peak memory 241708 kb
Host smart-2f4a7352-f4e8-4f65-808e-c2636dde62a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928163412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.928163412
Directory /workspace/83.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/83.otp_ctrl_stress_all_with_rand_reset.3699351054
Short name T310
Test name
Test status
Simulation time 88166793547 ps
CPU time 1341.6 seconds
Started Mar 28 03:33:56 PM PDT 24
Finished Mar 28 03:56:18 PM PDT 24
Peak memory 309884 kb
Host smart-080c7397-536f-4a1b-a46a-f646c814476f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699351054 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_stress_all_with_rand_reset.3699351054
Directory /workspace/83.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.otp_ctrl_init_fail.3130266738
Short name T890
Test name
Test status
Simulation time 183720175 ps
CPU time 3.84 seconds
Started Mar 28 03:34:01 PM PDT 24
Finished Mar 28 03:34:05 PM PDT 24
Peak memory 242076 kb
Host smart-0c5ae50c-7982-417c-bde8-adec8d2977a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130266738 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.3130266738
Directory /workspace/84.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/84.otp_ctrl_parallel_lc_esc.4037333390
Short name T1077
Test name
Test status
Simulation time 2888144227 ps
CPU time 6.99 seconds
Started Mar 28 03:34:00 PM PDT 24
Finished Mar 28 03:34:07 PM PDT 24
Peak memory 241760 kb
Host smart-f2d51eaf-a795-44e8-96f1-f9b1530f8832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037333390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.4037333390
Directory /workspace/84.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/85.otp_ctrl_init_fail.1470534558
Short name T544
Test name
Test status
Simulation time 116625169 ps
CPU time 3 seconds
Started Mar 28 03:34:01 PM PDT 24
Finished Mar 28 03:34:04 PM PDT 24
Peak memory 241916 kb
Host smart-22668060-b601-4dea-a1bc-ad29e106ce86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470534558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.1470534558
Directory /workspace/85.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/85.otp_ctrl_parallel_lc_esc.2118568610
Short name T74
Test name
Test status
Simulation time 2636368039 ps
CPU time 8.4 seconds
Started Mar 28 03:33:59 PM PDT 24
Finished Mar 28 03:34:08 PM PDT 24
Peak memory 241768 kb
Host smart-ed0a16df-ea1c-42dd-9e3d-c0e8aefc32ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118568610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.2118568610
Directory /workspace/85.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/85.otp_ctrl_stress_all_with_rand_reset.2648172917
Short name T292
Test name
Test status
Simulation time 261010407188 ps
CPU time 2710.35 seconds
Started Mar 28 03:34:00 PM PDT 24
Finished Mar 28 04:19:11 PM PDT 24
Peak memory 621796 kb
Host smart-d3504cba-cb8f-499b-88c4-b1c271108ef3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648172917 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_stress_all_with_rand_reset.2648172917
Directory /workspace/85.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.otp_ctrl_parallel_lc_esc.3875587831
Short name T871
Test name
Test status
Simulation time 468651565 ps
CPU time 11.22 seconds
Started Mar 28 03:34:03 PM PDT 24
Finished Mar 28 03:34:15 PM PDT 24
Peak memory 241624 kb
Host smart-4aa547b1-5f54-4fa7-8154-855227a0d286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875587831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.3875587831
Directory /workspace/86.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/86.otp_ctrl_stress_all_with_rand_reset.1594574047
Short name T296
Test name
Test status
Simulation time 251587342310 ps
CPU time 2629.47 seconds
Started Mar 28 03:34:00 PM PDT 24
Finished Mar 28 04:17:50 PM PDT 24
Peak memory 350056 kb
Host smart-763bea25-480e-4d0a-b619-f96d84e32a0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594574047 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_stress_all_with_rand_reset.1594574047
Directory /workspace/86.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.otp_ctrl_parallel_lc_esc.4007173585
Short name T1098
Test name
Test status
Simulation time 240043461 ps
CPU time 3.95 seconds
Started Mar 28 03:34:01 PM PDT 24
Finished Mar 28 03:34:05 PM PDT 24
Peak memory 241456 kb
Host smart-580eb66c-3d3e-42e5-a45e-facd20007611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007173585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.4007173585
Directory /workspace/87.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/87.otp_ctrl_stress_all_with_rand_reset.324008166
Short name T349
Test name
Test status
Simulation time 77075673532 ps
CPU time 2024.66 seconds
Started Mar 28 03:34:03 PM PDT 24
Finished Mar 28 04:07:49 PM PDT 24
Peak memory 383412 kb
Host smart-44f48177-3b67-441c-9f00-21038f5ce713
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324008166 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_stress_all_with_rand_reset.324008166
Directory /workspace/87.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.otp_ctrl_init_fail.2882297773
Short name T731
Test name
Test status
Simulation time 803129090 ps
CPU time 4.9 seconds
Started Mar 28 03:33:59 PM PDT 24
Finished Mar 28 03:34:04 PM PDT 24
Peak memory 241800 kb
Host smart-ff3bb9f2-7df6-4d09-a1f7-cf7f1be87725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882297773 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.2882297773
Directory /workspace/88.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/88.otp_ctrl_parallel_lc_esc.1257927101
Short name T767
Test name
Test status
Simulation time 623532496 ps
CPU time 9.07 seconds
Started Mar 28 03:34:00 PM PDT 24
Finished Mar 28 03:34:09 PM PDT 24
Peak memory 241792 kb
Host smart-053e0821-10f8-4909-89c8-017270af870f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257927101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.1257927101
Directory /workspace/88.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/88.otp_ctrl_stress_all_with_rand_reset.2176771572
Short name T976
Test name
Test status
Simulation time 1029346905898 ps
CPU time 1470.02 seconds
Started Mar 28 03:34:00 PM PDT 24
Finished Mar 28 03:58:31 PM PDT 24
Peak memory 327616 kb
Host smart-4bfc8722-8a24-44e2-ac73-2a1e1926ad64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176771572 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_stress_all_with_rand_reset.2176771572
Directory /workspace/88.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.otp_ctrl_init_fail.1145695000
Short name T1068
Test name
Test status
Simulation time 221706338 ps
CPU time 3.74 seconds
Started Mar 28 03:34:01 PM PDT 24
Finished Mar 28 03:34:05 PM PDT 24
Peak memory 241724 kb
Host smart-20d23174-58dd-4fe4-be60-f569517a7db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145695000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.1145695000
Directory /workspace/89.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/89.otp_ctrl_parallel_lc_esc.3190963151
Short name T519
Test name
Test status
Simulation time 783304219 ps
CPU time 6.59 seconds
Started Mar 28 03:34:02 PM PDT 24
Finished Mar 28 03:34:09 PM PDT 24
Peak memory 241768 kb
Host smart-23953c55-2422-41a6-859a-fc7110833f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190963151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.3190963151
Directory /workspace/89.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/89.otp_ctrl_stress_all_with_rand_reset.1922432604
Short name T856
Test name
Test status
Simulation time 217502570156 ps
CPU time 3158.14 seconds
Started Mar 28 03:33:58 PM PDT 24
Finished Mar 28 04:26:37 PM PDT 24
Peak memory 403988 kb
Host smart-19159b23-cb85-4c17-84a1-78e1f6a82c80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922432604 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_stress_all_with_rand_reset.1922432604
Directory /workspace/89.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_alert_test.3818991616
Short name T752
Test name
Test status
Simulation time 193785693 ps
CPU time 2.12 seconds
Started Mar 28 03:31:34 PM PDT 24
Finished Mar 28 03:31:37 PM PDT 24
Peak memory 240040 kb
Host smart-19046a12-bef2-495a-9910-b8d05d6bf298
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818991616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.3818991616
Directory /workspace/9.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.otp_ctrl_background_chks.2524596736
Short name T255
Test name
Test status
Simulation time 2070623537 ps
CPU time 12.87 seconds
Started Mar 28 03:31:35 PM PDT 24
Finished Mar 28 03:31:48 PM PDT 24
Peak memory 241944 kb
Host smart-dba3814c-ca6c-405c-b99b-ea5585e0c2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524596736 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.2524596736
Directory /workspace/9.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/9.otp_ctrl_check_fail.3699936529
Short name T249
Test name
Test status
Simulation time 982495616 ps
CPU time 16.73 seconds
Started Mar 28 03:31:34 PM PDT 24
Finished Mar 28 03:31:51 PM PDT 24
Peak memory 241748 kb
Host smart-4d196154-436a-4b11-8c69-b16aca6001a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699936529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.3699936529
Directory /workspace/9.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_errs.2794200327
Short name T763
Test name
Test status
Simulation time 758073040 ps
CPU time 10.7 seconds
Started Mar 28 03:31:34 PM PDT 24
Finished Mar 28 03:31:45 PM PDT 24
Peak memory 241980 kb
Host smart-9bf396f7-b152-413c-9d71-8b8fa9edec07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794200327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.2794200327
Directory /workspace/9.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_lock.4007692170
Short name T554
Test name
Test status
Simulation time 695407585 ps
CPU time 17.33 seconds
Started Mar 28 03:31:38 PM PDT 24
Finished Mar 28 03:31:56 PM PDT 24
Peak memory 241760 kb
Host smart-ff2e2785-5282-44e8-8730-6abc9ddf97ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007692170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.4007692170
Directory /workspace/9.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/9.otp_ctrl_init_fail.1480245238
Short name T873
Test name
Test status
Simulation time 414761921 ps
CPU time 3.78 seconds
Started Mar 28 03:31:35 PM PDT 24
Finished Mar 28 03:31:39 PM PDT 24
Peak memory 241656 kb
Host smart-ba767fbc-d7a2-4a67-be9d-a3f7e7c8e6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480245238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.1480245238
Directory /workspace/9.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_macro_errs.897064700
Short name T1037
Test name
Test status
Simulation time 11817066781 ps
CPU time 29.19 seconds
Started Mar 28 03:31:33 PM PDT 24
Finished Mar 28 03:32:02 PM PDT 24
Peak memory 244244 kb
Host smart-5c58c249-706d-40ba-aa00-8c8b689a9d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897064700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.897064700
Directory /workspace/9.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_key_req.1710969163
Short name T472
Test name
Test status
Simulation time 1230664830 ps
CPU time 9.27 seconds
Started Mar 28 03:31:34 PM PDT 24
Finished Mar 28 03:31:44 PM PDT 24
Peak memory 242252 kb
Host smart-86a829d4-8ddb-4d7f-92b2-bedbcb21768a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710969163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.1710969163
Directory /workspace/9.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_esc.1386326361
Short name T658
Test name
Test status
Simulation time 1977098832 ps
CPU time 18.84 seconds
Started Mar 28 03:31:33 PM PDT 24
Finished Mar 28 03:31:53 PM PDT 24
Peak memory 241652 kb
Host smart-9d648e08-25be-4532-92bf-17986032b642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386326361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.1386326361
Directory /workspace/9.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_req.1312498506
Short name T901
Test name
Test status
Simulation time 1618404525 ps
CPU time 13.76 seconds
Started Mar 28 03:31:37 PM PDT 24
Finished Mar 28 03:31:51 PM PDT 24
Peak memory 241772 kb
Host smart-c132234f-6299-4110-a613-ba28ff36942a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1312498506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.1312498506
Directory /workspace/9.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_regwen.3790261341
Short name T392
Test name
Test status
Simulation time 4775401687 ps
CPU time 12.27 seconds
Started Mar 28 03:31:35 PM PDT 24
Finished Mar 28 03:31:48 PM PDT 24
Peak memory 242104 kb
Host smart-9ad82dc9-6df1-45f0-907d-b4fa06be11f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3790261341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.3790261341
Directory /workspace/9.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/9.otp_ctrl_smoke.1026684771
Short name T620
Test name
Test status
Simulation time 470675220 ps
CPU time 9.26 seconds
Started Mar 28 03:31:34 PM PDT 24
Finished Mar 28 03:31:43 PM PDT 24
Peak memory 241720 kb
Host smart-199536af-5e38-4fb2-af0d-d0e0fd7284af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026684771 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.1026684771
Directory /workspace/9.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all_with_rand_reset.573355880
Short name T864
Test name
Test status
Simulation time 19159449182 ps
CPU time 543.69 seconds
Started Mar 28 03:31:32 PM PDT 24
Finished Mar 28 03:40:36 PM PDT 24
Peak memory 248756 kb
Host smart-baab130f-33af-4d9b-919b-b43b2aebaca6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573355880 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all_with_rand_reset.573355880
Directory /workspace/9.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_test_access.4123310031
Short name T905
Test name
Test status
Simulation time 2471909112 ps
CPU time 20.79 seconds
Started Mar 28 03:31:37 PM PDT 24
Finished Mar 28 03:31:58 PM PDT 24
Peak memory 242568 kb
Host smart-539d9b4b-4d18-4a1f-9e84-a3f5b0f5d0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123310031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.4123310031
Directory /workspace/9.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/90.otp_ctrl_init_fail.768996052
Short name T189
Test name
Test status
Simulation time 440561831 ps
CPU time 4.33 seconds
Started Mar 28 03:34:01 PM PDT 24
Finished Mar 28 03:34:06 PM PDT 24
Peak memory 241844 kb
Host smart-9c9e2ce6-7199-4682-84e5-093720dfc4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768996052 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.768996052
Directory /workspace/90.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/90.otp_ctrl_parallel_lc_esc.3086423118
Short name T228
Test name
Test status
Simulation time 1047324490 ps
CPU time 16.93 seconds
Started Mar 28 03:33:58 PM PDT 24
Finished Mar 28 03:34:15 PM PDT 24
Peak memory 241796 kb
Host smart-fd2cf385-4f52-4e04-a07c-04783d251f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086423118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.3086423118
Directory /workspace/90.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/90.otp_ctrl_stress_all_with_rand_reset.3109399391
Short name T1118
Test name
Test status
Simulation time 28597922512 ps
CPU time 398.37 seconds
Started Mar 28 03:34:02 PM PDT 24
Finished Mar 28 03:40:41 PM PDT 24
Peak memory 281608 kb
Host smart-10310797-82b1-4d5e-baf5-94d6bd2db608
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109399391 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_stress_all_with_rand_reset.3109399391
Directory /workspace/90.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.otp_ctrl_init_fail.3814109544
Short name T872
Test name
Test status
Simulation time 107934955 ps
CPU time 3.69 seconds
Started Mar 28 03:34:02 PM PDT 24
Finished Mar 28 03:34:06 PM PDT 24
Peak memory 241668 kb
Host smart-fad1a6ca-8568-4ff1-bb1f-491b9ec1c17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814109544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.3814109544
Directory /workspace/91.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/91.otp_ctrl_parallel_lc_esc.1977966675
Short name T656
Test name
Test status
Simulation time 4026184788 ps
CPU time 14.37 seconds
Started Mar 28 03:34:02 PM PDT 24
Finished Mar 28 03:34:16 PM PDT 24
Peak memory 241948 kb
Host smart-380a6a0d-5747-41aa-a94f-c542a8a68c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977966675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.1977966675
Directory /workspace/91.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/91.otp_ctrl_stress_all_with_rand_reset.1187599712
Short name T352
Test name
Test status
Simulation time 217985603720 ps
CPU time 1578.25 seconds
Started Mar 28 03:34:04 PM PDT 24
Finished Mar 28 04:00:22 PM PDT 24
Peak memory 265216 kb
Host smart-7cab930e-3685-4c7e-849a-e7cafd3a7f5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187599712 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_stress_all_with_rand_reset.1187599712
Directory /workspace/91.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.otp_ctrl_init_fail.3150329076
Short name T556
Test name
Test status
Simulation time 357034095 ps
CPU time 4.25 seconds
Started Mar 28 03:34:02 PM PDT 24
Finished Mar 28 03:34:06 PM PDT 24
Peak memory 242024 kb
Host smart-be119635-5ab5-400d-a9e0-4b39e80e5a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150329076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.3150329076
Directory /workspace/92.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/93.otp_ctrl_parallel_lc_esc.2795920378
Short name T707
Test name
Test status
Simulation time 1865779550 ps
CPU time 5.49 seconds
Started Mar 28 03:34:04 PM PDT 24
Finished Mar 28 03:34:09 PM PDT 24
Peak memory 242024 kb
Host smart-e411bacf-1962-484d-b5f9-76399abe95f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795920378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.2795920378
Directory /workspace/93.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/93.otp_ctrl_stress_all_with_rand_reset.1031203275
Short name T810
Test name
Test status
Simulation time 170342620504 ps
CPU time 1014.2 seconds
Started Mar 28 03:34:00 PM PDT 24
Finished Mar 28 03:50:54 PM PDT 24
Peak memory 314376 kb
Host smart-e84f32b3-e7fb-42ef-b4a0-8ceccacdf043
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031203275 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_stress_all_with_rand_reset.1031203275
Directory /workspace/93.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.otp_ctrl_init_fail.7036926
Short name T895
Test name
Test status
Simulation time 425979810 ps
CPU time 4.19 seconds
Started Mar 28 03:34:01 PM PDT 24
Finished Mar 28 03:34:05 PM PDT 24
Peak memory 241680 kb
Host smart-13c2e7fb-b94d-4e30-92a6-1cad1915f0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7036926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.7036926
Directory /workspace/94.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/94.otp_ctrl_parallel_lc_esc.2480523332
Short name T1028
Test name
Test status
Simulation time 7026240078 ps
CPU time 25 seconds
Started Mar 28 03:33:59 PM PDT 24
Finished Mar 28 03:34:24 PM PDT 24
Peak memory 242168 kb
Host smart-0691a3f7-165b-470e-bb89-e3d6adabec4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480523332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.2480523332
Directory /workspace/94.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/95.otp_ctrl_init_fail.1558580844
Short name T908
Test name
Test status
Simulation time 215481008 ps
CPU time 4.13 seconds
Started Mar 28 03:34:02 PM PDT 24
Finished Mar 28 03:34:06 PM PDT 24
Peak memory 241748 kb
Host smart-560b6269-ff84-442b-833e-6a7a01f3d906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558580844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.1558580844
Directory /workspace/95.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/95.otp_ctrl_parallel_lc_esc.2037734480
Short name T893
Test name
Test status
Simulation time 380798621 ps
CPU time 3.67 seconds
Started Mar 28 03:34:20 PM PDT 24
Finished Mar 28 03:34:24 PM PDT 24
Peak memory 241704 kb
Host smart-3b4b3752-03b4-4002-b2d7-626a1fb44e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037734480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.2037734480
Directory /workspace/95.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/95.otp_ctrl_stress_all_with_rand_reset.2912176338
Short name T286
Test name
Test status
Simulation time 59075545497 ps
CPU time 1760.87 seconds
Started Mar 28 03:34:19 PM PDT 24
Finished Mar 28 04:03:40 PM PDT 24
Peak memory 276976 kb
Host smart-08196911-a00b-48be-8dcf-aff18c8a48fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912176338 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_stress_all_with_rand_reset.2912176338
Directory /workspace/95.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.otp_ctrl_init_fail.1857447394
Short name T605
Test name
Test status
Simulation time 2158199181 ps
CPU time 5 seconds
Started Mar 28 03:34:20 PM PDT 24
Finished Mar 28 03:34:25 PM PDT 24
Peak memory 242000 kb
Host smart-cc9f2ef3-6de4-4418-bc91-eef2f6c6a4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857447394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.1857447394
Directory /workspace/96.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/96.otp_ctrl_parallel_lc_esc.1252080289
Short name T762
Test name
Test status
Simulation time 254157841 ps
CPU time 5.1 seconds
Started Mar 28 03:34:22 PM PDT 24
Finished Mar 28 03:34:27 PM PDT 24
Peak memory 241624 kb
Host smart-6c22f4d7-ed0d-4126-b0d2-a1e05ad536d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252080289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.1252080289
Directory /workspace/96.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/96.otp_ctrl_stress_all_with_rand_reset.1882267833
Short name T293
Test name
Test status
Simulation time 413744797594 ps
CPU time 4332.5 seconds
Started Mar 28 03:34:21 PM PDT 24
Finished Mar 28 04:46:34 PM PDT 24
Peak memory 339016 kb
Host smart-61df43dc-f073-4451-8a16-27dd06ea5952
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882267833 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_stress_all_with_rand_reset.1882267833
Directory /workspace/96.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.otp_ctrl_init_fail.3148623748
Short name T78
Test name
Test status
Simulation time 218525330 ps
CPU time 4.08 seconds
Started Mar 28 03:34:23 PM PDT 24
Finished Mar 28 03:34:27 PM PDT 24
Peak memory 241824 kb
Host smart-1df36e53-adf1-4d38-96ea-655ed80a4a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148623748 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.3148623748
Directory /workspace/97.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/97.otp_ctrl_parallel_lc_esc.2966982446
Short name T1146
Test name
Test status
Simulation time 457415206 ps
CPU time 6.54 seconds
Started Mar 28 03:34:21 PM PDT 24
Finished Mar 28 03:34:28 PM PDT 24
Peak memory 241784 kb
Host smart-bf34d277-9769-410c-9425-083329bf783a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966982446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.2966982446
Directory /workspace/97.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/98.otp_ctrl_init_fail.635577243
Short name T793
Test name
Test status
Simulation time 160620479 ps
CPU time 4.17 seconds
Started Mar 28 03:34:20 PM PDT 24
Finished Mar 28 03:34:25 PM PDT 24
Peak memory 242112 kb
Host smart-ae8392d2-399b-4d93-bbf5-ba9208a1384b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635577243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.635577243
Directory /workspace/98.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/98.otp_ctrl_parallel_lc_esc.1873924735
Short name T460
Test name
Test status
Simulation time 11963417490 ps
CPU time 27.9 seconds
Started Mar 28 03:34:21 PM PDT 24
Finished Mar 28 03:34:50 PM PDT 24
Peak memory 241756 kb
Host smart-58bc60f4-a98c-4f02-a92d-c474b9d553ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873924735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.1873924735
Directory /workspace/98.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.3535351630
Short name T870
Test name
Test status
Simulation time 83422391928 ps
CPU time 602.3 seconds
Started Mar 28 03:34:20 PM PDT 24
Finished Mar 28 03:44:22 PM PDT 24
Peak memory 259472 kb
Host smart-4d735fed-6646-4c67-a234-6aa3e03f4bb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535351630 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_stress_all_with_rand_reset.3535351630
Directory /workspace/98.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.otp_ctrl_init_fail.2651840181
Short name T1119
Test name
Test status
Simulation time 523558728 ps
CPU time 5.23 seconds
Started Mar 28 03:34:18 PM PDT 24
Finished Mar 28 03:34:23 PM PDT 24
Peak memory 242084 kb
Host smart-a57d2635-64f2-4c09-a598-0d2dbdbdf0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651840181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.2651840181
Directory /workspace/99.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/99.otp_ctrl_parallel_lc_esc.3886116691
Short name T886
Test name
Test status
Simulation time 152034167 ps
CPU time 4.89 seconds
Started Mar 28 03:34:20 PM PDT 24
Finished Mar 28 03:34:25 PM PDT 24
Peak memory 241672 kb
Host smart-31cd316e-53cd-4825-91c8-89e5e81d1327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886116691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.3886116691
Directory /workspace/99.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.959513718
Short name T256
Test name
Test status
Simulation time 72838499140 ps
CPU time 843.93 seconds
Started Mar 28 03:34:20 PM PDT 24
Finished Mar 28 03:48:24 PM PDT 24
Peak memory 265176 kb
Host smart-9742f1ce-b71b-4d83-a470-d2a6c9a5e88e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959513718 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_stress_all_with_rand_reset.959513718
Directory /workspace/99.otp_ctrl_stress_all_with_rand_reset/latest
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