Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

23004414

1

T1

3576

T2

896

T3

799

full_word

7591793

1

T1

2060

T2

640

T3

179

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	30595917	1			T1	5636		T2	1536		T3	978
auto[TlIntgErrCmd]	85	1			T260	5		T261	4		T262	4
auto[TlIntgErrData]	101	1			T260	3		T261	2		T262	10
auto[TlIntgErrBoth]	104	1			T260	2		T261	4		T262	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9362896

1

T1

5074

T2

959

T3

772

auto[1]

21233311

1

T1

562

T2

577

T3

206

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5956679	1			T1	3232		T2	566		T3	685
auto[TlIntgErrNone]	partial	auto[1]	17047470	1			T1	344		T2	330		T3	114
auto[TlIntgErrNone]	full_word	auto[0]	3406085	1			T1	1842		T2	393		T3	87
auto[TlIntgErrNone]	full_word	auto[1]	4185683	1			T1	218		T2	247		T3	92
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T260	1		T261	3		T262	2
auto[TlIntgErrCmd]	partial	auto[1]	43	1			T260	4		T262	2		T268	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T261	1		T369	2		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T267	1		T367	3		-	-
auto[TlIntgErrData]	partial	auto[0]	45	1			T260	1		T261	1		T262	6
auto[TlIntgErrData]	partial	auto[1]	44	1			T261	1		T262	4		T267	2
auto[TlIntgErrData]	full_word	auto[0]	8	1			T260	1		T370	1		T371	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T260	1		T371	1		T372	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T260	2		T261	1		T262	1
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T261	3		T262	4		T267	5
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T262	1		T265	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T372	1		T373	1		T374	1