Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.57	96.10	96.15	97.00		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	434250508	7057415	0	0
check_regwen_rd_A	434250508	3543	0	0
check_timeout_rd_A	434250508	3471	0	0
check_trigger_regwen_rd_A	434250508	3605	0	0
consistency_check_period_rd_A	434250508	3622	0	0
creator_sw_cfg_read_lock_rd_A	434250508	3338	0	0
direct_access_address_rd_A	434250508	2916	0	0
direct_access_wdata_0_rd_A	434250508	2072	0	0
direct_access_wdata_1_rd_A	434250508	2147	0	0
integrity_check_period_rd_A	434250508	3530	0	0
intr_enable_rd_A	434250508	4604	0	0
owner_sw_cfg_read_lock_rd_A	434250508	3202	0	0
rot_creator_auth_codesign_read_lock_rd_A	434250508	3583	0	0
rot_creator_auth_state_read_lock_rd_A	434250508	2948	0	0
vendor_test_read_lock_rd_A	434250508	2980	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434250508	7057415	0	0
T9	178466	26782	0	0
T13	0	116665	0	0
T14	0	40080	0	0
T19	0	60345	0	0
T20	0	88306	0	0
T27	0	51749	0	0
T35	0	94952	0	0
T47	15188	0	0	0
T94	91584	0	0	0
T95	14010	0	0	0
T96	13842	0	0	0
T97	28468	0	0	0
T99	50725	0	0	0
T112	0	109642	0	0
T134	0	137086	0	0
T179	8685	0	0	0
T180	14766	0	0	0
T270	0	84571	0	0
T271	22630	0	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434250508	3543	0	0
T9	178466	48	0	0
T19	0	74	0	0
T20	0	115	0	0
T27	0	86	0	0
T47	15188	0	0	0
T94	91584	0	0	0
T95	14010	0	0	0
T96	13842	0	0	0
T97	28468	0	0	0
T99	50725	0	0	0
T135	0	224	0	0
T179	8685	0	0	0
T180	14766	0	0	0
T238	0	60	0	0
T271	22630	0	0	0
T279	0	138	0	0
T280	0	45	0	0
T296	0	43	0	0
T347	0	84	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434250508	3471	0	0
T9	178466	33	0	0
T19	0	88	0	0
T20	0	120	0	0
T27	0	84	0	0
T47	15188	0	0	0
T94	91584	0	0	0
T95	14010	0	0	0
T96	13842	0	0	0
T97	28468	0	0	0
T99	50725	0	0	0
T135	0	236	0	0
T179	8685	0	0	0
T180	14766	0	0	0
T238	0	40	0	0
T271	22630	0	0	0
T279	0	176	0	0
T280	0	52	0	0
T296	0	51	0	0
T347	0	87	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434250508	3605	0	0
T9	178466	68	0	0
T19	0	47	0	0
T20	0	124	0	0
T27	0	54	0	0
T47	15188	0	0	0
T94	91584	0	0	0
T95	14010	0	0	0
T96	13842	0	0	0
T97	28468	0	0	0
T99	50725	0	0	0
T135	0	305	0	0
T179	8685	0	0	0
T180	14766	0	0	0
T238	0	27	0	0
T271	22630	0	0	0
T279	0	170	0	0
T280	0	51	0	0
T296	0	70	0	0
T347	0	93	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434250508	3622	0	0
T9	178466	52	0	0
T19	0	67	0	0
T20	0	121	0	0
T27	0	61	0	0
T47	15188	0	0	0
T94	91584	0	0	0
T95	14010	0	0	0
T96	13842	0	0	0
T97	28468	0	0	0
T99	50725	0	0	0
T135	0	319	0	0
T179	8685	0	0	0
T180	14766	0	0	0
T238	0	65	0	0
T271	22630	0	0	0
T279	0	126	0	0
T280	0	52	0	0
T296	0	63	0	0
T347	0	60	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434250508	3338	0	0
T9	178466	25	0	0
T19	0	65	0	0
T20	0	131	0	0
T27	0	55	0	0
T47	15188	0	0	0
T94	91584	0	0	0
T95	14010	0	0	0
T96	13842	0	0	0
T97	28468	0	0	0
T99	50725	0	0	0
T135	0	234	0	0
T179	8685	0	0	0
T180	14766	0	0	0
T238	0	61	0	0
T271	22630	0	0	0
T279	0	179	0	0
T280	0	47	0	0
T296	0	42	0	0
T347	0	97	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434250508	2916	0	0
T9	178466	29	0	0
T19	0	35	0	0
T20	0	91	0	0
T27	0	75	0	0
T47	15188	0	0	0
T94	91584	0	0	0
T95	14010	0	0	0
T96	13842	0	0	0
T97	28468	0	0	0
T99	50725	0	0	0
T135	0	285	0	0
T179	8685	0	0	0
T180	14766	0	0	0
T238	0	65	0	0
T271	22630	0	0	0
T279	0	125	0	0
T280	0	44	0	0
T296	0	62	0	0
T347	0	105	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434250508	2072	0	0
T9	178466	41	0	0
T19	0	55	0	0
T20	0	74	0	0
T27	0	62	0	0
T47	15188	0	0	0
T94	91584	0	0	0
T95	14010	0	0	0
T96	13842	0	0	0
T97	28468	0	0	0
T99	50725	0	0	0
T135	0	199	0	0
T179	8685	0	0	0
T180	14766	0	0	0
T238	0	39	0	0
T271	22630	0	0	0
T279	0	100	0	0
T280	0	43	0	0
T296	0	36	0	0
T347	0	80	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434250508	2147	0	0
T9	178466	5	0	0
T19	0	26	0	0
T20	0	74	0	0
T27	0	34	0	0
T47	15188	0	0	0
T94	91584	0	0	0
T95	14010	0	0	0
T96	13842	0	0	0
T97	28468	0	0	0
T99	50725	0	0	0
T135	0	277	0	0
T179	8685	0	0	0
T180	14766	0	0	0
T238	0	45	0	0
T271	22630	0	0	0
T279	0	121	0	0
T280	0	33	0	0
T296	0	21	0	0
T347	0	57	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434250508	3530	0	0
T9	178466	25	0	0
T19	0	66	0	0
T20	0	126	0	0
T27	0	62	0	0
T47	15188	0	0	0
T94	91584	0	0	0
T95	14010	0	0	0
T96	13842	0	0	0
T97	28468	0	0	0
T99	50725	0	0	0
T135	0	218	0	0
T179	8685	0	0	0
T180	14766	0	0	0
T238	0	62	0	0
T271	22630	0	0	0
T279	0	146	0	0
T280	0	37	0	0
T296	0	36	0	0
T347	0	130	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434250508	4604	0	0
T9	178466	43	0	0
T19	0	64	0	0
T20	0	110	0	0
T27	0	76	0	0
T47	15188	0	0	0
T94	91584	0	0	0
T95	14010	0	0	0
T96	13842	0	0	0
T97	28468	0	0	0
T99	50725	0	0	0
T179	8685	0	0	0
T180	14766	0	0	0
T223	0	3	0	0
T224	0	32	0	0
T227	0	68	0	0
T238	0	87	0	0
T255	0	17	0	0
T271	22630	0	0	0
T348	0	24	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434250508	3202	0	0
T9	178466	25	0	0
T19	0	52	0	0
T20	0	128	0	0
T27	0	79	0	0
T47	15188	0	0	0
T94	91584	0	0	0
T95	14010	0	0	0
T96	13842	0	0	0
T97	28468	0	0	0
T99	50725	0	0	0
T135	0	260	0	0
T179	8685	0	0	0
T180	14766	0	0	0
T238	0	49	0	0
T271	22630	0	0	0
T279	0	182	0	0
T280	0	39	0	0
T296	0	53	0	0
T347	0	133	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434250508	3583	0	0
T9	178466	50	0	0
T19	0	112	0	0
T20	0	124	0	0
T27	0	73	0	0
T47	15188	0	0	0
T94	91584	0	0	0
T95	14010	0	0	0
T96	13842	0	0	0
T97	28468	0	0	0
T99	50725	0	0	0
T135	0	274	0	0
T179	8685	0	0	0
T180	14766	0	0	0
T238	0	49	0	0
T271	22630	0	0	0
T279	0	184	0	0
T280	0	32	0	0
T296	0	33	0	0
T347	0	104	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434250508	2948	0	0
T9	178466	39	0	0
T19	0	45	0	0
T20	0	84	0	0
T27	0	65	0	0
T47	15188	0	0	0
T94	91584	0	0	0
T95	14010	0	0	0
T96	13842	0	0	0
T97	28468	0	0	0
T99	50725	0	0	0
T135	0	246	0	0
T179	8685	0	0	0
T180	14766	0	0	0
T238	0	31	0	0
T271	22630	0	0	0
T279	0	105	0	0
T280	0	79	0	0
T296	0	42	0	0
T347	0	94	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434250508	2980	0	0
T9	178466	62	0	0
T19	0	63	0	0
T20	0	115	0	0
T27	0	84	0	0
T47	15188	0	0	0
T94	91584	0	0	0
T95	14010	0	0	0
T96	13842	0	0	0
T97	28468	0	0	0
T99	50725	0	0	0
T135	0	246	0	0
T179	8685	0	0	0
T180	14766	0	0	0
T238	0	43	0	0
T271	22630	0	0	0
T279	0	124	0	0
T280	0	49	0	0
T296	0	34	0	0
T347	0	88	0	0