Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.23	100.00	100.00		90.00	100.00	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.56	100.00	100.00	100.00	90.00	98.15	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.57	96.10	96.15	97.00		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.57	96.10	96.15	97.00		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.57	96.10	96.15	97.00		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		86	86	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	61	61	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
153	1	1
154	1	1
156	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			==> MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
224		excluded
			Exclude Annotation: VC_COV_UNR
225		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
276		excluded
			Exclude Annotation: VC_COV_UNR
277		excluded
			Exclude Annotation: VC_COV_UNR
279		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
339	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T3,T4
1	Excluded		VC_COV_UNR

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T16,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T79
1	Covered	T79

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T2,T3,T10

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	11	84.62
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T10
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T3,T4
ReadWaitSt	252	Covered	T1,T3,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T3,T10
IdleSt->ReadSt	236	Covered	T1,T3,T4
InitSt->ErrorSt	315	Covered	T196,T197,T198
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T195,T199,T200
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T4,T5
ReadSt->ReadWaitSt	252	Covered	T1,T3,T4
ReadWaitSt->ErrorSt	276	Not Covered
ReadWaitSt->IdleSt	270	Covered	T1,T3,T4
ResetSt->ErrorSt	315	Covered	T77,T78,T79
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests	Exclude Annotation
AccessError	256	Covered	T1,T4,T5
CheckFailError	317	Covered	T79
FsmStateError	289	Covered	T2,T3,T10
MacroEccCorrError	221	Excluded		VC_COV_UNR
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded
AccessError->FsmStateError	325	Covered	T10,T7,T91
AccessError->MacroEccCorrError	221	Excluded
AccessError->NoError	235	Covered	T1,T4,T5
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded
CheckFailError->NoError	235	Covered	T79
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded
FsmStateError->NoError	235	Covered	T2,T3,T10
MacroEccCorrError->AccessError	256	Excluded
MacroEccCorrError->CheckFailError	317	Excluded
MacroEccCorrError->FsmStateError	325	Excluded
MacroEccCorrError->NoError	235	Excluded
NoError->AccessError	256	Covered	T1,T4,T5
NoError->CheckFailError	317	Covered	T79
NoError->FsmStateError	289	Covered	T2,T3,T11
NoError->MacroEccCorrError	221	Excluded

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	18	18	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests	Exclude Annotation
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T3,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T5,T117,T129
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T4,T5
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T10
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T10,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T10,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T79
1	0	Covered	T79
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T10
1	0	Covered	T2,T3,T10
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	431451301	430587063	0	0
DigestKnown_A	431451301	430587063	0	0
DigestOffsetMustBeRepresentable_A	1154	1154	0	0
EccErrorState_A	431451301	3316	0	0
ErrorKnown_A	431451301	430587063	0	0
FsmStateKnown_A	431451301	430587063	0	0
InitDoneKnown_A	431451301	430587063	0	0
InitReadLocksPartition_A	431451301	92772627	0	0
InitWriteLocksPartition_A	431451301	92772627	0	0
OffsetMustBeBlockAligned_A	1154	1154	0	0
OtpAddrKnown_A	431451301	430587063	0	0
OtpCmdKnown_A	431451301	430587063	0	0
OtpErrorState_A	431451301	0	0	0
OtpReqKnown_A	431451301	430587063	0	0
OtpSizeKnown_A	431451301	430587063	0	0
OtpWdataKnown_A	431451301	430587063	0	0
ReadLockPropagation_A	431451301	193184308	0	0
SizeMustBeBlockAligned_A	1154	1154	0	0
TlulGntKnown_A	431451301	430587063	0	0
TlulRdataKnown_A	431451301	430587063	0	0
TlulReadOnReadLock_A	431451301	7588	0	0
TlulRerrorKnown_A	431451301	430587063	0	0
TlulRvalidKnown_A	431451301	430587063	0	0
WriteLockPropagation_A	431451301	3152783	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	431451301	32161533	0	0
u_state_regs_A	431451301	430587063	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1154	1154	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	3316	0	0
T59	51704	0	0	0
T79	9295	3316	0	0
T80	16324	0	0	0
T113	11849	0	0	0
T173	8537	0	0	0
T174	37054	0	0	0
T175	28073	0	0	0
T176	13973	0	0	0
T177	73740	0	0	0
T178	10484	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	92772627	0	0
T1	68625	1116	0	0
T2	10470	4915	0	0
T3	9882	3436	0	0
T4	30941	255	0	0
T5	75471	4440	0	0
T6	20073	140	0	0
T7	33641	22431	0	0
T10	29404	16020	0	0
T11	10634	5012	0	0
T12	33901	23940	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	92772627	0	0
T1	68625	1116	0	0
T2	10470	4915	0	0
T3	9882	3436	0	0
T4	30941	255	0	0
T5	75471	4440	0	0
T6	20073	140	0	0
T7	33641	22431	0	0
T10	29404	16020	0	0
T11	10634	5012	0	0
T12	33901	23940	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1154	1154	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	193184308	0	0
T1	68625	20149	0	0
T2	10470	0	0	0
T3	9882	0	0	0
T4	30941	8705	0	0
T5	75471	9383	0	0
T6	20073	0	0	0
T7	33641	24665	0	0
T8	0	29387	0	0
T10	29404	17522	0	0
T11	10634	0	0	0
T12	33901	25915	0	0
T17	0	8596	0	0
T18	0	2849	0	0
T107	0	1667	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1154	1154	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	7588	0	0
T1	68625	3	0	0
T2	10470	17	0	0
T3	9882	0	0	0
T4	30941	1	0	0
T5	75471	5	0	0
T6	20073	0	0	0
T7	33641	20	0	0
T8	0	41	0	0
T10	29404	25	0	0
T11	10634	0	0	0
T12	33901	3	0	0
T105	0	17	0	0
T110	0	5	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	3152783	0	0
T1	68625	6035	0	0
T2	10470	0	0	0
T3	9882	0	0	0
T4	30941	0	0	0
T5	75471	0	0	0
T6	20073	0	0	0
T7	33641	0	0	0
T8	0	13838	0	0
T10	29404	0	0	0
T11	10634	0	0	0
T12	33901	0	0	0
T18	0	7027	0	0
T92	0	1195	0	0
T93	0	15238	0	0
T100	0	663	0	0
T101	0	1130	0	0
T102	0	38704	0	0
T103	0	6544	0	0
T118	0	4009	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	32161533	0	0
T1	68625	54210	0	0
T2	10470	0	0	0
T3	9882	2456	0	0
T4	30941	15223	0	0
T5	75471	65170	0	0
T6	20073	0	0	0
T7	33641	0	0	0
T8	0	196064	0	0
T10	29404	3798	0	0
T11	10634	0	0	0
T12	33901	0	0	0
T17	0	22862	0	0
T24	0	4952	0	0
T107	0	51521	0	0
T110	0	4820	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T156,T157,T158

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T96,T66,T70

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T16,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T78,T79,T159
1	Covered	T78,T79,T159

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T2,T10,T7

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T10
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T3,T4
ReadWaitSt	252	Covered	T1,T3,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T10,T7
IdleSt->ReadSt	236	Covered	T1,T3,T4
InitSt->ErrorSt	315	Covered	T195,T199,T200
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T3,T11,T95
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T5,T7
ReadSt->ReadWaitSt	252	Covered	T1,T3,T4
ReadWaitSt->ErrorSt	276	Covered	T201,T202,T203
ReadWaitSt->IdleSt	270	Covered	T1,T3,T4
ResetSt->ErrorSt	315	Covered	T77,T78,T79
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T5,T7
CheckFailError	317	Covered	T78,T79,T159
FsmStateError	289	Covered	T2,T10,T7
MacroEccCorrError	221	Covered	T96,T66,T70
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T7,T110,T91
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T1,T5,T8
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T78,T79,T159
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T10,T7
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T96,T156,T151
MacroEccCorrError->NoError	235	Covered	T66,T70,T164
NoError->AccessError	256	Covered	T1,T5,T7
NoError->CheckFailError	317	Covered	T78,T79,T159
NoError->FsmStateError	289	Covered	T2,T10,T12
NoError->MacroEccCorrError	221	Covered	T96,T66,T70

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T156,T157,T158
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T3,T11,T95
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T3,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T5,T9,T100
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T5,T7
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T96,T66,T70
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T201,T202,T203
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T10
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T10,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T10,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T78,T79,T159
1	0	Covered	T78,T79,T159
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T10,T7
1	0	Covered	T2,T3,T10
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	431451301	430587063	0	0
DigestKnown_A	431451301	430587063	0	0
DigestOffsetMustBeRepresentable_A	1154	1154	0	0
EccErrorState_A	431451301	9108	0	0
ErrorKnown_A	431451301	430587063	0	0
FsmStateKnown_A	431451301	430587063	0	0
InitDoneKnown_A	431451301	430587063	0	0
InitReadLocksPartition_A	431451301	92955341	0	0
InitWriteLocksPartition_A	431451301	92955341	0	0
OffsetMustBeBlockAligned_A	1154	1154	0	0
OtpAddrKnown_A	431451301	430587063	0	0
OtpCmdKnown_A	431451301	430587063	0	0
OtpErrorState_A	431451301	70	0	0
OtpReqKnown_A	431451301	430587063	0	0
OtpSizeKnown_A	431451301	430587063	0	0
OtpWdataKnown_A	431451301	430587063	0	0
ReadLockPropagation_A	431451301	188687932	0	0
SizeMustBeBlockAligned_A	1154	1154	0	0
TlulGntKnown_A	431451301	430587063	0	0
TlulRdataKnown_A	431451301	430587063	0	0
TlulReadOnReadLock_A	431451301	8005	0	0
TlulRerrorKnown_A	431451301	430587063	0	0
TlulRvalidKnown_A	431451301	430587063	0	0
WriteLockPropagation_A	431451301	2835126	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	431451301	30699042	0	0
u_state_regs_A	431451301	430587063	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1154	1154	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	9108	0	0
T78	9448	2590	0	0
T79	0	3316	0	0
T85	33734	0	0	0
T159	0	3202	0	0
T165	34245	0	0	0
T166	40671	0	0	0
T167	12737	0	0	0
T168	23302	0	0	0
T169	62995	0	0	0
T170	12753	0	0	0
T171	16548	0	0	0
T172	282669	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	92955341	0	0
T1	68625	1303	0	0
T2	10470	4949	0	0
T3	9882	3477	0	0
T4	30941	357	0	0
T5	75471	4661	0	0
T6	20073	191	0	0
T7	33641	22465	0	0
T10	29404	16088	0	0
T11	10634	5036	0	0
T12	33901	23991	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	92955341	0	0
T1	68625	1303	0	0
T2	10470	4949	0	0
T3	9882	3477	0	0
T4	30941	357	0	0
T5	75471	4661	0	0
T6	20073	191	0	0
T7	33641	22465	0	0
T10	29404	16088	0	0
T11	10634	5036	0	0
T12	33901	23991	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1154	1154	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	70	0	0
T3	9882	1	0	0
T4	30941	0	0	0
T5	75471	0	0	0
T6	20073	0	0	0
T7	33641	0	0	0
T8	443118	0	0	0
T10	29404	0	0	0
T11	10634	1	0	0
T12	33901	0	0	0
T95	0	1	0	0
T105	80627	0	0	0
T179	0	1	0	0
T180	0	1	0	0
T184	0	1	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	188687932	0	0
T1	68625	16782	0	0
T2	10470	0	0	0
T3	9882	0	0	0
T4	30941	2940	0	0
T5	75471	9985	0	0
T6	20073	0	0	0
T7	33641	25344	0	0
T8	0	30520	0	0
T10	29404	19401	0	0
T11	10634	0	0	0
T12	33901	25913	0	0
T17	0	2342	0	0
T107	0	4275	0	0
T110	0	4508	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1154	1154	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	8005	0	0
T1	68625	6	0	0
T2	10470	14	0	0
T3	9882	0	0	0
T4	30941	0	0	0
T5	75471	6	0	0
T6	20073	0	0	0
T7	33641	19	0	0
T8	0	35	0	0
T10	29404	17	0	0
T11	10634	0	0	0
T12	33901	8	0	0
T16	0	69	0	0
T105	0	15	0	0
T110	0	2	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	2835126	0	0
T1	68625	6035	0	0
T2	10470	0	0	0
T3	9882	0	0	0
T4	30941	0	0	0
T5	75471	6191	0	0
T6	20073	0	0	0
T7	33641	0	0	0
T8	0	11817	0	0
T10	29404	0	0	0
T11	10634	0	0	0
T12	33901	0	0	0
T92	0	2400	0	0
T93	0	5210	0	0
T100	0	1500	0	0
T101	0	2232	0	0
T107	0	5100	0	0
T108	0	15172	0	0
T117	0	2625	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	30699042	0	0
T1	68625	40935	0	0
T2	10470	0	0	0
T3	9882	2451	0	0
T4	30941	15155	0	0
T5	75471	64966	0	0
T6	20073	0	0	0
T7	33641	0	0	0
T8	0	199900	0	0
T10	29404	3764	0	0
T11	10634	2881	0	0
T12	33901	0	0	0
T17	0	22777	0	0
T107	0	51368	0	0
T110	0	4786	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T24,T69,T160

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T66,T70,T150

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T16,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T78,T161,T162
1	Covered	T78,T161,T162

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T2,T3,T10

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00111101000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T10
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T3,T4
ReadWaitSt	252	Covered	T1,T3,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T10,T7
IdleSt->ReadSt	236	Covered	T1,T3,T4
InitSt->ErrorSt	315	Covered	T195,T199,T200
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T3,T11,T95
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T5,T7
ReadSt->ReadWaitSt	252	Covered	T1,T3,T4
ReadWaitSt->ErrorSt	276	Covered	T163,T152,T204
ReadWaitSt->IdleSt	270	Covered	T1,T3,T4
ResetSt->ErrorSt	315	Covered	T77,T78,T79
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T5,T7
CheckFailError	317	Covered	T78,T161,T162
FsmStateError	289	Covered	T2,T3,T10
MacroEccCorrError	221	Covered	T24,T69,T66
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T7,T91,T205
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T1,T5,T7
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T78,T161,T162
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T3,T10
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T24,T69,T160
MacroEccCorrError->NoError	235	Covered	T66,T70,T163
NoError->AccessError	256	Covered	T1,T5,T7
NoError->CheckFailError	317	Covered	T78,T161,T162
NoError->FsmStateError	289	Covered	T2,T3,T10
NoError->MacroEccCorrError	221	Covered	T24,T69,T66

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T24,T69,T160
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T181,T182,T183
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T3,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T5,T100,T14
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T5,T7
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T66,T70,T150
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T163,T152,T204
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T10
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T10,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T10,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T78,T161,T162
1	0	Covered	T78,T161,T162
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T10
1	0	Covered	T2,T3,T10
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	431451301	430587063	0	0
DigestKnown_A	431451301	430587063	0	0
DigestOffsetMustBeRepresentable_A	1154	1154	0	0
EccErrorState_A	431451301	8475	0	0
ErrorKnown_A	431451301	430587063	0	0
FsmStateKnown_A	431451301	430587063	0	0
InitDoneKnown_A	431451301	430587063	0	0
InitReadLocksPartition_A	431451301	93136856	0	0
InitWriteLocksPartition_A	431451301	93136856	0	0
OffsetMustBeBlockAligned_A	1154	1154	0	0
OtpAddrKnown_A	431451301	430587063	0	0
OtpCmdKnown_A	431451301	430587063	0	0
OtpErrorState_A	431451301	58	0	0
OtpReqKnown_A	431451301	430587063	0	0
OtpSizeKnown_A	431451301	430587063	0	0
OtpWdataKnown_A	431451301	430587063	0	0
ReadLockPropagation_A	431451301	197759695	0	0
SizeMustBeBlockAligned_A	1154	1154	0	0
TlulGntKnown_A	431451301	430587063	0	0
TlulRdataKnown_A	431451301	430587063	0	0
TlulReadOnReadLock_A	431451301	7967	0	0
TlulRerrorKnown_A	431451301	430587063	0	0
TlulRvalidKnown_A	431451301	430587063	0	0
WriteLockPropagation_A	431451301	1542491	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	431451301	18752261	0	0
u_state_regs_A	431451301	430587063	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1154	1154	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	8475	0	0
T78	9448	2590	0	0
T85	33734	0	0	0
T161	0	2888	0	0
T162	0	2997	0	0
T165	34245	0	0	0
T166	40671	0	0	0
T167	12737	0	0	0
T168	23302	0	0	0
T169	62995	0	0	0
T170	12753	0	0	0
T171	16548	0	0	0
T172	282669	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	93136856	0	0
T1	68625	1490	0	0
T2	10470	4983	0	0
T3	9882	3511	0	0
T4	30941	459	0	0
T5	75471	4882	0	0
T6	20073	242	0	0
T7	33641	22499	0	0
T10	29404	16156	0	0
T11	10634	5053	0	0
T12	33901	24042	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	93136856	0	0
T1	68625	1490	0	0
T2	10470	4983	0	0
T3	9882	3511	0	0
T4	30941	459	0	0
T5	75471	4882	0	0
T6	20073	242	0	0
T7	33641	22499	0	0
T10	29404	16156	0	0
T11	10634	5053	0	0
T12	33901	24042	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1154	1154	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	58	0	0
T66	107329	0	0	0
T100	467665	0	0	0
T117	52691	0	0	0
T152	0	2	0	0
T153	68512	0	0	0
T154	27492	0	0	0
T163	0	1	0	0
T181	10272	1	0	0
T182	14660	1	0	0
T183	12662	1	0	0
T189	0	1	0	0
T190	0	1	0	0
T191	0	1	0	0
T192	0	1	0	0
T193	0	1	0	0
T194	22807	0	0	0
T195	14583	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	197759695	0	0
T1	68625	15664	0	0
T2	10470	0	0	0
T3	9882	0	0	0
T4	30941	8640	0	0
T5	75471	6662	0	0
T6	20073	0	0	0
T7	33641	25342	0	0
T8	0	23410	0	0
T10	29404	17518	0	0
T11	10634	0	0	0
T12	33901	0	0	0
T17	0	8195	0	0
T18	0	5793	0	0
T98	0	19298	0	0
T107	0	4253	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1154	1154	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	7967	0	0
T1	68625	2	0	0
T2	10470	13	0	0
T3	9882	0	0	0
T4	30941	0	0	0
T5	75471	6	0	0
T6	20073	0	0	0
T7	33641	21	0	0
T8	0	27	0	0
T10	29404	16	0	0
T11	10634	0	0	0
T12	33901	1	0	0
T105	0	13	0	0
T107	0	1	0	0
T110	0	8	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	1542491	0	0
T4	30941	6420	0	0
T5	75471	3738	0	0
T6	20073	0	0	0
T7	33641	0	0	0
T8	443118	2027	0	0
T10	29404	0	0	0
T11	10634	0	0	0
T12	33901	0	0	0
T18	0	2376	0	0
T70	0	13338	0	0
T92	0	1195	0	0
T93	0	6046	0	0
T100	0	4663	0	0
T102	0	9199	0	0
T105	80627	0	0	0
T106	13522	0	0	0
T117	0	3047	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	18752261	0	0
T1	68625	53904	0	0
T2	10470	0	0	0
T3	9882	0	0	0
T4	30941	15087	0	0
T5	75471	64762	0	0
T6	20073	0	0	0
T7	33641	0	0	0
T8	0	63368	0	0
T10	29404	0	0	0
T11	10634	0	0	0
T12	33901	0	0	0
T17	0	35416	0	0
T18	0	26390	0	0
T91	0	3491	0	0
T92	0	28266	0	0
T107	0	51215	0	0
T110	0	4752	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0