Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.57	96.10	96.15	97.00		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.57	96.10	96.15	97.00		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T69,T83,T130

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T132,T66,T70

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T16,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T78
1	Covered	T78

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T2,T3,T10

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

---

FSM Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T10
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T3,T4
ReadWaitSt	252	Covered	T1,T3,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T10,T7
IdleSt->ReadSt	236	Covered	T1,T3,T4
InitSt->ErrorSt	315	Covered	T3,T11,T95
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T181,T182,T183
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T4,T5
ReadSt->ReadWaitSt	252	Covered	T1,T3,T4
ReadWaitSt->ErrorSt	276	Covered	T150,T151,T152
ReadWaitSt->IdleSt	270	Covered	T1,T3,T4
ResetSt->ErrorSt	315	Covered	T77,T78,T79
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T4,T5
CheckFailError	317	Covered	T78
FsmStateError	289	Covered	T2,T3,T10
MacroEccCorrError	221	Covered	T132,T69,T66
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T7,T91,T100
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T1,T4,T5
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T78
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T3,T10
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T132,T69,T83
MacroEccCorrError->NoError	235	Covered	T66,T70,T52
NoError->AccessError	256	Covered	T1,T4,T5
NoError->CheckFailError	317	Covered	T78
NoError->FsmStateError	289	Covered	T2,T3,T10
NoError->MacroEccCorrError	221	Covered	T132,T69,T66

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T69,T83,T130
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T160,T206,T207
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T3,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T5,T100,T129
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T4,T5
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T132,T66,T70
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T150,T151,T152
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T10
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T10,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T10,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T78
1	0	Covered	T78
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T10
1	0	Covered	T2,T3,T10
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	431451301	430587063	0	0
DigestKnown_A	431451301	430587063	0	0
DigestOffsetMustBeRepresentable_A	1154	1154	0	0
EccErrorState_A	431451301	2590	0	0
ErrorKnown_A	431451301	430587063	0	0
FsmStateKnown_A	431451301	430587063	0	0
InitDoneKnown_A	431451301	430587063	0	0
InitReadLocksPartition_A	431451301	93317478	0	0
InitWriteLocksPartition_A	431451301	93317478	0	0
OffsetMustBeBlockAligned_A	1154	1154	0	0
OtpAddrKnown_A	431451301	430587063	0	0
OtpCmdKnown_A	431451301	430587063	0	0
OtpErrorState_A	431451301	44	0	0
OtpReqKnown_A	431451301	430587063	0	0
OtpSizeKnown_A	431451301	430587063	0	0
OtpWdataKnown_A	431451301	430587063	0	0
ReadLockPropagation_A	431451301	191784007	0	0
SizeMustBeBlockAligned_A	1154	1154	0	0
TlulGntKnown_A	431451301	430587063	0	0
TlulRdataKnown_A	431451301	430587063	0	0
TlulReadOnReadLock_A	431451301	7925	0	0
TlulRerrorKnown_A	431451301	430587063	0	0
TlulRvalidKnown_A	431451301	430587063	0	0
WriteLockPropagation_A	431451301	2796286	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	431451301	29390420	0	0
u_state_regs_A	431451301	430587063	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1154	1154	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	2590	0	0
T78	9448	2590	0	0
T85	33734	0	0	0
T165	34245	0	0	0
T166	40671	0	0	0
T167	12737	0	0	0
T168	23302	0	0	0
T169	62995	0	0	0
T170	12753	0	0	0
T171	16548	0	0	0
T172	282669	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	93317478	0	0
T1	68625	1677	0	0
T2	10470	5017	0	0
T3	9882	3545	0	0
T4	30941	561	0	0
T5	75471	5103	0	0
T6	20073	293	0	0
T7	33641	22533	0	0
T10	29404	16224	0	0
T11	10634	5070	0	0
T12	33901	24093	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	93317478	0	0
T1	68625	1677	0	0
T2	10470	5017	0	0
T3	9882	3545	0	0
T4	30941	561	0	0
T5	75471	5103	0	0
T6	20073	293	0	0
T7	33641	22533	0	0
T10	29404	16224	0	0
T11	10634	5070	0	0
T12	33901	24093	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1154	1154	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	44	0	0
T67	31608	0	0	0
T81	9148	0	0	0
T101	48547	0	0	0
T118	64456	0	0	0
T123	36621	0	0	0
T150	0	1	0	0
T151	0	2	0	0
T152	0	1	0	0
T157	0	1	0	0
T160	13125	1	0	0
T184	11907	0	0	0
T205	19178	0	0	0
T206	0	1	0	0
T207	0	1	0	0
T208	0	1	0	0
T209	0	1	0	0
T210	0	1	0	0
T211	11168	0	0	0
T212	6279	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	191784007	0	0
T1	68625	19070	0	0
T2	10470	0	0	0
T3	9882	0	0	0
T4	30941	9157	0	0
T5	75471	10103	0	0
T6	20073	0	0	0
T7	33641	24770	0	0
T8	0	23541	0	0
T10	29404	16537	0	0
T11	10634	0	0	0
T12	33901	25901	0	0
T17	0	4378	0	0
T107	0	7803	0	0
T110	0	4506	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1154	1154	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	7925	0	0
T1	68625	3	0	0
T2	10470	14	0	0
T3	9882	0	0	0
T4	30941	1	0	0
T5	75471	5	0	0
T6	20073	0	0	0
T7	33641	25	0	0
T8	0	33	0	0
T10	29404	17	0	0
T11	10634	0	0	0
T12	33901	8	0	0
T105	0	17	0	0
T110	0	10	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	2796286	0	0
T1	68625	6742	0	0
T2	10470	0	0	0
T3	9882	0	0	0
T4	30941	0	0	0
T5	75471	3769	0	0
T6	20073	0	0	0
T7	33641	0	0	0
T8	0	11996	0	0
T10	29404	0	0	0
T11	10634	0	0	0
T12	33901	0	0	0
T17	0	6596	0	0
T66	0	10684	0	0
T92	0	1205	0	0
T93	0	3982	0	0
T100	0	3524	0	0
T117	0	2197	0	0
T118	0	5486	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	29390420	0	0
T1	68625	53751	0	0
T2	10470	0	0	0
T3	9882	0	0	0
T4	30941	15019	0	0
T5	75471	64558	0	0
T6	20073	0	0	0
T7	33641	0	0	0
T8	0	205876	0	0
T10	29404	0	0	0
T11	10634	0	0	0
T12	33901	0	0	0
T17	0	22616	0	0
T18	0	26305	0	0
T91	0	3457	0	0
T98	0	18753	0	0
T107	0	42646	0	0
T110	0	4718	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T68,T83,T58

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T66,T150,T52

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T16,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T78,T79,T159
1	Covered	T78,T79,T159

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T2,T3,T10

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T8,T98

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T8,T98

---

FSM Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T3,T10
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T3,T4
ReadWaitSt	252	Covered	T1,T3,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T10,T7
IdleSt->ReadSt	236	Covered	T1,T3,T4
InitSt->ErrorSt	315	Covered	T3,T11,T95
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T69,T160,T206
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T5,T10
ReadSt->ReadWaitSt	252	Covered	T1,T3,T4
ReadWaitSt->ErrorSt	276	Covered	T169,T213,T202
ReadWaitSt->IdleSt	270	Covered	T1,T3,T4
ResetSt->ErrorSt	315	Covered	T77,T78,T79
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T5,T10
CheckFailError	317	Covered	T78,T79,T159
FsmStateError	289	Covered	T2,T3,T10
MacroEccCorrError	221	Covered	T68,T66,T150
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T10,T7,T91
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T1,T5,T7
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T78,T79,T159
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T3,T10
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T68,T150,T83
MacroEccCorrError->NoError	235	Covered	T66,T52,T151
NoError->AccessError	256	Covered	T1,T5,T10
NoError->CheckFailError	317	Covered	T78,T79,T159
NoError->FsmStateError	289	Covered	T2,T3,T11
NoError->MacroEccCorrError	221	Covered	T68,T66,T150

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T8,T98
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T68,T83,T58
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T69,T214,T156
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T3,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T5,T100,T117
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T5,T10
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T66,T150,T52
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T169,T213,T202
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T10
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T10,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T10,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T78,T79,T159
1	0	Covered	T78,T79,T159
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T10
1	0	Covered	T2,T3,T10
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	431451301	430587063	0	0
DigestKnown_A	431451301	430587063	0	0
DigestOffsetMustBeRepresentable_A	1154	1154	0	0
EccErrorState_A	431451301	9108	0	0
ErrorKnown_A	431451301	430587063	0	0
FsmStateKnown_A	431451301	430587063	0	0
InitDoneKnown_A	431451301	430587063	0	0
InitReadLocksPartition_A	431451301	93497323	0	0
InitWriteLocksPartition_A	431451301	93497323	0	0
OffsetMustBeBlockAligned_A	1154	1154	0	0
OtpAddrKnown_A	431451301	430587063	0	0
OtpCmdKnown_A	431451301	430587063	0	0
OtpErrorState_A	431451301	38	0	0
OtpReqKnown_A	431451301	430587063	0	0
OtpSizeKnown_A	431451301	430587063	0	0
OtpWdataKnown_A	431451301	430587063	0	0
ReadLockPropagation_A	431451301	195037330	0	0
SizeMustBeBlockAligned_A	1154	1154	0	0
TlulGntKnown_A	431451301	430587063	0	0
TlulRdataKnown_A	431451301	430587063	0	0
TlulReadOnReadLock_A	431451301	7577	0	0
TlulRerrorKnown_A	431451301	430587063	0	0
TlulRvalidKnown_A	431451301	430587063	0	0
WriteLockPropagation_A	431451301	1158822	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	431451301	14339933	0	0
u_state_regs_A	431451301	430587063	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1154	1154	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	9108	0	0
T78	9448	2590	0	0
T79	0	3316	0	0
T85	33734	0	0	0
T159	0	3202	0	0
T165	34245	0	0	0
T166	40671	0	0	0
T167	12737	0	0	0
T168	23302	0	0	0
T169	62995	0	0	0
T170	12753	0	0	0
T171	16548	0	0	0
T172	282669	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	93497323	0	0
T1	68625	1864	0	0
T2	10470	5051	0	0
T3	9882	3579	0	0
T4	30941	663	0	0
T5	75471	5324	0	0
T6	20073	344	0	0
T7	33641	22567	0	0
T10	29404	16292	0	0
T11	10634	5087	0	0
T12	33901	24144	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	93497323	0	0
T1	68625	1864	0	0
T2	10470	5051	0	0
T3	9882	3579	0	0
T4	30941	663	0	0
T5	75471	5324	0	0
T6	20073	344	0	0
T7	33641	22567	0	0
T10	29404	16292	0	0
T11	10634	5087	0	0
T12	33901	24144	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1154	1154	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	38	0	0
T9	178466	0	0	0
T30	17023	0	0	0
T68	11810	0	0	0
T69	12672	1	0	0
T91	12043	0	0	0
T92	35144	0	0	0
T93	75505	0	0	0
T94	91584	0	0	0
T95	14010	0	0	0
T156	0	1	0	0
T158	0	1	0	0
T169	0	1	0	0
T214	0	1	0	0
T215	0	1	0	0
T216	0	1	0	0
T217	0	1	0	0
T218	0	1	0	0
T219	0	1	0	0
T220	22673	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	195037330	0	0
T1	68625	15834	0	0
T2	10470	0	0	0
T3	9882	0	0	0
T4	30941	709	0	0
T5	75471	9181	0	0
T6	20073	0	0	0
T7	33641	24659	0	0
T8	0	31771	0	0
T10	29404	19399	0	0
T11	10634	0	0	0
T12	33901	25509	0	0
T17	0	9539	0	0
T107	0	7777	0	0
T110	0	4504	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1154	1154	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	7577	0	0
T1	68625	3	0	0
T2	10470	14	0	0
T3	9882	0	0	0
T4	30941	0	0	0
T5	75471	8	0	0
T6	20073	0	0	0
T7	33641	25	0	0
T8	0	37	0	0
T10	29404	20	0	0
T11	10634	0	0	0
T12	33901	10	0	0
T105	0	20	0	0
T107	0	1	0	0
T110	0	3	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	1158822	0	0
T8	443118	18753	0	0
T15	5841	0	0	0
T16	100906	0	0	0
T17	45410	0	0	0
T18	35697	0	0	0
T24	14149	0	0	0
T40	15665	0	0	0
T66	0	12577	0	0
T98	0	11321	0	0
T99	0	3436	0	0
T101	0	1276	0	0
T103	0	2873	0	0
T106	13522	0	0	0
T107	59325	0	0	0
T109	0	2739	0	0
T110	15338	0	0	0
T118	0	7537	0	0
T129	0	663	0	0
T221	0	14013	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	14339933	0	0
T7	33641	0	0	0
T8	443118	139472	0	0
T10	29404	3662	0	0
T11	10634	0	0	0
T12	33901	0	0	0
T15	5841	0	0	0
T66	0	87892	0	0
T69	0	2507	0	0
T98	0	18702	0	0
T99	0	30308	0	0
T101	0	24462	0	0
T105	80627	0	0	0
T106	13522	0	0	0
T107	59325	0	0	0
T110	15338	0	0	0
T118	0	53667	0	0
T123	0	26060	0	0
T129	0	15162	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431451301	430587063	0	0
T1	68625	67884	0	0
T2	10470	10336	0	0
T3	9882	9574	0	0
T4	30941	30514	0	0
T5	75471	74331	0	0
T6	20073	19770	0	0
T7	33641	33395	0	0
T10	29404	29150	0	0
T11	10634	10366	0	0
T12	33901	33645	0	0