SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
94.91 | 93.85 | 96.35 | 95.32 | 92.36 | 96.81 | 96.33 | 93.35 |
T1270 | /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.2724833977 | Mar 31 12:48:18 PM PDT 24 | Mar 31 12:48:19 PM PDT 24 | 76379485 ps | ||
T1271 | /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.1067432660 | Mar 31 12:47:52 PM PDT 24 | Mar 31 12:47:55 PM PDT 24 | 100598989 ps | ||
T1272 | /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.900074964 | Mar 31 12:48:15 PM PDT 24 | Mar 31 12:48:17 PM PDT 24 | 67708174 ps | ||
T368 | /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.1944354361 | Mar 31 12:48:08 PM PDT 24 | Mar 31 12:48:26 PM PDT 24 | 10296883781 ps | ||
T1273 | /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.2211760554 | Mar 31 12:47:29 PM PDT 24 | Mar 31 12:47:35 PM PDT 24 | 566607022 ps | ||
T309 | /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.2255971281 | Mar 31 12:47:31 PM PDT 24 | Mar 31 12:47:34 PM PDT 24 | 150028010 ps | ||
T1274 | /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.789665249 | Mar 31 12:47:29 PM PDT 24 | Mar 31 12:47:31 PM PDT 24 | 555148319 ps | ||
T310 | /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.1172130416 | Mar 31 12:47:40 PM PDT 24 | Mar 31 12:47:44 PM PDT 24 | 115377468 ps | ||
T1275 | /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.1089700696 | Mar 31 12:47:44 PM PDT 24 | Mar 31 12:47:47 PM PDT 24 | 443890423 ps | ||
T370 | /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.2643811530 | Mar 31 12:47:51 PM PDT 24 | Mar 31 12:48:03 PM PDT 24 | 2501986613 ps | ||
T1276 | /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.96645483 | Mar 31 12:48:01 PM PDT 24 | Mar 31 12:48:03 PM PDT 24 | 587361438 ps | ||
T1277 | /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.3479701394 | Mar 31 12:47:30 PM PDT 24 | Mar 31 12:47:32 PM PDT 24 | 1003205869 ps | ||
T1278 | /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.3941012812 | Mar 31 12:47:57 PM PDT 24 | Mar 31 12:47:59 PM PDT 24 | 38727219 ps | ||
T1279 | /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.1021017672 | Mar 31 12:47:36 PM PDT 24 | Mar 31 12:47:38 PM PDT 24 | 592599452 ps | ||
T1280 | /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.2446809618 | Mar 31 12:48:05 PM PDT 24 | Mar 31 12:48:06 PM PDT 24 | 80609942 ps | ||
T1281 | /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.3298850865 | Mar 31 12:47:46 PM PDT 24 | Mar 31 12:47:53 PM PDT 24 | 208981692 ps | ||
T1282 | /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.62801898 | Mar 31 12:48:14 PM PDT 24 | Mar 31 12:48:15 PM PDT 24 | 42591180 ps | ||
T1283 | /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.1162863778 | Mar 31 12:47:38 PM PDT 24 | Mar 31 12:47:41 PM PDT 24 | 110695459 ps | ||
T1284 | /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.917342779 | Mar 31 12:47:44 PM PDT 24 | Mar 31 12:47:46 PM PDT 24 | 136980747 ps | ||
T311 | /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.2256208772 | Mar 31 12:47:36 PM PDT 24 | Mar 31 12:47:39 PM PDT 24 | 96453314 ps | ||
T1285 | /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.138654696 | Mar 31 12:47:51 PM PDT 24 | Mar 31 12:47:53 PM PDT 24 | 70825126 ps | ||
T1286 | /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.3213878867 | Mar 31 12:48:15 PM PDT 24 | Mar 31 12:48:17 PM PDT 24 | 528566075 ps | ||
T371 | /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.1093281809 | Mar 31 12:47:59 PM PDT 24 | Mar 31 12:48:15 PM PDT 24 | 10263563536 ps | ||
T1287 | /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.2496988394 | Mar 31 12:47:46 PM PDT 24 | Mar 31 12:47:50 PM PDT 24 | 380675401 ps | ||
T1288 | /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.2626277301 | Mar 31 12:47:37 PM PDT 24 | Mar 31 12:47:38 PM PDT 24 | 129000889 ps | ||
T1289 | /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.713743788 | Mar 31 12:47:59 PM PDT 24 | Mar 31 12:48:19 PM PDT 24 | 1575663303 ps | ||
T1290 | /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.665614125 | Mar 31 12:48:07 PM PDT 24 | Mar 31 12:48:09 PM PDT 24 | 280849036 ps | ||
T1291 | /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.2928573190 | Mar 31 12:48:02 PM PDT 24 | Mar 31 12:48:04 PM PDT 24 | 80739731 ps | ||
T1292 | /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.3153622274 | Mar 31 12:47:30 PM PDT 24 | Mar 31 12:47:36 PM PDT 24 | 431736354 ps | ||
T1293 | /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.2579480779 | Mar 31 12:47:55 PM PDT 24 | Mar 31 12:48:03 PM PDT 24 | 546887938 ps | ||
T1294 | /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.3601286844 | Mar 31 12:48:08 PM PDT 24 | Mar 31 12:48:21 PM PDT 24 | 9715517522 ps | ||
T312 | /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.2806944115 | Mar 31 12:48:00 PM PDT 24 | Mar 31 12:48:02 PM PDT 24 | 170567211 ps | ||
T1295 | /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.554666125 | Mar 31 12:48:05 PM PDT 24 | Mar 31 12:48:08 PM PDT 24 | 202277770 ps | ||
T315 | /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.3929251374 | Mar 31 12:47:38 PM PDT 24 | Mar 31 12:47:40 PM PDT 24 | 248489398 ps | ||
T1296 | /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.3112554045 | Mar 31 12:48:12 PM PDT 24 | Mar 31 12:48:14 PM PDT 24 | 64694445 ps | ||
T1297 | /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.144622602 | Mar 31 12:48:15 PM PDT 24 | Mar 31 12:48:17 PM PDT 24 | 116118102 ps | ||
T316 | /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.4138149802 | Mar 31 12:47:49 PM PDT 24 | Mar 31 12:47:51 PM PDT 24 | 649278163 ps | ||
T1298 | /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.536716130 | Mar 31 12:47:59 PM PDT 24 | Mar 31 12:48:07 PM PDT 24 | 2752071027 ps | ||
T266 | /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.3751942752 | Mar 31 12:47:50 PM PDT 24 | Mar 31 12:48:01 PM PDT 24 | 639185099 ps | ||
T1299 | /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.314954551 | Mar 31 12:47:51 PM PDT 24 | Mar 31 12:48:02 PM PDT 24 | 1746496717 ps | ||
T1300 | /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.443350296 | Mar 31 12:47:43 PM PDT 24 | Mar 31 12:47:50 PM PDT 24 | 593043799 ps | ||
T1301 | /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.3548809407 | Mar 31 12:47:28 PM PDT 24 | Mar 31 12:47:30 PM PDT 24 | 67514219 ps | ||
T1302 | /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.903004439 | Mar 31 12:47:40 PM PDT 24 | Mar 31 12:47:42 PM PDT 24 | 38756304 ps | ||
T1303 | /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.3141093026 | Mar 31 12:47:39 PM PDT 24 | Mar 31 12:47:41 PM PDT 24 | 92803642 ps | ||
T317 | /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.3176006691 | Mar 31 12:47:22 PM PDT 24 | Mar 31 12:47:25 PM PDT 24 | 1446665739 ps | ||
T1304 | /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.1952949350 | Mar 31 12:48:13 PM PDT 24 | Mar 31 12:48:14 PM PDT 24 | 78714232 ps | ||
T1305 | /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.3269062294 | Mar 31 12:48:15 PM PDT 24 | Mar 31 12:48:16 PM PDT 24 | 70815282 ps | ||
T372 | /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.947154158 | Mar 31 12:47:39 PM PDT 24 | Mar 31 12:47:59 PM PDT 24 | 5063270900 ps | ||
T1306 | /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.4052592051 | Mar 31 12:48:00 PM PDT 24 | Mar 31 12:48:02 PM PDT 24 | 139224926 ps | ||
T1307 | /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.2864345662 | Mar 31 12:48:23 PM PDT 24 | Mar 31 12:48:24 PM PDT 24 | 70331423 ps | ||
T1308 | /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.2173875010 | Mar 31 12:48:01 PM PDT 24 | Mar 31 12:48:04 PM PDT 24 | 237315863 ps | ||
T1309 | /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.425044515 | Mar 31 12:47:50 PM PDT 24 | Mar 31 12:47:53 PM PDT 24 | 56331517 ps | ||
T1310 | /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.3666235387 | Mar 31 12:47:38 PM PDT 24 | Mar 31 12:47:40 PM PDT 24 | 69086573 ps | ||
T1311 | /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.1255905212 | Mar 31 12:47:42 PM PDT 24 | Mar 31 12:47:44 PM PDT 24 | 141231852 ps | ||
T1312 | /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.2485940630 | Mar 31 12:47:29 PM PDT 24 | Mar 31 12:47:31 PM PDT 24 | 42762599 ps | ||
T313 | /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.827586426 | Mar 31 12:47:46 PM PDT 24 | Mar 31 12:47:48 PM PDT 24 | 57667081 ps | ||
T1313 | /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.2818125336 | Mar 31 12:48:12 PM PDT 24 | Mar 31 12:48:13 PM PDT 24 | 66289938 ps | ||
T318 | /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.1342541399 | Mar 31 12:47:30 PM PDT 24 | Mar 31 12:47:35 PM PDT 24 | 313280124 ps | ||
T328 | /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.3955133666 | Mar 31 12:47:37 PM PDT 24 | Mar 31 12:47:40 PM PDT 24 | 1501571829 ps | ||
T319 | /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.615965051 | Mar 31 12:47:31 PM PDT 24 | Mar 31 12:47:36 PM PDT 24 | 1162970622 ps | ||
T1314 | /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.4125561636 | Mar 31 12:47:50 PM PDT 24 | Mar 31 12:47:53 PM PDT 24 | 1026288043 ps | ||
T1315 | /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.460950730 | Mar 31 12:47:38 PM PDT 24 | Mar 31 12:47:41 PM PDT 24 | 205748473 ps | ||
T1316 | /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.2913773565 | Mar 31 12:48:04 PM PDT 24 | Mar 31 12:48:06 PM PDT 24 | 74436553 ps | ||
T1317 | /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.403596658 | Mar 31 12:47:38 PM PDT 24 | Mar 31 12:47:45 PM PDT 24 | 347648198 ps | ||
T1318 | /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.1792658808 | Mar 31 12:47:57 PM PDT 24 | Mar 31 12:48:00 PM PDT 24 | 321682627 ps | ||
T1319 | /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.1336920773 | Mar 31 12:47:56 PM PDT 24 | Mar 31 12:47:58 PM PDT 24 | 171553485 ps | ||
T1320 | /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.1470831565 | Mar 31 12:47:58 PM PDT 24 | Mar 31 12:48:06 PM PDT 24 | 2212745702 ps | ||
T1321 | /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.697162196 | Mar 31 12:48:08 PM PDT 24 | Mar 31 12:48:14 PM PDT 24 | 209297433 ps | ||
T1322 | /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.3573724877 | Mar 31 12:47:46 PM PDT 24 | Mar 31 12:47:48 PM PDT 24 | 138201178 ps | ||
T1323 | /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.3626418776 | Mar 31 12:48:14 PM PDT 24 | Mar 31 12:48:16 PM PDT 24 | 38772753 ps | ||
T1324 | /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.2681158326 | Mar 31 12:48:11 PM PDT 24 | Mar 31 12:48:12 PM PDT 24 | 602626335 ps | ||
T1325 | /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.1324184213 | Mar 31 12:48:05 PM PDT 24 | Mar 31 12:48:07 PM PDT 24 | 150390756 ps | ||
T1326 | /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.2921387347 | Mar 31 12:47:36 PM PDT 24 | Mar 31 12:47:37 PM PDT 24 | 125675326 ps | ||
T373 | /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.3413289405 | Mar 31 12:47:57 PM PDT 24 | Mar 31 12:48:16 PM PDT 24 | 1357051517 ps | ||
T1327 | /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.3058231242 | Mar 31 12:48:14 PM PDT 24 | Mar 31 12:48:16 PM PDT 24 | 567115340 ps | ||
T1328 | /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.2839292966 | Mar 31 12:47:38 PM PDT 24 | Mar 31 12:47:39 PM PDT 24 | 47295574 ps | ||
T374 | /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.643288478 | Mar 31 12:47:36 PM PDT 24 | Mar 31 12:47:54 PM PDT 24 | 1189264775 ps | ||
T369 | /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.3612540850 | Mar 31 12:47:49 PM PDT 24 | Mar 31 12:47:58 PM PDT 24 | 2539605090 ps | ||
T1329 | /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.1826812597 | Mar 31 12:47:37 PM PDT 24 | Mar 31 12:47:39 PM PDT 24 | 148211772 ps |
Test location | /workspace/coverage/default/27.otp_ctrl_parallel_key_req.4040952817 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 707473377 ps |
CPU time | 18.9 seconds |
Started | Mar 31 03:30:36 PM PDT 24 |
Finished | Mar 31 03:30:55 PM PDT 24 |
Peak memory | 242276 kb |
Host | smart-b0475ea8-78dd-4103-88d4-e3001e46284f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4040952817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.4040952817 |
Directory | /workspace/27.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/20.otp_ctrl_stress_all.176756037 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 22045311756 ps |
CPU time | 167.93 seconds |
Started | Mar 31 03:30:09 PM PDT 24 |
Finished | Mar 31 03:32:57 PM PDT 24 |
Peak memory | 248864 kb |
Host | smart-0fc3f491-5c49-4e5a-a933-ae839550b598 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176756037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all. 176756037 |
Directory | /workspace/20.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/26.otp_ctrl_stress_all.3588500422 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 218596296523 ps |
CPU time | 377.13 seconds |
Started | Mar 31 03:30:36 PM PDT 24 |
Finished | Mar 31 03:36:53 PM PDT 24 |
Peak memory | 308140 kb |
Host | smart-2fdf04cc-9b35-4066-b277-fe79e7bcdc2f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588500422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all .3588500422 |
Directory | /workspace/26.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/33.otp_ctrl_stress_all_with_rand_reset.3342790391 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 44938841073 ps |
CPU time | 1217.62 seconds |
Started | Mar 31 03:31:03 PM PDT 24 |
Finished | Mar 31 03:51:21 PM PDT 24 |
Peak memory | 430960 kb |
Host | smart-a0bf9b74-e713-4644-8f4f-93960d45cafc |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342790391 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all_with_rand_reset.3342790391 |
Directory | /workspace/33.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/2.otp_ctrl_stress_all.2328189807 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 9742891876 ps |
CPU time | 146.55 seconds |
Started | Mar 31 03:28:44 PM PDT 24 |
Finished | Mar 31 03:31:11 PM PDT 24 |
Peak memory | 290940 kb |
Host | smart-2303a6fa-7a40-4538-8507-afd584ff1c51 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328189807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all. 2328189807 |
Directory | /workspace/2.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/102.otp_ctrl_init_fail.3929787720 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 377984795 ps |
CPU time | 3 seconds |
Started | Mar 31 03:32:51 PM PDT 24 |
Finished | Mar 31 03:32:54 PM PDT 24 |
Peak memory | 242056 kb |
Host | smart-e26d09ed-85e7-4d94-8df2-e48c34465001 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3929787720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.3929787720 |
Directory | /workspace/102.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/2.otp_ctrl_sec_cm.2289669668 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 10511418264 ps |
CPU time | 169.54 seconds |
Started | Mar 31 03:28:40 PM PDT 24 |
Finished | Mar 31 03:31:30 PM PDT 24 |
Peak memory | 264328 kb |
Host | smart-f8247e2c-24ec-4e6f-8e0d-0b81ee6b1a62 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289669668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.2289669668 |
Directory | /workspace/2.otp_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/5.otp_ctrl_check_fail.1020089163 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 2496096524 ps |
CPU time | 29.75 seconds |
Started | Mar 31 03:29:00 PM PDT 24 |
Finished | Mar 31 03:29:30 PM PDT 24 |
Peak memory | 241884 kb |
Host | smart-d342e0e8-cce3-4524-a398-e7c79a0abc6b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1020089163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.1020089163 |
Directory | /workspace/5.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/27.otp_ctrl_stress_all.1319821919 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 19322557047 ps |
CPU time | 262.95 seconds |
Started | Mar 31 03:30:42 PM PDT 24 |
Finished | Mar 31 03:35:05 PM PDT 24 |
Peak memory | 256972 kb |
Host | smart-4e702e5d-6bc8-41f4-95e5-a50fea31c1ee |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319821919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all .1319821919 |
Directory | /workspace/27.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/182.otp_ctrl_init_fail.1131304112 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 257301943 ps |
CPU time | 3.48 seconds |
Started | Mar 31 03:33:39 PM PDT 24 |
Finished | Mar 31 03:33:43 PM PDT 24 |
Peak memory | 242080 kb |
Host | smart-a877fdd8-0e2b-4575-9eb1-c9fd0bd9c84b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1131304112 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.1131304112 |
Directory | /workspace/182.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/183.otp_ctrl_parallel_lc_esc.1020065458 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 303820840 ps |
CPU time | 4.27 seconds |
Started | Mar 31 03:33:39 PM PDT 24 |
Finished | Mar 31 03:33:43 PM PDT 24 |
Peak memory | 241732 kb |
Host | smart-9957e815-8fe1-4b8a-97bd-f601f5b93b77 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1020065458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.1020065458 |
Directory | /workspace/183.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.1624575829 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 19119734907 ps |
CPU time | 23.82 seconds |
Started | Mar 31 12:47:30 PM PDT 24 |
Finished | Mar 31 12:47:54 PM PDT 24 |
Peak memory | 245820 kb |
Host | smart-3f4a9738-5dd6-411b-aa00-fcf8a6a8370e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624575829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_in tg_err.1624575829 |
Directory | /workspace/1.otp_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/39.otp_ctrl_macro_errs.3116266624 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 858483139 ps |
CPU time | 23.06 seconds |
Started | Mar 31 03:31:29 PM PDT 24 |
Finished | Mar 31 03:31:52 PM PDT 24 |
Peak memory | 242736 kb |
Host | smart-5cfc5815-60f1-4c36-ad84-203715d76b0f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3116266624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_macro_errs.3116266624 |
Directory | /workspace/39.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/3.otp_ctrl_stress_all_with_rand_reset.401747041 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 1066317984609 ps |
CPU time | 1928.18 seconds |
Started | Mar 31 03:28:47 PM PDT 24 |
Finished | Mar 31 04:00:55 PM PDT 24 |
Peak memory | 298384 kb |
Host | smart-9c565ea9-f01b-4f78-8359-1d8d7e26560d |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401747041 -assert nopo stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all_with_rand_reset.401747041 |
Directory | /workspace/3.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/128.otp_ctrl_init_fail.111018447 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 523819299 ps |
CPU time | 3.78 seconds |
Started | Mar 31 03:33:06 PM PDT 24 |
Finished | Mar 31 03:33:09 PM PDT 24 |
Peak memory | 241692 kb |
Host | smart-5fb64307-6011-4740-a946-5668a01091d9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=111018447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.111018447 |
Directory | /workspace/128.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/44.otp_ctrl_init_fail.1939941163 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 149740090 ps |
CPU time | 4.08 seconds |
Started | Mar 31 03:31:42 PM PDT 24 |
Finished | Mar 31 03:31:47 PM PDT 24 |
Peak memory | 241800 kb |
Host | smart-4a84b075-d19e-4448-92c7-aef941c8452e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1939941163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.1939941163 |
Directory | /workspace/44.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/28.otp_ctrl_stress_all.3170614743 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 13093785205 ps |
CPU time | 152.28 seconds |
Started | Mar 31 03:30:44 PM PDT 24 |
Finished | Mar 31 03:33:16 PM PDT 24 |
Peak memory | 248304 kb |
Host | smart-289a9b02-1c95-4396-90c2-a01afe70e0ad |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170614743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all .3170614743 |
Directory | /workspace/28.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/21.otp_ctrl_stress_all_with_rand_reset.2118248195 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 361005913178 ps |
CPU time | 2075.75 seconds |
Started | Mar 31 03:30:10 PM PDT 24 |
Finished | Mar 31 04:04:46 PM PDT 24 |
Peak memory | 322580 kb |
Host | smart-e6476546-4fa5-43cd-99d1-535f6e8876c9 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118248195 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all_with_rand_reset.2118248195 |
Directory | /workspace/21.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/155.otp_ctrl_init_fail.1513504254 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 264879621 ps |
CPU time | 5.1 seconds |
Started | Mar 31 03:33:20 PM PDT 24 |
Finished | Mar 31 03:33:25 PM PDT 24 |
Peak memory | 242068 kb |
Host | smart-bda9a93a-3358-488e-83aa-7def767df010 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1513504254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.1513504254 |
Directory | /workspace/155.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/216.otp_ctrl_init_fail.2182828794 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 615629991 ps |
CPU time | 4.97 seconds |
Started | Mar 31 03:33:50 PM PDT 24 |
Finished | Mar 31 03:33:56 PM PDT 24 |
Peak memory | 241684 kb |
Host | smart-743bf988-1dd0-4f21-8a1d-da882866b1ae |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2182828794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.2182828794 |
Directory | /workspace/216.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/18.otp_ctrl_stress_all_with_rand_reset.3280296053 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 91413474596 ps |
CPU time | 2521.21 seconds |
Started | Mar 31 03:30:02 PM PDT 24 |
Finished | Mar 31 04:12:04 PM PDT 24 |
Peak memory | 312092 kb |
Host | smart-ac49899b-0de2-4e72-9796-07fcafb81d02 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280296053 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all_with_rand_reset.3280296053 |
Directory | /workspace/18.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/260.otp_ctrl_init_fail.1801244375 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 279598024 ps |
CPU time | 5.14 seconds |
Started | Mar 31 03:33:59 PM PDT 24 |
Finished | Mar 31 03:34:04 PM PDT 24 |
Peak memory | 241576 kb |
Host | smart-70cf33c5-27b6-4c54-acb2-e027332817b7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1801244375 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.1801244375 |
Directory | /workspace/260.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/21.otp_ctrl_stress_all.2059635712 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 7798661272 ps |
CPU time | 169.86 seconds |
Started | Mar 31 03:30:09 PM PDT 24 |
Finished | Mar 31 03:32:58 PM PDT 24 |
Peak memory | 256868 kb |
Host | smart-4e28853e-354e-4a5a-b860-b58276af84d4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059635712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all .2059635712 |
Directory | /workspace/21.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/113.otp_ctrl_init_fail.1134443257 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 518936781 ps |
CPU time | 4.32 seconds |
Started | Mar 31 03:32:57 PM PDT 24 |
Finished | Mar 31 03:33:01 PM PDT 24 |
Peak memory | 241780 kb |
Host | smart-63d8f5b9-2206-4310-9cb3-b7baec140907 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1134443257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.1134443257 |
Directory | /workspace/113.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/144.otp_ctrl_init_fail.2872402640 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 371864949 ps |
CPU time | 4.08 seconds |
Started | Mar 31 03:33:12 PM PDT 24 |
Finished | Mar 31 03:33:16 PM PDT 24 |
Peak memory | 241748 kb |
Host | smart-cda4b402-a07d-49bf-82f7-acb1f8670530 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2872402640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.2872402640 |
Directory | /workspace/144.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/186.otp_ctrl_init_fail.2391760873 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 2089564128 ps |
CPU time | 5.31 seconds |
Started | Mar 31 03:33:40 PM PDT 24 |
Finished | Mar 31 03:33:46 PM PDT 24 |
Peak memory | 241848 kb |
Host | smart-238e386e-e884-4c8d-b2a7-430a89be273f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2391760873 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.2391760873 |
Directory | /workspace/186.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/23.otp_ctrl_check_fail.3025951920 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 3511668784 ps |
CPU time | 24.42 seconds |
Started | Mar 31 03:30:18 PM PDT 24 |
Finished | Mar 31 03:30:43 PM PDT 24 |
Peak memory | 248672 kb |
Host | smart-ce098697-914d-46ba-ba34-c4f941eab4e2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3025951920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.3025951920 |
Directory | /workspace/23.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/125.otp_ctrl_init_fail.1159654272 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 161513231 ps |
CPU time | 4.33 seconds |
Started | Mar 31 03:33:01 PM PDT 24 |
Finished | Mar 31 03:33:06 PM PDT 24 |
Peak memory | 241664 kb |
Host | smart-f076c8c1-71eb-4e6a-bd59-0888d2c2c7f2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1159654272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.1159654272 |
Directory | /workspace/125.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/14.otp_ctrl_macro_errs.1832209587 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 17163488746 ps |
CPU time | 32.62 seconds |
Started | Mar 31 03:29:48 PM PDT 24 |
Finished | Mar 31 03:30:21 PM PDT 24 |
Peak memory | 249948 kb |
Host | smart-588058f7-468e-4e0e-8607-93cd71d8a11d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1832209587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_macro_errs.1832209587 |
Directory | /workspace/14.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/72.otp_ctrl_init_fail.2691393197 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 577777167 ps |
CPU time | 4.46 seconds |
Started | Mar 31 03:32:23 PM PDT 24 |
Finished | Mar 31 03:32:28 PM PDT 24 |
Peak memory | 242008 kb |
Host | smart-655bf2b2-8dc8-48fa-b0d3-1f80aa8528b4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2691393197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.2691393197 |
Directory | /workspace/72.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/206.otp_ctrl_init_fail.1612348439 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 2426161994 ps |
CPU time | 6.04 seconds |
Started | Mar 31 03:33:48 PM PDT 24 |
Finished | Mar 31 03:33:55 PM PDT 24 |
Peak memory | 242152 kb |
Host | smart-8b1e5406-bbe6-4fc3-994e-96daccaba82e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1612348439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.1612348439 |
Directory | /workspace/206.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/145.otp_ctrl_parallel_lc_esc.986380376 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 427024565 ps |
CPU time | 11.51 seconds |
Started | Mar 31 03:33:11 PM PDT 24 |
Finished | Mar 31 03:33:23 PM PDT 24 |
Peak memory | 242032 kb |
Host | smart-e8179902-e7b1-459a-98bc-fdc359dfff86 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=986380376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.986380376 |
Directory | /workspace/145.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/46.otp_ctrl_stress_all.3418074942 |
Short name | T571 |
Test name | |
Test status | |
Simulation time | 16579386734 ps |
CPU time | 223.99 seconds |
Started | Mar 31 03:31:53 PM PDT 24 |
Finished | Mar 31 03:35:38 PM PDT 24 |
Peak memory | 256896 kb |
Host | smart-56ff78bb-cd19-4a1e-978c-c1a2eb2c77d8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418074942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all .3418074942 |
Directory | /workspace/46.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/1.otp_ctrl_alert_test.235132490 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 252715598 ps |
CPU time | 2.06 seconds |
Started | Mar 31 03:28:26 PM PDT 24 |
Finished | Mar 31 03:28:28 PM PDT 24 |
Peak memory | 240168 kb |
Host | smart-d1afbb17-f231-47ba-955c-ce0a931502f3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235132490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.235132490 |
Directory | /workspace/1.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/1.otp_ctrl_check_fail.1816806018 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 3486483257 ps |
CPU time | 46.32 seconds |
Started | Mar 31 03:28:28 PM PDT 24 |
Finished | Mar 31 03:29:15 PM PDT 24 |
Peak memory | 248700 kb |
Host | smart-7348b8b2-a29e-46be-9a1b-5ae8e04c82a0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1816806018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.1816806018 |
Directory | /workspace/1.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/76.otp_ctrl_parallel_lc_esc.811462710 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 114908194 ps |
CPU time | 4.2 seconds |
Started | Mar 31 03:32:34 PM PDT 24 |
Finished | Mar 31 03:32:38 PM PDT 24 |
Peak memory | 241552 kb |
Host | smart-09fd63c0-0fb2-46be-a400-18ea8e2cbc4d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=811462710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.811462710 |
Directory | /workspace/76.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/91.otp_ctrl_parallel_lc_esc.1097469628 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 2782104443 ps |
CPU time | 10.3 seconds |
Started | Mar 31 03:32:42 PM PDT 24 |
Finished | Mar 31 03:32:52 PM PDT 24 |
Peak memory | 242092 kb |
Host | smart-e1f5667f-72a2-4d73-b9e1-bf4f848004fb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1097469628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.1097469628 |
Directory | /workspace/91.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.804721717 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 589035804 ps |
CPU time | 2.36 seconds |
Started | Mar 31 12:48:00 PM PDT 24 |
Finished | Mar 31 12:48:02 PM PDT 24 |
Peak memory | 241800 kb |
Host | smart-0e7f48c6-7985-4cb8-8cca-d63c6d22bd21 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804721717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.804721717 |
Directory | /workspace/14.otp_ctrl_csr_rw/latest |
Test location | /workspace/coverage/default/45.otp_ctrl_stress_all.3769346993 |
Short name | T714 |
Test name | |
Test status | |
Simulation time | 12230093832 ps |
CPU time | 231.89 seconds |
Started | Mar 31 03:31:54 PM PDT 24 |
Finished | Mar 31 03:35:46 PM PDT 24 |
Peak memory | 278504 kb |
Host | smart-22c8f2f8-8c68-407d-afef-7f35b54f6f38 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769346993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all .3769346993 |
Directory | /workspace/45.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/45.otp_ctrl_regwen.2675237636 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 327506850 ps |
CPU time | 8.06 seconds |
Started | Mar 31 03:31:47 PM PDT 24 |
Finished | Mar 31 03:31:55 PM PDT 24 |
Peak memory | 241716 kb |
Host | smart-dff7be9c-a936-4754-af58-39d48eb73379 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2675237636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.2675237636 |
Directory | /workspace/45.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/266.otp_ctrl_init_fail.1020857615 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 411943115 ps |
CPU time | 4.6 seconds |
Started | Mar 31 03:34:00 PM PDT 24 |
Finished | Mar 31 03:34:05 PM PDT 24 |
Peak memory | 241864 kb |
Host | smart-34df57c6-00a3-4b3e-8048-31ace043657e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1020857615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.1020857615 |
Directory | /workspace/266.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/10.otp_ctrl_check_fail.2984058586 |
Short name | T831 |
Test name | |
Test status | |
Simulation time | 466262592 ps |
CPU time | 15.95 seconds |
Started | Mar 31 03:29:24 PM PDT 24 |
Finished | Mar 31 03:29:40 PM PDT 24 |
Peak memory | 242468 kb |
Host | smart-7f052adc-0e60-4ce0-9e47-b7dfb6f2722d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2984058586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.2984058586 |
Directory | /workspace/10.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/42.otp_ctrl_stress_all.1091542232 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 53546673659 ps |
CPU time | 286.31 seconds |
Started | Mar 31 03:31:40 PM PDT 24 |
Finished | Mar 31 03:36:26 PM PDT 24 |
Peak memory | 264872 kb |
Host | smart-fa7989ef-3ad9-4735-a761-c9f621f34768 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091542232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all .1091542232 |
Directory | /workspace/42.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.947154158 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 5063270900 ps |
CPU time | 19.93 seconds |
Started | Mar 31 12:47:39 PM PDT 24 |
Finished | Mar 31 12:47:59 PM PDT 24 |
Peak memory | 245220 kb |
Host | smart-6031cfca-8799-422c-92b9-3f1882a45926 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947154158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_int g_err.947154158 |
Directory | /workspace/4.otp_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/23.otp_ctrl_stress_all_with_rand_reset.311908113 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 170513558676 ps |
CPU time | 1415.11 seconds |
Started | Mar 31 03:30:18 PM PDT 24 |
Finished | Mar 31 03:53:54 PM PDT 24 |
Peak memory | 348172 kb |
Host | smart-5e6730a9-cedb-4997-bc85-11350216ea30 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311908113 -assert nopo stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all_with_rand_reset.311908113 |
Directory | /workspace/23.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/26.otp_ctrl_check_fail.2013245764 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 1224311636 ps |
CPU time | 11.67 seconds |
Started | Mar 31 03:30:29 PM PDT 24 |
Finished | Mar 31 03:30:41 PM PDT 24 |
Peak memory | 248656 kb |
Host | smart-07f4590b-28f4-4316-a41d-cdbed45261dc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2013245764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.2013245764 |
Directory | /workspace/26.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/69.otp_ctrl_parallel_lc_esc.4166512274 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 2261200991 ps |
CPU time | 8 seconds |
Started | Mar 31 03:32:22 PM PDT 24 |
Finished | Mar 31 03:32:31 PM PDT 24 |
Peak memory | 241896 kb |
Host | smart-0c8223a6-f110-4e91-9086-0aa292cc29cf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4166512274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.4166512274 |
Directory | /workspace/69.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/108.otp_ctrl_parallel_lc_esc.3752036827 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 1967065221 ps |
CPU time | 6.85 seconds |
Started | Mar 31 03:32:58 PM PDT 24 |
Finished | Mar 31 03:33:05 PM PDT 24 |
Peak memory | 241620 kb |
Host | smart-94d22312-9e38-4c0c-9f87-012b8cb51781 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3752036827 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.3752036827 |
Directory | /workspace/108.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/141.otp_ctrl_init_fail.1649310594 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 302967930 ps |
CPU time | 4.87 seconds |
Started | Mar 31 03:33:11 PM PDT 24 |
Finished | Mar 31 03:33:16 PM PDT 24 |
Peak memory | 241788 kb |
Host | smart-26c809ff-4303-4a53-874c-d51ac09c33f4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1649310594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.1649310594 |
Directory | /workspace/141.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/163.otp_ctrl_parallel_lc_esc.1769858755 |
Short name | T977 |
Test name | |
Test status | |
Simulation time | 109823684 ps |
CPU time | 3.23 seconds |
Started | Mar 31 03:33:28 PM PDT 24 |
Finished | Mar 31 03:33:31 PM PDT 24 |
Peak memory | 241636 kb |
Host | smart-decae309-1d7a-4cb0-b9f0-b81d2f15f8e7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1769858755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.1769858755 |
Directory | /workspace/163.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/116.otp_ctrl_init_fail.2053584712 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 309039186 ps |
CPU time | 4.22 seconds |
Started | Mar 31 03:33:01 PM PDT 24 |
Finished | Mar 31 03:33:05 PM PDT 24 |
Peak memory | 242044 kb |
Host | smart-d02563c7-7917-4ddd-a3ea-c28450ecec7b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2053584712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.2053584712 |
Directory | /workspace/116.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/123.otp_ctrl_parallel_lc_esc.2971415002 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 797826925 ps |
CPU time | 7.6 seconds |
Started | Mar 31 03:32:58 PM PDT 24 |
Finished | Mar 31 03:33:06 PM PDT 24 |
Peak memory | 242096 kb |
Host | smart-30fe4e05-78e4-47c5-8044-810301ee34c7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2971415002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.2971415002 |
Directory | /workspace/123.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/166.otp_ctrl_parallel_lc_esc.3987262126 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 498311510 ps |
CPU time | 9.87 seconds |
Started | Mar 31 03:33:30 PM PDT 24 |
Finished | Mar 31 03:33:40 PM PDT 24 |
Peak memory | 241768 kb |
Host | smart-cbcd89c1-9b26-4e21-83e6-e53d266ae3f6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3987262126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.3987262126 |
Directory | /workspace/166.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/169.otp_ctrl_parallel_lc_esc.3394293987 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 436213733 ps |
CPU time | 6.38 seconds |
Started | Mar 31 03:33:29 PM PDT 24 |
Finished | Mar 31 03:33:36 PM PDT 24 |
Peak memory | 241776 kb |
Host | smart-664046ea-b12b-4092-bfec-8d9314884872 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3394293987 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.3394293987 |
Directory | /workspace/169.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/25.otp_ctrl_stress_all_with_rand_reset.2860061697 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 47965542837 ps |
CPU time | 1326.17 seconds |
Started | Mar 31 03:30:31 PM PDT 24 |
Finished | Mar 31 03:52:38 PM PDT 24 |
Peak memory | 486800 kb |
Host | smart-52206486-deef-48b5-b258-85ef38f99049 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860061697 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all_with_rand_reset.2860061697 |
Directory | /workspace/25.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/59.otp_ctrl_stress_all_with_rand_reset.2294183700 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 244687737573 ps |
CPU time | 1424.26 seconds |
Started | Mar 31 03:32:13 PM PDT 24 |
Finished | Mar 31 03:55:57 PM PDT 24 |
Peak memory | 310032 kb |
Host | smart-05db422b-1d9e-42eb-8969-c7da9a3eb270 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294183700 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_stress_all_with_rand_reset.2294183700 |
Directory | /workspace/59.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/88.otp_ctrl_parallel_lc_esc.1492008332 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 196715259 ps |
CPU time | 3.33 seconds |
Started | Mar 31 03:32:37 PM PDT 24 |
Finished | Mar 31 03:32:40 PM PDT 24 |
Peak memory | 241528 kb |
Host | smart-45c4e645-0fbf-4773-b6b3-8835d21e3a94 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1492008332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.1492008332 |
Directory | /workspace/88.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/48.otp_ctrl_stress_all.2766729702 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 17646709783 ps |
CPU time | 131.86 seconds |
Started | Mar 31 03:32:00 PM PDT 24 |
Finished | Mar 31 03:34:12 PM PDT 24 |
Peak memory | 244932 kb |
Host | smart-38a7d32b-76fd-4dc7-95b3-7eedd199d279 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766729702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all .2766729702 |
Directory | /workspace/48.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/7.otp_ctrl_regwen.2940829953 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 3774328253 ps |
CPU time | 12.61 seconds |
Started | Mar 31 03:29:12 PM PDT 24 |
Finished | Mar 31 03:29:25 PM PDT 24 |
Peak memory | 242112 kb |
Host | smart-1185e585-46d3-4ea2-9ecc-fcd522c58a43 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2940829953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.2940829953 |
Directory | /workspace/7.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/81.otp_ctrl_stress_all_with_rand_reset.818222768 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 79444571295 ps |
CPU time | 517.97 seconds |
Started | Mar 31 03:32:35 PM PDT 24 |
Finished | Mar 31 03:41:13 PM PDT 24 |
Peak memory | 263840 kb |
Host | smart-05f63ef2-0fa0-46f6-ab8f-76b8344a61cb |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818222768 -assert nopo stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_stress_all_with_rand_reset.818222768 |
Directory | /workspace/81.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/31.otp_ctrl_regwen.1441051402 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 339059410 ps |
CPU time | 8.91 seconds |
Started | Mar 31 03:30:58 PM PDT 24 |
Finished | Mar 31 03:31:07 PM PDT 24 |
Peak memory | 241908 kb |
Host | smart-d6aab660-d649-40c1-8aca-3a0c34526fdd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1441051402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.1441051402 |
Directory | /workspace/31.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/48.otp_ctrl_check_fail.3011701597 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 3233935454 ps |
CPU time | 18.27 seconds |
Started | Mar 31 03:32:02 PM PDT 24 |
Finished | Mar 31 03:32:20 PM PDT 24 |
Peak memory | 242920 kb |
Host | smart-af8865a1-59e9-4a22-bf9c-ea277c54d7a7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3011701597 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.3011701597 |
Directory | /workspace/48.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/148.otp_ctrl_parallel_lc_esc.46063201 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 448043014 ps |
CPU time | 7.06 seconds |
Started | Mar 31 03:33:21 PM PDT 24 |
Finished | Mar 31 03:33:29 PM PDT 24 |
Peak memory | 241696 kb |
Host | smart-cf04ff58-43fe-41b4-a28d-6e5f12c93aa1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=46063201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.46063201 |
Directory | /workspace/148.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/2.otp_ctrl_check_fail.705557919 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 1571478462 ps |
CPU time | 26.48 seconds |
Started | Mar 31 03:28:36 PM PDT 24 |
Finished | Mar 31 03:29:03 PM PDT 24 |
Peak memory | 241928 kb |
Host | smart-381627b5-3fab-4151-9211-0407719b5f8f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=705557919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.705557919 |
Directory | /workspace/2.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/40.otp_ctrl_check_fail.2909558234 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 6916264465 ps |
CPU time | 16.72 seconds |
Started | Mar 31 03:31:32 PM PDT 24 |
Finished | Mar 31 03:31:49 PM PDT 24 |
Peak memory | 242664 kb |
Host | smart-97eaad2f-39ee-4a05-ab8f-6b08cd5813b1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2909558234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.2909558234 |
Directory | /workspace/40.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/277.otp_ctrl_init_fail.4092533811 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 610931546 ps |
CPU time | 5.08 seconds |
Started | Mar 31 03:34:04 PM PDT 24 |
Finished | Mar 31 03:34:10 PM PDT 24 |
Peak memory | 241796 kb |
Host | smart-3f6ff1d1-e715-40ec-8f84-1e8f3bcf1075 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4092533811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.4092533811 |
Directory | /workspace/277.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/124.otp_ctrl_init_fail.2394597741 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 101156422 ps |
CPU time | 3.35 seconds |
Started | Mar 31 03:32:57 PM PDT 24 |
Finished | Mar 31 03:33:01 PM PDT 24 |
Peak memory | 241648 kb |
Host | smart-f0bea9fc-bfc2-4475-9eb2-12a402f8bd94 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2394597741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.2394597741 |
Directory | /workspace/124.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/16.otp_ctrl_init_fail.2929960739 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 680216246 ps |
CPU time | 4.98 seconds |
Started | Mar 31 03:29:47 PM PDT 24 |
Finished | Mar 31 03:29:52 PM PDT 24 |
Peak memory | 241644 kb |
Host | smart-5ec47516-5beb-4539-a5f5-062e7f6dbc04 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2929960739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.2929960739 |
Directory | /workspace/16.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/10.otp_ctrl_macro_errs.1410844465 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 839929181 ps |
CPU time | 20.02 seconds |
Started | Mar 31 03:29:21 PM PDT 24 |
Finished | Mar 31 03:29:41 PM PDT 24 |
Peak memory | 243264 kb |
Host | smart-1cfcd0c3-b5f3-4076-bf56-8536e35717ee |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1410844465 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.1410844465 |
Directory | /workspace/10.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/31.otp_ctrl_stress_all.1623710486 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 4360817861 ps |
CPU time | 64.93 seconds |
Started | Mar 31 03:30:54 PM PDT 24 |
Finished | Mar 31 03:32:01 PM PDT 24 |
Peak memory | 248660 kb |
Host | smart-fe0a5e11-d389-4123-9a2a-5594ba6d31fb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623710486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all .1623710486 |
Directory | /workspace/31.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/60.otp_ctrl_stress_all_with_rand_reset.4272355800 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 263115368517 ps |
CPU time | 859.37 seconds |
Started | Mar 31 03:32:17 PM PDT 24 |
Finished | Mar 31 03:46:37 PM PDT 24 |
Peak memory | 267544 kb |
Host | smart-3c5690ff-4df6-4fd3-85ff-9f23998401ef |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272355800 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_stress_all_with_rand_reset.4272355800 |
Directory | /workspace/60.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.3712593438 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 706910844 ps |
CPU time | 10.05 seconds |
Started | Mar 31 12:47:22 PM PDT 24 |
Finished | Mar 31 12:47:32 PM PDT 24 |
Peak memory | 244124 kb |
Host | smart-a44f091f-09a2-435f-a7fe-ef4a13ed6445 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712593438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_in tg_err.3712593438 |
Directory | /workspace/0.otp_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.2553123666 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 20181222648 ps |
CPU time | 32.65 seconds |
Started | Mar 31 12:48:08 PM PDT 24 |
Finished | Mar 31 12:48:40 PM PDT 24 |
Peak memory | 245176 kb |
Host | smart-d15502b8-65ab-4f54-a8cd-afcfbc21d655 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553123666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_i ntg_err.2553123666 |
Directory | /workspace/17.otp_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.615965051 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 1162970622 ps |
CPU time | 5.02 seconds |
Started | Mar 31 12:47:31 PM PDT 24 |
Finished | Mar 31 12:47:36 PM PDT 24 |
Peak memory | 237516 kb |
Host | smart-e90428d5-fd10-45e8-a6aa-5818373d6317 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615965051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_alias ing.615965051 |
Directory | /workspace/1.otp_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/default/19.otp_ctrl_stress_all.2027021657 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 11470083007 ps |
CPU time | 152.14 seconds |
Started | Mar 31 03:30:01 PM PDT 24 |
Finished | Mar 31 03:32:33 PM PDT 24 |
Peak memory | 260348 kb |
Host | smart-c3c27d79-8b01-41f3-b6d3-2d4f5c02cc87 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027021657 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all .2027021657 |
Directory | /workspace/19.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/2.otp_ctrl_test_access.2310593831 |
Short name | T827 |
Test name | |
Test status | |
Simulation time | 4345479948 ps |
CPU time | 25.65 seconds |
Started | Mar 31 03:28:39 PM PDT 24 |
Finished | Mar 31 03:29:05 PM PDT 24 |
Peak memory | 242020 kb |
Host | smart-3eeed7ad-9606-4d66-971e-ca29292ea21e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2310593831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.2310593831 |
Directory | /workspace/2.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/41.otp_ctrl_stress_all.512020660 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 79067912159 ps |
CPU time | 557.48 seconds |
Started | Mar 31 03:31:30 PM PDT 24 |
Finished | Mar 31 03:40:48 PM PDT 24 |
Peak memory | 274332 kb |
Host | smart-adb4ea99-6873-46c7-8694-19fbde209d08 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512020660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all. 512020660 |
Directory | /workspace/41.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/0.otp_ctrl_wake_up.2035547028 |
Short name | T1069 |
Test name | |
Test status | |
Simulation time | 62364861 ps |
CPU time | 1.75 seconds |
Started | Mar 31 03:28:09 PM PDT 24 |
Finished | Mar 31 03:28:11 PM PDT 24 |
Peak memory | 240000 kb |
Host | smart-d4eb6457-4a30-4056-8706-077aebb19810 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2035547028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.2035547028 |
Directory | /workspace/0.otp_ctrl_wake_up/latest |
Test location | /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.3641289748 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 1252017537 ps |
CPU time | 17.33 seconds |
Started | Mar 31 12:47:50 PM PDT 24 |
Finished | Mar 31 12:48:07 PM PDT 24 |
Peak memory | 244420 kb |
Host | smart-223e914b-d5c0-4104-a179-76efbeaf8308 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641289748 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_in tg_err.3641289748 |
Directory | /workspace/5.otp_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.3751942752 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 639185099 ps |
CPU time | 10.96 seconds |
Started | Mar 31 12:47:50 PM PDT 24 |
Finished | Mar 31 12:48:01 PM PDT 24 |
Peak memory | 244320 kb |
Host | smart-8faff3c1-9ebc-4b13-8823-7d28675ca56e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751942752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_in tg_err.3751942752 |
Directory | /workspace/9.otp_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/78.otp_ctrl_stress_all_with_rand_reset.3351304170 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 30999589186 ps |
CPU time | 431.45 seconds |
Started | Mar 31 03:32:28 PM PDT 24 |
Finished | Mar 31 03:39:40 PM PDT 24 |
Peak memory | 345072 kb |
Host | smart-e33397b3-4d56-4559-b5e2-6b0021676985 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351304170 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_stress_all_with_rand_reset.3351304170 |
Directory | /workspace/78.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/273.otp_ctrl_init_fail.502973537 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 236243956 ps |
CPU time | 4.21 seconds |
Started | Mar 31 03:34:02 PM PDT 24 |
Finished | Mar 31 03:34:07 PM PDT 24 |
Peak memory | 241604 kb |
Host | smart-692862da-85ba-44d1-a8d3-ef632493587f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=502973537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.502973537 |
Directory | /workspace/273.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.2255971281 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 150028010 ps |
CPU time | 3.53 seconds |
Started | Mar 31 12:47:31 PM PDT 24 |
Finished | Mar 31 12:47:34 PM PDT 24 |
Peak memory | 239108 kb |
Host | smart-1178b842-cf25-4f3d-9cb1-eb0d9b4c93f9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255971281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_alia sing.2255971281 |
Directory | /workspace/0.otp_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.3153622274 |
Short name | T1292 |
Test name | |
Test status | |
Simulation time | 431736354 ps |
CPU time | 5.91 seconds |
Started | Mar 31 12:47:30 PM PDT 24 |
Finished | Mar 31 12:47:36 PM PDT 24 |
Peak memory | 239032 kb |
Host | smart-e49359b8-b208-47bf-91ff-aabf5fd49205 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153622274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_ bash.3153622274 |
Directory | /workspace/0.otp_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.3176006691 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 1446665739 ps |
CPU time | 3.14 seconds |
Started | Mar 31 12:47:22 PM PDT 24 |
Finished | Mar 31 12:47:25 PM PDT 24 |
Peak memory | 239104 kb |
Host | smart-366aa253-751c-4c42-964a-74a41c4aa765 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176006691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_r eset.3176006691 |
Directory | /workspace/0.otp_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.3888184781 |
Short name | T1262 |
Test name | |
Test status | |
Simulation time | 136705434 ps |
CPU time | 3.42 seconds |
Started | Mar 31 12:47:29 PM PDT 24 |
Finished | Mar 31 12:47:33 PM PDT 24 |
Peak memory | 247312 kb |
Host | smart-60cadfed-3cea-425e-9f61-062fbcf4dbdc |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888184781 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_mem_rw_with_rand_reset.3888184781 |
Directory | /workspace/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.4032227511 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 42232129 ps |
CPU time | 1.54 seconds |
Started | Mar 31 12:47:30 PM PDT 24 |
Finished | Mar 31 12:47:31 PM PDT 24 |
Peak memory | 239100 kb |
Host | smart-664e6ec9-d67d-4af4-8101-50a01a93e37d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032227511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.4032227511 |
Directory | /workspace/0.otp_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.1148315167 |
Short name | T1209 |
Test name | |
Test status | |
Simulation time | 74783772 ps |
CPU time | 1.39 seconds |
Started | Mar 31 12:47:21 PM PDT 24 |
Finished | Mar 31 12:47:23 PM PDT 24 |
Peak memory | 230844 kb |
Host | smart-9ba1f250-7a4f-4261-9f3d-d67a3b3d8f1e |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148315167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.1148315167 |
Directory | /workspace/0.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.3451640599 |
Short name | T1226 |
Test name | |
Test status | |
Simulation time | 553635078 ps |
CPU time | 1.33 seconds |
Started | Mar 31 12:47:29 PM PDT 24 |
Finished | Mar 31 12:47:31 PM PDT 24 |
Peak memory | 230508 kb |
Host | smart-e1504012-40fc-4484-bb47-ff1c79cb8ddb |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451640599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctr l_mem_partial_access.3451640599 |
Directory | /workspace/0.otp_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.4234361960 |
Short name | T1198 |
Test name | |
Test status | |
Simulation time | 140588696 ps |
CPU time | 1.38 seconds |
Started | Mar 31 12:47:23 PM PDT 24 |
Finished | Mar 31 12:47:25 PM PDT 24 |
Peak memory | 229272 kb |
Host | smart-09800b11-d036-4b3f-adb5-bd6a67f7c92c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234361960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk .4234361960 |
Directory | /workspace/0.otp_ctrl_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.4258270181 |
Short name | T1206 |
Test name | |
Test status | |
Simulation time | 128866288 ps |
CPU time | 2.04 seconds |
Started | Mar 31 12:47:31 PM PDT 24 |
Finished | Mar 31 12:47:33 PM PDT 24 |
Peak memory | 238012 kb |
Host | smart-59c20b53-3f30-471b-a156-480e11792511 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258270181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_c trl_same_csr_outstanding.4258270181 |
Directory | /workspace/0.otp_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.3758795514 |
Short name | T1228 |
Test name | |
Test status | |
Simulation time | 856255344 ps |
CPU time | 3.71 seconds |
Started | Mar 31 12:47:21 PM PDT 24 |
Finished | Mar 31 12:47:26 PM PDT 24 |
Peak memory | 246452 kb |
Host | smart-2ff2000a-dda2-4f60-82ff-9f0a65c81176 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758795514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.3758795514 |
Directory | /workspace/0.otp_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.1342541399 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 313280124 ps |
CPU time | 4.29 seconds |
Started | Mar 31 12:47:30 PM PDT 24 |
Finished | Mar 31 12:47:35 PM PDT 24 |
Peak memory | 237764 kb |
Host | smart-bd46ba87-e69c-4089-b84e-5903d0bc9d47 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342541399 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_ bash.1342541399 |
Directory | /workspace/1.otp_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.3479701394 |
Short name | T1277 |
Test name | |
Test status | |
Simulation time | 1003205869 ps |
CPU time | 2.04 seconds |
Started | Mar 31 12:47:30 PM PDT 24 |
Finished | Mar 31 12:47:32 PM PDT 24 |
Peak memory | 239012 kb |
Host | smart-32228765-3705-4250-93d4-15d39267e496 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479701394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_r eset.3479701394 |
Directory | /workspace/1.otp_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.1589105517 |
Short name | T1256 |
Test name | |
Test status | |
Simulation time | 1097497097 ps |
CPU time | 2.15 seconds |
Started | Mar 31 12:47:30 PM PDT 24 |
Finished | Mar 31 12:47:32 PM PDT 24 |
Peak memory | 243972 kb |
Host | smart-44f449f9-0b27-43e3-8b74-fe60a5b0345f |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589105517 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_mem_rw_with_rand_reset.1589105517 |
Directory | /workspace/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.2485940630 |
Short name | T1312 |
Test name | |
Test status | |
Simulation time | 42762599 ps |
CPU time | 1.59 seconds |
Started | Mar 31 12:47:29 PM PDT 24 |
Finished | Mar 31 12:47:31 PM PDT 24 |
Peak memory | 241276 kb |
Host | smart-446dd046-8444-46d3-8c65-2bb9cfd2aa24 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485940630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.2485940630 |
Directory | /workspace/1.otp_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.2027487158 |
Short name | T1223 |
Test name | |
Test status | |
Simulation time | 85653164 ps |
CPU time | 1.45 seconds |
Started | Mar 31 12:47:28 PM PDT 24 |
Finished | Mar 31 12:47:30 PM PDT 24 |
Peak memory | 230656 kb |
Host | smart-1886d25b-84c3-46a3-997b-a41f3149814a |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027487158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.2027487158 |
Directory | /workspace/1.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.789665249 |
Short name | T1274 |
Test name | |
Test status | |
Simulation time | 555148319 ps |
CPU time | 1.57 seconds |
Started | Mar 31 12:47:29 PM PDT 24 |
Finished | Mar 31 12:47:31 PM PDT 24 |
Peak memory | 230600 kb |
Host | smart-cbf87ef6-df2b-4bfa-95be-8ff98df84a18 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789665249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl _mem_partial_access.789665249 |
Directory | /workspace/1.otp_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.3548809407 |
Short name | T1301 |
Test name | |
Test status | |
Simulation time | 67514219 ps |
CPU time | 1.34 seconds |
Started | Mar 31 12:47:28 PM PDT 24 |
Finished | Mar 31 12:47:30 PM PDT 24 |
Peak memory | 230424 kb |
Host | smart-131a6f9c-1025-49e6-921d-f9e370a00ddc |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548809407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk .3548809407 |
Directory | /workspace/1.otp_ctrl_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.2626659832 |
Short name | T1240 |
Test name | |
Test status | |
Simulation time | 46508614 ps |
CPU time | 1.93 seconds |
Started | Mar 31 12:47:29 PM PDT 24 |
Finished | Mar 31 12:47:31 PM PDT 24 |
Peak memory | 238988 kb |
Host | smart-b2e7ce1d-45f3-4044-8a85-bbde104ca129 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626659832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_c trl_same_csr_outstanding.2626659832 |
Directory | /workspace/1.otp_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.870436800 |
Short name | T1236 |
Test name | |
Test status | |
Simulation time | 151482301 ps |
CPU time | 5.86 seconds |
Started | Mar 31 12:47:28 PM PDT 24 |
Finished | Mar 31 12:47:35 PM PDT 24 |
Peak memory | 247124 kb |
Host | smart-61721a29-5721-4e32-922a-50be08c20a8e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870436800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.870436800 |
Directory | /workspace/1.otp_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.1415652978 |
Short name | T1225 |
Test name | |
Test status | |
Simulation time | 227973980 ps |
CPU time | 3.57 seconds |
Started | Mar 31 12:47:59 PM PDT 24 |
Finished | Mar 31 12:48:03 PM PDT 24 |
Peak memory | 247368 kb |
Host | smart-e8bc9422-6e05-4cf5-8dd1-18436f776a9c |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415652978 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_mem_rw_with_rand_reset.1415652978 |
Directory | /workspace/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.2806944115 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 170567211 ps |
CPU time | 1.86 seconds |
Started | Mar 31 12:48:00 PM PDT 24 |
Finished | Mar 31 12:48:02 PM PDT 24 |
Peak memory | 240180 kb |
Host | smart-a2a4b6d9-1e44-4079-b867-bf234d0221ab |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806944115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.2806944115 |
Directory | /workspace/10.otp_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.2913773565 |
Short name | T1316 |
Test name | |
Test status | |
Simulation time | 74436553 ps |
CPU time | 1.43 seconds |
Started | Mar 31 12:48:04 PM PDT 24 |
Finished | Mar 31 12:48:06 PM PDT 24 |
Peak memory | 230816 kb |
Host | smart-a34c0eae-6fc7-421e-94c9-0005045c9f18 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913773565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.2913773565 |
Directory | /workspace/10.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.1921186607 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 383629393 ps |
CPU time | 3.23 seconds |
Started | Mar 31 12:48:02 PM PDT 24 |
Finished | Mar 31 12:48:05 PM PDT 24 |
Peak memory | 239060 kb |
Host | smart-b0ad4fdd-2705-4046-8b00-4b8c7cc8bbfe |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921186607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ ctrl_same_csr_outstanding.1921186607 |
Directory | /workspace/10.otp_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.425044515 |
Short name | T1309 |
Test name | |
Test status | |
Simulation time | 56331517 ps |
CPU time | 2.86 seconds |
Started | Mar 31 12:47:50 PM PDT 24 |
Finished | Mar 31 12:47:53 PM PDT 24 |
Peak memory | 239024 kb |
Host | smart-79bf94bb-1063-47b1-89a2-1b690d43b0ad |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425044515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.425044515 |
Directory | /workspace/10.otp_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.314954551 |
Short name | T1299 |
Test name | |
Test status | |
Simulation time | 1746496717 ps |
CPU time | 10.46 seconds |
Started | Mar 31 12:47:51 PM PDT 24 |
Finished | Mar 31 12:48:02 PM PDT 24 |
Peak memory | 244260 kb |
Host | smart-3b802b74-8284-438f-8ae2-bca3d4db5dba |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314954551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_in tg_err.314954551 |
Directory | /workspace/10.otp_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.4052592051 |
Short name | T1306 |
Test name | |
Test status | |
Simulation time | 139224926 ps |
CPU time | 2.07 seconds |
Started | Mar 31 12:48:00 PM PDT 24 |
Finished | Mar 31 12:48:02 PM PDT 24 |
Peak memory | 245680 kb |
Host | smart-dcf486f8-d796-45ac-b835-5eee37ef6b58 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052592051 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_mem_rw_with_rand_reset.4052592051 |
Directory | /workspace/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.3545944825 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 554011514 ps |
CPU time | 2.24 seconds |
Started | Mar 31 12:47:59 PM PDT 24 |
Finished | Mar 31 12:48:01 PM PDT 24 |
Peak memory | 239012 kb |
Host | smart-1c620e11-0912-42c9-8c50-a6b20604bb8e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545944825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.3545944825 |
Directory | /workspace/11.otp_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.4070844491 |
Short name | T1254 |
Test name | |
Test status | |
Simulation time | 50836038 ps |
CPU time | 1.55 seconds |
Started | Mar 31 12:47:59 PM PDT 24 |
Finished | Mar 31 12:48:01 PM PDT 24 |
Peak memory | 229484 kb |
Host | smart-5ff061b1-edb5-4939-8679-a3a3c5679b22 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070844491 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.4070844491 |
Directory | /workspace/11.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.1792658808 |
Short name | T1318 |
Test name | |
Test status | |
Simulation time | 321682627 ps |
CPU time | 2.62 seconds |
Started | Mar 31 12:47:57 PM PDT 24 |
Finished | Mar 31 12:48:00 PM PDT 24 |
Peak memory | 239112 kb |
Host | smart-9b392ebf-e40f-4764-af00-10d377b1d40b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792658808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ ctrl_same_csr_outstanding.1792658808 |
Directory | /workspace/11.otp_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.536716130 |
Short name | T1298 |
Test name | |
Test status | |
Simulation time | 2752071027 ps |
CPU time | 8.31 seconds |
Started | Mar 31 12:47:59 PM PDT 24 |
Finished | Mar 31 12:48:07 PM PDT 24 |
Peak memory | 246156 kb |
Host | smart-31cb2aa4-7b2a-48ce-8fda-21ed910aea61 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536716130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.536716130 |
Directory | /workspace/11.otp_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.3413289405 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 1357051517 ps |
CPU time | 18.56 seconds |
Started | Mar 31 12:47:57 PM PDT 24 |
Finished | Mar 31 12:48:16 PM PDT 24 |
Peak memory | 244616 kb |
Host | smart-36ee8a58-ba14-4672-9cf6-1ab6739b48d4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413289405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_i ntg_err.3413289405 |
Directory | /workspace/11.otp_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.2173875010 |
Short name | T1308 |
Test name | |
Test status | |
Simulation time | 237315863 ps |
CPU time | 2.91 seconds |
Started | Mar 31 12:48:01 PM PDT 24 |
Finished | Mar 31 12:48:04 PM PDT 24 |
Peak memory | 246680 kb |
Host | smart-01aa2609-e09d-4187-b822-c711761da4c0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173875010 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_mem_rw_with_rand_reset.2173875010 |
Directory | /workspace/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.1336920773 |
Short name | T1319 |
Test name | |
Test status | |
Simulation time | 171553485 ps |
CPU time | 1.79 seconds |
Started | Mar 31 12:47:56 PM PDT 24 |
Finished | Mar 31 12:47:58 PM PDT 24 |
Peak memory | 241800 kb |
Host | smart-671d7386-c866-46e3-a3da-a5df41b77f7c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336920773 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.1336920773 |
Directory | /workspace/12.otp_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.96645483 |
Short name | T1276 |
Test name | |
Test status | |
Simulation time | 587361438 ps |
CPU time | 2.09 seconds |
Started | Mar 31 12:48:01 PM PDT 24 |
Finished | Mar 31 12:48:03 PM PDT 24 |
Peak memory | 230100 kb |
Host | smart-c899bafd-bd42-420a-9861-d7baffc1f453 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96645483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.96645483 |
Directory | /workspace/12.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.1455858494 |
Short name | T1249 |
Test name | |
Test status | |
Simulation time | 123642707 ps |
CPU time | 2.29 seconds |
Started | Mar 31 12:48:01 PM PDT 24 |
Finished | Mar 31 12:48:03 PM PDT 24 |
Peak memory | 237964 kb |
Host | smart-2a845e17-7983-44ae-8a3f-75a00cf5fa3c |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455858494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ ctrl_same_csr_outstanding.1455858494 |
Directory | /workspace/12.otp_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.2002436622 |
Short name | T1234 |
Test name | |
Test status | |
Simulation time | 78795097 ps |
CPU time | 4.94 seconds |
Started | Mar 31 12:47:59 PM PDT 24 |
Finished | Mar 31 12:48:04 PM PDT 24 |
Peak memory | 247324 kb |
Host | smart-f75ef73c-2944-4b00-a8f8-84372f0b3e7a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002436622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.2002436622 |
Directory | /workspace/12.otp_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.713743788 |
Short name | T1289 |
Test name | |
Test status | |
Simulation time | 1575663303 ps |
CPU time | 18.88 seconds |
Started | Mar 31 12:47:59 PM PDT 24 |
Finished | Mar 31 12:48:19 PM PDT 24 |
Peak memory | 244380 kb |
Host | smart-43245553-431c-445b-9b9d-00be4b6ba716 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713743788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_in tg_err.713743788 |
Directory | /workspace/12.otp_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.3643158850 |
Short name | T1267 |
Test name | |
Test status | |
Simulation time | 71931033 ps |
CPU time | 2.4 seconds |
Started | Mar 31 12:47:59 PM PDT 24 |
Finished | Mar 31 12:48:02 PM PDT 24 |
Peak memory | 245736 kb |
Host | smart-e386b4ad-fa64-4bc0-8f54-b2b5155eb404 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643158850 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_mem_rw_with_rand_reset.3643158850 |
Directory | /workspace/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.1807573763 |
Short name | T1214 |
Test name | |
Test status | |
Simulation time | 140663891 ps |
CPU time | 1.58 seconds |
Started | Mar 31 12:48:00 PM PDT 24 |
Finished | Mar 31 12:48:02 PM PDT 24 |
Peak memory | 241272 kb |
Host | smart-76e5a81b-5a65-4981-b901-da2c1c7da544 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807573763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.1807573763 |
Directory | /workspace/13.otp_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.2928573190 |
Short name | T1291 |
Test name | |
Test status | |
Simulation time | 80739731 ps |
CPU time | 1.5 seconds |
Started | Mar 31 12:48:02 PM PDT 24 |
Finished | Mar 31 12:48:04 PM PDT 24 |
Peak memory | 229784 kb |
Host | smart-7a7ac00d-b27e-4d55-b3fa-a4ea2b9d7f03 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928573190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.2928573190 |
Directory | /workspace/13.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.497980170 |
Short name | T1255 |
Test name | |
Test status | |
Simulation time | 89407971 ps |
CPU time | 2.05 seconds |
Started | Mar 31 12:48:04 PM PDT 24 |
Finished | Mar 31 12:48:06 PM PDT 24 |
Peak memory | 239000 kb |
Host | smart-b84871ac-7881-482c-96f8-7726acb3dde3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497980170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_c trl_same_csr_outstanding.497980170 |
Directory | /workspace/13.otp_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.1470831565 |
Short name | T1320 |
Test name | |
Test status | |
Simulation time | 2212745702 ps |
CPU time | 7.49 seconds |
Started | Mar 31 12:47:58 PM PDT 24 |
Finished | Mar 31 12:48:06 PM PDT 24 |
Peak memory | 245932 kb |
Host | smart-86f07890-2fb9-4528-93e0-52d2bd1a2b58 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470831565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.1470831565 |
Directory | /workspace/13.otp_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.1106898842 |
Short name | T1265 |
Test name | |
Test status | |
Simulation time | 1663435792 ps |
CPU time | 18.43 seconds |
Started | Mar 31 12:48:01 PM PDT 24 |
Finished | Mar 31 12:48:19 PM PDT 24 |
Peak memory | 243608 kb |
Host | smart-004479cf-7874-4d85-b194-74a181aa9b72 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106898842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_i ntg_err.1106898842 |
Directory | /workspace/13.otp_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.1977292577 |
Short name | T1259 |
Test name | |
Test status | |
Simulation time | 213770453 ps |
CPU time | 3.24 seconds |
Started | Mar 31 12:47:58 PM PDT 24 |
Finished | Mar 31 12:48:02 PM PDT 24 |
Peak memory | 247228 kb |
Host | smart-72fa90a5-19c3-44bd-854c-4938727d0012 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977292577 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_mem_rw_with_rand_reset.1977292577 |
Directory | /workspace/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.3941012812 |
Short name | T1278 |
Test name | |
Test status | |
Simulation time | 38727219 ps |
CPU time | 1.41 seconds |
Started | Mar 31 12:47:57 PM PDT 24 |
Finished | Mar 31 12:47:59 PM PDT 24 |
Peak memory | 229464 kb |
Host | smart-6f5530ac-113a-4134-9d8c-33b03e629fe6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941012812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.3941012812 |
Directory | /workspace/14.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.538706256 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 1616848437 ps |
CPU time | 4.83 seconds |
Started | Mar 31 12:48:01 PM PDT 24 |
Finished | Mar 31 12:48:06 PM PDT 24 |
Peak memory | 238956 kb |
Host | smart-d8253043-8666-40ba-a956-e9e3f20952fc |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538706256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_c trl_same_csr_outstanding.538706256 |
Directory | /workspace/14.otp_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.2169719586 |
Short name | T1201 |
Test name | |
Test status | |
Simulation time | 312368965 ps |
CPU time | 6.22 seconds |
Started | Mar 31 12:47:59 PM PDT 24 |
Finished | Mar 31 12:48:06 PM PDT 24 |
Peak memory | 247016 kb |
Host | smart-aefad295-a650-4585-ab92-a20bef028f66 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169719586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.2169719586 |
Directory | /workspace/14.otp_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.1093281809 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 10263563536 ps |
CPU time | 15.47 seconds |
Started | Mar 31 12:47:59 PM PDT 24 |
Finished | Mar 31 12:48:15 PM PDT 24 |
Peak memory | 239196 kb |
Host | smart-b572cc50-0972-49f4-9a22-beae5e82e38b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093281809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_i ntg_err.1093281809 |
Directory | /workspace/14.otp_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.2014903607 |
Short name | T1230 |
Test name | |
Test status | |
Simulation time | 108765090 ps |
CPU time | 2.73 seconds |
Started | Mar 31 12:48:08 PM PDT 24 |
Finished | Mar 31 12:48:11 PM PDT 24 |
Peak memory | 246096 kb |
Host | smart-0f7a659c-1646-43f3-b005-b25f73a7cb67 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014903607 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_mem_rw_with_rand_reset.2014903607 |
Directory | /workspace/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.1724967544 |
Short name | T1227 |
Test name | |
Test status | |
Simulation time | 159814823 ps |
CPU time | 1.46 seconds |
Started | Mar 31 12:48:06 PM PDT 24 |
Finished | Mar 31 12:48:08 PM PDT 24 |
Peak memory | 241156 kb |
Host | smart-6e8b7a0a-fb70-4873-bd96-4b89459cfc06 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724967544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.1724967544 |
Directory | /workspace/15.otp_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.2696625076 |
Short name | T1244 |
Test name | |
Test status | |
Simulation time | 42363715 ps |
CPU time | 1.45 seconds |
Started | Mar 31 12:48:11 PM PDT 24 |
Finished | Mar 31 12:48:12 PM PDT 24 |
Peak memory | 229504 kb |
Host | smart-f1a683b0-8288-4d76-b512-ed835a4be8f0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696625076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.2696625076 |
Directory | /workspace/15.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.3181003073 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 156195627 ps |
CPU time | 2.91 seconds |
Started | Mar 31 12:48:07 PM PDT 24 |
Finished | Mar 31 12:48:10 PM PDT 24 |
Peak memory | 239076 kb |
Host | smart-101d2919-9f4e-4f24-a7e8-7f77be2dc5db |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181003073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ ctrl_same_csr_outstanding.3181003073 |
Directory | /workspace/15.otp_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.1915904515 |
Short name | T1205 |
Test name | |
Test status | |
Simulation time | 80639784 ps |
CPU time | 4.75 seconds |
Started | Mar 31 12:48:07 PM PDT 24 |
Finished | Mar 31 12:48:12 PM PDT 24 |
Peak memory | 246660 kb |
Host | smart-629596ad-0ffc-4538-9f66-c0c610134f72 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915904515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.1915904515 |
Directory | /workspace/15.otp_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.1944354361 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 10296883781 ps |
CPU time | 18.17 seconds |
Started | Mar 31 12:48:08 PM PDT 24 |
Finished | Mar 31 12:48:26 PM PDT 24 |
Peak memory | 244276 kb |
Host | smart-93603e8d-e027-4881-9a04-d364946208ad |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944354361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_i ntg_err.1944354361 |
Directory | /workspace/15.otp_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.665614125 |
Short name | T1290 |
Test name | |
Test status | |
Simulation time | 280849036 ps |
CPU time | 2.14 seconds |
Started | Mar 31 12:48:07 PM PDT 24 |
Finished | Mar 31 12:48:09 PM PDT 24 |
Peak memory | 244756 kb |
Host | smart-bafc4606-a4c3-4021-b1fc-c77026a0738c |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665614125 -assert nopostproc +UVM_TESTNAME= otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_mem_rw_with_rand_reset.665614125 |
Directory | /workspace/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.2102141973 |
Short name | T1216 |
Test name | |
Test status | |
Simulation time | 40505043 ps |
CPU time | 1.61 seconds |
Started | Mar 31 12:48:07 PM PDT 24 |
Finished | Mar 31 12:48:09 PM PDT 24 |
Peak memory | 241140 kb |
Host | smart-0e9d6f99-2f2d-4dde-9837-03578f11b517 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102141973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.2102141973 |
Directory | /workspace/16.otp_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.2446809618 |
Short name | T1280 |
Test name | |
Test status | |
Simulation time | 80609942 ps |
CPU time | 1.46 seconds |
Started | Mar 31 12:48:05 PM PDT 24 |
Finished | Mar 31 12:48:06 PM PDT 24 |
Peak memory | 230616 kb |
Host | smart-bd445ae4-b40f-4dff-bef2-67c7abc54ea4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446809618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.2446809618 |
Directory | /workspace/16.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.219316660 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 185702754 ps |
CPU time | 1.95 seconds |
Started | Mar 31 12:48:09 PM PDT 24 |
Finished | Mar 31 12:48:11 PM PDT 24 |
Peak memory | 239008 kb |
Host | smart-ff5757e8-87b9-477b-8a86-ff4648cdf7e3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219316660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_c trl_same_csr_outstanding.219316660 |
Directory | /workspace/16.otp_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.1590699532 |
Short name | T1239 |
Test name | |
Test status | |
Simulation time | 217065343 ps |
CPU time | 3.5 seconds |
Started | Mar 31 12:48:06 PM PDT 24 |
Finished | Mar 31 12:48:10 PM PDT 24 |
Peak memory | 246788 kb |
Host | smart-30a11e0c-f730-4245-8dd7-1d95e85ec36a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590699532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.1590699532 |
Directory | /workspace/16.otp_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.2770416774 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 10193532175 ps |
CPU time | 21.9 seconds |
Started | Mar 31 12:48:06 PM PDT 24 |
Finished | Mar 31 12:48:28 PM PDT 24 |
Peak memory | 244744 kb |
Host | smart-47402164-8c2e-48b4-b9b9-337010f454e0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770416774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_i ntg_err.2770416774 |
Directory | /workspace/16.otp_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.1324184213 |
Short name | T1325 |
Test name | |
Test status | |
Simulation time | 150390756 ps |
CPU time | 2.09 seconds |
Started | Mar 31 12:48:05 PM PDT 24 |
Finished | Mar 31 12:48:07 PM PDT 24 |
Peak memory | 245608 kb |
Host | smart-84e6fdf0-7f4b-474e-9710-b7d977d44c17 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324184213 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_mem_rw_with_rand_reset.1324184213 |
Directory | /workspace/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.4205448389 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 85937949 ps |
CPU time | 1.83 seconds |
Started | Mar 31 12:48:07 PM PDT 24 |
Finished | Mar 31 12:48:09 PM PDT 24 |
Peak memory | 238932 kb |
Host | smart-6d7f68a7-9ce3-456b-aecd-e785f52b5cb0 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205448389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.4205448389 |
Directory | /workspace/17.otp_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.1625488844 |
Short name | T1264 |
Test name | |
Test status | |
Simulation time | 43620773 ps |
CPU time | 1.43 seconds |
Started | Mar 31 12:48:06 PM PDT 24 |
Finished | Mar 31 12:48:07 PM PDT 24 |
Peak memory | 230640 kb |
Host | smart-0545203f-e979-470d-83d2-fcea3758b40f |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625488844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.1625488844 |
Directory | /workspace/17.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.1885303086 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 66830198 ps |
CPU time | 2.13 seconds |
Started | Mar 31 12:48:08 PM PDT 24 |
Finished | Mar 31 12:48:10 PM PDT 24 |
Peak memory | 239052 kb |
Host | smart-f4e76413-9cb9-4bde-a8fa-7925d93d86f2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885303086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ ctrl_same_csr_outstanding.1885303086 |
Directory | /workspace/17.otp_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.697162196 |
Short name | T1321 |
Test name | |
Test status | |
Simulation time | 209297433 ps |
CPU time | 5.79 seconds |
Started | Mar 31 12:48:08 PM PDT 24 |
Finished | Mar 31 12:48:14 PM PDT 24 |
Peak memory | 245952 kb |
Host | smart-f57ca355-9315-4d7c-b756-b6c1c7e18d66 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697162196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.697162196 |
Directory | /workspace/17.otp_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.2074243374 |
Short name | T1221 |
Test name | |
Test status | |
Simulation time | 131721513 ps |
CPU time | 2.99 seconds |
Started | Mar 31 12:48:07 PM PDT 24 |
Finished | Mar 31 12:48:10 PM PDT 24 |
Peak memory | 247180 kb |
Host | smart-07e0f28c-48f2-4001-965e-8431af11e5e8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074243374 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_mem_rw_with_rand_reset.2074243374 |
Directory | /workspace/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.4246222363 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 38946541 ps |
CPU time | 1.5 seconds |
Started | Mar 31 12:48:08 PM PDT 24 |
Finished | Mar 31 12:48:10 PM PDT 24 |
Peak memory | 239856 kb |
Host | smart-4ad23c98-247c-4bce-aded-11a0cfcfe0de |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246222363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.4246222363 |
Directory | /workspace/18.otp_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.2681158326 |
Short name | T1324 |
Test name | |
Test status | |
Simulation time | 602626335 ps |
CPU time | 1.72 seconds |
Started | Mar 31 12:48:11 PM PDT 24 |
Finished | Mar 31 12:48:12 PM PDT 24 |
Peak memory | 230664 kb |
Host | smart-a57214cb-270f-40c6-9680-5d1e88097664 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681158326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.2681158326 |
Directory | /workspace/18.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.554666125 |
Short name | T1295 |
Test name | |
Test status | |
Simulation time | 202277770 ps |
CPU time | 2.64 seconds |
Started | Mar 31 12:48:05 PM PDT 24 |
Finished | Mar 31 12:48:08 PM PDT 24 |
Peak memory | 237932 kb |
Host | smart-85a420e1-4490-4c49-9a26-36de13877205 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554666125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_c trl_same_csr_outstanding.554666125 |
Directory | /workspace/18.otp_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.2772255141 |
Short name | T1248 |
Test name | |
Test status | |
Simulation time | 615669061 ps |
CPU time | 6.42 seconds |
Started | Mar 31 12:48:08 PM PDT 24 |
Finished | Mar 31 12:48:14 PM PDT 24 |
Peak memory | 239220 kb |
Host | smart-0264db02-530c-4acf-b8e2-39e9faa83c3a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772255141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.2772255141 |
Directory | /workspace/18.otp_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.3601286844 |
Short name | T1294 |
Test name | |
Test status | |
Simulation time | 9715517522 ps |
CPU time | 12.31 seconds |
Started | Mar 31 12:48:08 PM PDT 24 |
Finished | Mar 31 12:48:21 PM PDT 24 |
Peak memory | 239184 kb |
Host | smart-53e1232c-8948-4028-8b46-d4592d22a026 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601286844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_i ntg_err.3601286844 |
Directory | /workspace/18.otp_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.3112554045 |
Short name | T1296 |
Test name | |
Test status | |
Simulation time | 64694445 ps |
CPU time | 2.19 seconds |
Started | Mar 31 12:48:12 PM PDT 24 |
Finished | Mar 31 12:48:14 PM PDT 24 |
Peak memory | 246940 kb |
Host | smart-5f1e990b-6134-45c4-b733-7339416ad6c9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112554045 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_mem_rw_with_rand_reset.3112554045 |
Directory | /workspace/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.3728415595 |
Short name | T1266 |
Test name | |
Test status | |
Simulation time | 50625923 ps |
CPU time | 1.68 seconds |
Started | Mar 31 12:48:06 PM PDT 24 |
Finished | Mar 31 12:48:08 PM PDT 24 |
Peak memory | 239828 kb |
Host | smart-ea71d3c8-aa33-4c62-8213-2e0ea18a398a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728415595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.3728415595 |
Directory | /workspace/19.otp_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.3297471909 |
Short name | T1222 |
Test name | |
Test status | |
Simulation time | 565810279 ps |
CPU time | 2.18 seconds |
Started | Mar 31 12:48:06 PM PDT 24 |
Finished | Mar 31 12:48:08 PM PDT 24 |
Peak memory | 230836 kb |
Host | smart-133a6384-3800-4774-81fe-6acb4589d6bc |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297471909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.3297471909 |
Directory | /workspace/19.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.3826505715 |
Short name | T1218 |
Test name | |
Test status | |
Simulation time | 53872780 ps |
CPU time | 1.99 seconds |
Started | Mar 31 12:48:07 PM PDT 24 |
Finished | Mar 31 12:48:09 PM PDT 24 |
Peak memory | 238004 kb |
Host | smart-05d2a956-cf91-4914-b12f-1c295a5a82ad |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826505715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ ctrl_same_csr_outstanding.3826505715 |
Directory | /workspace/19.otp_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.2800252736 |
Short name | T1241 |
Test name | |
Test status | |
Simulation time | 165881783 ps |
CPU time | 3.33 seconds |
Started | Mar 31 12:48:06 PM PDT 24 |
Finished | Mar 31 12:48:10 PM PDT 24 |
Peak memory | 239048 kb |
Host | smart-b2b3cd55-eb37-4b3a-9af4-3cb4a4ab9100 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800252736 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.2800252736 |
Directory | /workspace/19.otp_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.2730252617 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 10471457339 ps |
CPU time | 16.81 seconds |
Started | Mar 31 12:48:08 PM PDT 24 |
Finished | Mar 31 12:48:25 PM PDT 24 |
Peak memory | 244932 kb |
Host | smart-caf01c46-67ad-46c4-8f20-20c01f1938fa |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730252617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_i ntg_err.2730252617 |
Directory | /workspace/19.otp_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.3254913183 |
Short name | T1202 |
Test name | |
Test status | |
Simulation time | 104978877 ps |
CPU time | 5.01 seconds |
Started | Mar 31 12:47:39 PM PDT 24 |
Finished | Mar 31 12:47:44 PM PDT 24 |
Peak memory | 238964 kb |
Host | smart-83f5af59-e151-4f4d-abac-6cdd82e6afae |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254913183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_alia sing.3254913183 |
Directory | /workspace/2.otp_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.1556748250 |
Short name | T1257 |
Test name | |
Test status | |
Simulation time | 5577789033 ps |
CPU time | 8.81 seconds |
Started | Mar 31 12:47:36 PM PDT 24 |
Finished | Mar 31 12:47:45 PM PDT 24 |
Peak memory | 237856 kb |
Host | smart-57e4c4f1-9dd2-40e3-816a-1a996e6ff180 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556748250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_ bash.1556748250 |
Directory | /workspace/2.otp_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.3929251374 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 248489398 ps |
CPU time | 2.23 seconds |
Started | Mar 31 12:47:38 PM PDT 24 |
Finished | Mar 31 12:47:40 PM PDT 24 |
Peak memory | 238988 kb |
Host | smart-a816568a-0901-45e4-b21e-66a4303ba995 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929251374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_r eset.3929251374 |
Directory | /workspace/2.otp_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.1826812597 |
Short name | T1329 |
Test name | |
Test status | |
Simulation time | 148211772 ps |
CPU time | 2.22 seconds |
Started | Mar 31 12:47:37 PM PDT 24 |
Finished | Mar 31 12:47:39 PM PDT 24 |
Peak memory | 246068 kb |
Host | smart-47820228-1ca7-4e99-bf85-003b56dba153 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826812597 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_mem_rw_with_rand_reset.1826812597 |
Directory | /workspace/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.4272411327 |
Short name | T1269 |
Test name | |
Test status | |
Simulation time | 43251366 ps |
CPU time | 1.56 seconds |
Started | Mar 31 12:47:37 PM PDT 24 |
Finished | Mar 31 12:47:38 PM PDT 24 |
Peak memory | 241108 kb |
Host | smart-4ef78789-461d-4c80-b055-ce307ac673f8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272411327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.4272411327 |
Directory | /workspace/2.otp_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.1638624999 |
Short name | T1208 |
Test name | |
Test status | |
Simulation time | 146093852 ps |
CPU time | 1.52 seconds |
Started | Mar 31 12:47:36 PM PDT 24 |
Finished | Mar 31 12:47:38 PM PDT 24 |
Peak memory | 229708 kb |
Host | smart-059b6137-a80d-4659-a3a5-f70086304bb3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638624999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.1638624999 |
Directory | /workspace/2.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.3735343193 |
Short name | T1232 |
Test name | |
Test status | |
Simulation time | 45983703 ps |
CPU time | 1.37 seconds |
Started | Mar 31 12:47:39 PM PDT 24 |
Finished | Mar 31 12:47:41 PM PDT 24 |
Peak memory | 230140 kb |
Host | smart-1714ee16-1ce3-4ee4-be2a-729daa607d5a |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735343193 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctr l_mem_partial_access.3735343193 |
Directory | /workspace/2.otp_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.3666235387 |
Short name | T1310 |
Test name | |
Test status | |
Simulation time | 69086573 ps |
CPU time | 1.39 seconds |
Started | Mar 31 12:47:38 PM PDT 24 |
Finished | Mar 31 12:47:40 PM PDT 24 |
Peak memory | 230676 kb |
Host | smart-3a15a36d-f081-4c93-be7e-a7847c527c43 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666235387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk .3666235387 |
Directory | /workspace/2.otp_ctrl_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.1976994329 |
Short name | T1210 |
Test name | |
Test status | |
Simulation time | 126637580 ps |
CPU time | 2.2 seconds |
Started | Mar 31 12:47:37 PM PDT 24 |
Finished | Mar 31 12:47:39 PM PDT 24 |
Peak memory | 239056 kb |
Host | smart-10201fe0-9257-4991-9a96-f7963f409b9f |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976994329 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_c trl_same_csr_outstanding.1976994329 |
Directory | /workspace/2.otp_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.2211760554 |
Short name | T1273 |
Test name | |
Test status | |
Simulation time | 566607022 ps |
CPU time | 5.87 seconds |
Started | Mar 31 12:47:29 PM PDT 24 |
Finished | Mar 31 12:47:35 PM PDT 24 |
Peak memory | 245968 kb |
Host | smart-931999fc-c2a8-4c4b-92f9-de589974d822 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211760554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.2211760554 |
Directory | /workspace/2.otp_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.914023184 |
Short name | T1252 |
Test name | |
Test status | |
Simulation time | 664777965 ps |
CPU time | 9.4 seconds |
Started | Mar 31 12:47:37 PM PDT 24 |
Finished | Mar 31 12:47:46 PM PDT 24 |
Peak memory | 244004 kb |
Host | smart-c5c9c154-eded-4ccc-aa68-1691fa77971b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914023184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_int g_err.914023184 |
Directory | /workspace/2.otp_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.62801898 |
Short name | T1282 |
Test name | |
Test status | |
Simulation time | 42591180 ps |
CPU time | 1.42 seconds |
Started | Mar 31 12:48:14 PM PDT 24 |
Finished | Mar 31 12:48:15 PM PDT 24 |
Peak memory | 229440 kb |
Host | smart-2315e580-bc3f-42c7-aade-336274b1685e |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62801898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.62801898 |
Directory | /workspace/20.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.144622602 |
Short name | T1297 |
Test name | |
Test status | |
Simulation time | 116118102 ps |
CPU time | 1.55 seconds |
Started | Mar 31 12:48:15 PM PDT 24 |
Finished | Mar 31 12:48:17 PM PDT 24 |
Peak memory | 230712 kb |
Host | smart-e635e45c-c947-41a7-96d7-7ab5870b4136 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144622602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.144622602 |
Directory | /workspace/21.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.379153757 |
Short name | T1213 |
Test name | |
Test status | |
Simulation time | 53281247 ps |
CPU time | 1.61 seconds |
Started | Mar 31 12:48:23 PM PDT 24 |
Finished | Mar 31 12:48:25 PM PDT 24 |
Peak memory | 229712 kb |
Host | smart-6dc1143a-ee31-4b77-aa8a-8444b5beb143 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379153757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.379153757 |
Directory | /workspace/22.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.3578290512 |
Short name | T1229 |
Test name | |
Test status | |
Simulation time | 601184387 ps |
CPU time | 2.18 seconds |
Started | Mar 31 12:48:12 PM PDT 24 |
Finished | Mar 31 12:48:15 PM PDT 24 |
Peak memory | 230844 kb |
Host | smart-0a109d87-7356-4cac-9ed6-69c7e7cc64ee |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578290512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.3578290512 |
Directory | /workspace/23.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.1326505055 |
Short name | T1263 |
Test name | |
Test status | |
Simulation time | 143633173 ps |
CPU time | 1.42 seconds |
Started | Mar 31 12:48:23 PM PDT 24 |
Finished | Mar 31 12:48:24 PM PDT 24 |
Peak memory | 230008 kb |
Host | smart-e2773ca4-4ef6-4ede-9d4f-8f88aae8f705 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326505055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.1326505055 |
Directory | /workspace/24.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.4104299302 |
Short name | T1258 |
Test name | |
Test status | |
Simulation time | 565282529 ps |
CPU time | 1.52 seconds |
Started | Mar 31 12:48:12 PM PDT 24 |
Finished | Mar 31 12:48:13 PM PDT 24 |
Peak memory | 230836 kb |
Host | smart-8d539053-2107-4e19-ba61-0388f13beae4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104299302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.4104299302 |
Directory | /workspace/25.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.2522238091 |
Short name | T1203 |
Test name | |
Test status | |
Simulation time | 49674994 ps |
CPU time | 1.5 seconds |
Started | Mar 31 12:48:14 PM PDT 24 |
Finished | Mar 31 12:48:15 PM PDT 24 |
Peak memory | 229740 kb |
Host | smart-b624df94-cc8c-489b-9f86-dae9a74eb880 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522238091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.2522238091 |
Directory | /workspace/26.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.1464420485 |
Short name | T1268 |
Test name | |
Test status | |
Simulation time | 560032678 ps |
CPU time | 1.31 seconds |
Started | Mar 31 12:48:11 PM PDT 24 |
Finished | Mar 31 12:48:13 PM PDT 24 |
Peak memory | 230864 kb |
Host | smart-c6818a79-72c7-4da9-baf3-268f7e0db614 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464420485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.1464420485 |
Directory | /workspace/27.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.3907841855 |
Short name | T1238 |
Test name | |
Test status | |
Simulation time | 129415347 ps |
CPU time | 1.31 seconds |
Started | Mar 31 12:48:15 PM PDT 24 |
Finished | Mar 31 12:48:16 PM PDT 24 |
Peak memory | 230876 kb |
Host | smart-51d35c06-f268-4c11-97fb-1ad1c86ae357 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907841855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.3907841855 |
Directory | /workspace/28.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.3269062294 |
Short name | T1305 |
Test name | |
Test status | |
Simulation time | 70815282 ps |
CPU time | 1.44 seconds |
Started | Mar 31 12:48:15 PM PDT 24 |
Finished | Mar 31 12:48:16 PM PDT 24 |
Peak memory | 230684 kb |
Host | smart-62efc3e9-a975-4ac0-917e-e910f7b751b6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269062294 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.3269062294 |
Directory | /workspace/29.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.1172130416 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 115377468 ps |
CPU time | 3.57 seconds |
Started | Mar 31 12:47:40 PM PDT 24 |
Finished | Mar 31 12:47:44 PM PDT 24 |
Peak memory | 239084 kb |
Host | smart-6d3e0668-95b6-422c-985b-90bb83d53954 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172130416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_alia sing.1172130416 |
Directory | /workspace/3.otp_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.1675055759 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 173847136 ps |
CPU time | 3.6 seconds |
Started | Mar 31 12:47:37 PM PDT 24 |
Finished | Mar 31 12:47:41 PM PDT 24 |
Peak memory | 239028 kb |
Host | smart-ae6980b1-a781-44f1-a465-66282371e948 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675055759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_ bash.1675055759 |
Directory | /workspace/3.otp_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.3955133666 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 1501571829 ps |
CPU time | 3.11 seconds |
Started | Mar 31 12:47:37 PM PDT 24 |
Finished | Mar 31 12:47:40 PM PDT 24 |
Peak memory | 239120 kb |
Host | smart-135c3b8d-6afa-4c46-a283-e05fee542100 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955133666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_r eset.3955133666 |
Directory | /workspace/3.otp_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.1162863778 |
Short name | T1283 |
Test name | |
Test status | |
Simulation time | 110695459 ps |
CPU time | 2.25 seconds |
Started | Mar 31 12:47:38 PM PDT 24 |
Finished | Mar 31 12:47:41 PM PDT 24 |
Peak memory | 247364 kb |
Host | smart-9b26941f-7c3b-4bf5-9b0b-9d6882ac8621 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162863778 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_mem_rw_with_rand_reset.1162863778 |
Directory | /workspace/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.2977322672 |
Short name | T1231 |
Test name | |
Test status | |
Simulation time | 180620207 ps |
CPU time | 1.83 seconds |
Started | Mar 31 12:47:39 PM PDT 24 |
Finished | Mar 31 12:47:41 PM PDT 24 |
Peak memory | 238960 kb |
Host | smart-b411e415-7baa-4fc0-9369-52075b554a39 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977322672 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.2977322672 |
Directory | /workspace/3.otp_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.1441343180 |
Short name | T1247 |
Test name | |
Test status | |
Simulation time | 38736286 ps |
CPU time | 1.37 seconds |
Started | Mar 31 12:47:37 PM PDT 24 |
Finished | Mar 31 12:47:39 PM PDT 24 |
Peak memory | 229408 kb |
Host | smart-b52b2c18-9c9d-49a6-9aca-016d86798c37 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441343180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.1441343180 |
Directory | /workspace/3.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.2626277301 |
Short name | T1288 |
Test name | |
Test status | |
Simulation time | 129000889 ps |
CPU time | 1.34 seconds |
Started | Mar 31 12:47:37 PM PDT 24 |
Finished | Mar 31 12:47:38 PM PDT 24 |
Peak memory | 230444 kb |
Host | smart-0c622a8f-e48a-4209-88e9-bf14004f727f |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626277301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctr l_mem_partial_access.2626277301 |
Directory | /workspace/3.otp_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.2839292966 |
Short name | T1328 |
Test name | |
Test status | |
Simulation time | 47295574 ps |
CPU time | 1.31 seconds |
Started | Mar 31 12:47:38 PM PDT 24 |
Finished | Mar 31 12:47:39 PM PDT 24 |
Peak memory | 229232 kb |
Host | smart-f4214adc-618a-4d07-9ee0-7fcf1e13b076 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839292966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk .2839292966 |
Directory | /workspace/3.otp_ctrl_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.3933336563 |
Short name | T1220 |
Test name | |
Test status | |
Simulation time | 523993480 ps |
CPU time | 3.34 seconds |
Started | Mar 31 12:47:36 PM PDT 24 |
Finished | Mar 31 12:47:40 PM PDT 24 |
Peak memory | 237976 kb |
Host | smart-791ad8bd-7c4f-4e4e-873f-4db76fee0c79 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933336563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_c trl_same_csr_outstanding.3933336563 |
Directory | /workspace/3.otp_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.460950730 |
Short name | T1315 |
Test name | |
Test status | |
Simulation time | 205748473 ps |
CPU time | 2.91 seconds |
Started | Mar 31 12:47:38 PM PDT 24 |
Finished | Mar 31 12:47:41 PM PDT 24 |
Peak memory | 246248 kb |
Host | smart-cf755ae1-a5da-4993-a129-ced402c4f057 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460950730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.460950730 |
Directory | /workspace/3.otp_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.643288478 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 1189264775 ps |
CPU time | 17.58 seconds |
Started | Mar 31 12:47:36 PM PDT 24 |
Finished | Mar 31 12:47:54 PM PDT 24 |
Peak memory | 239092 kb |
Host | smart-2655101d-0ec2-42e8-a948-193fedb8ccd2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643288478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_int g_err.643288478 |
Directory | /workspace/3.otp_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.2864345662 |
Short name | T1307 |
Test name | |
Test status | |
Simulation time | 70331423 ps |
CPU time | 1.51 seconds |
Started | Mar 31 12:48:23 PM PDT 24 |
Finished | Mar 31 12:48:24 PM PDT 24 |
Peak memory | 230648 kb |
Host | smart-481f5a46-8aad-434f-b60e-253ff20ba346 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864345662 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.2864345662 |
Directory | /workspace/30.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.3626418776 |
Short name | T1323 |
Test name | |
Test status | |
Simulation time | 38772753 ps |
CPU time | 1.35 seconds |
Started | Mar 31 12:48:14 PM PDT 24 |
Finished | Mar 31 12:48:16 PM PDT 24 |
Peak memory | 230684 kb |
Host | smart-c3a6b6c7-6c05-4f5f-825c-93fe95cb4623 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626418776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.3626418776 |
Directory | /workspace/31.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.2724833977 |
Short name | T1270 |
Test name | |
Test status | |
Simulation time | 76379485 ps |
CPU time | 1.44 seconds |
Started | Mar 31 12:48:18 PM PDT 24 |
Finished | Mar 31 12:48:19 PM PDT 24 |
Peak memory | 230696 kb |
Host | smart-d358ce3c-3f9f-4c4e-9d3e-b034ce2be93d |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724833977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.2724833977 |
Directory | /workspace/32.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.1952949350 |
Short name | T1304 |
Test name | |
Test status | |
Simulation time | 78714232 ps |
CPU time | 1.46 seconds |
Started | Mar 31 12:48:13 PM PDT 24 |
Finished | Mar 31 12:48:14 PM PDT 24 |
Peak memory | 229456 kb |
Host | smart-e62f8c31-2cf2-4add-beb0-5669d1e1240c |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952949350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.1952949350 |
Directory | /workspace/33.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.3213878867 |
Short name | T1286 |
Test name | |
Test status | |
Simulation time | 528566075 ps |
CPU time | 1.46 seconds |
Started | Mar 31 12:48:15 PM PDT 24 |
Finished | Mar 31 12:48:17 PM PDT 24 |
Peak memory | 230740 kb |
Host | smart-2778b94b-f9d7-4b9c-ae16-aec5bd9ff364 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213878867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.3213878867 |
Directory | /workspace/34.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.900074964 |
Short name | T1272 |
Test name | |
Test status | |
Simulation time | 67708174 ps |
CPU time | 1.38 seconds |
Started | Mar 31 12:48:15 PM PDT 24 |
Finished | Mar 31 12:48:17 PM PDT 24 |
Peak memory | 230804 kb |
Host | smart-c3b72f25-2380-4ae8-9497-ebe22f59b6b7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900074964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.900074964 |
Directory | /workspace/35.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.2318570381 |
Short name | T1212 |
Test name | |
Test status | |
Simulation time | 79460378 ps |
CPU time | 1.37 seconds |
Started | Mar 31 12:48:12 PM PDT 24 |
Finished | Mar 31 12:48:13 PM PDT 24 |
Peak memory | 229512 kb |
Host | smart-1b13819f-85aa-44d8-8513-28f608d3d0db |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318570381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.2318570381 |
Directory | /workspace/36.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.3058231242 |
Short name | T1327 |
Test name | |
Test status | |
Simulation time | 567115340 ps |
CPU time | 1.65 seconds |
Started | Mar 31 12:48:14 PM PDT 24 |
Finished | Mar 31 12:48:16 PM PDT 24 |
Peak memory | 229760 kb |
Host | smart-00f23848-7576-4013-a52c-b5409dd06c64 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058231242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.3058231242 |
Directory | /workspace/37.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.2591253257 |
Short name | T1204 |
Test name | |
Test status | |
Simulation time | 570678182 ps |
CPU time | 2.17 seconds |
Started | Mar 31 12:48:13 PM PDT 24 |
Finished | Mar 31 12:48:16 PM PDT 24 |
Peak memory | 230668 kb |
Host | smart-4337ca29-37e5-44fc-9f8a-899c2e5eb388 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591253257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.2591253257 |
Directory | /workspace/38.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.2078392351 |
Short name | T1200 |
Test name | |
Test status | |
Simulation time | 41199262 ps |
CPU time | 1.43 seconds |
Started | Mar 31 12:48:12 PM PDT 24 |
Finished | Mar 31 12:48:14 PM PDT 24 |
Peak memory | 230684 kb |
Host | smart-ba99c9ce-2124-4966-8096-9c4b9d0bbf84 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078392351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.2078392351 |
Directory | /workspace/39.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.2496988394 |
Short name | T1287 |
Test name | |
Test status | |
Simulation time | 380675401 ps |
CPU time | 4.09 seconds |
Started | Mar 31 12:47:46 PM PDT 24 |
Finished | Mar 31 12:47:50 PM PDT 24 |
Peak memory | 239016 kb |
Host | smart-6f4b86f1-d8f2-451f-9f85-f8baddc913ce |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496988394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_alia sing.2496988394 |
Directory | /workspace/4.otp_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.403596658 |
Short name | T1317 |
Test name | |
Test status | |
Simulation time | 347648198 ps |
CPU time | 6.59 seconds |
Started | Mar 31 12:47:38 PM PDT 24 |
Finished | Mar 31 12:47:45 PM PDT 24 |
Peak memory | 238924 kb |
Host | smart-9ec30f47-447d-40d4-89a5-99c6013f7543 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403596658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_b ash.403596658 |
Directory | /workspace/4.otp_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.2256208772 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 96453314 ps |
CPU time | 2.24 seconds |
Started | Mar 31 12:47:36 PM PDT 24 |
Finished | Mar 31 12:47:39 PM PDT 24 |
Peak memory | 237712 kb |
Host | smart-d962d336-a0c4-4e75-a77b-8436f726b435 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256208772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_r eset.2256208772 |
Directory | /workspace/4.otp_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.917342779 |
Short name | T1284 |
Test name | |
Test status | |
Simulation time | 136980747 ps |
CPU time | 2.18 seconds |
Started | Mar 31 12:47:44 PM PDT 24 |
Finished | Mar 31 12:47:46 PM PDT 24 |
Peak memory | 239220 kb |
Host | smart-87b66e8d-8880-4831-9672-8cbfa32416e4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917342779 -assert nopostproc +UVM_TESTNAME= otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_mem_rw_with_rand_reset.917342779 |
Directory | /workspace/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.3141093026 |
Short name | T1303 |
Test name | |
Test status | |
Simulation time | 92803642 ps |
CPU time | 1.66 seconds |
Started | Mar 31 12:47:39 PM PDT 24 |
Finished | Mar 31 12:47:41 PM PDT 24 |
Peak memory | 241484 kb |
Host | smart-41c0d97e-044f-40fe-815b-fb4bd2fb9b22 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141093026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.3141093026 |
Directory | /workspace/4.otp_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.1021017672 |
Short name | T1279 |
Test name | |
Test status | |
Simulation time | 592599452 ps |
CPU time | 1.41 seconds |
Started | Mar 31 12:47:36 PM PDT 24 |
Finished | Mar 31 12:47:38 PM PDT 24 |
Peak memory | 230800 kb |
Host | smart-7cc04056-313a-4538-b0fd-5935cd146d22 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021017672 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.1021017672 |
Directory | /workspace/4.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.903004439 |
Short name | T1302 |
Test name | |
Test status | |
Simulation time | 38756304 ps |
CPU time | 1.32 seconds |
Started | Mar 31 12:47:40 PM PDT 24 |
Finished | Mar 31 12:47:42 PM PDT 24 |
Peak memory | 230596 kb |
Host | smart-eab0e329-1bca-40c0-b075-741dccb4ad74 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903004439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl _mem_partial_access.903004439 |
Directory | /workspace/4.otp_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.2921387347 |
Short name | T1326 |
Test name | |
Test status | |
Simulation time | 125675326 ps |
CPU time | 1.29 seconds |
Started | Mar 31 12:47:36 PM PDT 24 |
Finished | Mar 31 12:47:37 PM PDT 24 |
Peak memory | 230688 kb |
Host | smart-f0593311-0d44-404c-a50d-59f901cb4932 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921387347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk .2921387347 |
Directory | /workspace/4.otp_ctrl_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.1142802281 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 120860071 ps |
CPU time | 3.47 seconds |
Started | Mar 31 12:47:43 PM PDT 24 |
Finished | Mar 31 12:47:47 PM PDT 24 |
Peak memory | 238920 kb |
Host | smart-52b7b4e5-8d41-48c7-be7c-ec9d1d743a38 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142802281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_c trl_same_csr_outstanding.1142802281 |
Directory | /workspace/4.otp_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.255668551 |
Short name | T1199 |
Test name | |
Test status | |
Simulation time | 335409569 ps |
CPU time | 3.35 seconds |
Started | Mar 31 12:47:38 PM PDT 24 |
Finished | Mar 31 12:47:41 PM PDT 24 |
Peak memory | 247224 kb |
Host | smart-a65c7b3c-d4d3-492c-98aa-49ce0341a5d7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255668551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.255668551 |
Directory | /workspace/4.otp_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.2606061495 |
Short name | T1245 |
Test name | |
Test status | |
Simulation time | 69343701 ps |
CPU time | 1.47 seconds |
Started | Mar 31 12:48:16 PM PDT 24 |
Finished | Mar 31 12:48:17 PM PDT 24 |
Peak memory | 230788 kb |
Host | smart-55134ebb-227f-42ac-b9e6-e2f74c76941d |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606061495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.2606061495 |
Directory | /workspace/40.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.3367614941 |
Short name | T1219 |
Test name | |
Test status | |
Simulation time | 93309414 ps |
CPU time | 1.48 seconds |
Started | Mar 31 12:48:13 PM PDT 24 |
Finished | Mar 31 12:48:15 PM PDT 24 |
Peak memory | 230868 kb |
Host | smart-82c33c88-5e2d-4009-9f30-342e625b0c81 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367614941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.3367614941 |
Directory | /workspace/41.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.1706708679 |
Short name | T1211 |
Test name | |
Test status | |
Simulation time | 65873334 ps |
CPU time | 1.36 seconds |
Started | Mar 31 12:48:11 PM PDT 24 |
Finished | Mar 31 12:48:13 PM PDT 24 |
Peak memory | 230696 kb |
Host | smart-fe0bfdb2-1d5b-48df-b0ed-affdd844ad4c |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706708679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.1706708679 |
Directory | /workspace/42.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.406904796 |
Short name | T1253 |
Test name | |
Test status | |
Simulation time | 80097664 ps |
CPU time | 1.33 seconds |
Started | Mar 31 12:48:13 PM PDT 24 |
Finished | Mar 31 12:48:15 PM PDT 24 |
Peak memory | 230640 kb |
Host | smart-5c5ff318-7318-43ca-95f0-bd4a6a5b1114 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406904796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.406904796 |
Directory | /workspace/43.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.3899869921 |
Short name | T1251 |
Test name | |
Test status | |
Simulation time | 38407489 ps |
CPU time | 1.36 seconds |
Started | Mar 31 12:48:15 PM PDT 24 |
Finished | Mar 31 12:48:17 PM PDT 24 |
Peak memory | 230892 kb |
Host | smart-ef33d4dc-6be0-4bc1-95b7-b2df6b61fac5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899869921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.3899869921 |
Directory | /workspace/44.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.1990015174 |
Short name | T1197 |
Test name | |
Test status | |
Simulation time | 55645778 ps |
CPU time | 1.46 seconds |
Started | Mar 31 12:48:13 PM PDT 24 |
Finished | Mar 31 12:48:14 PM PDT 24 |
Peak memory | 230832 kb |
Host | smart-0b2852b4-98a1-47cf-8e51-364c13fd9a89 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990015174 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.1990015174 |
Directory | /workspace/45.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.2818125336 |
Short name | T1313 |
Test name | |
Test status | |
Simulation time | 66289938 ps |
CPU time | 1.35 seconds |
Started | Mar 31 12:48:12 PM PDT 24 |
Finished | Mar 31 12:48:13 PM PDT 24 |
Peak memory | 230868 kb |
Host | smart-33f18e5e-5e17-4507-b71d-2f563d3ef1ca |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818125336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.2818125336 |
Directory | /workspace/46.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.2350389851 |
Short name | T1224 |
Test name | |
Test status | |
Simulation time | 71429720 ps |
CPU time | 1.4 seconds |
Started | Mar 31 12:48:12 PM PDT 24 |
Finished | Mar 31 12:48:14 PM PDT 24 |
Peak memory | 230764 kb |
Host | smart-d6ff1ddc-c940-440d-80f9-ed4a81c1bb52 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350389851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.2350389851 |
Directory | /workspace/47.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.2369870824 |
Short name | T1207 |
Test name | |
Test status | |
Simulation time | 77492555 ps |
CPU time | 1.55 seconds |
Started | Mar 31 12:48:14 PM PDT 24 |
Finished | Mar 31 12:48:16 PM PDT 24 |
Peak memory | 229444 kb |
Host | smart-eb4a6fd5-3e1f-4f09-841d-d83603678464 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369870824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.2369870824 |
Directory | /workspace/48.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.1028880825 |
Short name | T1261 |
Test name | |
Test status | |
Simulation time | 78376873 ps |
CPU time | 1.55 seconds |
Started | Mar 31 12:48:23 PM PDT 24 |
Finished | Mar 31 12:48:25 PM PDT 24 |
Peak memory | 230264 kb |
Host | smart-63ab25b5-0534-4c55-9828-4c9f897be7f3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028880825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.1028880825 |
Directory | /workspace/49.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.4255267378 |
Short name | T1246 |
Test name | |
Test status | |
Simulation time | 78978817 ps |
CPU time | 2.01 seconds |
Started | Mar 31 12:47:44 PM PDT 24 |
Finished | Mar 31 12:47:46 PM PDT 24 |
Peak memory | 244824 kb |
Host | smart-f5799a2c-1f70-4e16-b89d-0827d22c5cf7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255267378 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_mem_rw_with_rand_reset.4255267378 |
Directory | /workspace/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.63508536 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 173406997 ps |
CPU time | 1.84 seconds |
Started | Mar 31 12:47:43 PM PDT 24 |
Finished | Mar 31 12:47:45 PM PDT 24 |
Peak memory | 241768 kb |
Host | smart-15566d5e-8f9f-41d0-98ad-98810cae2d9c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63508536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.63508536 |
Directory | /workspace/5.otp_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.3573724877 |
Short name | T1322 |
Test name | |
Test status | |
Simulation time | 138201178 ps |
CPU time | 1.43 seconds |
Started | Mar 31 12:47:46 PM PDT 24 |
Finished | Mar 31 12:47:48 PM PDT 24 |
Peak memory | 230852 kb |
Host | smart-49ab4898-f826-4321-ba79-72aeea4fd35b |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573724877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.3573724877 |
Directory | /workspace/5.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.3018179000 |
Short name | T1260 |
Test name | |
Test status | |
Simulation time | 665470273 ps |
CPU time | 2.76 seconds |
Started | Mar 31 12:47:49 PM PDT 24 |
Finished | Mar 31 12:47:52 PM PDT 24 |
Peak memory | 239076 kb |
Host | smart-1cfc4571-55aa-4c3f-a8ab-8f1b50e05210 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018179000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_c trl_same_csr_outstanding.3018179000 |
Directory | /workspace/5.otp_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.3298850865 |
Short name | T1281 |
Test name | |
Test status | |
Simulation time | 208981692 ps |
CPU time | 7.35 seconds |
Started | Mar 31 12:47:46 PM PDT 24 |
Finished | Mar 31 12:47:53 PM PDT 24 |
Peak memory | 246780 kb |
Host | smart-cb9cbdb5-2a25-4fb0-9576-74ca480bd2c6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298850865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.3298850865 |
Directory | /workspace/5.otp_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.4246481536 |
Short name | T1243 |
Test name | |
Test status | |
Simulation time | 131168703 ps |
CPU time | 2.92 seconds |
Started | Mar 31 12:47:46 PM PDT 24 |
Finished | Mar 31 12:47:49 PM PDT 24 |
Peak memory | 246432 kb |
Host | smart-21944587-a6a7-4987-97d2-c7309b61829a |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246481536 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_mem_rw_with_rand_reset.4246481536 |
Directory | /workspace/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.3728503191 |
Short name | T1250 |
Test name | |
Test status | |
Simulation time | 49981040 ps |
CPU time | 1.71 seconds |
Started | Mar 31 12:47:44 PM PDT 24 |
Finished | Mar 31 12:47:46 PM PDT 24 |
Peak memory | 241176 kb |
Host | smart-5ab60626-29ba-42ae-a751-4b3e419cd75a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728503191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.3728503191 |
Directory | /workspace/6.otp_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.1255905212 |
Short name | T1311 |
Test name | |
Test status | |
Simulation time | 141231852 ps |
CPU time | 1.41 seconds |
Started | Mar 31 12:47:42 PM PDT 24 |
Finished | Mar 31 12:47:44 PM PDT 24 |
Peak memory | 229448 kb |
Host | smart-05e70742-0944-4918-9a86-8ab85040820d |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255905212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.1255905212 |
Directory | /workspace/6.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.1356596561 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 1474923907 ps |
CPU time | 4.43 seconds |
Started | Mar 31 12:47:50 PM PDT 24 |
Finished | Mar 31 12:47:55 PM PDT 24 |
Peak memory | 239140 kb |
Host | smart-72c46b2d-567f-4d1d-b2e9-9ed35f3a9d26 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356596561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_c trl_same_csr_outstanding.1356596561 |
Directory | /workspace/6.otp_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.138662298 |
Short name | T1237 |
Test name | |
Test status | |
Simulation time | 120206142 ps |
CPU time | 3.47 seconds |
Started | Mar 31 12:47:42 PM PDT 24 |
Finished | Mar 31 12:47:45 PM PDT 24 |
Peak memory | 246744 kb |
Host | smart-9970a859-ebdc-4686-89b7-1d28a764251c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138662298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.138662298 |
Directory | /workspace/6.otp_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.3217597320 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 1280632867 ps |
CPU time | 17.09 seconds |
Started | Mar 31 12:47:42 PM PDT 24 |
Finished | Mar 31 12:48:00 PM PDT 24 |
Peak memory | 239224 kb |
Host | smart-bbe2877c-96f6-4e32-adf8-f62bed292875 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217597320 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_in tg_err.3217597320 |
Directory | /workspace/6.otp_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.3967812391 |
Short name | T1242 |
Test name | |
Test status | |
Simulation time | 74898591 ps |
CPU time | 2.14 seconds |
Started | Mar 31 12:47:43 PM PDT 24 |
Finished | Mar 31 12:47:46 PM PDT 24 |
Peak memory | 245040 kb |
Host | smart-56394e5f-89a6-423a-b8ce-5f6ff1d08206 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967812391 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_mem_rw_with_rand_reset.3967812391 |
Directory | /workspace/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.827586426 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 57667081 ps |
CPU time | 1.53 seconds |
Started | Mar 31 12:47:46 PM PDT 24 |
Finished | Mar 31 12:47:48 PM PDT 24 |
Peak memory | 238960 kb |
Host | smart-d7b5e160-7dc8-419e-913f-b677629a668f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827586426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.827586426 |
Directory | /workspace/7.otp_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.1360154030 |
Short name | T1233 |
Test name | |
Test status | |
Simulation time | 41648568 ps |
CPU time | 1.35 seconds |
Started | Mar 31 12:47:42 PM PDT 24 |
Finished | Mar 31 12:47:43 PM PDT 24 |
Peak memory | 229480 kb |
Host | smart-6e7b9e78-c399-441a-aede-bdd381e19286 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360154030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.1360154030 |
Directory | /workspace/7.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.1089700696 |
Short name | T1275 |
Test name | |
Test status | |
Simulation time | 443890423 ps |
CPU time | 3.71 seconds |
Started | Mar 31 12:47:44 PM PDT 24 |
Finished | Mar 31 12:47:47 PM PDT 24 |
Peak memory | 239032 kb |
Host | smart-17e3ebd3-4135-4fd1-a710-cd55732356cc |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089700696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_c trl_same_csr_outstanding.1089700696 |
Directory | /workspace/7.otp_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.443350296 |
Short name | T1300 |
Test name | |
Test status | |
Simulation time | 593043799 ps |
CPU time | 6.73 seconds |
Started | Mar 31 12:47:43 PM PDT 24 |
Finished | Mar 31 12:47:50 PM PDT 24 |
Peak memory | 247216 kb |
Host | smart-2bd27f0e-55c1-4897-90c5-3c3cb90dd515 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443350296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.443350296 |
Directory | /workspace/7.otp_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.3612540850 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 2539605090 ps |
CPU time | 9.69 seconds |
Started | Mar 31 12:47:49 PM PDT 24 |
Finished | Mar 31 12:47:58 PM PDT 24 |
Peak memory | 239416 kb |
Host | smart-c4856bde-40b5-4f2b-935f-91fc4f546e6e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612540850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_in tg_err.3612540850 |
Directory | /workspace/7.otp_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.4125561636 |
Short name | T1314 |
Test name | |
Test status | |
Simulation time | 1026288043 ps |
CPU time | 2.65 seconds |
Started | Mar 31 12:47:50 PM PDT 24 |
Finished | Mar 31 12:47:53 PM PDT 24 |
Peak memory | 247420 kb |
Host | smart-cedd274e-8a98-460d-b66f-90c5620700fd |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125561636 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_mem_rw_with_rand_reset.4125561636 |
Directory | /workspace/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.2192667457 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 107514659 ps |
CPU time | 1.49 seconds |
Started | Mar 31 12:47:52 PM PDT 24 |
Finished | Mar 31 12:47:54 PM PDT 24 |
Peak memory | 241320 kb |
Host | smart-19fa5b52-9b4d-41df-b049-74c25952b9ec |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192667457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.2192667457 |
Directory | /workspace/8.otp_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.589630101 |
Short name | T1215 |
Test name | |
Test status | |
Simulation time | 68789313 ps |
CPU time | 1.35 seconds |
Started | Mar 31 12:47:50 PM PDT 24 |
Finished | Mar 31 12:47:52 PM PDT 24 |
Peak memory | 229516 kb |
Host | smart-49e7564b-4add-46c8-89f3-ca075a4e4256 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589630101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.589630101 |
Directory | /workspace/8.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.2465993271 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 79052044 ps |
CPU time | 2.32 seconds |
Started | Mar 31 12:47:50 PM PDT 24 |
Finished | Mar 31 12:47:52 PM PDT 24 |
Peak memory | 237804 kb |
Host | smart-8a3acef9-d4cd-44f4-a720-058c59182030 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465993271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_c trl_same_csr_outstanding.2465993271 |
Directory | /workspace/8.otp_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.2002612009 |
Short name | T1235 |
Test name | |
Test status | |
Simulation time | 159997160 ps |
CPU time | 5.9 seconds |
Started | Mar 31 12:47:53 PM PDT 24 |
Finished | Mar 31 12:47:59 PM PDT 24 |
Peak memory | 246976 kb |
Host | smart-91cfa718-cb13-4002-ab70-db50f5783d54 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002612009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.2002612009 |
Directory | /workspace/8.otp_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.2643811530 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 2501986613 ps |
CPU time | 11.62 seconds |
Started | Mar 31 12:47:51 PM PDT 24 |
Finished | Mar 31 12:48:03 PM PDT 24 |
Peak memory | 244520 kb |
Host | smart-88eeb664-7880-4214-80f3-4bfde247e495 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643811530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_in tg_err.2643811530 |
Directory | /workspace/8.otp_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.1067432660 |
Short name | T1271 |
Test name | |
Test status | |
Simulation time | 100598989 ps |
CPU time | 2.67 seconds |
Started | Mar 31 12:47:52 PM PDT 24 |
Finished | Mar 31 12:47:55 PM PDT 24 |
Peak memory | 239220 kb |
Host | smart-7f5afde9-627b-4db7-9b9c-06ae4cde86d4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067432660 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_mem_rw_with_rand_reset.1067432660 |
Directory | /workspace/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.4138149802 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 649278163 ps |
CPU time | 1.65 seconds |
Started | Mar 31 12:47:49 PM PDT 24 |
Finished | Mar 31 12:47:51 PM PDT 24 |
Peak memory | 238980 kb |
Host | smart-9db2345c-59ba-4757-9981-e54800dd10b0 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138149802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.4138149802 |
Directory | /workspace/9.otp_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.138654696 |
Short name | T1285 |
Test name | |
Test status | |
Simulation time | 70825126 ps |
CPU time | 1.42 seconds |
Started | Mar 31 12:47:51 PM PDT 24 |
Finished | Mar 31 12:47:53 PM PDT 24 |
Peak memory | 230632 kb |
Host | smart-2c0d34c2-dd39-4b15-a8b1-d67fae6a586f |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138654696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.138654696 |
Directory | /workspace/9.otp_ctrl_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.2585817102 |
Short name | T1217 |
Test name | |
Test status | |
Simulation time | 131293134 ps |
CPU time | 2.14 seconds |
Started | Mar 31 12:47:52 PM PDT 24 |
Finished | Mar 31 12:47:54 PM PDT 24 |
Peak memory | 238056 kb |
Host | smart-218b6ccb-ef3a-4fee-be7d-581f9792952a |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585817102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_c trl_same_csr_outstanding.2585817102 |
Directory | /workspace/9.otp_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.2579480779 |
Short name | T1293 |
Test name | |
Test status | |
Simulation time | 546887938 ps |
CPU time | 7 seconds |
Started | Mar 31 12:47:55 PM PDT 24 |
Finished | Mar 31 12:48:03 PM PDT 24 |
Peak memory | 246988 kb |
Host | smart-c7acb53f-df47-4c20-969a-d9163a2de08a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579480779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.2579480779 |
Directory | /workspace/9.otp_ctrl_tl_errors/latest |
Test location | /workspace/coverage/default/0.otp_ctrl_alert_test.4226194030 |
Short name | T1155 |
Test name | |
Test status | |
Simulation time | 1075844315 ps |
CPU time | 4.12 seconds |
Started | Mar 31 03:28:21 PM PDT 24 |
Finished | Mar 31 03:28:26 PM PDT 24 |
Peak memory | 240368 kb |
Host | smart-0bcc1e41-cfbe-444b-9b23-fbe7fd4091e5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226194030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.4226194030 |
Directory | /workspace/0.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/0.otp_ctrl_background_chks.4225883654 |
Short name | T945 |
Test name | |
Test status | |
Simulation time | 1150482402 ps |
CPU time | 6.92 seconds |
Started | Mar 31 03:28:16 PM PDT 24 |
Finished | Mar 31 03:28:23 PM PDT 24 |
Peak memory | 241888 kb |
Host | smart-85d9e1a5-2a3f-4e72-b11c-e205a69cb3dc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4225883654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.4225883654 |
Directory | /workspace/0.otp_ctrl_background_chks/latest |
Test location | /workspace/coverage/default/0.otp_ctrl_check_fail.2106933376 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 351434930 ps |
CPU time | 7.1 seconds |
Started | Mar 31 03:28:13 PM PDT 24 |
Finished | Mar 31 03:28:20 PM PDT 24 |
Peak memory | 241808 kb |
Host | smart-e0433192-fafa-4965-afec-8984922271aa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2106933376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.2106933376 |
Directory | /workspace/0.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/0.otp_ctrl_dai_errs.68418106 |
Short name | T580 |
Test name | |
Test status | |
Simulation time | 801973926 ps |
CPU time | 21.27 seconds |
Started | Mar 31 03:28:14 PM PDT 24 |
Finished | Mar 31 03:28:36 PM PDT 24 |
Peak memory | 242192 kb |
Host | smart-6d68071f-cd6d-4cc8-94b0-241c4dcc76fb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=68418106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.68418106 |
Directory | /workspace/0.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/0.otp_ctrl_dai_lock.1888014580 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 5157228288 ps |
CPU time | 10.32 seconds |
Started | Mar 31 03:28:15 PM PDT 24 |
Finished | Mar 31 03:28:26 PM PDT 24 |
Peak memory | 242120 kb |
Host | smart-52a12d01-e969-490f-b8f9-3d8ee3f069c9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1888014580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.1888014580 |
Directory | /workspace/0.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/0.otp_ctrl_init_fail.2731280429 |
Short name | T545 |
Test name | |
Test status | |
Simulation time | 258979129 ps |
CPU time | 5.44 seconds |
Started | Mar 31 03:28:16 PM PDT 24 |
Finished | Mar 31 03:28:22 PM PDT 24 |
Peak memory | 241936 kb |
Host | smart-2e88b8ec-ba11-44ba-a5dd-4ff287307142 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2731280429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.2731280429 |
Directory | /workspace/0.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/0.otp_ctrl_low_freq_read.2053601808 |
Short name | T461 |
Test name | |
Test status | |
Simulation time | 7519880227 ps |
CPU time | 17.99 seconds |
Started | Mar 31 03:28:17 PM PDT 24 |
Finished | Mar 31 03:28:35 PM PDT 24 |
Peak memory | 241372 kb |
Host | smart-31b76ccc-2ce3-440d-bb1d-96411cc45b07 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2053601808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.2053601808 |
Directory | /workspace/0.otp_ctrl_low_freq_read/latest |
Test location | /workspace/coverage/default/0.otp_ctrl_macro_errs.438463126 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 3251526243 ps |
CPU time | 20.26 seconds |
Started | Mar 31 03:28:21 PM PDT 24 |
Finished | Mar 31 03:28:41 PM PDT 24 |
Peak memory | 248720 kb |
Host | smart-3e8c63e6-b66c-44e4-8ac2-2f9e57b0afdd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=438463126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.438463126 |
Directory | /workspace/0.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/0.otp_ctrl_parallel_key_req.3739657940 |
Short name | T1016 |
Test name | |
Test status | |
Simulation time | 643246980 ps |
CPU time | 14.36 seconds |
Started | Mar 31 03:28:21 PM PDT 24 |
Finished | Mar 31 03:28:36 PM PDT 24 |
Peak memory | 241844 kb |
Host | smart-4db97a69-6669-4bef-8459-cda9fe83cbc2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3739657940 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.3739657940 |
Directory | /workspace/0.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/0.otp_ctrl_parallel_lc_esc.3657385305 |
Short name | T560 |
Test name | |
Test status | |
Simulation time | 176550599 ps |
CPU time | 4.87 seconds |
Started | Mar 31 03:28:14 PM PDT 24 |
Finished | Mar 31 03:28:19 PM PDT 24 |
Peak memory | 241832 kb |
Host | smart-d0de8457-6a5d-4223-ad34-183cbd6a47d6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3657385305 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.3657385305 |
Directory | /workspace/0.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/0.otp_ctrl_parallel_lc_req.3632459736 |
Short name | T780 |
Test name | |
Test status | |
Simulation time | 420156004 ps |
CPU time | 12.63 seconds |
Started | Mar 31 03:28:15 PM PDT 24 |
Finished | Mar 31 03:28:27 PM PDT 24 |
Peak memory | 241600 kb |
Host | smart-7c009a57-180a-4ca8-a15d-e1776fbf55fd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3632459736 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.3632459736 |
Directory | /workspace/0.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/0.otp_ctrl_partition_walk.1517132807 |
Short name | T942 |
Test name | |
Test status | |
Simulation time | 1170017302 ps |
CPU time | 17.82 seconds |
Started | Mar 31 03:28:15 PM PDT 24 |
Finished | Mar 31 03:28:32 PM PDT 24 |
Peak memory | 241248 kb |
Host | smart-e07b31b3-2a24-4d57-b92a-bbd22df0e241 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1517132807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.1517132807 |
Directory | /workspace/0.otp_ctrl_partition_walk/latest |
Test location | /workspace/coverage/default/0.otp_ctrl_regwen.2546864589 |
Short name | T730 |
Test name | |
Test status | |
Simulation time | 3292390795 ps |
CPU time | 9.86 seconds |
Started | Mar 31 03:28:20 PM PDT 24 |
Finished | Mar 31 03:28:30 PM PDT 24 |
Peak memory | 242160 kb |
Host | smart-de5febe9-09cd-44c5-aaac-bb9a65cb2dc5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2546864589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.2546864589 |
Directory | /workspace/0.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/0.otp_ctrl_sec_cm.2460225238 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 173113184157 ps |
CPU time | 249.71 seconds |
Started | Mar 31 03:28:19 PM PDT 24 |
Finished | Mar 31 03:32:29 PM PDT 24 |
Peak memory | 279608 kb |
Host | smart-456a042a-2c7b-4427-8ce7-f4adf3011cef |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460225238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.2460225238 |
Directory | /workspace/0.otp_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/0.otp_ctrl_smoke.1235792730 |
Short name | T1122 |
Test name | |
Test status | |
Simulation time | 434647611 ps |
CPU time | 9.1 seconds |
Started | Mar 31 03:28:08 PM PDT 24 |
Finished | Mar 31 03:28:18 PM PDT 24 |
Peak memory | 241636 kb |
Host | smart-64bfbff8-2fa5-4a74-8a46-11ed39178442 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1235792730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.1235792730 |
Directory | /workspace/0.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/0.otp_ctrl_stress_all.797617361 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 7697573499 ps |
CPU time | 155.88 seconds |
Started | Mar 31 03:28:21 PM PDT 24 |
Finished | Mar 31 03:30:57 PM PDT 24 |
Peak memory | 256916 kb |
Host | smart-57d123d9-41e8-4fff-b21f-0472fdefb05e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797617361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all.797617361 |
Directory | /workspace/0.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/0.otp_ctrl_stress_all_with_rand_reset.2615053354 |
Short name | T569 |
Test name | |
Test status | |
Simulation time | 91137850414 ps |
CPU time | 1716.04 seconds |
Started | Mar 31 03:28:20 PM PDT 24 |
Finished | Mar 31 03:56:56 PM PDT 24 |
Peak memory | 437684 kb |
Host | smart-5de99f66-ed3e-415f-b316-dbd6b128ac37 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615053354 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all_with_rand_reset.2615053354 |
Directory | /workspace/0.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/0.otp_ctrl_test_access.36704540 |
Short name | T712 |
Test name | |
Test status | |
Simulation time | 485142572 ps |
CPU time | 13.37 seconds |
Started | Mar 31 03:28:20 PM PDT 24 |
Finished | Mar 31 03:28:34 PM PDT 24 |
Peak memory | 242180 kb |
Host | smart-6b15ac10-afe2-47e4-8291-76db5df62bfe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=36704540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.36704540 |
Directory | /workspace/0.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/1.otp_ctrl_background_chks.4190142155 |
Short name | T903 |
Test name | |
Test status | |
Simulation time | 22111975918 ps |
CPU time | 27.18 seconds |
Started | Mar 31 03:28:20 PM PDT 24 |
Finished | Mar 31 03:28:48 PM PDT 24 |
Peak memory | 242896 kb |
Host | smart-aa40a7c7-1ab7-478d-b5d7-661158945451 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4190142155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.4190142155 |
Directory | /workspace/1.otp_ctrl_background_chks/latest |
Test location | /workspace/coverage/default/1.otp_ctrl_dai_errs.3924204149 |
Short name | T940 |
Test name | |
Test status | |
Simulation time | 602813019 ps |
CPU time | 18.19 seconds |
Started | Mar 31 03:28:29 PM PDT 24 |
Finished | Mar 31 03:28:47 PM PDT 24 |
Peak memory | 241680 kb |
Host | smart-b128ced7-aa98-4106-91a3-e4a5d92794e9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3924204149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.3924204149 |
Directory | /workspace/1.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/1.otp_ctrl_dai_lock.2762382615 |
Short name | T826 |
Test name | |
Test status | |
Simulation time | 952361569 ps |
CPU time | 9.14 seconds |
Started | Mar 31 03:28:27 PM PDT 24 |
Finished | Mar 31 03:28:36 PM PDT 24 |
Peak memory | 242024 kb |
Host | smart-e551d4dd-bc64-40dd-b2d7-90feedb75e9d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2762382615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.2762382615 |
Directory | /workspace/1.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/1.otp_ctrl_init_fail.1107684895 |
Short name | T675 |
Test name | |
Test status | |
Simulation time | 99505771 ps |
CPU time | 3.22 seconds |
Started | Mar 31 03:28:21 PM PDT 24 |
Finished | Mar 31 03:28:24 PM PDT 24 |
Peak memory | 241676 kb |
Host | smart-e3d9c6ca-54c0-423a-8336-a4076b85eda9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1107684895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.1107684895 |
Directory | /workspace/1.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/1.otp_ctrl_macro_errs.624820989 |
Short name | T1124 |
Test name | |
Test status | |
Simulation time | 1435928556 ps |
CPU time | 11.08 seconds |
Started | Mar 31 03:28:28 PM PDT 24 |
Finished | Mar 31 03:28:39 PM PDT 24 |
Peak memory | 242560 kb |
Host | smart-76cd1ef3-36bb-40b1-870e-5a58865a47ea |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=624820989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.624820989 |
Directory | /workspace/1.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/1.otp_ctrl_parallel_key_req.945730436 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 1170829784 ps |
CPU time | 30.88 seconds |
Started | Mar 31 03:28:25 PM PDT 24 |
Finished | Mar 31 03:28:56 PM PDT 24 |
Peak memory | 241780 kb |
Host | smart-63fbafa1-b35e-47b2-8e55-0addc7240640 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=945730436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.945730436 |
Directory | /workspace/1.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/1.otp_ctrl_parallel_lc_esc.2004188328 |
Short name | T551 |
Test name | |
Test status | |
Simulation time | 1479994809 ps |
CPU time | 3.33 seconds |
Started | Mar 31 03:28:20 PM PDT 24 |
Finished | Mar 31 03:28:24 PM PDT 24 |
Peak memory | 241768 kb |
Host | smart-ce594737-6cd0-44ea-b02d-64106b8334a9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2004188328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.2004188328 |
Directory | /workspace/1.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/1.otp_ctrl_parallel_lc_req.1411038419 |
Short name | T1085 |
Test name | |
Test status | |
Simulation time | 374582876 ps |
CPU time | 5.96 seconds |
Started | Mar 31 03:28:20 PM PDT 24 |
Finished | Mar 31 03:28:26 PM PDT 24 |
Peak memory | 241548 kb |
Host | smart-92bd69a0-44bc-4a0e-b9ef-75845d67bdf7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1411038419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.1411038419 |
Directory | /workspace/1.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/1.otp_ctrl_regwen.525034950 |
Short name | T598 |
Test name | |
Test status | |
Simulation time | 253949608 ps |
CPU time | 5.88 seconds |
Started | Mar 31 03:28:28 PM PDT 24 |
Finished | Mar 31 03:28:34 PM PDT 24 |
Peak memory | 242008 kb |
Host | smart-73881500-477a-4982-a19f-dc3440c56953 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=525034950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.525034950 |
Directory | /workspace/1.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/1.otp_ctrl_sec_cm.780565870 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 25058500821 ps |
CPU time | 192.3 seconds |
Started | Mar 31 03:28:29 PM PDT 24 |
Finished | Mar 31 03:31:41 PM PDT 24 |
Peak memory | 270420 kb |
Host | smart-0320f7de-0028-48ec-aed5-708765c9679f |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780565870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.780565870 |
Directory | /workspace/1.otp_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/1.otp_ctrl_smoke.4288705869 |
Short name | T928 |
Test name | |
Test status | |
Simulation time | 195487804 ps |
CPU time | 4.99 seconds |
Started | Mar 31 03:28:21 PM PDT 24 |
Finished | Mar 31 03:28:26 PM PDT 24 |
Peak memory | 241572 kb |
Host | smart-2383e94a-a58b-4a15-b61b-2726ec083ecd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4288705869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.4288705869 |
Directory | /workspace/1.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/1.otp_ctrl_stress_all.3069083312 |
Short name | T890 |
Test name | |
Test status | |
Simulation time | 489915029 ps |
CPU time | 8.39 seconds |
Started | Mar 31 03:28:26 PM PDT 24 |
Finished | Mar 31 03:28:34 PM PDT 24 |
Peak memory | 241780 kb |
Host | smart-4b913f0b-a635-4a06-b31a-bf606586b449 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069083312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all. 3069083312 |
Directory | /workspace/1.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/1.otp_ctrl_test_access.2618405453 |
Short name | T682 |
Test name | |
Test status | |
Simulation time | 2643053344 ps |
CPU time | 6.56 seconds |
Started | Mar 31 03:28:28 PM PDT 24 |
Finished | Mar 31 03:28:35 PM PDT 24 |
Peak memory | 241724 kb |
Host | smart-acba6356-d65d-44c9-9229-865ad2d2a11f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2618405453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.2618405453 |
Directory | /workspace/1.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/10.otp_ctrl_alert_test.1174273401 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 116865753 ps |
CPU time | 2.01 seconds |
Started | Mar 31 03:29:19 PM PDT 24 |
Finished | Mar 31 03:29:21 PM PDT 24 |
Peak memory | 240220 kb |
Host | smart-2b139d26-4e90-4fe8-b559-ec522bd046a1 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174273401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.1174273401 |
Directory | /workspace/10.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/10.otp_ctrl_dai_errs.3188807808 |
Short name | T1028 |
Test name | |
Test status | |
Simulation time | 3255238665 ps |
CPU time | 22.53 seconds |
Started | Mar 31 03:29:24 PM PDT 24 |
Finished | Mar 31 03:29:48 PM PDT 24 |
Peak memory | 241676 kb |
Host | smart-b14a4ea3-2d73-4a59-8624-52b7fd199c44 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3188807808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.3188807808 |
Directory | /workspace/10.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/10.otp_ctrl_dai_lock.1615919436 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 640529231 ps |
CPU time | 8.7 seconds |
Started | Mar 31 03:29:23 PM PDT 24 |
Finished | Mar 31 03:29:32 PM PDT 24 |
Peak memory | 242048 kb |
Host | smart-47dd8fcb-db93-47e5-8d18-55955491f4d0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1615919436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.1615919436 |
Directory | /workspace/10.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/10.otp_ctrl_init_fail.253788646 |
Short name | T548 |
Test name | |
Test status | |
Simulation time | 1419400881 ps |
CPU time | 5.19 seconds |
Started | Mar 31 03:29:20 PM PDT 24 |
Finished | Mar 31 03:29:25 PM PDT 24 |
Peak memory | 241740 kb |
Host | smart-4249ec55-afaf-43b4-94eb-fde4100eac7e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=253788646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.253788646 |
Directory | /workspace/10.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/10.otp_ctrl_parallel_key_req.1869285725 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 1114768925 ps |
CPU time | 15.41 seconds |
Started | Mar 31 03:29:21 PM PDT 24 |
Finished | Mar 31 03:29:36 PM PDT 24 |
Peak memory | 241920 kb |
Host | smart-90e387cf-b847-4370-93b8-b61af90a8ad9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1869285725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.1869285725 |
Directory | /workspace/10.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/10.otp_ctrl_parallel_lc_esc.3770582556 |
Short name | T781 |
Test name | |
Test status | |
Simulation time | 529288868 ps |
CPU time | 13.72 seconds |
Started | Mar 31 03:29:21 PM PDT 24 |
Finished | Mar 31 03:29:35 PM PDT 24 |
Peak memory | 241564 kb |
Host | smart-2c281c9a-69f1-430d-9c9e-1b7ded98c52a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3770582556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.3770582556 |
Directory | /workspace/10.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/10.otp_ctrl_parallel_lc_req.3172590811 |
Short name | T932 |
Test name | |
Test status | |
Simulation time | 1412223127 ps |
CPU time | 24 seconds |
Started | Mar 31 03:29:23 PM PDT 24 |
Finished | Mar 31 03:29:48 PM PDT 24 |
Peak memory | 241704 kb |
Host | smart-3fc364a3-ca2f-40dd-8f2f-677281300ec5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3172590811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.3172590811 |
Directory | /workspace/10.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/10.otp_ctrl_regwen.2741501585 |
Short name | T570 |
Test name | |
Test status | |
Simulation time | 1044239063 ps |
CPU time | 7.68 seconds |
Started | Mar 31 03:29:27 PM PDT 24 |
Finished | Mar 31 03:29:35 PM PDT 24 |
Peak memory | 242084 kb |
Host | smart-b4f71e40-1d5e-43cb-8b70-78ba31aa384d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2741501585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.2741501585 |
Directory | /workspace/10.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/10.otp_ctrl_smoke.2463605871 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 287570614 ps |
CPU time | 8.02 seconds |
Started | Mar 31 03:29:20 PM PDT 24 |
Finished | Mar 31 03:29:28 PM PDT 24 |
Peak memory | 241816 kb |
Host | smart-7d25e809-d369-44ff-8ca9-aebda78527ad |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2463605871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.2463605871 |
Directory | /workspace/10.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/10.otp_ctrl_stress_all.1292259742 |
Short name | T1005 |
Test name | |
Test status | |
Simulation time | 289499626 ps |
CPU time | 5.97 seconds |
Started | Mar 31 03:29:21 PM PDT 24 |
Finished | Mar 31 03:29:27 PM PDT 24 |
Peak memory | 241700 kb |
Host | smart-126d66a5-ca30-4c3b-8f1d-5189668b5ecc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292259742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all .1292259742 |
Directory | /workspace/10.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/10.otp_ctrl_stress_all_with_rand_reset.2238084917 |
Short name | T739 |
Test name | |
Test status | |
Simulation time | 46223083740 ps |
CPU time | 412.46 seconds |
Started | Mar 31 03:29:21 PM PDT 24 |
Finished | Mar 31 03:36:14 PM PDT 24 |
Peak memory | 256860 kb |
Host | smart-4b6a5682-050b-4195-aac2-91a1b41fd72f |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238084917 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all_with_rand_reset.2238084917 |
Directory | /workspace/10.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/10.otp_ctrl_test_access.3840562789 |
Short name | T849 |
Test name | |
Test status | |
Simulation time | 196734678 ps |
CPU time | 4.28 seconds |
Started | Mar 31 03:29:20 PM PDT 24 |
Finished | Mar 31 03:29:24 PM PDT 24 |
Peak memory | 242000 kb |
Host | smart-2dda9462-aeee-4ef3-abd4-cd1259bbf850 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3840562789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.3840562789 |
Directory | /workspace/10.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/100.otp_ctrl_init_fail.2516602089 |
Short name | T482 |
Test name | |
Test status | |
Simulation time | 133588847 ps |
CPU time | 3.61 seconds |
Started | Mar 31 03:32:50 PM PDT 24 |
Finished | Mar 31 03:32:54 PM PDT 24 |
Peak memory | 241956 kb |
Host | smart-879c7704-663f-411a-978c-2952830884cf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2516602089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.2516602089 |
Directory | /workspace/100.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/100.otp_ctrl_parallel_lc_esc.2415566007 |
Short name | T516 |
Test name | |
Test status | |
Simulation time | 597162285 ps |
CPU time | 7.72 seconds |
Started | Mar 31 03:32:50 PM PDT 24 |
Finished | Mar 31 03:32:58 PM PDT 24 |
Peak memory | 241620 kb |
Host | smart-48ce3547-b029-4e8c-b9e3-e2861db80386 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2415566007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.2415566007 |
Directory | /workspace/100.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/101.otp_ctrl_init_fail.1492611460 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 530770241 ps |
CPU time | 4.17 seconds |
Started | Mar 31 03:32:51 PM PDT 24 |
Finished | Mar 31 03:32:55 PM PDT 24 |
Peak memory | 241684 kb |
Host | smart-e531eea8-b9ff-4a2d-9c37-87e802560fc1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1492611460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.1492611460 |
Directory | /workspace/101.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/101.otp_ctrl_parallel_lc_esc.946460606 |
Short name | T1047 |
Test name | |
Test status | |
Simulation time | 269364312 ps |
CPU time | 7.04 seconds |
Started | Mar 31 03:32:55 PM PDT 24 |
Finished | Mar 31 03:33:02 PM PDT 24 |
Peak memory | 241508 kb |
Host | smart-6c84cebc-7d2b-46b5-a38e-f6203163fb50 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=946460606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.946460606 |
Directory | /workspace/101.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/102.otp_ctrl_parallel_lc_esc.242187975 |
Short name | T847 |
Test name | |
Test status | |
Simulation time | 2706184632 ps |
CPU time | 10.18 seconds |
Started | Mar 31 03:32:53 PM PDT 24 |
Finished | Mar 31 03:33:04 PM PDT 24 |
Peak memory | 242060 kb |
Host | smart-b2103920-87a8-4323-b659-4f0d33c56a71 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=242187975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.242187975 |
Directory | /workspace/102.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/103.otp_ctrl_init_fail.2792682169 |
Short name | T1026 |
Test name | |
Test status | |
Simulation time | 135012869 ps |
CPU time | 3.55 seconds |
Started | Mar 31 03:32:53 PM PDT 24 |
Finished | Mar 31 03:32:57 PM PDT 24 |
Peak memory | 241672 kb |
Host | smart-32ba084e-3a46-4167-a86d-35df96aed33f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2792682169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.2792682169 |
Directory | /workspace/103.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/103.otp_ctrl_parallel_lc_esc.1087563672 |
Short name | T523 |
Test name | |
Test status | |
Simulation time | 819727317 ps |
CPU time | 13.47 seconds |
Started | Mar 31 03:33:02 PM PDT 24 |
Finished | Mar 31 03:33:15 PM PDT 24 |
Peak memory | 241596 kb |
Host | smart-ff2006fc-add4-4c40-af13-83b9a5427cce |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1087563672 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.1087563672 |
Directory | /workspace/103.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/104.otp_ctrl_init_fail.1467302058 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 111725625 ps |
CPU time | 4.34 seconds |
Started | Mar 31 03:32:58 PM PDT 24 |
Finished | Mar 31 03:33:03 PM PDT 24 |
Peak memory | 241584 kb |
Host | smart-3f6e6267-e65b-44cd-bcbd-523f688b558d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1467302058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.1467302058 |
Directory | /workspace/104.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/104.otp_ctrl_parallel_lc_esc.1726894498 |
Short name | T535 |
Test name | |
Test status | |
Simulation time | 6940817792 ps |
CPU time | 18.98 seconds |
Started | Mar 31 03:32:59 PM PDT 24 |
Finished | Mar 31 03:33:18 PM PDT 24 |
Peak memory | 242120 kb |
Host | smart-99be7933-779c-474a-a109-b07f04e9f381 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1726894498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.1726894498 |
Directory | /workspace/104.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/105.otp_ctrl_init_fail.4151202635 |
Short name | T1158 |
Test name | |
Test status | |
Simulation time | 155618784 ps |
CPU time | 3.92 seconds |
Started | Mar 31 03:33:00 PM PDT 24 |
Finished | Mar 31 03:33:04 PM PDT 24 |
Peak memory | 241612 kb |
Host | smart-57b03c4b-42f3-498b-b166-85abbb1daeb2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4151202635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.4151202635 |
Directory | /workspace/105.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/105.otp_ctrl_parallel_lc_esc.4290029831 |
Short name | T533 |
Test name | |
Test status | |
Simulation time | 213872008 ps |
CPU time | 7.89 seconds |
Started | Mar 31 03:33:06 PM PDT 24 |
Finished | Mar 31 03:33:14 PM PDT 24 |
Peak memory | 241704 kb |
Host | smart-e44f30b7-0c76-4776-8367-689f126d1fb5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4290029831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.4290029831 |
Directory | /workspace/105.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/106.otp_ctrl_init_fail.2618487405 |
Short name | T489 |
Test name | |
Test status | |
Simulation time | 2119887798 ps |
CPU time | 5.58 seconds |
Started | Mar 31 03:32:57 PM PDT 24 |
Finished | Mar 31 03:33:03 PM PDT 24 |
Peak memory | 241796 kb |
Host | smart-fa0d706d-a9f6-4896-bbc1-5a21356df92b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2618487405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.2618487405 |
Directory | /workspace/106.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/106.otp_ctrl_parallel_lc_esc.51553255 |
Short name | T1022 |
Test name | |
Test status | |
Simulation time | 477196807 ps |
CPU time | 4.55 seconds |
Started | Mar 31 03:33:07 PM PDT 24 |
Finished | Mar 31 03:33:11 PM PDT 24 |
Peak memory | 241688 kb |
Host | smart-36bd9d88-d131-4b21-851b-63c751ac30fb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=51553255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.51553255 |
Directory | /workspace/106.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/107.otp_ctrl_init_fail.4005667826 |
Short name | T591 |
Test name | |
Test status | |
Simulation time | 2185105908 ps |
CPU time | 5.87 seconds |
Started | Mar 31 03:33:00 PM PDT 24 |
Finished | Mar 31 03:33:06 PM PDT 24 |
Peak memory | 242164 kb |
Host | smart-9f58a9f0-feaf-450c-b2a8-5c92074b1c31 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4005667826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.4005667826 |
Directory | /workspace/107.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/107.otp_ctrl_parallel_lc_esc.566565678 |
Short name | T620 |
Test name | |
Test status | |
Simulation time | 473690309 ps |
CPU time | 6.07 seconds |
Started | Mar 31 03:32:59 PM PDT 24 |
Finished | Mar 31 03:33:05 PM PDT 24 |
Peak memory | 241836 kb |
Host | smart-a8f2b2f7-983c-467e-bb9b-df68e2284be0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=566565678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.566565678 |
Directory | /workspace/107.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/108.otp_ctrl_init_fail.3250483815 |
Short name | T933 |
Test name | |
Test status | |
Simulation time | 115910689 ps |
CPU time | 4.43 seconds |
Started | Mar 31 03:32:59 PM PDT 24 |
Finished | Mar 31 03:33:04 PM PDT 24 |
Peak memory | 241732 kb |
Host | smart-ffb05faa-f709-44d1-a87a-c6ef15cf9b1c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3250483815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.3250483815 |
Directory | /workspace/108.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/109.otp_ctrl_init_fail.3217355953 |
Short name | T563 |
Test name | |
Test status | |
Simulation time | 414247899 ps |
CPU time | 4.61 seconds |
Started | Mar 31 03:33:02 PM PDT 24 |
Finished | Mar 31 03:33:06 PM PDT 24 |
Peak memory | 241780 kb |
Host | smart-bf9f8cc0-42f1-4505-8468-17d6d8682949 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3217355953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.3217355953 |
Directory | /workspace/109.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/109.otp_ctrl_parallel_lc_esc.843871396 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 277981031 ps |
CPU time | 10.67 seconds |
Started | Mar 31 03:33:02 PM PDT 24 |
Finished | Mar 31 03:33:13 PM PDT 24 |
Peak memory | 241656 kb |
Host | smart-27840309-5092-4970-b429-7a3389f8c525 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=843871396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.843871396 |
Directory | /workspace/109.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/11.otp_ctrl_alert_test.3720195799 |
Short name | T451 |
Test name | |
Test status | |
Simulation time | 78954293 ps |
CPU time | 1.75 seconds |
Started | Mar 31 03:29:25 PM PDT 24 |
Finished | Mar 31 03:29:27 PM PDT 24 |
Peak memory | 240052 kb |
Host | smart-f35c68ba-ddcc-44dd-b500-abf96d9729d5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720195799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.3720195799 |
Directory | /workspace/11.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/11.otp_ctrl_check_fail.1669257922 |
Short name | T595 |
Test name | |
Test status | |
Simulation time | 926187262 ps |
CPU time | 18.54 seconds |
Started | Mar 31 03:29:24 PM PDT 24 |
Finished | Mar 31 03:29:43 PM PDT 24 |
Peak memory | 242284 kb |
Host | smart-c06742f1-dcf6-4c5e-98fc-19e4aecb51de |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1669257922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.1669257922 |
Directory | /workspace/11.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/11.otp_ctrl_dai_errs.3759497090 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 599276265 ps |
CPU time | 9.82 seconds |
Started | Mar 31 03:29:23 PM PDT 24 |
Finished | Mar 31 03:29:33 PM PDT 24 |
Peak memory | 241796 kb |
Host | smart-28657b07-7ebf-4735-aa50-8e88ca4cbd53 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3759497090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.3759497090 |
Directory | /workspace/11.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/11.otp_ctrl_dai_lock.4149066763 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 431255479 ps |
CPU time | 10.39 seconds |
Started | Mar 31 03:29:27 PM PDT 24 |
Finished | Mar 31 03:29:37 PM PDT 24 |
Peak memory | 241940 kb |
Host | smart-74f7b759-194f-4a2d-96d7-47e3532fcff3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4149066763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.4149066763 |
Directory | /workspace/11.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/11.otp_ctrl_init_fail.741040092 |
Short name | T1032 |
Test name | |
Test status | |
Simulation time | 146601562 ps |
CPU time | 3.86 seconds |
Started | Mar 31 03:29:25 PM PDT 24 |
Finished | Mar 31 03:29:29 PM PDT 24 |
Peak memory | 241664 kb |
Host | smart-8feee713-85c5-427a-9c95-879143ed7d4e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=741040092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.741040092 |
Directory | /workspace/11.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/11.otp_ctrl_macro_errs.2449312933 |
Short name | T1194 |
Test name | |
Test status | |
Simulation time | 1060190986 ps |
CPU time | 31.6 seconds |
Started | Mar 31 03:29:25 PM PDT 24 |
Finished | Mar 31 03:29:57 PM PDT 24 |
Peak memory | 242192 kb |
Host | smart-d4ba6faa-2f05-47ca-83d5-4e6eb810dc29 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2449312933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.2449312933 |
Directory | /workspace/11.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/11.otp_ctrl_parallel_key_req.2547962394 |
Short name | T819 |
Test name | |
Test status | |
Simulation time | 635489048 ps |
CPU time | 16.71 seconds |
Started | Mar 31 03:29:22 PM PDT 24 |
Finished | Mar 31 03:29:39 PM PDT 24 |
Peak memory | 242376 kb |
Host | smart-bcba3e79-ec67-4088-a9fb-f57011620900 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2547962394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.2547962394 |
Directory | /workspace/11.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/11.otp_ctrl_parallel_lc_esc.2516536424 |
Short name | T1068 |
Test name | |
Test status | |
Simulation time | 199349064 ps |
CPU time | 4.5 seconds |
Started | Mar 31 03:29:24 PM PDT 24 |
Finished | Mar 31 03:29:30 PM PDT 24 |
Peak memory | 242024 kb |
Host | smart-fd924d65-7f86-4946-a59a-38210cae91c0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2516536424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.2516536424 |
Directory | /workspace/11.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/11.otp_ctrl_parallel_lc_req.607393908 |
Short name | T652 |
Test name | |
Test status | |
Simulation time | 757815021 ps |
CPU time | 22.86 seconds |
Started | Mar 31 03:29:24 PM PDT 24 |
Finished | Mar 31 03:29:47 PM PDT 24 |
Peak memory | 241600 kb |
Host | smart-72f91943-3c60-4953-a0d6-49df86a69b99 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=607393908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.607393908 |
Directory | /workspace/11.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/11.otp_ctrl_regwen.1268582869 |
Short name | T1031 |
Test name | |
Test status | |
Simulation time | 280512509 ps |
CPU time | 6.27 seconds |
Started | Mar 31 03:29:28 PM PDT 24 |
Finished | Mar 31 03:29:34 PM PDT 24 |
Peak memory | 242012 kb |
Host | smart-6f1f637b-979e-4d97-b3e3-531d9c824898 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1268582869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.1268582869 |
Directory | /workspace/11.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/11.otp_ctrl_smoke.1972312583 |
Short name | T820 |
Test name | |
Test status | |
Simulation time | 320246014 ps |
CPU time | 3.34 seconds |
Started | Mar 31 03:29:27 PM PDT 24 |
Finished | Mar 31 03:29:31 PM PDT 24 |
Peak memory | 241820 kb |
Host | smart-95031fe5-3503-42b8-846b-750ec6f4871c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1972312583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.1972312583 |
Directory | /workspace/11.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/11.otp_ctrl_stress_all.890986839 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 38119281157 ps |
CPU time | 196.75 seconds |
Started | Mar 31 03:29:28 PM PDT 24 |
Finished | Mar 31 03:32:45 PM PDT 24 |
Peak memory | 256668 kb |
Host | smart-84d487aa-9160-4430-a4fe-9984b20343f8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890986839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all. 890986839 |
Directory | /workspace/11.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/11.otp_ctrl_test_access.1319995461 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 8454528373 ps |
CPU time | 17.24 seconds |
Started | Mar 31 03:29:28 PM PDT 24 |
Finished | Mar 31 03:29:45 PM PDT 24 |
Peak memory | 242644 kb |
Host | smart-a150979b-9419-4ad9-903b-aebf6f261524 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1319995461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.1319995461 |
Directory | /workspace/11.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/110.otp_ctrl_init_fail.3651892210 |
Short name | T705 |
Test name | |
Test status | |
Simulation time | 251658090 ps |
CPU time | 3.71 seconds |
Started | Mar 31 03:32:58 PM PDT 24 |
Finished | Mar 31 03:33:02 PM PDT 24 |
Peak memory | 241680 kb |
Host | smart-20529ac1-047a-48a1-aae3-c32171a1ccc7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3651892210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.3651892210 |
Directory | /workspace/110.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/110.otp_ctrl_parallel_lc_esc.786305866 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 483848663 ps |
CPU time | 13.81 seconds |
Started | Mar 31 03:32:59 PM PDT 24 |
Finished | Mar 31 03:33:13 PM PDT 24 |
Peak memory | 242068 kb |
Host | smart-882b1734-6453-4c29-b91d-743c38d032ed |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=786305866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.786305866 |
Directory | /workspace/110.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/111.otp_ctrl_init_fail.3192690458 |
Short name | T578 |
Test name | |
Test status | |
Simulation time | 137416563 ps |
CPU time | 4.45 seconds |
Started | Mar 31 03:33:03 PM PDT 24 |
Finished | Mar 31 03:33:08 PM PDT 24 |
Peak memory | 242056 kb |
Host | smart-b7ef1d32-24f8-46f3-ac7d-9b0f340dac62 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3192690458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.3192690458 |
Directory | /workspace/111.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/111.otp_ctrl_parallel_lc_esc.3877856335 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 3976348423 ps |
CPU time | 7.86 seconds |
Started | Mar 31 03:32:57 PM PDT 24 |
Finished | Mar 31 03:33:05 PM PDT 24 |
Peak memory | 241612 kb |
Host | smart-6354a8ea-8c5e-43c9-80b9-d3c75734663d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3877856335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.3877856335 |
Directory | /workspace/111.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/112.otp_ctrl_init_fail.3833899456 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 476340534 ps |
CPU time | 4.77 seconds |
Started | Mar 31 03:33:03 PM PDT 24 |
Finished | Mar 31 03:33:08 PM PDT 24 |
Peak memory | 241732 kb |
Host | smart-4119e2bc-6ecd-40a3-9230-0ebd8238ddeb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3833899456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.3833899456 |
Directory | /workspace/112.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/112.otp_ctrl_parallel_lc_esc.3958582849 |
Short name | T800 |
Test name | |
Test status | |
Simulation time | 285979279 ps |
CPU time | 15.71 seconds |
Started | Mar 31 03:32:58 PM PDT 24 |
Finished | Mar 31 03:33:14 PM PDT 24 |
Peak memory | 241792 kb |
Host | smart-76215718-7748-4c56-a2c2-e21e9d1d1262 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3958582849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.3958582849 |
Directory | /workspace/112.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/113.otp_ctrl_parallel_lc_esc.3529878593 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 1190360849 ps |
CPU time | 9.32 seconds |
Started | Mar 31 03:32:59 PM PDT 24 |
Finished | Mar 31 03:33:09 PM PDT 24 |
Peak memory | 242084 kb |
Host | smart-691911b9-64f1-4ae7-85c9-ada9ccba1614 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3529878593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.3529878593 |
Directory | /workspace/113.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/114.otp_ctrl_init_fail.3634963259 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 148704409 ps |
CPU time | 4.33 seconds |
Started | Mar 31 03:33:03 PM PDT 24 |
Finished | Mar 31 03:33:07 PM PDT 24 |
Peak memory | 241784 kb |
Host | smart-e2d81025-c1b4-4f7f-836f-a412d4f69601 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3634963259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.3634963259 |
Directory | /workspace/114.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/114.otp_ctrl_parallel_lc_esc.2852889450 |
Short name | T648 |
Test name | |
Test status | |
Simulation time | 186898341 ps |
CPU time | 4.49 seconds |
Started | Mar 31 03:32:57 PM PDT 24 |
Finished | Mar 31 03:33:02 PM PDT 24 |
Peak memory | 241488 kb |
Host | smart-8af95002-4d7c-42bb-9479-930d44b9dbee |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2852889450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.2852889450 |
Directory | /workspace/114.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/115.otp_ctrl_init_fail.2822393786 |
Short name | T555 |
Test name | |
Test status | |
Simulation time | 2362992077 ps |
CPU time | 5.27 seconds |
Started | Mar 31 03:33:01 PM PDT 24 |
Finished | Mar 31 03:33:07 PM PDT 24 |
Peak memory | 242008 kb |
Host | smart-df4c8582-cd8a-401b-9536-fe14eae47de1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2822393786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.2822393786 |
Directory | /workspace/115.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/115.otp_ctrl_parallel_lc_esc.1622553409 |
Short name | T1100 |
Test name | |
Test status | |
Simulation time | 471113574 ps |
CPU time | 12.19 seconds |
Started | Mar 31 03:32:57 PM PDT 24 |
Finished | Mar 31 03:33:09 PM PDT 24 |
Peak memory | 241832 kb |
Host | smart-9cd69ca6-edbb-43c8-8b4e-7070a8738d23 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1622553409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.1622553409 |
Directory | /workspace/115.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/116.otp_ctrl_parallel_lc_esc.1799642844 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 1467501385 ps |
CPU time | 3.48 seconds |
Started | Mar 31 03:33:01 PM PDT 24 |
Finished | Mar 31 03:33:04 PM PDT 24 |
Peak memory | 241512 kb |
Host | smart-1b5eddb1-d24d-422c-9da7-491e08d61a91 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1799642844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.1799642844 |
Directory | /workspace/116.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/117.otp_ctrl_init_fail.1259197646 |
Short name | T1147 |
Test name | |
Test status | |
Simulation time | 608555340 ps |
CPU time | 4.85 seconds |
Started | Mar 31 03:33:01 PM PDT 24 |
Finished | Mar 31 03:33:06 PM PDT 24 |
Peak memory | 241732 kb |
Host | smart-7275b6da-9dae-4d86-ba43-b09190687944 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1259197646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.1259197646 |
Directory | /workspace/117.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/117.otp_ctrl_parallel_lc_esc.2220366911 |
Short name | T638 |
Test name | |
Test status | |
Simulation time | 6775052907 ps |
CPU time | 19.24 seconds |
Started | Mar 31 03:32:58 PM PDT 24 |
Finished | Mar 31 03:33:18 PM PDT 24 |
Peak memory | 241728 kb |
Host | smart-eaf2d58b-0ca6-4bb7-8337-d372f214f313 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2220366911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.2220366911 |
Directory | /workspace/117.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/118.otp_ctrl_init_fail.2051389790 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 2499336461 ps |
CPU time | 5.13 seconds |
Started | Mar 31 03:32:59 PM PDT 24 |
Finished | Mar 31 03:33:04 PM PDT 24 |
Peak memory | 242024 kb |
Host | smart-4402cfd5-6eb0-46ff-92c7-21af2f5d2174 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2051389790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.2051389790 |
Directory | /workspace/118.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/118.otp_ctrl_parallel_lc_esc.3909755264 |
Short name | T869 |
Test name | |
Test status | |
Simulation time | 1655601967 ps |
CPU time | 18.43 seconds |
Started | Mar 31 03:33:00 PM PDT 24 |
Finished | Mar 31 03:33:18 PM PDT 24 |
Peak memory | 241992 kb |
Host | smart-869f8e24-e3fd-4461-9a21-bbb36c8b16f9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3909755264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.3909755264 |
Directory | /workspace/118.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/119.otp_ctrl_init_fail.1570957490 |
Short name | T778 |
Test name | |
Test status | |
Simulation time | 2941256867 ps |
CPU time | 7.99 seconds |
Started | Mar 31 03:33:00 PM PDT 24 |
Finished | Mar 31 03:33:08 PM PDT 24 |
Peak memory | 242084 kb |
Host | smart-c1dfb366-04b2-4dd7-97c0-083fe5d5436b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1570957490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.1570957490 |
Directory | /workspace/119.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/119.otp_ctrl_parallel_lc_esc.2310642797 |
Short name | T1076 |
Test name | |
Test status | |
Simulation time | 196171195 ps |
CPU time | 5.74 seconds |
Started | Mar 31 03:33:01 PM PDT 24 |
Finished | Mar 31 03:33:07 PM PDT 24 |
Peak memory | 241636 kb |
Host | smart-b573490e-ea94-40ed-b336-592b5552ccc6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2310642797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.2310642797 |
Directory | /workspace/119.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/12.otp_ctrl_alert_test.1822858297 |
Short name | T596 |
Test name | |
Test status | |
Simulation time | 65749172 ps |
CPU time | 1.69 seconds |
Started | Mar 31 03:29:38 PM PDT 24 |
Finished | Mar 31 03:29:40 PM PDT 24 |
Peak memory | 239884 kb |
Host | smart-34b14a6d-35c3-43da-bd45-ea411dcf47fb |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822858297 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.1822858297 |
Directory | /workspace/12.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/12.otp_ctrl_check_fail.3440242408 |
Short name | T1187 |
Test name | |
Test status | |
Simulation time | 1298533338 ps |
CPU time | 22.1 seconds |
Started | Mar 31 03:29:33 PM PDT 24 |
Finished | Mar 31 03:29:55 PM PDT 24 |
Peak memory | 241764 kb |
Host | smart-dc15c2df-92a4-451e-9581-637bd626eabe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3440242408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.3440242408 |
Directory | /workspace/12.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/12.otp_ctrl_dai_errs.2747954082 |
Short name | T830 |
Test name | |
Test status | |
Simulation time | 1295242747 ps |
CPU time | 20.8 seconds |
Started | Mar 31 03:29:33 PM PDT 24 |
Finished | Mar 31 03:29:54 PM PDT 24 |
Peak memory | 241520 kb |
Host | smart-bddfac91-89b3-41fc-9f74-9d43a92942d0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2747954082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.2747954082 |
Directory | /workspace/12.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/12.otp_ctrl_dai_lock.1306047131 |
Short name | T834 |
Test name | |
Test status | |
Simulation time | 12782035097 ps |
CPU time | 26.07 seconds |
Started | Mar 31 03:29:27 PM PDT 24 |
Finished | Mar 31 03:29:53 PM PDT 24 |
Peak memory | 243008 kb |
Host | smart-829952c5-f70d-45ba-a517-797d655edbf5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1306047131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.1306047131 |
Directory | /workspace/12.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/12.otp_ctrl_init_fail.3517671338 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 153650121 ps |
CPU time | 4.09 seconds |
Started | Mar 31 03:29:29 PM PDT 24 |
Finished | Mar 31 03:29:33 PM PDT 24 |
Peak memory | 241732 kb |
Host | smart-98e02d34-29b1-4b72-b00c-faa46d7e8cfd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3517671338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.3517671338 |
Directory | /workspace/12.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/12.otp_ctrl_macro_errs.2779748056 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 597242232 ps |
CPU time | 12.63 seconds |
Started | Mar 31 03:29:31 PM PDT 24 |
Finished | Mar 31 03:29:43 PM PDT 24 |
Peak memory | 243228 kb |
Host | smart-678747ba-c229-4d7b-b4df-24249a484dee |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2779748056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.2779748056 |
Directory | /workspace/12.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/12.otp_ctrl_parallel_key_req.3629274659 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 806722512 ps |
CPU time | 32.85 seconds |
Started | Mar 31 03:29:35 PM PDT 24 |
Finished | Mar 31 03:30:08 PM PDT 24 |
Peak memory | 242032 kb |
Host | smart-9d8607fc-a5b1-4d2d-aad9-0eabbe924b6d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3629274659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.3629274659 |
Directory | /workspace/12.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/12.otp_ctrl_parallel_lc_esc.1757928540 |
Short name | T1074 |
Test name | |
Test status | |
Simulation time | 1467695776 ps |
CPU time | 21.47 seconds |
Started | Mar 31 03:29:30 PM PDT 24 |
Finished | Mar 31 03:29:52 PM PDT 24 |
Peak memory | 241672 kb |
Host | smart-252ce62b-cb26-40fc-bfe4-a77a30d1e40e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1757928540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.1757928540 |
Directory | /workspace/12.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/12.otp_ctrl_parallel_lc_req.4005671208 |
Short name | T541 |
Test name | |
Test status | |
Simulation time | 453171525 ps |
CPU time | 14.67 seconds |
Started | Mar 31 03:29:31 PM PDT 24 |
Finished | Mar 31 03:29:46 PM PDT 24 |
Peak memory | 241652 kb |
Host | smart-b17b3566-9cdc-4e48-b028-4c3944248a63 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4005671208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.4005671208 |
Directory | /workspace/12.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/12.otp_ctrl_regwen.2334598970 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 550492818 ps |
CPU time | 10.84 seconds |
Started | Mar 31 03:29:37 PM PDT 24 |
Finished | Mar 31 03:29:48 PM PDT 24 |
Peak memory | 242020 kb |
Host | smart-621acde7-0a38-4f89-a7fd-653a0c57e714 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2334598970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.2334598970 |
Directory | /workspace/12.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/12.otp_ctrl_smoke.1046768989 |
Short name | T1001 |
Test name | |
Test status | |
Simulation time | 354112572 ps |
CPU time | 4.2 seconds |
Started | Mar 31 03:29:31 PM PDT 24 |
Finished | Mar 31 03:29:36 PM PDT 24 |
Peak memory | 241828 kb |
Host | smart-b49d8ee5-611d-451e-8840-f911c1e24685 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1046768989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.1046768989 |
Directory | /workspace/12.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/12.otp_ctrl_stress_all.1361857449 |
Short name | T626 |
Test name | |
Test status | |
Simulation time | 26023228627 ps |
CPU time | 222.99 seconds |
Started | Mar 31 03:29:36 PM PDT 24 |
Finished | Mar 31 03:33:20 PM PDT 24 |
Peak memory | 273296 kb |
Host | smart-0649966d-346a-4b8f-8bd2-ed06fbc26b0e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361857449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all .1361857449 |
Directory | /workspace/12.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/12.otp_ctrl_stress_all_with_rand_reset.4241076385 |
Short name | T744 |
Test name | |
Test status | |
Simulation time | 28925750926 ps |
CPU time | 718.86 seconds |
Started | Mar 31 03:29:36 PM PDT 24 |
Finished | Mar 31 03:41:35 PM PDT 24 |
Peak memory | 272336 kb |
Host | smart-0a78362a-8c8e-41af-a4cb-4eb2497e19da |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241076385 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all_with_rand_reset.4241076385 |
Directory | /workspace/12.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/12.otp_ctrl_test_access.3143871684 |
Short name | T816 |
Test name | |
Test status | |
Simulation time | 2309567276 ps |
CPU time | 6.38 seconds |
Started | Mar 31 03:29:35 PM PDT 24 |
Finished | Mar 31 03:29:42 PM PDT 24 |
Peak memory | 241928 kb |
Host | smart-8db27e3c-c21a-487d-b6be-04dc6e4316a1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3143871684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.3143871684 |
Directory | /workspace/12.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/120.otp_ctrl_init_fail.3628661596 |
Short name | T1183 |
Test name | |
Test status | |
Simulation time | 107223073 ps |
CPU time | 4 seconds |
Started | Mar 31 03:32:58 PM PDT 24 |
Finished | Mar 31 03:33:03 PM PDT 24 |
Peak memory | 241744 kb |
Host | smart-0e1198ea-7ae3-48d5-9f0c-2ccabce2979e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3628661596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.3628661596 |
Directory | /workspace/120.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/120.otp_ctrl_parallel_lc_esc.3943071230 |
Short name | T1123 |
Test name | |
Test status | |
Simulation time | 172640802 ps |
CPU time | 8.79 seconds |
Started | Mar 31 03:33:01 PM PDT 24 |
Finished | Mar 31 03:33:10 PM PDT 24 |
Peak memory | 241912 kb |
Host | smart-f2af0b16-fd70-419e-8109-aa020eaaf7ca |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3943071230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.3943071230 |
Directory | /workspace/120.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/121.otp_ctrl_init_fail.653450795 |
Short name | T1169 |
Test name | |
Test status | |
Simulation time | 2049526145 ps |
CPU time | 8.32 seconds |
Started | Mar 31 03:32:59 PM PDT 24 |
Finished | Mar 31 03:33:07 PM PDT 24 |
Peak memory | 241864 kb |
Host | smart-941924a6-f2e2-4de6-96b6-436fdc66c0c1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=653450795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.653450795 |
Directory | /workspace/121.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/121.otp_ctrl_parallel_lc_esc.3094536459 |
Short name | T517 |
Test name | |
Test status | |
Simulation time | 286845858 ps |
CPU time | 7.58 seconds |
Started | Mar 31 03:33:05 PM PDT 24 |
Finished | Mar 31 03:33:12 PM PDT 24 |
Peak memory | 242036 kb |
Host | smart-cb98c0d3-606a-4e07-8ab6-cb3e33fe35e4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3094536459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.3094536459 |
Directory | /workspace/121.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/122.otp_ctrl_init_fail.3483963741 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 157678400 ps |
CPU time | 4.31 seconds |
Started | Mar 31 03:33:00 PM PDT 24 |
Finished | Mar 31 03:33:05 PM PDT 24 |
Peak memory | 241632 kb |
Host | smart-fb297cde-779f-4276-8b35-48563219a1dd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3483963741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.3483963741 |
Directory | /workspace/122.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/122.otp_ctrl_parallel_lc_esc.460531740 |
Short name | T763 |
Test name | |
Test status | |
Simulation time | 1625499397 ps |
CPU time | 23.79 seconds |
Started | Mar 31 03:32:59 PM PDT 24 |
Finished | Mar 31 03:33:23 PM PDT 24 |
Peak memory | 241788 kb |
Host | smart-5efde09d-8c93-4842-a9c7-c813adfe8302 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=460531740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.460531740 |
Directory | /workspace/122.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/123.otp_ctrl_init_fail.478319046 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 149886262 ps |
CPU time | 3.18 seconds |
Started | Mar 31 03:32:59 PM PDT 24 |
Finished | Mar 31 03:33:03 PM PDT 24 |
Peak memory | 241700 kb |
Host | smart-c6fba435-b69e-44bd-9eab-47b51f6ee6b0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=478319046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.478319046 |
Directory | /workspace/123.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/124.otp_ctrl_parallel_lc_esc.1914889885 |
Short name | T567 |
Test name | |
Test status | |
Simulation time | 1519695700 ps |
CPU time | 5.44 seconds |
Started | Mar 31 03:32:59 PM PDT 24 |
Finished | Mar 31 03:33:05 PM PDT 24 |
Peak memory | 241928 kb |
Host | smart-a03eb919-13b5-4790-ba4f-eef830e315bd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1914889885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.1914889885 |
Directory | /workspace/124.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/125.otp_ctrl_parallel_lc_esc.1657750849 |
Short name | T561 |
Test name | |
Test status | |
Simulation time | 1142887239 ps |
CPU time | 8.64 seconds |
Started | Mar 31 03:33:02 PM PDT 24 |
Finished | Mar 31 03:33:11 PM PDT 24 |
Peak memory | 242220 kb |
Host | smart-ffbbabb2-e9c4-4efd-a8e4-4e95bc059724 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1657750849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.1657750849 |
Directory | /workspace/125.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/126.otp_ctrl_init_fail.3734060359 |
Short name | T574 |
Test name | |
Test status | |
Simulation time | 1969801151 ps |
CPU time | 6.05 seconds |
Started | Mar 31 03:32:59 PM PDT 24 |
Finished | Mar 31 03:33:05 PM PDT 24 |
Peak memory | 241608 kb |
Host | smart-3762707c-fd71-4796-8914-e7d38d2dd621 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3734060359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.3734060359 |
Directory | /workspace/126.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/126.otp_ctrl_parallel_lc_esc.1226377333 |
Short name | T1098 |
Test name | |
Test status | |
Simulation time | 430995045 ps |
CPU time | 11.82 seconds |
Started | Mar 31 03:33:07 PM PDT 24 |
Finished | Mar 31 03:33:19 PM PDT 24 |
Peak memory | 241632 kb |
Host | smart-0ba54f75-8d96-4b90-a18b-de20f9f4cd61 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1226377333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.1226377333 |
Directory | /workspace/126.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/127.otp_ctrl_init_fail.1564216218 |
Short name | T1044 |
Test name | |
Test status | |
Simulation time | 265312098 ps |
CPU time | 4.07 seconds |
Started | Mar 31 03:33:08 PM PDT 24 |
Finished | Mar 31 03:33:12 PM PDT 24 |
Peak memory | 242048 kb |
Host | smart-f828f897-f490-4aac-b669-b487a75129bd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1564216218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.1564216218 |
Directory | /workspace/127.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/127.otp_ctrl_parallel_lc_esc.3372862472 |
Short name | T750 |
Test name | |
Test status | |
Simulation time | 1130165954 ps |
CPU time | 13.97 seconds |
Started | Mar 31 03:33:05 PM PDT 24 |
Finished | Mar 31 03:33:19 PM PDT 24 |
Peak memory | 242084 kb |
Host | smart-8b9b8d3a-6ecd-4308-b6fb-394645a3e2f5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3372862472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.3372862472 |
Directory | /workspace/127.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/128.otp_ctrl_parallel_lc_esc.371357729 |
Short name | T614 |
Test name | |
Test status | |
Simulation time | 543636377 ps |
CPU time | 5.55 seconds |
Started | Mar 31 03:33:09 PM PDT 24 |
Finished | Mar 31 03:33:14 PM PDT 24 |
Peak memory | 241580 kb |
Host | smart-94ffffa8-079d-48ee-aaea-28acda6d0593 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=371357729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.371357729 |
Directory | /workspace/128.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/129.otp_ctrl_init_fail.1588131902 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 362698551 ps |
CPU time | 3.5 seconds |
Started | Mar 31 03:33:06 PM PDT 24 |
Finished | Mar 31 03:33:10 PM PDT 24 |
Peak memory | 241756 kb |
Host | smart-6bde1919-a088-492c-9410-502559d87b8d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1588131902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.1588131902 |
Directory | /workspace/129.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/129.otp_ctrl_parallel_lc_esc.2978969427 |
Short name | T532 |
Test name | |
Test status | |
Simulation time | 207216652 ps |
CPU time | 5.29 seconds |
Started | Mar 31 03:33:06 PM PDT 24 |
Finished | Mar 31 03:33:11 PM PDT 24 |
Peak memory | 241700 kb |
Host | smart-999289b1-7a84-4daf-95d8-9eeb6462236e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2978969427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.2978969427 |
Directory | /workspace/129.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/13.otp_ctrl_alert_test.1342409554 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 165885021 ps |
CPU time | 1.61 seconds |
Started | Mar 31 03:29:41 PM PDT 24 |
Finished | Mar 31 03:29:43 PM PDT 24 |
Peak memory | 240116 kb |
Host | smart-22b24ace-1702-4d50-abaf-59f5ead83b4f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342409554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.1342409554 |
Directory | /workspace/13.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/13.otp_ctrl_check_fail.530219636 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 8831009930 ps |
CPU time | 24.94 seconds |
Started | Mar 31 03:29:34 PM PDT 24 |
Finished | Mar 31 03:29:59 PM PDT 24 |
Peak memory | 241816 kb |
Host | smart-227ddb9b-c5f3-4613-bfef-b4c6b1c10ad7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=530219636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.530219636 |
Directory | /workspace/13.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/13.otp_ctrl_dai_errs.1969801586 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 1658129327 ps |
CPU time | 22.57 seconds |
Started | Mar 31 03:29:38 PM PDT 24 |
Finished | Mar 31 03:30:01 PM PDT 24 |
Peak memory | 242008 kb |
Host | smart-3ccea341-8e04-460a-a415-01fa018a326e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1969801586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.1969801586 |
Directory | /workspace/13.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/13.otp_ctrl_dai_lock.3716037231 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 475563068 ps |
CPU time | 6.28 seconds |
Started | Mar 31 03:29:37 PM PDT 24 |
Finished | Mar 31 03:29:44 PM PDT 24 |
Peak memory | 241756 kb |
Host | smart-be5da2e8-3989-4af1-861d-5d3767f5d794 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3716037231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.3716037231 |
Directory | /workspace/13.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/13.otp_ctrl_init_fail.3028722088 |
Short name | T1079 |
Test name | |
Test status | |
Simulation time | 149498418 ps |
CPU time | 4.07 seconds |
Started | Mar 31 03:29:35 PM PDT 24 |
Finished | Mar 31 03:29:40 PM PDT 24 |
Peak memory | 241764 kb |
Host | smart-5835b91e-0f3a-4431-b1a2-361363c31429 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3028722088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.3028722088 |
Directory | /workspace/13.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/13.otp_ctrl_macro_errs.3063121683 |
Short name | T671 |
Test name | |
Test status | |
Simulation time | 951813403 ps |
CPU time | 12.48 seconds |
Started | Mar 31 03:29:36 PM PDT 24 |
Finished | Mar 31 03:29:48 PM PDT 24 |
Peak memory | 242236 kb |
Host | smart-14dedb55-3951-474d-ac3a-739b37766672 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3063121683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.3063121683 |
Directory | /workspace/13.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/13.otp_ctrl_parallel_key_req.656698028 |
Short name | T537 |
Test name | |
Test status | |
Simulation time | 324621594 ps |
CPU time | 9.21 seconds |
Started | Mar 31 03:29:42 PM PDT 24 |
Finished | Mar 31 03:29:52 PM PDT 24 |
Peak memory | 241828 kb |
Host | smart-14111ec5-b67a-41de-868a-fc3aa605f06c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=656698028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.656698028 |
Directory | /workspace/13.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/13.otp_ctrl_parallel_lc_esc.309601200 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 9664918759 ps |
CPU time | 21.05 seconds |
Started | Mar 31 03:29:34 PM PDT 24 |
Finished | Mar 31 03:29:55 PM PDT 24 |
Peak memory | 241840 kb |
Host | smart-b0404ec3-8d03-456f-acc5-5e7074879126 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=309601200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.309601200 |
Directory | /workspace/13.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/13.otp_ctrl_parallel_lc_req.2936358225 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 309701129 ps |
CPU time | 8.4 seconds |
Started | Mar 31 03:29:35 PM PDT 24 |
Finished | Mar 31 03:29:43 PM PDT 24 |
Peak memory | 241724 kb |
Host | smart-6bb10b0e-b979-4637-88a2-e5ea3ae4841a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2936358225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.2936358225 |
Directory | /workspace/13.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/13.otp_ctrl_regwen.639136664 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 196008533 ps |
CPU time | 4.97 seconds |
Started | Mar 31 03:29:44 PM PDT 24 |
Finished | Mar 31 03:29:50 PM PDT 24 |
Peak memory | 241540 kb |
Host | smart-ecf0ef5f-060f-4a33-842f-65b3e99224f0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=639136664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.639136664 |
Directory | /workspace/13.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/13.otp_ctrl_smoke.1647024551 |
Short name | T904 |
Test name | |
Test status | |
Simulation time | 750625846 ps |
CPU time | 10.71 seconds |
Started | Mar 31 03:29:39 PM PDT 24 |
Finished | Mar 31 03:29:50 PM PDT 24 |
Peak memory | 241768 kb |
Host | smart-ee066447-18ba-48b9-b192-9aca341d521d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1647024551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.1647024551 |
Directory | /workspace/13.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/13.otp_ctrl_stress_all.486911148 |
Short name | T1157 |
Test name | |
Test status | |
Simulation time | 2944601181 ps |
CPU time | 35.11 seconds |
Started | Mar 31 03:29:39 PM PDT 24 |
Finished | Mar 31 03:30:14 PM PDT 24 |
Peak memory | 241860 kb |
Host | smart-8ee831a9-c53e-4ad5-873f-8ddbd6cbc2d7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486911148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all. 486911148 |
Directory | /workspace/13.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/13.otp_ctrl_stress_all_with_rand_reset.3206831454 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 110939112709 ps |
CPU time | 962.89 seconds |
Started | Mar 31 03:29:44 PM PDT 24 |
Finished | Mar 31 03:45:47 PM PDT 24 |
Peak memory | 454936 kb |
Host | smart-166d7f9a-4bf5-45f3-8ab7-22056925526d |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206831454 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all_with_rand_reset.3206831454 |
Directory | /workspace/13.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/13.otp_ctrl_test_access.62367434 |
Short name | T880 |
Test name | |
Test status | |
Simulation time | 671527941 ps |
CPU time | 18.56 seconds |
Started | Mar 31 03:29:41 PM PDT 24 |
Finished | Mar 31 03:30:00 PM PDT 24 |
Peak memory | 242032 kb |
Host | smart-5f6f81be-b57a-4796-b7e3-c363ab6d5c1e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=62367434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.62367434 |
Directory | /workspace/13.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/130.otp_ctrl_init_fail.2294655029 |
Short name | T645 |
Test name | |
Test status | |
Simulation time | 92253652 ps |
CPU time | 4.14 seconds |
Started | Mar 31 03:33:06 PM PDT 24 |
Finished | Mar 31 03:33:10 PM PDT 24 |
Peak memory | 241840 kb |
Host | smart-6e43048e-2d8a-4384-9587-2a17e7afa4bb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2294655029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.2294655029 |
Directory | /workspace/130.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/130.otp_ctrl_parallel_lc_esc.2083061069 |
Short name | T564 |
Test name | |
Test status | |
Simulation time | 335430791 ps |
CPU time | 4.01 seconds |
Started | Mar 31 03:33:07 PM PDT 24 |
Finished | Mar 31 03:33:11 PM PDT 24 |
Peak memory | 241624 kb |
Host | smart-2279ec96-a2d4-4c6c-9983-09c8a650aeb8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2083061069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.2083061069 |
Directory | /workspace/130.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/131.otp_ctrl_init_fail.2399220958 |
Short name | T1146 |
Test name | |
Test status | |
Simulation time | 240558396 ps |
CPU time | 3.86 seconds |
Started | Mar 31 03:33:04 PM PDT 24 |
Finished | Mar 31 03:33:08 PM PDT 24 |
Peak memory | 241748 kb |
Host | smart-2c6944ae-4168-4a25-87a9-713da0802311 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2399220958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.2399220958 |
Directory | /workspace/131.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/131.otp_ctrl_parallel_lc_esc.1307664944 |
Short name | T1034 |
Test name | |
Test status | |
Simulation time | 124985430 ps |
CPU time | 3.14 seconds |
Started | Mar 31 03:33:06 PM PDT 24 |
Finished | Mar 31 03:33:09 PM PDT 24 |
Peak memory | 241732 kb |
Host | smart-6d8a3d11-7c0e-4cfb-abdc-5ed762d1dd70 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1307664944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.1307664944 |
Directory | /workspace/131.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/132.otp_ctrl_init_fail.513150650 |
Short name | T738 |
Test name | |
Test status | |
Simulation time | 156078081 ps |
CPU time | 4.34 seconds |
Started | Mar 31 03:33:06 PM PDT 24 |
Finished | Mar 31 03:33:10 PM PDT 24 |
Peak memory | 241704 kb |
Host | smart-7a01ce59-929b-418d-85ea-6ad0bee2fafb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=513150650 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.513150650 |
Directory | /workspace/132.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/132.otp_ctrl_parallel_lc_esc.422165310 |
Short name | T651 |
Test name | |
Test status | |
Simulation time | 278470722 ps |
CPU time | 7.05 seconds |
Started | Mar 31 03:33:06 PM PDT 24 |
Finished | Mar 31 03:33:13 PM PDT 24 |
Peak memory | 241532 kb |
Host | smart-558deb95-4043-484f-acba-8cc83288bb64 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=422165310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.422165310 |
Directory | /workspace/132.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/133.otp_ctrl_init_fail.2993199716 |
Short name | T902 |
Test name | |
Test status | |
Simulation time | 1526646403 ps |
CPU time | 3.05 seconds |
Started | Mar 31 03:33:05 PM PDT 24 |
Finished | Mar 31 03:33:08 PM PDT 24 |
Peak memory | 241996 kb |
Host | smart-0144c77c-644c-4406-9610-7987c02d3cd2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2993199716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.2993199716 |
Directory | /workspace/133.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/133.otp_ctrl_parallel_lc_esc.2556195802 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 549351302 ps |
CPU time | 5.77 seconds |
Started | Mar 31 03:33:07 PM PDT 24 |
Finished | Mar 31 03:33:13 PM PDT 24 |
Peak memory | 241612 kb |
Host | smart-40736964-4f47-4677-a23e-322881409b2c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2556195802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.2556195802 |
Directory | /workspace/133.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/134.otp_ctrl_init_fail.14243026 |
Short name | T888 |
Test name | |
Test status | |
Simulation time | 235587116 ps |
CPU time | 4.73 seconds |
Started | Mar 31 03:33:04 PM PDT 24 |
Finished | Mar 31 03:33:09 PM PDT 24 |
Peak memory | 241756 kb |
Host | smart-4929901b-49a4-4e2c-90df-dcd534a35bc1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=14243026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.14243026 |
Directory | /workspace/134.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/134.otp_ctrl_parallel_lc_esc.2004530597 |
Short name | T812 |
Test name | |
Test status | |
Simulation time | 1962783558 ps |
CPU time | 8.77 seconds |
Started | Mar 31 03:33:07 PM PDT 24 |
Finished | Mar 31 03:33:16 PM PDT 24 |
Peak memory | 241484 kb |
Host | smart-5df66afc-4aca-43f4-b7dc-fb1fc554c8e2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2004530597 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.2004530597 |
Directory | /workspace/134.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/135.otp_ctrl_init_fail.437953569 |
Short name | T715 |
Test name | |
Test status | |
Simulation time | 2248450471 ps |
CPU time | 4.93 seconds |
Started | Mar 31 03:33:04 PM PDT 24 |
Finished | Mar 31 03:33:09 PM PDT 24 |
Peak memory | 242000 kb |
Host | smart-a34d1337-18df-4c49-866f-dba25b46d12d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=437953569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.437953569 |
Directory | /workspace/135.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/135.otp_ctrl_parallel_lc_esc.3935240759 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 1526010257 ps |
CPU time | 12.11 seconds |
Started | Mar 31 03:33:06 PM PDT 24 |
Finished | Mar 31 03:33:18 PM PDT 24 |
Peak memory | 241844 kb |
Host | smart-5d91f71a-8b95-49a2-8a81-3246df3a3ebb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3935240759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.3935240759 |
Directory | /workspace/135.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/136.otp_ctrl_init_fail.2188073940 |
Short name | T635 |
Test name | |
Test status | |
Simulation time | 231593707 ps |
CPU time | 4.8 seconds |
Started | Mar 31 03:33:12 PM PDT 24 |
Finished | Mar 31 03:33:17 PM PDT 24 |
Peak memory | 241684 kb |
Host | smart-11f59f9c-ac20-4cee-94b8-3a106b0aa80c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2188073940 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.2188073940 |
Directory | /workspace/136.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/136.otp_ctrl_parallel_lc_esc.1415362770 |
Short name | T616 |
Test name | |
Test status | |
Simulation time | 9453742582 ps |
CPU time | 27.02 seconds |
Started | Mar 31 03:33:14 PM PDT 24 |
Finished | Mar 31 03:33:41 PM PDT 24 |
Peak memory | 241872 kb |
Host | smart-ef445d2c-28ff-44bb-b19e-113bce3eb551 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1415362770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.1415362770 |
Directory | /workspace/136.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/137.otp_ctrl_init_fail.468518950 |
Short name | T458 |
Test name | |
Test status | |
Simulation time | 199759972 ps |
CPU time | 3.59 seconds |
Started | Mar 31 03:33:13 PM PDT 24 |
Finished | Mar 31 03:33:17 PM PDT 24 |
Peak memory | 241976 kb |
Host | smart-8d3d10b2-e5a4-42ef-9590-ec51ea6f3112 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=468518950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.468518950 |
Directory | /workspace/137.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/137.otp_ctrl_parallel_lc_esc.2834365903 |
Short name | T636 |
Test name | |
Test status | |
Simulation time | 143977355 ps |
CPU time | 6.72 seconds |
Started | Mar 31 03:33:12 PM PDT 24 |
Finished | Mar 31 03:33:19 PM PDT 24 |
Peak memory | 241968 kb |
Host | smart-f2e37189-4722-4626-89d3-7fc424974f88 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2834365903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.2834365903 |
Directory | /workspace/137.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/138.otp_ctrl_init_fail.2430362524 |
Short name | T725 |
Test name | |
Test status | |
Simulation time | 509815363 ps |
CPU time | 4.33 seconds |
Started | Mar 31 03:33:11 PM PDT 24 |
Finished | Mar 31 03:33:16 PM PDT 24 |
Peak memory | 241708 kb |
Host | smart-eb8be855-bdcb-4786-bff6-67607f64a9d9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2430362524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.2430362524 |
Directory | /workspace/138.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/138.otp_ctrl_parallel_lc_esc.3776941352 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 473711037 ps |
CPU time | 7.04 seconds |
Started | Mar 31 03:33:12 PM PDT 24 |
Finished | Mar 31 03:33:19 PM PDT 24 |
Peak memory | 241648 kb |
Host | smart-bf9a57c3-dc07-4aa4-9224-de83d28464d2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3776941352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.3776941352 |
Directory | /workspace/138.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/139.otp_ctrl_init_fail.2204244799 |
Short name | T661 |
Test name | |
Test status | |
Simulation time | 108321201 ps |
CPU time | 3.89 seconds |
Started | Mar 31 03:33:12 PM PDT 24 |
Finished | Mar 31 03:33:16 PM PDT 24 |
Peak memory | 241712 kb |
Host | smart-8bb1590b-9446-432e-8993-878f746fde7a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2204244799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.2204244799 |
Directory | /workspace/139.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/139.otp_ctrl_parallel_lc_esc.4169508088 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 483596908 ps |
CPU time | 6.93 seconds |
Started | Mar 31 03:33:14 PM PDT 24 |
Finished | Mar 31 03:33:21 PM PDT 24 |
Peak memory | 241588 kb |
Host | smart-3ebd9696-78dd-4b11-827a-071468669942 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4169508088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.4169508088 |
Directory | /workspace/139.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/14.otp_ctrl_alert_test.1131090497 |
Short name | T882 |
Test name | |
Test status | |
Simulation time | 566458470 ps |
CPU time | 2.15 seconds |
Started | Mar 31 03:29:45 PM PDT 24 |
Finished | Mar 31 03:29:47 PM PDT 24 |
Peak memory | 240040 kb |
Host | smart-26fc7d85-26d5-4975-984d-f28f6ba38fc6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131090497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.1131090497 |
Directory | /workspace/14.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/14.otp_ctrl_check_fail.2643447636 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 1090002942 ps |
CPU time | 8.51 seconds |
Started | Mar 31 03:29:47 PM PDT 24 |
Finished | Mar 31 03:29:56 PM PDT 24 |
Peak memory | 242172 kb |
Host | smart-dc10774c-a3f2-48b7-984d-40c14ffe632f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2643447636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.2643447636 |
Directory | /workspace/14.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/14.otp_ctrl_dai_errs.3446384267 |
Short name | T587 |
Test name | |
Test status | |
Simulation time | 389277326 ps |
CPU time | 11.17 seconds |
Started | Mar 31 03:29:39 PM PDT 24 |
Finished | Mar 31 03:29:50 PM PDT 24 |
Peak memory | 241324 kb |
Host | smart-08c790e3-b2dc-4459-b9e9-63228fee1138 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3446384267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.3446384267 |
Directory | /workspace/14.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/14.otp_ctrl_dai_lock.2372988927 |
Short name | T540 |
Test name | |
Test status | |
Simulation time | 16419334334 ps |
CPU time | 42.52 seconds |
Started | Mar 31 03:29:41 PM PDT 24 |
Finished | Mar 31 03:30:24 PM PDT 24 |
Peak memory | 243372 kb |
Host | smart-26c6da87-0c1a-475f-b6be-34f8e8df0d82 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2372988927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.2372988927 |
Directory | /workspace/14.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/14.otp_ctrl_init_fail.2483722716 |
Short name | T1115 |
Test name | |
Test status | |
Simulation time | 129790125 ps |
CPU time | 5.26 seconds |
Started | Mar 31 03:29:40 PM PDT 24 |
Finished | Mar 31 03:29:46 PM PDT 24 |
Peak memory | 241808 kb |
Host | smart-13683159-b740-4153-af87-0c74dad1e670 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2483722716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.2483722716 |
Directory | /workspace/14.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/14.otp_ctrl_parallel_key_req.3493135805 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 1083205347 ps |
CPU time | 22.1 seconds |
Started | Mar 31 03:29:49 PM PDT 24 |
Finished | Mar 31 03:30:11 PM PDT 24 |
Peak memory | 242300 kb |
Host | smart-cc4bc2d4-ce9b-44c8-97eb-4d95edd0cf52 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3493135805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.3493135805 |
Directory | /workspace/14.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/14.otp_ctrl_parallel_lc_esc.3611772029 |
Short name | T1170 |
Test name | |
Test status | |
Simulation time | 882695611 ps |
CPU time | 12.35 seconds |
Started | Mar 31 03:29:39 PM PDT 24 |
Finished | Mar 31 03:29:52 PM PDT 24 |
Peak memory | 241676 kb |
Host | smart-c7111367-02c0-40cc-b737-e1b1b00d8013 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3611772029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.3611772029 |
Directory | /workspace/14.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/14.otp_ctrl_parallel_lc_req.1848438764 |
Short name | T755 |
Test name | |
Test status | |
Simulation time | 254083512 ps |
CPU time | 6.85 seconds |
Started | Mar 31 03:29:45 PM PDT 24 |
Finished | Mar 31 03:29:52 PM PDT 24 |
Peak memory | 241736 kb |
Host | smart-f9ef1353-1de3-4494-abc0-c34f7ed7a08a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1848438764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.1848438764 |
Directory | /workspace/14.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/14.otp_ctrl_regwen.1277536649 |
Short name | T503 |
Test name | |
Test status | |
Simulation time | 438405236 ps |
CPU time | 6.94 seconds |
Started | Mar 31 03:29:46 PM PDT 24 |
Finished | Mar 31 03:29:54 PM PDT 24 |
Peak memory | 241732 kb |
Host | smart-95734c5b-8051-4fca-8e68-3a510a1346a2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1277536649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.1277536649 |
Directory | /workspace/14.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/14.otp_ctrl_smoke.3371361108 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 261994269 ps |
CPU time | 4.99 seconds |
Started | Mar 31 03:29:41 PM PDT 24 |
Finished | Mar 31 03:29:46 PM PDT 24 |
Peak memory | 241628 kb |
Host | smart-2ca9d180-bff0-4f2c-a950-969f8efd3749 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3371361108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.3371361108 |
Directory | /workspace/14.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/14.otp_ctrl_stress_all.1337494912 |
Short name | T1038 |
Test name | |
Test status | |
Simulation time | 11817415529 ps |
CPU time | 15.44 seconds |
Started | Mar 31 03:29:46 PM PDT 24 |
Finished | Mar 31 03:30:01 PM PDT 24 |
Peak memory | 242556 kb |
Host | smart-ca0b2734-bbc5-4e22-8815-a81e9347939d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337494912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all .1337494912 |
Directory | /workspace/14.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/14.otp_ctrl_stress_all_with_rand_reset.588457840 |
Short name | T1088 |
Test name | |
Test status | |
Simulation time | 23678240870 ps |
CPU time | 595.69 seconds |
Started | Mar 31 03:29:47 PM PDT 24 |
Finished | Mar 31 03:39:42 PM PDT 24 |
Peak memory | 257020 kb |
Host | smart-ce3a2d5d-5f4b-4d0e-962f-3a3b5ad40d8b |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588457840 -assert nopo stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all_with_rand_reset.588457840 |
Directory | /workspace/14.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/14.otp_ctrl_test_access.822723663 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 1130724839 ps |
CPU time | 15.98 seconds |
Started | Mar 31 03:29:48 PM PDT 24 |
Finished | Mar 31 03:30:04 PM PDT 24 |
Peak memory | 241764 kb |
Host | smart-eb7661fd-d1b8-46a9-b272-40892faf4895 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=822723663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.822723663 |
Directory | /workspace/14.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/140.otp_ctrl_init_fail.3451873282 |
Short name | T667 |
Test name | |
Test status | |
Simulation time | 270917590 ps |
CPU time | 2.98 seconds |
Started | Mar 31 03:33:12 PM PDT 24 |
Finished | Mar 31 03:33:15 PM PDT 24 |
Peak memory | 241800 kb |
Host | smart-c69e8ac0-bde0-441b-baf9-87382f3ba1a7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3451873282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.3451873282 |
Directory | /workspace/140.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/140.otp_ctrl_parallel_lc_esc.1700127680 |
Short name | T462 |
Test name | |
Test status | |
Simulation time | 225100221 ps |
CPU time | 13.29 seconds |
Started | Mar 31 03:33:14 PM PDT 24 |
Finished | Mar 31 03:33:28 PM PDT 24 |
Peak memory | 241772 kb |
Host | smart-7d448114-9e2c-48af-9641-f5864f6b7e85 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1700127680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.1700127680 |
Directory | /workspace/140.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/141.otp_ctrl_parallel_lc_esc.439448604 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 5650507440 ps |
CPU time | 12.71 seconds |
Started | Mar 31 03:33:12 PM PDT 24 |
Finished | Mar 31 03:33:25 PM PDT 24 |
Peak memory | 242148 kb |
Host | smart-157d3ce2-be91-40bb-a2e9-4b6e25250794 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=439448604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.439448604 |
Directory | /workspace/141.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/142.otp_ctrl_init_fail.1698337651 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 238610357 ps |
CPU time | 3.17 seconds |
Started | Mar 31 03:33:14 PM PDT 24 |
Finished | Mar 31 03:33:18 PM PDT 24 |
Peak memory | 241992 kb |
Host | smart-271db925-7c54-42e7-bf15-a289537bf942 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1698337651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.1698337651 |
Directory | /workspace/142.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/142.otp_ctrl_parallel_lc_esc.310788653 |
Short name | T986 |
Test name | |
Test status | |
Simulation time | 6770360917 ps |
CPU time | 13.11 seconds |
Started | Mar 31 03:33:11 PM PDT 24 |
Finished | Mar 31 03:33:24 PM PDT 24 |
Peak memory | 241736 kb |
Host | smart-3e627b68-9a5d-42c1-ada3-49489cd7e0a5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=310788653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.310788653 |
Directory | /workspace/142.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/143.otp_ctrl_init_fail.120217135 |
Short name | T483 |
Test name | |
Test status | |
Simulation time | 196470058 ps |
CPU time | 4.72 seconds |
Started | Mar 31 03:33:11 PM PDT 24 |
Finished | Mar 31 03:33:15 PM PDT 24 |
Peak memory | 241884 kb |
Host | smart-be9dfbaf-4a7c-473c-9b85-dd3a4fcb66a9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=120217135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.120217135 |
Directory | /workspace/143.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/143.otp_ctrl_parallel_lc_esc.1387387949 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 215293887 ps |
CPU time | 9.72 seconds |
Started | Mar 31 03:33:12 PM PDT 24 |
Finished | Mar 31 03:33:22 PM PDT 24 |
Peak memory | 241692 kb |
Host | smart-4bfd8536-18bc-4f49-a3ac-86f524f52195 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1387387949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.1387387949 |
Directory | /workspace/143.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/144.otp_ctrl_parallel_lc_esc.2052337573 |
Short name | T1167 |
Test name | |
Test status | |
Simulation time | 305240852 ps |
CPU time | 17.53 seconds |
Started | Mar 31 03:33:14 PM PDT 24 |
Finished | Mar 31 03:33:32 PM PDT 24 |
Peak memory | 241516 kb |
Host | smart-14f3eb78-2259-4ea9-a848-ad3b59911d12 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2052337573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.2052337573 |
Directory | /workspace/144.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/145.otp_ctrl_init_fail.1209871820 |
Short name | T872 |
Test name | |
Test status | |
Simulation time | 1640811375 ps |
CPU time | 6.64 seconds |
Started | Mar 31 03:33:12 PM PDT 24 |
Finished | Mar 31 03:33:19 PM PDT 24 |
Peak memory | 242016 kb |
Host | smart-20e56d47-3b24-49be-99b7-7548a5e32b72 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1209871820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.1209871820 |
Directory | /workspace/145.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/146.otp_ctrl_init_fail.3967169939 |
Short name | T898 |
Test name | |
Test status | |
Simulation time | 145898495 ps |
CPU time | 3.83 seconds |
Started | Mar 31 03:33:12 PM PDT 24 |
Finished | Mar 31 03:33:16 PM PDT 24 |
Peak memory | 241712 kb |
Host | smart-2aeb919f-b2d0-42a7-a0ed-42173273d118 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3967169939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.3967169939 |
Directory | /workspace/146.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/146.otp_ctrl_parallel_lc_esc.1152086141 |
Short name | T707 |
Test name | |
Test status | |
Simulation time | 310915980 ps |
CPU time | 7.51 seconds |
Started | Mar 31 03:33:12 PM PDT 24 |
Finished | Mar 31 03:33:19 PM PDT 24 |
Peak memory | 241944 kb |
Host | smart-c5fc6a37-3387-4858-9915-613d80d3a6fb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1152086141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.1152086141 |
Directory | /workspace/146.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/147.otp_ctrl_init_fail.2046898278 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 256718770 ps |
CPU time | 4.04 seconds |
Started | Mar 31 03:33:13 PM PDT 24 |
Finished | Mar 31 03:33:17 PM PDT 24 |
Peak memory | 241716 kb |
Host | smart-7d173704-b0c2-4268-9c1b-a459e6ebdbb6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2046898278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.2046898278 |
Directory | /workspace/147.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/147.otp_ctrl_parallel_lc_esc.3068003537 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 101615099 ps |
CPU time | 4.38 seconds |
Started | Mar 31 03:33:12 PM PDT 24 |
Finished | Mar 31 03:33:16 PM PDT 24 |
Peak memory | 241824 kb |
Host | smart-ef04cf1a-64f2-4a16-a874-4611ed40c360 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3068003537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.3068003537 |
Directory | /workspace/147.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/148.otp_ctrl_init_fail.1100847503 |
Short name | T500 |
Test name | |
Test status | |
Simulation time | 1499143223 ps |
CPU time | 4.81 seconds |
Started | Mar 31 03:33:21 PM PDT 24 |
Finished | Mar 31 03:33:26 PM PDT 24 |
Peak memory | 241804 kb |
Host | smart-624d0771-876a-4138-bc3b-ee4473dfeef5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1100847503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.1100847503 |
Directory | /workspace/148.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/149.otp_ctrl_init_fail.3239134425 |
Short name | T868 |
Test name | |
Test status | |
Simulation time | 1542054891 ps |
CPU time | 4.85 seconds |
Started | Mar 31 03:33:21 PM PDT 24 |
Finished | Mar 31 03:33:26 PM PDT 24 |
Peak memory | 241812 kb |
Host | smart-d88f0e33-773d-4a9d-9139-e161d7d36b86 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3239134425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.3239134425 |
Directory | /workspace/149.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/149.otp_ctrl_parallel_lc_esc.2746445574 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 252544279 ps |
CPU time | 3.58 seconds |
Started | Mar 31 03:33:19 PM PDT 24 |
Finished | Mar 31 03:33:23 PM PDT 24 |
Peak memory | 241656 kb |
Host | smart-b54541c9-6041-4b4d-88b8-fd8e2f1fc88c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2746445574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.2746445574 |
Directory | /workspace/149.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/15.otp_ctrl_alert_test.2011754826 |
Short name | T885 |
Test name | |
Test status | |
Simulation time | 810277865 ps |
CPU time | 2.36 seconds |
Started | Mar 31 03:29:49 PM PDT 24 |
Finished | Mar 31 03:29:51 PM PDT 24 |
Peak memory | 240024 kb |
Host | smart-21846c59-dc61-4dce-a104-752a738d7272 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011754826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.2011754826 |
Directory | /workspace/15.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/15.otp_ctrl_check_fail.1941230437 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 17037076530 ps |
CPU time | 34.73 seconds |
Started | Mar 31 03:29:49 PM PDT 24 |
Finished | Mar 31 03:30:23 PM PDT 24 |
Peak memory | 244996 kb |
Host | smart-6030fd52-f7bb-4f32-9882-885d156104ba |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1941230437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.1941230437 |
Directory | /workspace/15.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/15.otp_ctrl_dai_errs.1525494560 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 1345691884 ps |
CPU time | 22.78 seconds |
Started | Mar 31 03:29:47 PM PDT 24 |
Finished | Mar 31 03:30:10 PM PDT 24 |
Peak memory | 241788 kb |
Host | smart-fdb0d4cd-9af8-4320-ac71-3b3bbf55b083 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1525494560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.1525494560 |
Directory | /workspace/15.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/15.otp_ctrl_dai_lock.459537732 |
Short name | T504 |
Test name | |
Test status | |
Simulation time | 1818712293 ps |
CPU time | 23.37 seconds |
Started | Mar 31 03:29:48 PM PDT 24 |
Finished | Mar 31 03:30:11 PM PDT 24 |
Peak memory | 241756 kb |
Host | smart-12073386-b241-4473-b860-c58b45558119 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=459537732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.459537732 |
Directory | /workspace/15.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/15.otp_ctrl_init_fail.2750375643 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 118762880 ps |
CPU time | 4.41 seconds |
Started | Mar 31 03:29:48 PM PDT 24 |
Finished | Mar 31 03:29:52 PM PDT 24 |
Peak memory | 241696 kb |
Host | smart-70ef47d5-ed7c-4b72-9c07-be08c032dc61 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2750375643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.2750375643 |
Directory | /workspace/15.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/15.otp_ctrl_macro_errs.3861241667 |
Short name | T674 |
Test name | |
Test status | |
Simulation time | 2836299505 ps |
CPU time | 19.21 seconds |
Started | Mar 31 03:29:47 PM PDT 24 |
Finished | Mar 31 03:30:07 PM PDT 24 |
Peak memory | 243052 kb |
Host | smart-44f00ecd-77d0-4697-92c5-6b24d5e4b3d7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3861241667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.3861241667 |
Directory | /workspace/15.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/15.otp_ctrl_parallel_key_req.8065686 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 5857498969 ps |
CPU time | 13.76 seconds |
Started | Mar 31 03:29:47 PM PDT 24 |
Finished | Mar 31 03:30:01 PM PDT 24 |
Peak memory | 242116 kb |
Host | smart-34630d5b-3ad5-4b7f-9188-f663ce5e0127 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=8065686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.8065686 |
Directory | /workspace/15.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/15.otp_ctrl_parallel_lc_esc.460739714 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 316037267 ps |
CPU time | 3.75 seconds |
Started | Mar 31 03:29:46 PM PDT 24 |
Finished | Mar 31 03:29:50 PM PDT 24 |
Peak memory | 241700 kb |
Host | smart-94fedcea-29eb-4741-a2a3-ebaf2bcfc3dc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=460739714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.460739714 |
Directory | /workspace/15.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/15.otp_ctrl_parallel_lc_req.3960583490 |
Short name | T838 |
Test name | |
Test status | |
Simulation time | 878437346 ps |
CPU time | 12.33 seconds |
Started | Mar 31 03:29:45 PM PDT 24 |
Finished | Mar 31 03:29:57 PM PDT 24 |
Peak memory | 241596 kb |
Host | smart-99dac958-705b-4898-a324-c34bd5e38ce2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3960583490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.3960583490 |
Directory | /workspace/15.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/15.otp_ctrl_regwen.3055752255 |
Short name | T860 |
Test name | |
Test status | |
Simulation time | 437575985 ps |
CPU time | 7.7 seconds |
Started | Mar 31 03:29:48 PM PDT 24 |
Finished | Mar 31 03:29:56 PM PDT 24 |
Peak memory | 241784 kb |
Host | smart-af4a8434-3609-4746-82e2-813327e2b7f3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3055752255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.3055752255 |
Directory | /workspace/15.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/15.otp_ctrl_smoke.3667015080 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 5379741096 ps |
CPU time | 15.53 seconds |
Started | Mar 31 03:29:46 PM PDT 24 |
Finished | Mar 31 03:30:01 PM PDT 24 |
Peak memory | 241856 kb |
Host | smart-f4c8184e-0e38-44f7-96c4-e402fb9f983e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3667015080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.3667015080 |
Directory | /workspace/15.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/15.otp_ctrl_stress_all.3951578910 |
Short name | T1181 |
Test name | |
Test status | |
Simulation time | 77734724600 ps |
CPU time | 383.22 seconds |
Started | Mar 31 03:29:48 PM PDT 24 |
Finished | Mar 31 03:36:12 PM PDT 24 |
Peak memory | 249096 kb |
Host | smart-178844b5-00de-42e1-9207-ed0f6c73af67 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951578910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all .3951578910 |
Directory | /workspace/15.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/15.otp_ctrl_stress_all_with_rand_reset.3572630013 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 35438130413 ps |
CPU time | 801.41 seconds |
Started | Mar 31 03:29:48 PM PDT 24 |
Finished | Mar 31 03:43:10 PM PDT 24 |
Peak memory | 258628 kb |
Host | smart-70d2d8c5-6055-4702-8e2f-98e35f92d854 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572630013 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all_with_rand_reset.3572630013 |
Directory | /workspace/15.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/15.otp_ctrl_test_access.780405652 |
Short name | T669 |
Test name | |
Test status | |
Simulation time | 5856394553 ps |
CPU time | 39.8 seconds |
Started | Mar 31 03:29:47 PM PDT 24 |
Finished | Mar 31 03:30:27 PM PDT 24 |
Peak memory | 242888 kb |
Host | smart-586f7287-07d6-4406-9873-adf99e1f7a56 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=780405652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.780405652 |
Directory | /workspace/15.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/150.otp_ctrl_init_fail.2446374882 |
Short name | T1049 |
Test name | |
Test status | |
Simulation time | 123377574 ps |
CPU time | 3.18 seconds |
Started | Mar 31 03:33:20 PM PDT 24 |
Finished | Mar 31 03:33:23 PM PDT 24 |
Peak memory | 241776 kb |
Host | smart-0668c1d2-ebee-4134-a6ef-a370a4583c29 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2446374882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.2446374882 |
Directory | /workspace/150.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/150.otp_ctrl_parallel_lc_esc.1862102049 |
Short name | T848 |
Test name | |
Test status | |
Simulation time | 325158230 ps |
CPU time | 3.65 seconds |
Started | Mar 31 03:33:21 PM PDT 24 |
Finished | Mar 31 03:33:25 PM PDT 24 |
Peak memory | 241624 kb |
Host | smart-3e7103ad-6329-4614-9973-457d6f93a748 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1862102049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.1862102049 |
Directory | /workspace/150.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/151.otp_ctrl_init_fail.2947531048 |
Short name | T1070 |
Test name | |
Test status | |
Simulation time | 614179358 ps |
CPU time | 4.45 seconds |
Started | Mar 31 03:33:22 PM PDT 24 |
Finished | Mar 31 03:33:26 PM PDT 24 |
Peak memory | 242076 kb |
Host | smart-f3318725-2d91-4820-a090-31fc9f6de1cf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2947531048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.2947531048 |
Directory | /workspace/151.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/151.otp_ctrl_parallel_lc_esc.360493595 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 1314959987 ps |
CPU time | 5.02 seconds |
Started | Mar 31 03:33:22 PM PDT 24 |
Finished | Mar 31 03:33:27 PM PDT 24 |
Peak memory | 241872 kb |
Host | smart-ae06875a-9580-46b1-8899-700d1ed2ed12 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=360493595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.360493595 |
Directory | /workspace/151.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/152.otp_ctrl_init_fail.2515040569 |
Short name | T1177 |
Test name | |
Test status | |
Simulation time | 156276783 ps |
CPU time | 4.44 seconds |
Started | Mar 31 03:33:19 PM PDT 24 |
Finished | Mar 31 03:33:23 PM PDT 24 |
Peak memory | 241584 kb |
Host | smart-24978a1c-ade5-471e-b04e-2d358db55351 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2515040569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.2515040569 |
Directory | /workspace/152.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/152.otp_ctrl_parallel_lc_esc.1109981201 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 373983228 ps |
CPU time | 4.18 seconds |
Started | Mar 31 03:33:21 PM PDT 24 |
Finished | Mar 31 03:33:25 PM PDT 24 |
Peak memory | 241876 kb |
Host | smart-72cc4bc6-e9cb-403f-8a41-d49f76bf731f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1109981201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.1109981201 |
Directory | /workspace/152.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/153.otp_ctrl_init_fail.951785193 |
Short name | T808 |
Test name | |
Test status | |
Simulation time | 208572220 ps |
CPU time | 3.38 seconds |
Started | Mar 31 03:33:22 PM PDT 24 |
Finished | Mar 31 03:33:25 PM PDT 24 |
Peak memory | 241692 kb |
Host | smart-db43f37a-9f39-484d-8ed3-f1bcc0aacd30 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=951785193 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.951785193 |
Directory | /workspace/153.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/153.otp_ctrl_parallel_lc_esc.10190624 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 346766980 ps |
CPU time | 3.92 seconds |
Started | Mar 31 03:33:21 PM PDT 24 |
Finished | Mar 31 03:33:25 PM PDT 24 |
Peak memory | 241964 kb |
Host | smart-ef370318-63e7-4fa8-af2a-374267c2a952 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=10190624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.10190624 |
Directory | /workspace/153.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/154.otp_ctrl_init_fail.2236351034 |
Short name | T883 |
Test name | |
Test status | |
Simulation time | 553591412 ps |
CPU time | 3.97 seconds |
Started | Mar 31 03:33:20 PM PDT 24 |
Finished | Mar 31 03:33:24 PM PDT 24 |
Peak memory | 242052 kb |
Host | smart-b37dfc92-b688-44af-954a-d508dfbcc575 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2236351034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.2236351034 |
Directory | /workspace/154.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/154.otp_ctrl_parallel_lc_esc.4186679830 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 4024464632 ps |
CPU time | 15.33 seconds |
Started | Mar 31 03:33:22 PM PDT 24 |
Finished | Mar 31 03:33:37 PM PDT 24 |
Peak memory | 241740 kb |
Host | smart-fb554167-8846-44d0-9b3d-a49d7e053d93 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4186679830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.4186679830 |
Directory | /workspace/154.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/155.otp_ctrl_parallel_lc_esc.1782218407 |
Short name | T585 |
Test name | |
Test status | |
Simulation time | 337441558 ps |
CPU time | 8.9 seconds |
Started | Mar 31 03:33:21 PM PDT 24 |
Finished | Mar 31 03:33:30 PM PDT 24 |
Peak memory | 241428 kb |
Host | smart-90bd3120-44a4-4e5c-b29b-a156b82c84b4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1782218407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.1782218407 |
Directory | /workspace/155.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/156.otp_ctrl_init_fail.3782423630 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 205901145 ps |
CPU time | 3.97 seconds |
Started | Mar 31 03:33:23 PM PDT 24 |
Finished | Mar 31 03:33:27 PM PDT 24 |
Peak memory | 241612 kb |
Host | smart-65415d6c-f4b0-4163-9b74-c520ede63990 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3782423630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.3782423630 |
Directory | /workspace/156.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/156.otp_ctrl_parallel_lc_esc.1999799347 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 232776572 ps |
CPU time | 5.15 seconds |
Started | Mar 31 03:33:21 PM PDT 24 |
Finished | Mar 31 03:33:27 PM PDT 24 |
Peak memory | 241572 kb |
Host | smart-3a60c3c6-6d66-488d-8e6e-c58f16d7f1b5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1999799347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.1999799347 |
Directory | /workspace/156.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/157.otp_ctrl_init_fail.576360054 |
Short name | T1179 |
Test name | |
Test status | |
Simulation time | 156055934 ps |
CPU time | 4.05 seconds |
Started | Mar 31 03:33:21 PM PDT 24 |
Finished | Mar 31 03:33:25 PM PDT 24 |
Peak memory | 241652 kb |
Host | smart-63e37593-df2f-446a-a322-08e03ef76961 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=576360054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.576360054 |
Directory | /workspace/157.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/157.otp_ctrl_parallel_lc_esc.589101825 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 2794136857 ps |
CPU time | 19.25 seconds |
Started | Mar 31 03:33:22 PM PDT 24 |
Finished | Mar 31 03:33:41 PM PDT 24 |
Peak memory | 241840 kb |
Host | smart-0a25b2f4-6472-4f53-8b67-06881d3b3345 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=589101825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.589101825 |
Directory | /workspace/157.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/158.otp_ctrl_init_fail.3633936714 |
Short name | T634 |
Test name | |
Test status | |
Simulation time | 117667060 ps |
CPU time | 4.44 seconds |
Started | Mar 31 03:33:24 PM PDT 24 |
Finished | Mar 31 03:33:28 PM PDT 24 |
Peak memory | 241672 kb |
Host | smart-922230c5-cd96-4225-97bc-11ad9f44039a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3633936714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.3633936714 |
Directory | /workspace/158.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/158.otp_ctrl_parallel_lc_esc.1635768962 |
Short name | T445 |
Test name | |
Test status | |
Simulation time | 519084438 ps |
CPU time | 12.9 seconds |
Started | Mar 31 03:33:21 PM PDT 24 |
Finished | Mar 31 03:33:34 PM PDT 24 |
Peak memory | 241612 kb |
Host | smart-4c755b1d-a8c6-469b-a389-d34131c4e8dd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1635768962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.1635768962 |
Directory | /workspace/158.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/159.otp_ctrl_init_fail.225218616 |
Short name | T998 |
Test name | |
Test status | |
Simulation time | 291792012 ps |
CPU time | 4.34 seconds |
Started | Mar 31 03:33:23 PM PDT 24 |
Finished | Mar 31 03:33:27 PM PDT 24 |
Peak memory | 241976 kb |
Host | smart-54eed1e4-9ab8-4bb2-9eac-399b34897b6e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=225218616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.225218616 |
Directory | /workspace/159.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/159.otp_ctrl_parallel_lc_esc.3189345347 |
Short name | T468 |
Test name | |
Test status | |
Simulation time | 986415722 ps |
CPU time | 15.73 seconds |
Started | Mar 31 03:33:22 PM PDT 24 |
Finished | Mar 31 03:33:37 PM PDT 24 |
Peak memory | 242072 kb |
Host | smart-446481a0-2956-4dc3-bc1e-f695a4df3b7e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3189345347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.3189345347 |
Directory | /workspace/159.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/16.otp_ctrl_alert_test.2928615410 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 1116639404 ps |
CPU time | 2.58 seconds |
Started | Mar 31 03:29:54 PM PDT 24 |
Finished | Mar 31 03:29:57 PM PDT 24 |
Peak memory | 240152 kb |
Host | smart-fe62f28d-418b-48e2-ab1b-c57f530ca3c3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928615410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.2928615410 |
Directory | /workspace/16.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/16.otp_ctrl_check_fail.1580291245 |
Short name | T978 |
Test name | |
Test status | |
Simulation time | 2306447730 ps |
CPU time | 14.55 seconds |
Started | Mar 31 03:29:54 PM PDT 24 |
Finished | Mar 31 03:30:08 PM PDT 24 |
Peak memory | 242048 kb |
Host | smart-7fd5f063-0945-4521-af2b-270f5bb35fc8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1580291245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.1580291245 |
Directory | /workspace/16.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/16.otp_ctrl_dai_errs.2167805838 |
Short name | T1007 |
Test name | |
Test status | |
Simulation time | 1331260413 ps |
CPU time | 18.82 seconds |
Started | Mar 31 03:29:52 PM PDT 24 |
Finished | Mar 31 03:30:11 PM PDT 24 |
Peak memory | 242224 kb |
Host | smart-7ceff7dd-ebf2-488d-88ae-d4c66e324bbb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2167805838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.2167805838 |
Directory | /workspace/16.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/16.otp_ctrl_dai_lock.709366713 |
Short name | T1172 |
Test name | |
Test status | |
Simulation time | 1661135972 ps |
CPU time | 14.28 seconds |
Started | Mar 31 03:29:53 PM PDT 24 |
Finished | Mar 31 03:30:07 PM PDT 24 |
Peak memory | 241748 kb |
Host | smart-d063683c-d30d-45c6-88ca-a860cb89b8c3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=709366713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.709366713 |
Directory | /workspace/16.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/16.otp_ctrl_macro_errs.1907856799 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 1843115074 ps |
CPU time | 13.27 seconds |
Started | Mar 31 03:29:52 PM PDT 24 |
Finished | Mar 31 03:30:05 PM PDT 24 |
Peak memory | 242068 kb |
Host | smart-30443b1a-ad9d-4bc1-9f5d-3f4e24f59bd3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1907856799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.1907856799 |
Directory | /workspace/16.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/16.otp_ctrl_parallel_key_req.4161942332 |
Short name | T491 |
Test name | |
Test status | |
Simulation time | 12963424156 ps |
CPU time | 27.85 seconds |
Started | Mar 31 03:29:53 PM PDT 24 |
Finished | Mar 31 03:30:21 PM PDT 24 |
Peak memory | 243168 kb |
Host | smart-6d793ed9-d4a3-41c5-8282-c4a851268c0b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4161942332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.4161942332 |
Directory | /workspace/16.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/16.otp_ctrl_parallel_lc_esc.3889896310 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 523516286 ps |
CPU time | 7.08 seconds |
Started | Mar 31 03:29:53 PM PDT 24 |
Finished | Mar 31 03:30:00 PM PDT 24 |
Peak memory | 241684 kb |
Host | smart-dd6d984a-c97d-4698-99ec-0a66814917c6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3889896310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.3889896310 |
Directory | /workspace/16.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/16.otp_ctrl_parallel_lc_req.2796310594 |
Short name | T672 |
Test name | |
Test status | |
Simulation time | 2159036859 ps |
CPU time | 17.8 seconds |
Started | Mar 31 03:29:47 PM PDT 24 |
Finished | Mar 31 03:30:05 PM PDT 24 |
Peak memory | 241844 kb |
Host | smart-e4669cb6-02e8-4c41-a2d0-06d174d4e562 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2796310594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_req.2796310594 |
Directory | /workspace/16.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/16.otp_ctrl_regwen.1450905570 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 91825603 ps |
CPU time | 3.29 seconds |
Started | Mar 31 03:29:54 PM PDT 24 |
Finished | Mar 31 03:29:57 PM PDT 24 |
Peak memory | 241556 kb |
Host | smart-134093b2-8edb-48b7-b91a-b9b64ca3856b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1450905570 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.1450905570 |
Directory | /workspace/16.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/16.otp_ctrl_smoke.1262711317 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 2473735368 ps |
CPU time | 23.09 seconds |
Started | Mar 31 03:29:46 PM PDT 24 |
Finished | Mar 31 03:30:09 PM PDT 24 |
Peak memory | 241592 kb |
Host | smart-e0b41498-6bd8-4057-983e-21de11649994 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1262711317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_smoke.1262711317 |
Directory | /workspace/16.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/16.otp_ctrl_stress_all.1549455931 |
Short name | T836 |
Test name | |
Test status | |
Simulation time | 11937055633 ps |
CPU time | 70.71 seconds |
Started | Mar 31 03:29:53 PM PDT 24 |
Finished | Mar 31 03:31:04 PM PDT 24 |
Peak memory | 244428 kb |
Host | smart-b664fe08-e590-4784-908e-5b8999775d26 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549455931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all .1549455931 |
Directory | /workspace/16.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/16.otp_ctrl_stress_all_with_rand_reset.2400109654 |
Short name | T604 |
Test name | |
Test status | |
Simulation time | 96190067750 ps |
CPU time | 1178.82 seconds |
Started | Mar 31 03:29:54 PM PDT 24 |
Finished | Mar 31 03:49:33 PM PDT 24 |
Peak memory | 313048 kb |
Host | smart-2b0de2c2-b44d-4024-a31b-33525116c854 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400109654 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all_with_rand_reset.2400109654 |
Directory | /workspace/16.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/16.otp_ctrl_test_access.1978862854 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 2328732779 ps |
CPU time | 28.1 seconds |
Started | Mar 31 03:29:52 PM PDT 24 |
Finished | Mar 31 03:30:20 PM PDT 24 |
Peak memory | 242156 kb |
Host | smart-c7a01b9b-b447-4ed9-a0ec-3380a3d0e0fe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1978862854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.1978862854 |
Directory | /workspace/16.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/160.otp_ctrl_init_fail.2775829807 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 582290152 ps |
CPU time | 4.11 seconds |
Started | Mar 31 03:33:29 PM PDT 24 |
Finished | Mar 31 03:33:33 PM PDT 24 |
Peak memory | 241924 kb |
Host | smart-9365b13a-0772-4a41-b1b1-b15dd94738a4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2775829807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.2775829807 |
Directory | /workspace/160.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/160.otp_ctrl_parallel_lc_esc.1540177466 |
Short name | T927 |
Test name | |
Test status | |
Simulation time | 428090618 ps |
CPU time | 10.94 seconds |
Started | Mar 31 03:33:23 PM PDT 24 |
Finished | Mar 31 03:33:34 PM PDT 24 |
Peak memory | 241640 kb |
Host | smart-96991326-39f8-4d99-a57f-aba4a1f1947e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1540177466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.1540177466 |
Directory | /workspace/160.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/161.otp_ctrl_init_fail.3386018320 |
Short name | T706 |
Test name | |
Test status | |
Simulation time | 178823019 ps |
CPU time | 4.39 seconds |
Started | Mar 31 03:33:22 PM PDT 24 |
Finished | Mar 31 03:33:26 PM PDT 24 |
Peak memory | 241828 kb |
Host | smart-12e76baf-c402-4ace-a24f-35204bf82f24 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3386018320 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.3386018320 |
Directory | /workspace/161.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/161.otp_ctrl_parallel_lc_esc.582600152 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 6175983682 ps |
CPU time | 21.12 seconds |
Started | Mar 31 03:33:26 PM PDT 24 |
Finished | Mar 31 03:33:47 PM PDT 24 |
Peak memory | 242088 kb |
Host | smart-635bbde7-19e6-4abe-95be-a1867bef4ae4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=582600152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.582600152 |
Directory | /workspace/161.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/162.otp_ctrl_init_fail.1078016355 |
Short name | T479 |
Test name | |
Test status | |
Simulation time | 133453142 ps |
CPU time | 3.88 seconds |
Started | Mar 31 03:33:25 PM PDT 24 |
Finished | Mar 31 03:33:29 PM PDT 24 |
Peak memory | 242028 kb |
Host | smart-ecca44a2-5b88-414d-bebd-440c51333a51 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1078016355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.1078016355 |
Directory | /workspace/162.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/162.otp_ctrl_parallel_lc_esc.2788315980 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 359698013 ps |
CPU time | 6.44 seconds |
Started | Mar 31 03:33:22 PM PDT 24 |
Finished | Mar 31 03:33:29 PM PDT 24 |
Peak memory | 241772 kb |
Host | smart-a244ee90-25bd-4238-aed9-e3727397c513 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2788315980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.2788315980 |
Directory | /workspace/162.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/163.otp_ctrl_init_fail.1975197961 |
Short name | T828 |
Test name | |
Test status | |
Simulation time | 182750493 ps |
CPU time | 4.37 seconds |
Started | Mar 31 03:33:25 PM PDT 24 |
Finished | Mar 31 03:33:30 PM PDT 24 |
Peak memory | 241740 kb |
Host | smart-017d8827-829c-4405-b9d3-b0fec638f0a2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1975197961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.1975197961 |
Directory | /workspace/163.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/164.otp_ctrl_init_fail.3453390506 |
Short name | T1189 |
Test name | |
Test status | |
Simulation time | 300089663 ps |
CPU time | 4.55 seconds |
Started | Mar 31 03:33:28 PM PDT 24 |
Finished | Mar 31 03:33:33 PM PDT 24 |
Peak memory | 242084 kb |
Host | smart-4c289a7a-fccc-46dc-930a-c146a25e1ba3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3453390506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.3453390506 |
Directory | /workspace/164.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/164.otp_ctrl_parallel_lc_esc.170212068 |
Short name | T806 |
Test name | |
Test status | |
Simulation time | 422454418 ps |
CPU time | 2.75 seconds |
Started | Mar 31 03:33:22 PM PDT 24 |
Finished | Mar 31 03:33:25 PM PDT 24 |
Peak memory | 241624 kb |
Host | smart-58d4d653-ffd4-472c-a259-59fd670b3c91 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=170212068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.170212068 |
Directory | /workspace/164.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/165.otp_ctrl_init_fail.3881858938 |
Short name | T967 |
Test name | |
Test status | |
Simulation time | 209068925 ps |
CPU time | 4.02 seconds |
Started | Mar 31 03:33:28 PM PDT 24 |
Finished | Mar 31 03:33:32 PM PDT 24 |
Peak memory | 242080 kb |
Host | smart-33b457b0-24a4-44a7-a568-7f17e77e2152 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3881858938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.3881858938 |
Directory | /workspace/165.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/165.otp_ctrl_parallel_lc_esc.3605118702 |
Short name | T1117 |
Test name | |
Test status | |
Simulation time | 3741441362 ps |
CPU time | 15.09 seconds |
Started | Mar 31 03:33:28 PM PDT 24 |
Finished | Mar 31 03:33:43 PM PDT 24 |
Peak memory | 241516 kb |
Host | smart-b90bd9fd-d333-4401-8e5a-54047fbbe8bc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3605118702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.3605118702 |
Directory | /workspace/165.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/166.otp_ctrl_init_fail.389297910 |
Short name | T685 |
Test name | |
Test status | |
Simulation time | 1954947967 ps |
CPU time | 4.76 seconds |
Started | Mar 31 03:33:34 PM PDT 24 |
Finished | Mar 31 03:33:39 PM PDT 24 |
Peak memory | 241748 kb |
Host | smart-716a56ca-f104-498f-a447-07437f9e0ac9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=389297910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.389297910 |
Directory | /workspace/166.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/167.otp_ctrl_init_fail.3561199054 |
Short name | T976 |
Test name | |
Test status | |
Simulation time | 2458656755 ps |
CPU time | 4.7 seconds |
Started | Mar 31 03:33:29 PM PDT 24 |
Finished | Mar 31 03:33:34 PM PDT 24 |
Peak memory | 241736 kb |
Host | smart-7734ea85-3e84-4223-bdaf-961d606fcca2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3561199054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.3561199054 |
Directory | /workspace/167.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/167.otp_ctrl_parallel_lc_esc.2442497454 |
Short name | T793 |
Test name | |
Test status | |
Simulation time | 163183939 ps |
CPU time | 4.95 seconds |
Started | Mar 31 03:33:28 PM PDT 24 |
Finished | Mar 31 03:33:33 PM PDT 24 |
Peak memory | 241624 kb |
Host | smart-064430c4-6948-4e4b-bcc6-4f5e6d118255 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2442497454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.2442497454 |
Directory | /workspace/167.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/168.otp_ctrl_init_fail.2917784528 |
Short name | T568 |
Test name | |
Test status | |
Simulation time | 657873256 ps |
CPU time | 4.48 seconds |
Started | Mar 31 03:33:27 PM PDT 24 |
Finished | Mar 31 03:33:32 PM PDT 24 |
Peak memory | 241880 kb |
Host | smart-cc73b496-d636-47bd-95c3-907d3649ea3b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2917784528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.2917784528 |
Directory | /workspace/168.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/168.otp_ctrl_parallel_lc_esc.3722450281 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 1350176307 ps |
CPU time | 4.65 seconds |
Started | Mar 31 03:33:33 PM PDT 24 |
Finished | Mar 31 03:33:38 PM PDT 24 |
Peak memory | 241628 kb |
Host | smart-f04cdcdb-8f83-4779-bf4b-8cc2da86e9e5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3722450281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.3722450281 |
Directory | /workspace/168.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/169.otp_ctrl_init_fail.831390213 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 143302064 ps |
CPU time | 4.11 seconds |
Started | Mar 31 03:33:33 PM PDT 24 |
Finished | Mar 31 03:33:38 PM PDT 24 |
Peak memory | 242068 kb |
Host | smart-2eb31544-0f55-41ba-a1f7-adab94f49d4f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=831390213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.831390213 |
Directory | /workspace/169.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/17.otp_ctrl_alert_test.3056588522 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 1046859446 ps |
CPU time | 2.25 seconds |
Started | Mar 31 03:29:56 PM PDT 24 |
Finished | Mar 31 03:29:58 PM PDT 24 |
Peak memory | 240220 kb |
Host | smart-d58cf2f8-6e6a-47e6-8fd7-0949f830228a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056588522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.3056588522 |
Directory | /workspace/17.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/17.otp_ctrl_check_fail.67460416 |
Short name | T642 |
Test name | |
Test status | |
Simulation time | 1871703365 ps |
CPU time | 26.78 seconds |
Started | Mar 31 03:29:53 PM PDT 24 |
Finished | Mar 31 03:30:20 PM PDT 24 |
Peak memory | 242684 kb |
Host | smart-592444a5-86ca-4b9f-b97e-84e8bc06b774 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=67460416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.67460416 |
Directory | /workspace/17.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/17.otp_ctrl_dai_errs.1197056876 |
Short name | T1046 |
Test name | |
Test status | |
Simulation time | 404862197 ps |
CPU time | 16 seconds |
Started | Mar 31 03:29:52 PM PDT 24 |
Finished | Mar 31 03:30:08 PM PDT 24 |
Peak memory | 241388 kb |
Host | smart-990feaa4-0a08-4a9d-bef5-48efe9dd8fe3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1197056876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.1197056876 |
Directory | /workspace/17.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/17.otp_ctrl_dai_lock.3810711306 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 584538227 ps |
CPU time | 16.1 seconds |
Started | Mar 31 03:29:52 PM PDT 24 |
Finished | Mar 31 03:30:08 PM PDT 24 |
Peak memory | 242136 kb |
Host | smart-159fecba-af17-4080-9966-f90e42645d28 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3810711306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.3810711306 |
Directory | /workspace/17.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/17.otp_ctrl_init_fail.3342531033 |
Short name | T528 |
Test name | |
Test status | |
Simulation time | 324029044 ps |
CPU time | 4.41 seconds |
Started | Mar 31 03:29:52 PM PDT 24 |
Finished | Mar 31 03:29:56 PM PDT 24 |
Peak memory | 241920 kb |
Host | smart-99711de0-6423-4fd5-815b-1fbefd71154a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3342531033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.3342531033 |
Directory | /workspace/17.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/17.otp_ctrl_macro_errs.3763439581 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 11031507516 ps |
CPU time | 34.91 seconds |
Started | Mar 31 03:29:53 PM PDT 24 |
Finished | Mar 31 03:30:27 PM PDT 24 |
Peak memory | 244860 kb |
Host | smart-937930ab-dc88-4544-ac0c-64d3c23b3586 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3763439581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.3763439581 |
Directory | /workspace/17.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/17.otp_ctrl_parallel_key_req.2598109025 |
Short name | T1182 |
Test name | |
Test status | |
Simulation time | 1253212384 ps |
CPU time | 30.78 seconds |
Started | Mar 31 03:29:51 PM PDT 24 |
Finished | Mar 31 03:30:22 PM PDT 24 |
Peak memory | 242184 kb |
Host | smart-386e2eca-1408-4f33-b139-958738ff8b68 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2598109025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.2598109025 |
Directory | /workspace/17.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/17.otp_ctrl_parallel_lc_esc.3385418100 |
Short name | T509 |
Test name | |
Test status | |
Simulation time | 635660336 ps |
CPU time | 5.62 seconds |
Started | Mar 31 03:29:54 PM PDT 24 |
Finished | Mar 31 03:30:00 PM PDT 24 |
Peak memory | 241760 kb |
Host | smart-4a5970a8-546a-4204-8b6c-9c4539e91d34 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3385418100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.3385418100 |
Directory | /workspace/17.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/17.otp_ctrl_parallel_lc_req.1394897189 |
Short name | T606 |
Test name | |
Test status | |
Simulation time | 194160136 ps |
CPU time | 5.04 seconds |
Started | Mar 31 03:29:53 PM PDT 24 |
Finished | Mar 31 03:29:58 PM PDT 24 |
Peak memory | 241612 kb |
Host | smart-3d5a8300-7d76-48c9-a008-efbf54f3fc57 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1394897189 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.1394897189 |
Directory | /workspace/17.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/17.otp_ctrl_regwen.2185898790 |
Short name | T1176 |
Test name | |
Test status | |
Simulation time | 169778426 ps |
CPU time | 6.07 seconds |
Started | Mar 31 03:29:54 PM PDT 24 |
Finished | Mar 31 03:30:00 PM PDT 24 |
Peak memory | 241608 kb |
Host | smart-fe7d6ec2-1865-415b-8c19-07f80f2a9bef |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2185898790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.2185898790 |
Directory | /workspace/17.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/17.otp_ctrl_smoke.3435281742 |
Short name | T703 |
Test name | |
Test status | |
Simulation time | 167839220 ps |
CPU time | 6.12 seconds |
Started | Mar 31 03:29:53 PM PDT 24 |
Finished | Mar 31 03:30:00 PM PDT 24 |
Peak memory | 242044 kb |
Host | smart-4a1eb3ab-8594-434b-b579-e2c141186db9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3435281742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.3435281742 |
Directory | /workspace/17.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/17.otp_ctrl_stress_all.2964072458 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 19268527838 ps |
CPU time | 296.85 seconds |
Started | Mar 31 03:30:00 PM PDT 24 |
Finished | Mar 31 03:34:57 PM PDT 24 |
Peak memory | 260076 kb |
Host | smart-56fba173-7f05-4ef1-9591-5966991f5e59 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964072458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all .2964072458 |
Directory | /workspace/17.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/17.otp_ctrl_stress_all_with_rand_reset.2755577822 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 87765586842 ps |
CPU time | 536.52 seconds |
Started | Mar 31 03:29:58 PM PDT 24 |
Finished | Mar 31 03:38:55 PM PDT 24 |
Peak memory | 375044 kb |
Host | smart-07083eed-3425-4706-9976-edf0f817e7ce |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755577822 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all_with_rand_reset.2755577822 |
Directory | /workspace/17.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/17.otp_ctrl_test_access.3929494408 |
Short name | T472 |
Test name | |
Test status | |
Simulation time | 2540594276 ps |
CPU time | 18.57 seconds |
Started | Mar 31 03:29:59 PM PDT 24 |
Finished | Mar 31 03:30:17 PM PDT 24 |
Peak memory | 241832 kb |
Host | smart-d0b04f1d-a4fd-47b7-900b-90d8ed90b0ea |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3929494408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.3929494408 |
Directory | /workspace/17.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/170.otp_ctrl_init_fail.3497617203 |
Short name | T677 |
Test name | |
Test status | |
Simulation time | 178498936 ps |
CPU time | 4.24 seconds |
Started | Mar 31 03:33:30 PM PDT 24 |
Finished | Mar 31 03:33:34 PM PDT 24 |
Peak memory | 241780 kb |
Host | smart-ce25c07d-b03f-4744-a06b-0b7d3df35d02 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3497617203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.3497617203 |
Directory | /workspace/170.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/170.otp_ctrl_parallel_lc_esc.2992997335 |
Short name | T987 |
Test name | |
Test status | |
Simulation time | 581882774 ps |
CPU time | 7.19 seconds |
Started | Mar 31 03:33:28 PM PDT 24 |
Finished | Mar 31 03:33:35 PM PDT 24 |
Peak memory | 241608 kb |
Host | smart-855a97af-daa4-4f80-a8c3-dfa7bca699af |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2992997335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.2992997335 |
Directory | /workspace/170.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/171.otp_ctrl_init_fail.2080108636 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 2015198604 ps |
CPU time | 3.78 seconds |
Started | Mar 31 03:33:29 PM PDT 24 |
Finished | Mar 31 03:33:33 PM PDT 24 |
Peak memory | 241808 kb |
Host | smart-ff298f4f-c545-4eb3-aefb-5f2ca4e8d5f6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2080108636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.2080108636 |
Directory | /workspace/171.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/171.otp_ctrl_parallel_lc_esc.126764641 |
Short name | T637 |
Test name | |
Test status | |
Simulation time | 352920151 ps |
CPU time | 11.01 seconds |
Started | Mar 31 03:33:33 PM PDT 24 |
Finished | Mar 31 03:33:44 PM PDT 24 |
Peak memory | 241704 kb |
Host | smart-61df9b79-f0d5-494d-9216-3ac2fee9e66e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=126764641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.126764641 |
Directory | /workspace/171.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/172.otp_ctrl_init_fail.958461090 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 347716818 ps |
CPU time | 3.47 seconds |
Started | Mar 31 03:33:36 PM PDT 24 |
Finished | Mar 31 03:33:40 PM PDT 24 |
Peak memory | 241816 kb |
Host | smart-e8a1b65f-0e44-4772-aac4-0429fcbe3515 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=958461090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.958461090 |
Directory | /workspace/172.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/172.otp_ctrl_parallel_lc_esc.3545783647 |
Short name | T862 |
Test name | |
Test status | |
Simulation time | 93869217 ps |
CPU time | 3.73 seconds |
Started | Mar 31 03:33:34 PM PDT 24 |
Finished | Mar 31 03:33:39 PM PDT 24 |
Peak memory | 241620 kb |
Host | smart-dd1a91f7-0cdb-4bb3-98ed-5c522f2f055a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3545783647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.3545783647 |
Directory | /workspace/172.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/173.otp_ctrl_init_fail.2370324278 |
Short name | T1113 |
Test name | |
Test status | |
Simulation time | 146306973 ps |
CPU time | 3.11 seconds |
Started | Mar 31 03:33:35 PM PDT 24 |
Finished | Mar 31 03:33:38 PM PDT 24 |
Peak memory | 241552 kb |
Host | smart-d3134455-48cd-45e5-a39f-5dad78f1ef55 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2370324278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.2370324278 |
Directory | /workspace/173.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/173.otp_ctrl_parallel_lc_esc.2847649068 |
Short name | T444 |
Test name | |
Test status | |
Simulation time | 155349328 ps |
CPU time | 4.09 seconds |
Started | Mar 31 03:33:33 PM PDT 24 |
Finished | Mar 31 03:33:37 PM PDT 24 |
Peak memory | 241708 kb |
Host | smart-6f96b83e-ed0b-4413-9858-ad7e7a50961b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2847649068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.2847649068 |
Directory | /workspace/173.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/174.otp_ctrl_init_fail.2283003085 |
Short name | T441 |
Test name | |
Test status | |
Simulation time | 2415455825 ps |
CPU time | 6.67 seconds |
Started | Mar 31 03:33:34 PM PDT 24 |
Finished | Mar 31 03:33:41 PM PDT 24 |
Peak memory | 241728 kb |
Host | smart-3d8ca76b-b8a2-441d-9201-afbe5858c4a3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2283003085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.2283003085 |
Directory | /workspace/174.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/174.otp_ctrl_parallel_lc_esc.1214146473 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 165510933 ps |
CPU time | 5.33 seconds |
Started | Mar 31 03:33:33 PM PDT 24 |
Finished | Mar 31 03:33:39 PM PDT 24 |
Peak memory | 241616 kb |
Host | smart-9f40b70e-bbc5-421a-999f-558e36392174 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1214146473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.1214146473 |
Directory | /workspace/174.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/175.otp_ctrl_init_fail.980359683 |
Short name | T480 |
Test name | |
Test status | |
Simulation time | 265652871 ps |
CPU time | 3.7 seconds |
Started | Mar 31 03:33:35 PM PDT 24 |
Finished | Mar 31 03:33:39 PM PDT 24 |
Peak memory | 242000 kb |
Host | smart-a1c62e8d-fd5c-4413-b6d6-b38f452dda49 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=980359683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.980359683 |
Directory | /workspace/175.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/175.otp_ctrl_parallel_lc_esc.4033069960 |
Short name | T752 |
Test name | |
Test status | |
Simulation time | 633818054 ps |
CPU time | 5.78 seconds |
Started | Mar 31 03:33:33 PM PDT 24 |
Finished | Mar 31 03:33:39 PM PDT 24 |
Peak memory | 241740 kb |
Host | smart-ffdd214e-f640-4de3-bd65-96d4119c8677 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4033069960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.4033069960 |
Directory | /workspace/175.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/176.otp_ctrl_init_fail.2225260152 |
Short name | T1036 |
Test name | |
Test status | |
Simulation time | 375075260 ps |
CPU time | 3.32 seconds |
Started | Mar 31 03:33:34 PM PDT 24 |
Finished | Mar 31 03:33:37 PM PDT 24 |
Peak memory | 241924 kb |
Host | smart-26c6f240-9ce6-4544-8f75-75e2fb94463e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2225260152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.2225260152 |
Directory | /workspace/176.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/176.otp_ctrl_parallel_lc_esc.3739528734 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 1485990119 ps |
CPU time | 5.95 seconds |
Started | Mar 31 03:33:34 PM PDT 24 |
Finished | Mar 31 03:33:40 PM PDT 24 |
Peak memory | 241656 kb |
Host | smart-fa9ff669-6ff8-4777-a772-dc54616bce46 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3739528734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.3739528734 |
Directory | /workspace/176.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/177.otp_ctrl_init_fail.4281643376 |
Short name | T772 |
Test name | |
Test status | |
Simulation time | 336930181 ps |
CPU time | 4.82 seconds |
Started | Mar 31 03:33:35 PM PDT 24 |
Finished | Mar 31 03:33:41 PM PDT 24 |
Peak memory | 241760 kb |
Host | smart-c7bf153a-e1de-4e99-982a-b761a5606c0f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4281643376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.4281643376 |
Directory | /workspace/177.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/177.otp_ctrl_parallel_lc_esc.1924376550 |
Short name | T511 |
Test name | |
Test status | |
Simulation time | 112777088 ps |
CPU time | 3.71 seconds |
Started | Mar 31 03:33:33 PM PDT 24 |
Finished | Mar 31 03:33:37 PM PDT 24 |
Peak memory | 241664 kb |
Host | smart-309162cf-db94-4f50-88a6-93418f1f4d0d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1924376550 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.1924376550 |
Directory | /workspace/177.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/178.otp_ctrl_init_fail.423191809 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 389076739 ps |
CPU time | 3.72 seconds |
Started | Mar 31 03:33:36 PM PDT 24 |
Finished | Mar 31 03:33:40 PM PDT 24 |
Peak memory | 241772 kb |
Host | smart-ad4f06ad-f133-404e-a44c-22f4deacb34f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=423191809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.423191809 |
Directory | /workspace/178.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/178.otp_ctrl_parallel_lc_esc.189812196 |
Short name | T691 |
Test name | |
Test status | |
Simulation time | 1273381568 ps |
CPU time | 26.51 seconds |
Started | Mar 31 03:33:36 PM PDT 24 |
Finished | Mar 31 03:34:02 PM PDT 24 |
Peak memory | 242028 kb |
Host | smart-613dc486-cd16-4ae8-bdb1-a568d9bb44d4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=189812196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.189812196 |
Directory | /workspace/178.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/179.otp_ctrl_init_fail.914414456 |
Short name | T964 |
Test name | |
Test status | |
Simulation time | 219328580 ps |
CPU time | 4.78 seconds |
Started | Mar 31 03:33:34 PM PDT 24 |
Finished | Mar 31 03:33:39 PM PDT 24 |
Peak memory | 241704 kb |
Host | smart-c4e72bb6-c0f8-4a9f-984b-426faaf83a30 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=914414456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.914414456 |
Directory | /workspace/179.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/179.otp_ctrl_parallel_lc_esc.3063902476 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 118040027 ps |
CPU time | 3.09 seconds |
Started | Mar 31 03:33:34 PM PDT 24 |
Finished | Mar 31 03:33:38 PM PDT 24 |
Peak memory | 241616 kb |
Host | smart-5a64ddf5-9b5b-4885-805e-e4be8ad56740 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3063902476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.3063902476 |
Directory | /workspace/179.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/18.otp_ctrl_alert_test.3497166080 |
Short name | T542 |
Test name | |
Test status | |
Simulation time | 84994502 ps |
CPU time | 2.14 seconds |
Started | Mar 31 03:30:02 PM PDT 24 |
Finished | Mar 31 03:30:04 PM PDT 24 |
Peak memory | 240088 kb |
Host | smart-75939260-85a0-487b-8683-23605623eeea |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497166080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.3497166080 |
Directory | /workspace/18.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/18.otp_ctrl_check_fail.1575183982 |
Short name | T952 |
Test name | |
Test status | |
Simulation time | 955542296 ps |
CPU time | 17.53 seconds |
Started | Mar 31 03:29:57 PM PDT 24 |
Finished | Mar 31 03:30:14 PM PDT 24 |
Peak memory | 243400 kb |
Host | smart-d118492c-5b06-4eb4-8e20-87fd5e860c80 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1575183982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.1575183982 |
Directory | /workspace/18.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/18.otp_ctrl_dai_errs.2970613077 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 839922192 ps |
CPU time | 25.26 seconds |
Started | Mar 31 03:29:56 PM PDT 24 |
Finished | Mar 31 03:30:22 PM PDT 24 |
Peak memory | 241752 kb |
Host | smart-f0925c91-5e1f-4d1b-b0fe-fc8d337e8dea |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2970613077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.2970613077 |
Directory | /workspace/18.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/18.otp_ctrl_dai_lock.1077910448 |
Short name | T490 |
Test name | |
Test status | |
Simulation time | 1222158506 ps |
CPU time | 13.08 seconds |
Started | Mar 31 03:29:58 PM PDT 24 |
Finished | Mar 31 03:30:11 PM PDT 24 |
Peak memory | 241948 kb |
Host | smart-5477e2c6-c214-4a6a-87cd-2135a80ff3e8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1077910448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.1077910448 |
Directory | /workspace/18.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/18.otp_ctrl_init_fail.1793708125 |
Short name | T624 |
Test name | |
Test status | |
Simulation time | 499417404 ps |
CPU time | 5.49 seconds |
Started | Mar 31 03:29:57 PM PDT 24 |
Finished | Mar 31 03:30:03 PM PDT 24 |
Peak memory | 241716 kb |
Host | smart-aa00afe9-cf6d-498c-b1d2-4324487a06ae |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1793708125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.1793708125 |
Directory | /workspace/18.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/18.otp_ctrl_macro_errs.3590488154 |
Short name | T456 |
Test name | |
Test status | |
Simulation time | 1135349227 ps |
CPU time | 12.92 seconds |
Started | Mar 31 03:29:56 PM PDT 24 |
Finished | Mar 31 03:30:09 PM PDT 24 |
Peak memory | 241816 kb |
Host | smart-9272aa6a-039f-43ea-b07f-238ef435b263 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3590488154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.3590488154 |
Directory | /workspace/18.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/18.otp_ctrl_parallel_key_req.2591858746 |
Short name | T629 |
Test name | |
Test status | |
Simulation time | 577238407 ps |
CPU time | 12.2 seconds |
Started | Mar 31 03:29:57 PM PDT 24 |
Finished | Mar 31 03:30:09 PM PDT 24 |
Peak memory | 241928 kb |
Host | smart-b742e9ca-8790-437e-aa96-58eb58a2b45f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2591858746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.2591858746 |
Directory | /workspace/18.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/18.otp_ctrl_parallel_lc_esc.2562788559 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 651420971 ps |
CPU time | 8.83 seconds |
Started | Mar 31 03:30:00 PM PDT 24 |
Finished | Mar 31 03:30:09 PM PDT 24 |
Peak memory | 241072 kb |
Host | smart-8f05d87a-742f-4cd4-9379-4d5379c6a90c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2562788559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.2562788559 |
Directory | /workspace/18.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/18.otp_ctrl_parallel_lc_req.1923566211 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 605342160 ps |
CPU time | 9.31 seconds |
Started | Mar 31 03:29:59 PM PDT 24 |
Finished | Mar 31 03:30:08 PM PDT 24 |
Peak memory | 241688 kb |
Host | smart-5314567e-54dc-4647-a34a-55cde0ca2408 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1923566211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.1923566211 |
Directory | /workspace/18.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/18.otp_ctrl_regwen.1634885642 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 278598566 ps |
CPU time | 6.11 seconds |
Started | Mar 31 03:30:01 PM PDT 24 |
Finished | Mar 31 03:30:07 PM PDT 24 |
Peak memory | 241824 kb |
Host | smart-eff778d6-40b7-4537-8c39-9331d37a8be1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1634885642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.1634885642 |
Directory | /workspace/18.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/18.otp_ctrl_smoke.903924903 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 394704185 ps |
CPU time | 9.38 seconds |
Started | Mar 31 03:30:00 PM PDT 24 |
Finished | Mar 31 03:30:10 PM PDT 24 |
Peak memory | 241692 kb |
Host | smart-7cd6ed07-502c-40dd-ae70-ed99efa5ebb9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=903924903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.903924903 |
Directory | /workspace/18.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/18.otp_ctrl_stress_all.3848553703 |
Short name | T741 |
Test name | |
Test status | |
Simulation time | 156760770143 ps |
CPU time | 297.61 seconds |
Started | Mar 31 03:30:04 PM PDT 24 |
Finished | Mar 31 03:35:01 PM PDT 24 |
Peak memory | 273380 kb |
Host | smart-35cbdee6-c982-4b21-83f4-8128868689f7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848553703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all .3848553703 |
Directory | /workspace/18.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/18.otp_ctrl_test_access.3057935293 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 507617580 ps |
CPU time | 8.36 seconds |
Started | Mar 31 03:30:00 PM PDT 24 |
Finished | Mar 31 03:30:09 PM PDT 24 |
Peak memory | 240928 kb |
Host | smart-d807d679-682e-476d-8fe6-f4aacf3c2083 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3057935293 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.3057935293 |
Directory | /workspace/18.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/180.otp_ctrl_init_fail.3897962013 |
Short name | T991 |
Test name | |
Test status | |
Simulation time | 539287593 ps |
CPU time | 4.66 seconds |
Started | Mar 31 03:33:35 PM PDT 24 |
Finished | Mar 31 03:33:40 PM PDT 24 |
Peak memory | 241788 kb |
Host | smart-d0c8104b-a80e-405f-b8d1-bc46b544873c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3897962013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.3897962013 |
Directory | /workspace/180.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/180.otp_ctrl_parallel_lc_esc.3766665318 |
Short name | T720 |
Test name | |
Test status | |
Simulation time | 1819334174 ps |
CPU time | 7.48 seconds |
Started | Mar 31 03:33:42 PM PDT 24 |
Finished | Mar 31 03:33:50 PM PDT 24 |
Peak memory | 241520 kb |
Host | smart-41a3756d-af70-4dd2-a0a6-5fb10dfdafc0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3766665318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.3766665318 |
Directory | /workspace/180.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/181.otp_ctrl_init_fail.2456191382 |
Short name | T963 |
Test name | |
Test status | |
Simulation time | 1821140934 ps |
CPU time | 5.25 seconds |
Started | Mar 31 03:33:41 PM PDT 24 |
Finished | Mar 31 03:33:47 PM PDT 24 |
Peak memory | 242048 kb |
Host | smart-9ea927b1-a797-42f8-bf4c-22357d5ea09f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2456191382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.2456191382 |
Directory | /workspace/181.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/181.otp_ctrl_parallel_lc_esc.2387540200 |
Short name | T467 |
Test name | |
Test status | |
Simulation time | 319145443 ps |
CPU time | 3.98 seconds |
Started | Mar 31 03:33:39 PM PDT 24 |
Finished | Mar 31 03:33:44 PM PDT 24 |
Peak memory | 241576 kb |
Host | smart-e02b941c-3f56-4980-ac87-f64b9311a9a0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2387540200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.2387540200 |
Directory | /workspace/181.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/182.otp_ctrl_parallel_lc_esc.689548759 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 122039214 ps |
CPU time | 3.26 seconds |
Started | Mar 31 03:33:40 PM PDT 24 |
Finished | Mar 31 03:33:44 PM PDT 24 |
Peak memory | 241720 kb |
Host | smart-e354e74a-5b82-4b5f-b11a-bef7bed5723b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=689548759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.689548759 |
Directory | /workspace/182.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/183.otp_ctrl_init_fail.2762001545 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 1782397045 ps |
CPU time | 4.68 seconds |
Started | Mar 31 03:33:41 PM PDT 24 |
Finished | Mar 31 03:33:46 PM PDT 24 |
Peak memory | 242052 kb |
Host | smart-4e63be17-24d2-4afc-8b60-145e3f4560b4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2762001545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.2762001545 |
Directory | /workspace/183.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/184.otp_ctrl_init_fail.2507073102 |
Short name | T810 |
Test name | |
Test status | |
Simulation time | 164949578 ps |
CPU time | 4.56 seconds |
Started | Mar 31 03:33:45 PM PDT 24 |
Finished | Mar 31 03:33:50 PM PDT 24 |
Peak memory | 241692 kb |
Host | smart-b1005117-a705-4bdd-b289-522a31495fb3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2507073102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.2507073102 |
Directory | /workspace/184.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/184.otp_ctrl_parallel_lc_esc.541443237 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 201018980 ps |
CPU time | 5.52 seconds |
Started | Mar 31 03:33:47 PM PDT 24 |
Finished | Mar 31 03:33:53 PM PDT 24 |
Peak memory | 241680 kb |
Host | smart-837ae3d9-ede3-4b70-bc9a-b7100417ce1d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=541443237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.541443237 |
Directory | /workspace/184.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/185.otp_ctrl_init_fail.3665713620 |
Short name | T850 |
Test name | |
Test status | |
Simulation time | 149925821 ps |
CPU time | 4.33 seconds |
Started | Mar 31 03:33:42 PM PDT 24 |
Finished | Mar 31 03:33:47 PM PDT 24 |
Peak memory | 241804 kb |
Host | smart-3319506c-cbb7-4b5f-84eb-7029ffc61dc5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3665713620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.3665713620 |
Directory | /workspace/185.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/185.otp_ctrl_parallel_lc_esc.2093806661 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 2911407826 ps |
CPU time | 25.45 seconds |
Started | Mar 31 03:33:47 PM PDT 24 |
Finished | Mar 31 03:34:13 PM PDT 24 |
Peak memory | 241748 kb |
Host | smart-fd4324fa-77de-4c23-a185-f49a0f5abf17 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2093806661 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.2093806661 |
Directory | /workspace/185.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/186.otp_ctrl_parallel_lc_esc.1071220552 |
Short name | T577 |
Test name | |
Test status | |
Simulation time | 213495536 ps |
CPU time | 5.25 seconds |
Started | Mar 31 03:33:40 PM PDT 24 |
Finished | Mar 31 03:33:45 PM PDT 24 |
Peak memory | 241844 kb |
Host | smart-4e346f55-e7c2-4999-a150-0d2849e19f34 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1071220552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.1071220552 |
Directory | /workspace/186.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/187.otp_ctrl_init_fail.2685696056 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 247508735 ps |
CPU time | 4.4 seconds |
Started | Mar 31 03:33:40 PM PDT 24 |
Finished | Mar 31 03:33:45 PM PDT 24 |
Peak memory | 241732 kb |
Host | smart-c373b453-220a-4af3-ad03-88712d8dac39 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2685696056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.2685696056 |
Directory | /workspace/187.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/187.otp_ctrl_parallel_lc_esc.3886945841 |
Short name | T768 |
Test name | |
Test status | |
Simulation time | 1411565600 ps |
CPU time | 11.86 seconds |
Started | Mar 31 03:33:38 PM PDT 24 |
Finished | Mar 31 03:33:50 PM PDT 24 |
Peak memory | 241892 kb |
Host | smart-09dfa546-1fca-46ce-9c88-d2062ba6b078 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3886945841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.3886945841 |
Directory | /workspace/187.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/188.otp_ctrl_init_fail.1837195408 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 114806808 ps |
CPU time | 4.31 seconds |
Started | Mar 31 03:33:47 PM PDT 24 |
Finished | Mar 31 03:33:51 PM PDT 24 |
Peak memory | 241620 kb |
Host | smart-8b28d394-c73b-4677-b941-2de1986fce9b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1837195408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.1837195408 |
Directory | /workspace/188.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/188.otp_ctrl_parallel_lc_esc.3512012292 |
Short name | T477 |
Test name | |
Test status | |
Simulation time | 10813547284 ps |
CPU time | 25.34 seconds |
Started | Mar 31 03:33:42 PM PDT 24 |
Finished | Mar 31 03:34:07 PM PDT 24 |
Peak memory | 241612 kb |
Host | smart-996d1482-79b2-45b5-93e4-3fa14d23ed0e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3512012292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.3512012292 |
Directory | /workspace/188.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/189.otp_ctrl_init_fail.1798833100 |
Short name | T779 |
Test name | |
Test status | |
Simulation time | 1717547436 ps |
CPU time | 5.71 seconds |
Started | Mar 31 03:33:42 PM PDT 24 |
Finished | Mar 31 03:33:47 PM PDT 24 |
Peak memory | 242020 kb |
Host | smart-9168ebc7-8875-4d1a-892c-218ec7659028 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1798833100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.1798833100 |
Directory | /workspace/189.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/189.otp_ctrl_parallel_lc_esc.1392181992 |
Short name | T990 |
Test name | |
Test status | |
Simulation time | 3490273895 ps |
CPU time | 7.84 seconds |
Started | Mar 31 03:33:39 PM PDT 24 |
Finished | Mar 31 03:33:47 PM PDT 24 |
Peak memory | 241948 kb |
Host | smart-aec03c7f-6613-456b-8237-7fa367c273f2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1392181992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.1392181992 |
Directory | /workspace/189.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/19.otp_ctrl_alert_test.71547176 |
Short name | T982 |
Test name | |
Test status | |
Simulation time | 117397371 ps |
CPU time | 1.49 seconds |
Started | Mar 31 03:30:02 PM PDT 24 |
Finished | Mar 31 03:30:04 PM PDT 24 |
Peak memory | 240036 kb |
Host | smart-87a85d2a-3ff3-4151-8875-bd7fdb310a37 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71547176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.71547176 |
Directory | /workspace/19.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/19.otp_ctrl_check_fail.1292247880 |
Short name | T506 |
Test name | |
Test status | |
Simulation time | 575876624 ps |
CPU time | 4.4 seconds |
Started | Mar 31 03:30:05 PM PDT 24 |
Finished | Mar 31 03:30:09 PM PDT 24 |
Peak memory | 248508 kb |
Host | smart-5655f147-c262-4eed-9dcc-cacec2e098f7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1292247880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.1292247880 |
Directory | /workspace/19.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/19.otp_ctrl_dai_errs.2665930598 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 372779425 ps |
CPU time | 22.55 seconds |
Started | Mar 31 03:30:04 PM PDT 24 |
Finished | Mar 31 03:30:26 PM PDT 24 |
Peak memory | 241756 kb |
Host | smart-61df4ae9-dc79-48c1-82a4-d4a27ca8262e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2665930598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.2665930598 |
Directory | /workspace/19.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/19.otp_ctrl_dai_lock.3159923660 |
Short name | T994 |
Test name | |
Test status | |
Simulation time | 548814875 ps |
CPU time | 21.45 seconds |
Started | Mar 31 03:30:01 PM PDT 24 |
Finished | Mar 31 03:30:23 PM PDT 24 |
Peak memory | 242280 kb |
Host | smart-7e3ce57d-5192-4dd0-bad7-82d3875f7f80 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3159923660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.3159923660 |
Directory | /workspace/19.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/19.otp_ctrl_init_fail.3951886621 |
Short name | T809 |
Test name | |
Test status | |
Simulation time | 271907802 ps |
CPU time | 4.88 seconds |
Started | Mar 31 03:30:05 PM PDT 24 |
Finished | Mar 31 03:30:10 PM PDT 24 |
Peak memory | 241648 kb |
Host | smart-19d56731-7815-43be-b360-4fe7c641847b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3951886621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.3951886621 |
Directory | /workspace/19.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/19.otp_ctrl_macro_errs.145473361 |
Short name | T1024 |
Test name | |
Test status | |
Simulation time | 4554671720 ps |
CPU time | 12.78 seconds |
Started | Mar 31 03:30:01 PM PDT 24 |
Finished | Mar 31 03:30:14 PM PDT 24 |
Peak memory | 242332 kb |
Host | smart-bb126e92-f286-47b7-8b4f-c85e3bcc54c2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=145473361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.145473361 |
Directory | /workspace/19.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/19.otp_ctrl_parallel_key_req.1492948426 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 1498878414 ps |
CPU time | 32.5 seconds |
Started | Mar 31 03:30:03 PM PDT 24 |
Finished | Mar 31 03:30:35 PM PDT 24 |
Peak memory | 242728 kb |
Host | smart-70e9090a-0fe6-43ff-96f9-650d1e82aee4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1492948426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_key_req.1492948426 |
Directory | /workspace/19.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/19.otp_ctrl_parallel_lc_esc.3340627758 |
Short name | T592 |
Test name | |
Test status | |
Simulation time | 1859897484 ps |
CPU time | 15.03 seconds |
Started | Mar 31 03:30:05 PM PDT 24 |
Finished | Mar 31 03:30:20 PM PDT 24 |
Peak memory | 241556 kb |
Host | smart-502fa4c2-ba80-4a02-a91c-97c41cd4eac8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3340627758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.3340627758 |
Directory | /workspace/19.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/19.otp_ctrl_parallel_lc_req.4098892887 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 786962286 ps |
CPU time | 10.9 seconds |
Started | Mar 31 03:30:07 PM PDT 24 |
Finished | Mar 31 03:30:18 PM PDT 24 |
Peak memory | 241548 kb |
Host | smart-13f5e06a-8b3d-4b2f-8ddc-91131eea650e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4098892887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_req.4098892887 |
Directory | /workspace/19.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/19.otp_ctrl_regwen.1211054242 |
Short name | T857 |
Test name | |
Test status | |
Simulation time | 516361340 ps |
CPU time | 4.83 seconds |
Started | Mar 31 03:30:01 PM PDT 24 |
Finished | Mar 31 03:30:06 PM PDT 24 |
Peak memory | 241840 kb |
Host | smart-401b56c5-ce05-4021-806d-3da7238463f2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1211054242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.1211054242 |
Directory | /workspace/19.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/19.otp_ctrl_smoke.270869330 |
Short name | T698 |
Test name | |
Test status | |
Simulation time | 156744137 ps |
CPU time | 5.46 seconds |
Started | Mar 31 03:30:02 PM PDT 24 |
Finished | Mar 31 03:30:07 PM PDT 24 |
Peak memory | 242032 kb |
Host | smart-045e44bd-16bf-49fd-b3b2-d06402cba9a3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=270869330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.270869330 |
Directory | /workspace/19.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/19.otp_ctrl_stress_all_with_rand_reset.2914011310 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 249129260966 ps |
CPU time | 945.9 seconds |
Started | Mar 31 03:30:03 PM PDT 24 |
Finished | Mar 31 03:45:49 PM PDT 24 |
Peak memory | 257336 kb |
Host | smart-7b60e638-3c5c-49cd-b6a9-ee410b62592a |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914011310 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all_with_rand_reset.2914011310 |
Directory | /workspace/19.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/19.otp_ctrl_test_access.3597919967 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 10489190498 ps |
CPU time | 29.66 seconds |
Started | Mar 31 03:30:03 PM PDT 24 |
Finished | Mar 31 03:30:33 PM PDT 24 |
Peak memory | 243132 kb |
Host | smart-7d4b7375-8554-431d-bc44-a36850ae07cc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3597919967 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.3597919967 |
Directory | /workspace/19.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/190.otp_ctrl_init_fail.1422633632 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 1524957797 ps |
CPU time | 4.94 seconds |
Started | Mar 31 03:33:40 PM PDT 24 |
Finished | Mar 31 03:33:45 PM PDT 24 |
Peak memory | 241620 kb |
Host | smart-1a87367a-90cd-452e-b209-cc6c7c75dd61 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1422633632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.1422633632 |
Directory | /workspace/190.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/190.otp_ctrl_parallel_lc_esc.3842141926 |
Short name | T795 |
Test name | |
Test status | |
Simulation time | 285651742 ps |
CPU time | 7.42 seconds |
Started | Mar 31 03:33:39 PM PDT 24 |
Finished | Mar 31 03:33:47 PM PDT 24 |
Peak memory | 241968 kb |
Host | smart-ad363cad-8b2c-423f-abaf-a8bd1e5316cb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3842141926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.3842141926 |
Directory | /workspace/190.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/191.otp_ctrl_init_fail.2019378533 |
Short name | T801 |
Test name | |
Test status | |
Simulation time | 2336665629 ps |
CPU time | 7.57 seconds |
Started | Mar 31 03:33:44 PM PDT 24 |
Finished | Mar 31 03:33:52 PM PDT 24 |
Peak memory | 242112 kb |
Host | smart-aec81431-2462-49d6-86ed-d6e274ea3f43 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2019378533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.2019378533 |
Directory | /workspace/191.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/191.otp_ctrl_parallel_lc_esc.3943244471 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 298739857 ps |
CPU time | 5.35 seconds |
Started | Mar 31 03:33:43 PM PDT 24 |
Finished | Mar 31 03:33:50 PM PDT 24 |
Peak memory | 241804 kb |
Host | smart-52e96915-8d9c-4798-b124-ac79f3b8283c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3943244471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.3943244471 |
Directory | /workspace/191.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/192.otp_ctrl_init_fail.320223725 |
Short name | T475 |
Test name | |
Test status | |
Simulation time | 166715419 ps |
CPU time | 3.31 seconds |
Started | Mar 31 03:33:41 PM PDT 24 |
Finished | Mar 31 03:33:44 PM PDT 24 |
Peak memory | 241744 kb |
Host | smart-37104a02-313b-4ac6-94b5-18a9b6620e8f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=320223725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.320223725 |
Directory | /workspace/192.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/192.otp_ctrl_parallel_lc_esc.1936028805 |
Short name | T1002 |
Test name | |
Test status | |
Simulation time | 175819393 ps |
CPU time | 6.37 seconds |
Started | Mar 31 03:33:40 PM PDT 24 |
Finished | Mar 31 03:33:46 PM PDT 24 |
Peak memory | 241656 kb |
Host | smart-59bf34cd-1e00-4b40-ac11-2bdbbd0cb92d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1936028805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.1936028805 |
Directory | /workspace/192.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/193.otp_ctrl_init_fail.1795895678 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 107298619 ps |
CPU time | 3.73 seconds |
Started | Mar 31 03:33:41 PM PDT 24 |
Finished | Mar 31 03:33:45 PM PDT 24 |
Peak memory | 241628 kb |
Host | smart-b7c13160-e28d-44a7-bea9-474794042d59 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1795895678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.1795895678 |
Directory | /workspace/193.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/193.otp_ctrl_parallel_lc_esc.408819849 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 446793016 ps |
CPU time | 3.45 seconds |
Started | Mar 31 03:33:40 PM PDT 24 |
Finished | Mar 31 03:33:43 PM PDT 24 |
Peak memory | 242060 kb |
Host | smart-e3e428c8-37c7-408b-8cc0-b75029d9a524 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=408819849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.408819849 |
Directory | /workspace/193.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/194.otp_ctrl_init_fail.1912806370 |
Short name | T1033 |
Test name | |
Test status | |
Simulation time | 107158954 ps |
CPU time | 4.27 seconds |
Started | Mar 31 03:33:41 PM PDT 24 |
Finished | Mar 31 03:33:46 PM PDT 24 |
Peak memory | 242108 kb |
Host | smart-d4fdd8d0-cb5b-4684-a0ef-0e26e98d9e53 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1912806370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.1912806370 |
Directory | /workspace/194.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/194.otp_ctrl_parallel_lc_esc.1658656831 |
Short name | T737 |
Test name | |
Test status | |
Simulation time | 602180637 ps |
CPU time | 7.4 seconds |
Started | Mar 31 03:33:40 PM PDT 24 |
Finished | Mar 31 03:33:47 PM PDT 24 |
Peak memory | 242020 kb |
Host | smart-1b3610af-691b-43ed-8ff3-b77e468477ef |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1658656831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.1658656831 |
Directory | /workspace/194.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/195.otp_ctrl_init_fail.3888197176 |
Short name | T594 |
Test name | |
Test status | |
Simulation time | 2606332685 ps |
CPU time | 5.69 seconds |
Started | Mar 31 03:33:51 PM PDT 24 |
Finished | Mar 31 03:33:57 PM PDT 24 |
Peak memory | 241696 kb |
Host | smart-5a564a0f-9870-48e6-bec8-e1ec13114c6d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3888197176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.3888197176 |
Directory | /workspace/195.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/195.otp_ctrl_parallel_lc_esc.325990010 |
Short name | T1134 |
Test name | |
Test status | |
Simulation time | 931657400 ps |
CPU time | 7.02 seconds |
Started | Mar 31 03:33:49 PM PDT 24 |
Finished | Mar 31 03:33:56 PM PDT 24 |
Peak memory | 241848 kb |
Host | smart-f3c9628e-810b-439c-b067-576cee9ab876 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=325990010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.325990010 |
Directory | /workspace/195.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/196.otp_ctrl_init_fail.2922261127 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 418969926 ps |
CPU time | 4.77 seconds |
Started | Mar 31 03:33:46 PM PDT 24 |
Finished | Mar 31 03:33:51 PM PDT 24 |
Peak memory | 241752 kb |
Host | smart-9c47397b-550d-481c-9f4d-f2ad29c759a6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2922261127 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.2922261127 |
Directory | /workspace/196.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/196.otp_ctrl_parallel_lc_esc.4042733521 |
Short name | T471 |
Test name | |
Test status | |
Simulation time | 563654890 ps |
CPU time | 9.59 seconds |
Started | Mar 31 03:33:49 PM PDT 24 |
Finished | Mar 31 03:33:59 PM PDT 24 |
Peak memory | 241612 kb |
Host | smart-7f2d4c36-ad05-4c51-bd87-558ca9da93a0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4042733521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.4042733521 |
Directory | /workspace/196.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/197.otp_ctrl_init_fail.676314870 |
Short name | T878 |
Test name | |
Test status | |
Simulation time | 1921552128 ps |
CPU time | 6.09 seconds |
Started | Mar 31 03:33:51 PM PDT 24 |
Finished | Mar 31 03:33:58 PM PDT 24 |
Peak memory | 242000 kb |
Host | smart-965b74c7-d4c3-4215-a8e0-01944a21c8b5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=676314870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.676314870 |
Directory | /workspace/197.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/197.otp_ctrl_parallel_lc_esc.15269359 |
Short name | T599 |
Test name | |
Test status | |
Simulation time | 361778492 ps |
CPU time | 5.46 seconds |
Started | Mar 31 03:33:48 PM PDT 24 |
Finished | Mar 31 03:33:53 PM PDT 24 |
Peak memory | 241920 kb |
Host | smart-9d79b699-591e-4f94-aa6d-a0663759ad1f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=15269359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.15269359 |
Directory | /workspace/197.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/198.otp_ctrl_init_fail.1512898541 |
Short name | T562 |
Test name | |
Test status | |
Simulation time | 212124305 ps |
CPU time | 4.18 seconds |
Started | Mar 31 03:33:47 PM PDT 24 |
Finished | Mar 31 03:33:51 PM PDT 24 |
Peak memory | 241684 kb |
Host | smart-27c39120-d0d1-4603-baea-592b2d6bfd1c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1512898541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.1512898541 |
Directory | /workspace/198.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/198.otp_ctrl_parallel_lc_esc.3163418170 |
Short name | T665 |
Test name | |
Test status | |
Simulation time | 1878605889 ps |
CPU time | 3.68 seconds |
Started | Mar 31 03:33:47 PM PDT 24 |
Finished | Mar 31 03:33:51 PM PDT 24 |
Peak memory | 242040 kb |
Host | smart-9a86118c-d998-460d-912c-5f3a29dc9e37 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3163418170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.3163418170 |
Directory | /workspace/198.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/199.otp_ctrl_init_fail.3337508424 |
Short name | T833 |
Test name | |
Test status | |
Simulation time | 152345505 ps |
CPU time | 3.47 seconds |
Started | Mar 31 03:33:46 PM PDT 24 |
Finished | Mar 31 03:33:50 PM PDT 24 |
Peak memory | 241748 kb |
Host | smart-4ac38ecf-1b35-4c42-8004-8899691cdffd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3337508424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.3337508424 |
Directory | /workspace/199.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/199.otp_ctrl_parallel_lc_esc.763732256 |
Short name | T1010 |
Test name | |
Test status | |
Simulation time | 160313810 ps |
CPU time | 3.77 seconds |
Started | Mar 31 03:33:49 PM PDT 24 |
Finished | Mar 31 03:33:52 PM PDT 24 |
Peak memory | 241588 kb |
Host | smart-8abcbf36-4a20-4238-9c83-0c961397059a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=763732256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.763732256 |
Directory | /workspace/199.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/2.otp_ctrl_alert_test.3921859186 |
Short name | T666 |
Test name | |
Test status | |
Simulation time | 822135765 ps |
CPU time | 2.51 seconds |
Started | Mar 31 03:28:44 PM PDT 24 |
Finished | Mar 31 03:28:47 PM PDT 24 |
Peak memory | 240040 kb |
Host | smart-86434cb8-969a-4d81-8bcf-ca7a934ab999 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921859186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.3921859186 |
Directory | /workspace/2.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/2.otp_ctrl_background_chks.1474726927 |
Short name | T522 |
Test name | |
Test status | |
Simulation time | 3771592195 ps |
CPU time | 37.96 seconds |
Started | Mar 31 03:28:34 PM PDT 24 |
Finished | Mar 31 03:29:13 PM PDT 24 |
Peak memory | 242460 kb |
Host | smart-13b7d490-1095-419b-a833-06ccc334ce8e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1474726927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.1474726927 |
Directory | /workspace/2.otp_ctrl_background_chks/latest |
Test location | /workspace/coverage/default/2.otp_ctrl_dai_errs.2165066788 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 1416353323 ps |
CPU time | 36.19 seconds |
Started | Mar 31 03:28:35 PM PDT 24 |
Finished | Mar 31 03:29:11 PM PDT 24 |
Peak memory | 243644 kb |
Host | smart-8ed6dbc9-cbe4-4afe-8b65-211826e726dd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2165066788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.2165066788 |
Directory | /workspace/2.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/2.otp_ctrl_dai_lock.1928495452 |
Short name | T749 |
Test name | |
Test status | |
Simulation time | 612792045 ps |
CPU time | 14.74 seconds |
Started | Mar 31 03:28:34 PM PDT 24 |
Finished | Mar 31 03:28:49 PM PDT 24 |
Peak memory | 241712 kb |
Host | smart-3c94a258-6103-495e-953b-5d9b98257397 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1928495452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.1928495452 |
Directory | /workspace/2.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/2.otp_ctrl_init_fail.1608080213 |
Short name | T680 |
Test name | |
Test status | |
Simulation time | 2031808385 ps |
CPU time | 4.94 seconds |
Started | Mar 31 03:28:34 PM PDT 24 |
Finished | Mar 31 03:28:39 PM PDT 24 |
Peak memory | 241968 kb |
Host | smart-793e1a67-6b07-48dd-8104-2d771f135609 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1608080213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.1608080213 |
Directory | /workspace/2.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/2.otp_ctrl_macro_errs.4240143631 |
Short name | T1149 |
Test name | |
Test status | |
Simulation time | 786283486 ps |
CPU time | 13.57 seconds |
Started | Mar 31 03:28:36 PM PDT 24 |
Finished | Mar 31 03:28:50 PM PDT 24 |
Peak memory | 248588 kb |
Host | smart-3ee5a06e-46ad-425d-8980-5e4c2eaa13e6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4240143631 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.4240143631 |
Directory | /workspace/2.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/2.otp_ctrl_parallel_key_req.2281144547 |
Short name | T609 |
Test name | |
Test status | |
Simulation time | 139505062 ps |
CPU time | 6.5 seconds |
Started | Mar 31 03:28:34 PM PDT 24 |
Finished | Mar 31 03:28:41 PM PDT 24 |
Peak memory | 241692 kb |
Host | smart-ec89e962-5df4-4a00-af18-9b3f16e9baea |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2281144547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.2281144547 |
Directory | /workspace/2.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/2.otp_ctrl_parallel_lc_esc.2614533248 |
Short name | T554 |
Test name | |
Test status | |
Simulation time | 3285987999 ps |
CPU time | 8.61 seconds |
Started | Mar 31 03:28:35 PM PDT 24 |
Finished | Mar 31 03:28:43 PM PDT 24 |
Peak memory | 241676 kb |
Host | smart-b808cf6c-973f-4a01-a54e-508c29eaaa34 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2614533248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.2614533248 |
Directory | /workspace/2.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/2.otp_ctrl_parallel_lc_req.2222099993 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 1075330954 ps |
CPU time | 16.98 seconds |
Started | Mar 31 03:28:34 PM PDT 24 |
Finished | Mar 31 03:28:51 PM PDT 24 |
Peak memory | 241928 kb |
Host | smart-b85df89e-1bf9-47d9-898f-7fe4db2e13de |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2222099993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.2222099993 |
Directory | /workspace/2.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/2.otp_ctrl_regwen.1634269546 |
Short name | T792 |
Test name | |
Test status | |
Simulation time | 155517699 ps |
CPU time | 4.75 seconds |
Started | Mar 31 03:28:34 PM PDT 24 |
Finished | Mar 31 03:28:38 PM PDT 24 |
Peak memory | 241632 kb |
Host | smart-3214edc9-0b32-43d9-a8b5-a27c6b94da4e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1634269546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.1634269546 |
Directory | /workspace/2.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/2.otp_ctrl_smoke.1357353679 |
Short name | T602 |
Test name | |
Test status | |
Simulation time | 138536142 ps |
CPU time | 4.51 seconds |
Started | Mar 31 03:28:35 PM PDT 24 |
Finished | Mar 31 03:28:40 PM PDT 24 |
Peak memory | 241960 kb |
Host | smart-cc18f3c4-2bbf-4df1-844d-38d7fc6c0fc6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1357353679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.1357353679 |
Directory | /workspace/2.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/20.otp_ctrl_alert_test.4215500656 |
Short name | T473 |
Test name | |
Test status | |
Simulation time | 965272348 ps |
CPU time | 2.83 seconds |
Started | Mar 31 03:30:09 PM PDT 24 |
Finished | Mar 31 03:30:11 PM PDT 24 |
Peak memory | 240044 kb |
Host | smart-15d1f85e-f36a-4d20-aeda-b19e05e137c4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215500656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.4215500656 |
Directory | /workspace/20.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/20.otp_ctrl_check_fail.2712459409 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 2936356836 ps |
CPU time | 19.2 seconds |
Started | Mar 31 03:30:07 PM PDT 24 |
Finished | Mar 31 03:30:26 PM PDT 24 |
Peak memory | 248708 kb |
Host | smart-1a40285e-2fa7-482d-b7bf-18a8d303f02f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2712459409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.2712459409 |
Directory | /workspace/20.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/20.otp_ctrl_dai_errs.3780130172 |
Short name | T1025 |
Test name | |
Test status | |
Simulation time | 5242281300 ps |
CPU time | 41.85 seconds |
Started | Mar 31 03:30:09 PM PDT 24 |
Finished | Mar 31 03:30:51 PM PDT 24 |
Peak memory | 251712 kb |
Host | smart-9f419f2c-56ba-4932-888a-49aa0033a2df |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3780130172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.3780130172 |
Directory | /workspace/20.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/20.otp_ctrl_dai_lock.2167977000 |
Short name | T711 |
Test name | |
Test status | |
Simulation time | 1048465652 ps |
CPU time | 15.66 seconds |
Started | Mar 31 03:30:04 PM PDT 24 |
Finished | Mar 31 03:30:19 PM PDT 24 |
Peak memory | 242060 kb |
Host | smart-65422d3a-e45e-48fb-8b9a-fc841c2e591f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2167977000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.2167977000 |
Directory | /workspace/20.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/20.otp_ctrl_init_fail.2069909042 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 110800220 ps |
CPU time | 3.79 seconds |
Started | Mar 31 03:30:03 PM PDT 24 |
Finished | Mar 31 03:30:07 PM PDT 24 |
Peak memory | 241644 kb |
Host | smart-8b4275f1-2392-4d9c-ac56-7210f5dab21d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2069909042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.2069909042 |
Directory | /workspace/20.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/20.otp_ctrl_macro_errs.1187670837 |
Short name | T536 |
Test name | |
Test status | |
Simulation time | 1063543288 ps |
CPU time | 24.96 seconds |
Started | Mar 31 03:30:09 PM PDT 24 |
Finished | Mar 31 03:30:34 PM PDT 24 |
Peak memory | 242552 kb |
Host | smart-fdc19200-c04e-4c0a-988a-6543a8b49cab |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1187670837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_macro_errs.1187670837 |
Directory | /workspace/20.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/20.otp_ctrl_parallel_key_req.777339422 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 1405914938 ps |
CPU time | 10.16 seconds |
Started | Mar 31 03:30:07 PM PDT 24 |
Finished | Mar 31 03:30:17 PM PDT 24 |
Peak memory | 241940 kb |
Host | smart-7b954deb-0062-4653-830d-d2cd061e1fa0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=777339422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.777339422 |
Directory | /workspace/20.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/20.otp_ctrl_parallel_lc_esc.1229734383 |
Short name | T531 |
Test name | |
Test status | |
Simulation time | 665219047 ps |
CPU time | 10.06 seconds |
Started | Mar 31 03:30:02 PM PDT 24 |
Finished | Mar 31 03:30:12 PM PDT 24 |
Peak memory | 241612 kb |
Host | smart-77f7a5f1-80d4-4a5e-8f0d-68dc9f9f9ffa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1229734383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.1229734383 |
Directory | /workspace/20.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/20.otp_ctrl_parallel_lc_req.2092677177 |
Short name | T917 |
Test name | |
Test status | |
Simulation time | 8473889288 ps |
CPU time | 25.74 seconds |
Started | Mar 31 03:30:08 PM PDT 24 |
Finished | Mar 31 03:30:34 PM PDT 24 |
Peak memory | 242060 kb |
Host | smart-bb6fcb4e-1470-4d1e-9162-6fe8ba8e94b8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2092677177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.2092677177 |
Directory | /workspace/20.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/20.otp_ctrl_regwen.539094123 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 104374447 ps |
CPU time | 3.34 seconds |
Started | Mar 31 03:30:08 PM PDT 24 |
Finished | Mar 31 03:30:11 PM PDT 24 |
Peak memory | 241960 kb |
Host | smart-a354ad3c-03f4-4203-91c1-ad10db77fefd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=539094123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.539094123 |
Directory | /workspace/20.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/20.otp_ctrl_smoke.930795961 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 311082298 ps |
CPU time | 6.6 seconds |
Started | Mar 31 03:30:04 PM PDT 24 |
Finished | Mar 31 03:30:11 PM PDT 24 |
Peak memory | 241952 kb |
Host | smart-6f252470-5252-49fa-ba18-29683880505d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=930795961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.930795961 |
Directory | /workspace/20.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/20.otp_ctrl_stress_all_with_rand_reset.1141268271 |
Short name | T1048 |
Test name | |
Test status | |
Simulation time | 39272041869 ps |
CPU time | 469.83 seconds |
Started | Mar 31 03:30:09 PM PDT 24 |
Finished | Mar 31 03:37:59 PM PDT 24 |
Peak memory | 332636 kb |
Host | smart-70e77180-fd50-4a2a-97fb-2e93bc0ed028 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141268271 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all_with_rand_reset.1141268271 |
Directory | /workspace/20.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/20.otp_ctrl_test_access.209142278 |
Short name | T550 |
Test name | |
Test status | |
Simulation time | 655012066 ps |
CPU time | 6.06 seconds |
Started | Mar 31 03:30:09 PM PDT 24 |
Finished | Mar 31 03:30:15 PM PDT 24 |
Peak memory | 241944 kb |
Host | smart-4eaeead2-410f-4a2e-8100-2dad36d73e1f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=209142278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.209142278 |
Directory | /workspace/20.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/200.otp_ctrl_init_fail.2653594610 |
Short name | T1000 |
Test name | |
Test status | |
Simulation time | 1463863999 ps |
CPU time | 5.75 seconds |
Started | Mar 31 03:33:47 PM PDT 24 |
Finished | Mar 31 03:33:53 PM PDT 24 |
Peak memory | 241740 kb |
Host | smart-9976d8e5-2198-4f67-9edf-784616cdd6a8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2653594610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.2653594610 |
Directory | /workspace/200.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/201.otp_ctrl_init_fail.4022743990 |
Short name | T751 |
Test name | |
Test status | |
Simulation time | 383933780 ps |
CPU time | 5.39 seconds |
Started | Mar 31 03:33:49 PM PDT 24 |
Finished | Mar 31 03:33:55 PM PDT 24 |
Peak memory | 241756 kb |
Host | smart-eed2a8d4-a01a-4579-88cc-2a28044c4810 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4022743990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.4022743990 |
Directory | /workspace/201.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/202.otp_ctrl_init_fail.3075003767 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 133654175 ps |
CPU time | 3.47 seconds |
Started | Mar 31 03:33:52 PM PDT 24 |
Finished | Mar 31 03:33:55 PM PDT 24 |
Peak memory | 241864 kb |
Host | smart-e6eb3514-a179-4124-86db-5fd8624ab00e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3075003767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.3075003767 |
Directory | /workspace/202.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/203.otp_ctrl_init_fail.2625193958 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 2510323517 ps |
CPU time | 4.81 seconds |
Started | Mar 31 03:33:46 PM PDT 24 |
Finished | Mar 31 03:33:51 PM PDT 24 |
Peak memory | 241796 kb |
Host | smart-1c3f7953-5b30-48e8-b9f5-52c19d1d3b32 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2625193958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.2625193958 |
Directory | /workspace/203.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/204.otp_ctrl_init_fail.3099511010 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 2714103885 ps |
CPU time | 4.98 seconds |
Started | Mar 31 03:33:47 PM PDT 24 |
Finished | Mar 31 03:33:52 PM PDT 24 |
Peak memory | 241872 kb |
Host | smart-b73c0eaa-dccb-4d68-9487-7186828d3920 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3099511010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.3099511010 |
Directory | /workspace/204.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/205.otp_ctrl_init_fail.1919644248 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 406697904 ps |
CPU time | 4.2 seconds |
Started | Mar 31 03:33:49 PM PDT 24 |
Finished | Mar 31 03:33:53 PM PDT 24 |
Peak memory | 241808 kb |
Host | smart-12a65f9c-3262-4047-b108-c4ce289def8d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1919644248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.1919644248 |
Directory | /workspace/205.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/207.otp_ctrl_init_fail.3352380858 |
Short name | T835 |
Test name | |
Test status | |
Simulation time | 131505130 ps |
CPU time | 3.31 seconds |
Started | Mar 31 03:33:48 PM PDT 24 |
Finished | Mar 31 03:33:52 PM PDT 24 |
Peak memory | 241564 kb |
Host | smart-6d128aa8-a846-47ba-9390-589c233d3b8b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3352380858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.3352380858 |
Directory | /workspace/207.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/208.otp_ctrl_init_fail.4076002106 |
Short name | T507 |
Test name | |
Test status | |
Simulation time | 106822600 ps |
CPU time | 4.3 seconds |
Started | Mar 31 03:33:47 PM PDT 24 |
Finished | Mar 31 03:33:51 PM PDT 24 |
Peak memory | 242124 kb |
Host | smart-c955e621-3f38-4cb1-9121-b283ff355d78 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4076002106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.4076002106 |
Directory | /workspace/208.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/209.otp_ctrl_init_fail.1889768569 |
Short name | T863 |
Test name | |
Test status | |
Simulation time | 1520462715 ps |
CPU time | 4.16 seconds |
Started | Mar 31 03:33:46 PM PDT 24 |
Finished | Mar 31 03:33:51 PM PDT 24 |
Peak memory | 241972 kb |
Host | smart-2a25adba-66f8-477e-ab9f-a6696df80b22 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1889768569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.1889768569 |
Directory | /workspace/209.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/21.otp_ctrl_alert_test.3053117132 |
Short name | T1018 |
Test name | |
Test status | |
Simulation time | 108554355 ps |
CPU time | 1.61 seconds |
Started | Mar 31 03:30:09 PM PDT 24 |
Finished | Mar 31 03:30:11 PM PDT 24 |
Peak memory | 240076 kb |
Host | smart-37326d6d-1bf5-4c0f-b05d-8e471868e197 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053117132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.3053117132 |
Directory | /workspace/21.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/21.otp_ctrl_check_fail.2446924453 |
Short name | T721 |
Test name | |
Test status | |
Simulation time | 281039072 ps |
CPU time | 8.5 seconds |
Started | Mar 31 03:30:07 PM PDT 24 |
Finished | Mar 31 03:30:15 PM PDT 24 |
Peak memory | 242028 kb |
Host | smart-61171768-c400-4ed5-bd60-9590e1584836 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2446924453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.2446924453 |
Directory | /workspace/21.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/21.otp_ctrl_dai_errs.3073630695 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 699441266 ps |
CPU time | 18.36 seconds |
Started | Mar 31 03:30:07 PM PDT 24 |
Finished | Mar 31 03:30:26 PM PDT 24 |
Peak memory | 241472 kb |
Host | smart-5e4b9182-07bd-4a38-b939-d517d0b49cae |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3073630695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.3073630695 |
Directory | /workspace/21.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/21.otp_ctrl_dai_lock.408352845 |
Short name | T973 |
Test name | |
Test status | |
Simulation time | 3631742144 ps |
CPU time | 6.81 seconds |
Started | Mar 31 03:30:09 PM PDT 24 |
Finished | Mar 31 03:30:16 PM PDT 24 |
Peak memory | 241676 kb |
Host | smart-513b6eaf-977c-4da1-a3e2-afcf68516189 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=408352845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.408352845 |
Directory | /workspace/21.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/21.otp_ctrl_init_fail.1856443404 |
Short name | T797 |
Test name | |
Test status | |
Simulation time | 205829446 ps |
CPU time | 3.97 seconds |
Started | Mar 31 03:30:09 PM PDT 24 |
Finished | Mar 31 03:30:13 PM PDT 24 |
Peak memory | 241736 kb |
Host | smart-ee84e7fe-6ba1-4404-b979-5b5f9a7cc4dc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1856443404 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.1856443404 |
Directory | /workspace/21.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/21.otp_ctrl_macro_errs.670711971 |
Short name | T1153 |
Test name | |
Test status | |
Simulation time | 343923306 ps |
CPU time | 7.68 seconds |
Started | Mar 31 03:30:11 PM PDT 24 |
Finished | Mar 31 03:30:20 PM PDT 24 |
Peak memory | 242212 kb |
Host | smart-ecc1badd-0d31-4334-94fe-c02955e26261 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=670711971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_macro_errs.670711971 |
Directory | /workspace/21.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/21.otp_ctrl_parallel_key_req.942583919 |
Short name | T845 |
Test name | |
Test status | |
Simulation time | 861014748 ps |
CPU time | 41.23 seconds |
Started | Mar 31 03:30:10 PM PDT 24 |
Finished | Mar 31 03:30:51 PM PDT 24 |
Peak memory | 242016 kb |
Host | smart-348022c0-dd81-47b7-9d00-384063177c1b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=942583919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.942583919 |
Directory | /workspace/21.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/21.otp_ctrl_parallel_lc_esc.2000658038 |
Short name | T996 |
Test name | |
Test status | |
Simulation time | 239696477 ps |
CPU time | 9.85 seconds |
Started | Mar 31 03:30:05 PM PDT 24 |
Finished | Mar 31 03:30:16 PM PDT 24 |
Peak memory | 241996 kb |
Host | smart-30cba67b-9e53-4709-b903-4b6654375819 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2000658038 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.2000658038 |
Directory | /workspace/21.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/21.otp_ctrl_parallel_lc_req.2023158236 |
Short name | T684 |
Test name | |
Test status | |
Simulation time | 233794209 ps |
CPU time | 8.59 seconds |
Started | Mar 31 03:30:10 PM PDT 24 |
Finished | Mar 31 03:30:18 PM PDT 24 |
Peak memory | 241696 kb |
Host | smart-681aabe8-d126-4db2-8dd3-7e452216fc3c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2023158236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_req.2023158236 |
Directory | /workspace/21.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/21.otp_ctrl_regwen.1255238897 |
Short name | T1108 |
Test name | |
Test status | |
Simulation time | 272343610 ps |
CPU time | 4.32 seconds |
Started | Mar 31 03:30:08 PM PDT 24 |
Finished | Mar 31 03:30:12 PM PDT 24 |
Peak memory | 241684 kb |
Host | smart-f2d181cd-3a82-4a90-8d08-0d2d8a14a8eb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1255238897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.1255238897 |
Directory | /workspace/21.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/21.otp_ctrl_smoke.2879891206 |
Short name | T526 |
Test name | |
Test status | |
Simulation time | 321682815 ps |
CPU time | 4.39 seconds |
Started | Mar 31 03:30:09 PM PDT 24 |
Finished | Mar 31 03:30:14 PM PDT 24 |
Peak memory | 241968 kb |
Host | smart-38c98138-2180-4789-88f9-b85864cdaae1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2879891206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.2879891206 |
Directory | /workspace/21.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/21.otp_ctrl_test_access.1233851670 |
Short name | T907 |
Test name | |
Test status | |
Simulation time | 750291589 ps |
CPU time | 20.2 seconds |
Started | Mar 31 03:30:11 PM PDT 24 |
Finished | Mar 31 03:30:32 PM PDT 24 |
Peak memory | 241756 kb |
Host | smart-5a0769cd-fdae-4728-adbf-bb7daf74317e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1233851670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.1233851670 |
Directory | /workspace/21.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/210.otp_ctrl_init_fail.1573190463 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 1986071845 ps |
CPU time | 4.6 seconds |
Started | Mar 31 03:33:46 PM PDT 24 |
Finished | Mar 31 03:33:51 PM PDT 24 |
Peak memory | 241656 kb |
Host | smart-695af3d6-443c-492c-a241-66d3a718938f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1573190463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.1573190463 |
Directory | /workspace/210.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/211.otp_ctrl_init_fail.2091193521 |
Short name | T736 |
Test name | |
Test status | |
Simulation time | 123769341 ps |
CPU time | 3.61 seconds |
Started | Mar 31 03:33:48 PM PDT 24 |
Finished | Mar 31 03:33:52 PM PDT 24 |
Peak memory | 241644 kb |
Host | smart-52c3859b-494b-466a-9f01-c49af1e7f63b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2091193521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.2091193521 |
Directory | /workspace/211.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/212.otp_ctrl_init_fail.3111917504 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 2065209872 ps |
CPU time | 4.86 seconds |
Started | Mar 31 03:33:46 PM PDT 24 |
Finished | Mar 31 03:33:51 PM PDT 24 |
Peak memory | 241772 kb |
Host | smart-97a7ef1b-c7d3-4e78-a8e4-2bd2515fbf62 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3111917504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.3111917504 |
Directory | /workspace/212.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/213.otp_ctrl_init_fail.3892966281 |
Short name | T488 |
Test name | |
Test status | |
Simulation time | 183365759 ps |
CPU time | 3.03 seconds |
Started | Mar 31 03:33:47 PM PDT 24 |
Finished | Mar 31 03:33:51 PM PDT 24 |
Peak memory | 241652 kb |
Host | smart-f15a9149-e8a5-4be5-bd83-74e63e5ed6c0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3892966281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.3892966281 |
Directory | /workspace/213.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/214.otp_ctrl_init_fail.3026785559 |
Short name | T518 |
Test name | |
Test status | |
Simulation time | 2007518955 ps |
CPU time | 5.58 seconds |
Started | Mar 31 03:33:46 PM PDT 24 |
Finished | Mar 31 03:33:52 PM PDT 24 |
Peak memory | 241808 kb |
Host | smart-6bf67372-4e32-4e33-bcef-54bc448ec856 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3026785559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.3026785559 |
Directory | /workspace/214.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/215.otp_ctrl_init_fail.2751471506 |
Short name | T1114 |
Test name | |
Test status | |
Simulation time | 2300492192 ps |
CPU time | 4.6 seconds |
Started | Mar 31 03:33:51 PM PDT 24 |
Finished | Mar 31 03:33:56 PM PDT 24 |
Peak memory | 241756 kb |
Host | smart-e263d3d0-5706-4f45-9973-b93d89b0a35d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2751471506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.2751471506 |
Directory | /workspace/215.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/217.otp_ctrl_init_fail.1960021012 |
Short name | T1040 |
Test name | |
Test status | |
Simulation time | 153331882 ps |
CPU time | 3.64 seconds |
Started | Mar 31 03:33:55 PM PDT 24 |
Finished | Mar 31 03:33:59 PM PDT 24 |
Peak memory | 242008 kb |
Host | smart-0fc9e3eb-4688-459d-8ade-27c3e7180537 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1960021012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.1960021012 |
Directory | /workspace/217.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/218.otp_ctrl_init_fail.2600646892 |
Short name | T753 |
Test name | |
Test status | |
Simulation time | 159690866 ps |
CPU time | 4.04 seconds |
Started | Mar 31 03:33:55 PM PDT 24 |
Finished | Mar 31 03:33:59 PM PDT 24 |
Peak memory | 241948 kb |
Host | smart-a3b7a82f-639c-42d9-a676-debff61333fe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2600646892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.2600646892 |
Directory | /workspace/218.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/219.otp_ctrl_init_fail.1663398064 |
Short name | T799 |
Test name | |
Test status | |
Simulation time | 151880655 ps |
CPU time | 4.29 seconds |
Started | Mar 31 03:33:54 PM PDT 24 |
Finished | Mar 31 03:33:59 PM PDT 24 |
Peak memory | 241748 kb |
Host | smart-10d57838-7c84-4832-a316-8a790eec5853 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1663398064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.1663398064 |
Directory | /workspace/219.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/22.otp_ctrl_alert_test.2858999259 |
Short name | T1150 |
Test name | |
Test status | |
Simulation time | 1031907834 ps |
CPU time | 3.22 seconds |
Started | Mar 31 03:30:13 PM PDT 24 |
Finished | Mar 31 03:30:17 PM PDT 24 |
Peak memory | 240156 kb |
Host | smart-b35f33f9-c6e2-4be0-9912-7a89ea697dc0 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858999259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.2858999259 |
Directory | /workspace/22.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/22.otp_ctrl_check_fail.3012948831 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 997103762 ps |
CPU time | 20.32 seconds |
Started | Mar 31 03:30:15 PM PDT 24 |
Finished | Mar 31 03:30:37 PM PDT 24 |
Peak memory | 242224 kb |
Host | smart-6c21b414-f7bc-4102-81d1-0521cf63e0f0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3012948831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.3012948831 |
Directory | /workspace/22.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/22.otp_ctrl_dai_errs.458067774 |
Short name | T515 |
Test name | |
Test status | |
Simulation time | 1483935753 ps |
CPU time | 24.84 seconds |
Started | Mar 31 03:30:13 PM PDT 24 |
Finished | Mar 31 03:30:38 PM PDT 24 |
Peak memory | 241512 kb |
Host | smart-faf8ff96-0424-4d13-ac46-640581189fcd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=458067774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.458067774 |
Directory | /workspace/22.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/22.otp_ctrl_dai_lock.3087050712 |
Short name | T1053 |
Test name | |
Test status | |
Simulation time | 2651917350 ps |
CPU time | 34.95 seconds |
Started | Mar 31 03:30:16 PM PDT 24 |
Finished | Mar 31 03:30:51 PM PDT 24 |
Peak memory | 242332 kb |
Host | smart-ad265576-0d7f-4ec4-b1ba-f066f9acfd84 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3087050712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.3087050712 |
Directory | /workspace/22.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/22.otp_ctrl_init_fail.1544861430 |
Short name | T1030 |
Test name | |
Test status | |
Simulation time | 229590369 ps |
CPU time | 4.21 seconds |
Started | Mar 31 03:30:12 PM PDT 24 |
Finished | Mar 31 03:30:17 PM PDT 24 |
Peak memory | 241816 kb |
Host | smart-7cafa728-8987-4d79-87ff-cc61988b5451 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1544861430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.1544861430 |
Directory | /workspace/22.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/22.otp_ctrl_macro_errs.3781398084 |
Short name | T1037 |
Test name | |
Test status | |
Simulation time | 11504254622 ps |
CPU time | 30.7 seconds |
Started | Mar 31 03:30:13 PM PDT 24 |
Finished | Mar 31 03:30:44 PM PDT 24 |
Peak memory | 247432 kb |
Host | smart-08664af4-96c3-48ad-acbf-a9ad7145532d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3781398084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_macro_errs.3781398084 |
Directory | /workspace/22.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/22.otp_ctrl_parallel_key_req.3861617981 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 4283214378 ps |
CPU time | 33.74 seconds |
Started | Mar 31 03:30:15 PM PDT 24 |
Finished | Mar 31 03:30:50 PM PDT 24 |
Peak memory | 242760 kb |
Host | smart-f8160855-0f16-4102-be44-f346b48842df |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3861617981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.3861617981 |
Directory | /workspace/22.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/22.otp_ctrl_parallel_lc_esc.2263514844 |
Short name | T1067 |
Test name | |
Test status | |
Simulation time | 230598688 ps |
CPU time | 5.68 seconds |
Started | Mar 31 03:30:12 PM PDT 24 |
Finished | Mar 31 03:30:18 PM PDT 24 |
Peak memory | 241820 kb |
Host | smart-128e5d63-5607-4c53-882b-265194589001 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2263514844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.2263514844 |
Directory | /workspace/22.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/22.otp_ctrl_parallel_lc_req.1485261775 |
Short name | T686 |
Test name | |
Test status | |
Simulation time | 4560494372 ps |
CPU time | 14.94 seconds |
Started | Mar 31 03:30:13 PM PDT 24 |
Finished | Mar 31 03:30:29 PM PDT 24 |
Peak memory | 241692 kb |
Host | smart-d08247c8-ac3b-469e-9e42-6cbf048744b0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1485261775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_req.1485261775 |
Directory | /workspace/22.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/22.otp_ctrl_regwen.1511412008 |
Short name | T854 |
Test name | |
Test status | |
Simulation time | 932587561 ps |
CPU time | 7.07 seconds |
Started | Mar 31 03:30:13 PM PDT 24 |
Finished | Mar 31 03:30:21 PM PDT 24 |
Peak memory | 241784 kb |
Host | smart-938f4b1a-7885-4299-9389-eaa15b371849 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1511412008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.1511412008 |
Directory | /workspace/22.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/22.otp_ctrl_smoke.3115507217 |
Short name | T969 |
Test name | |
Test status | |
Simulation time | 303871051 ps |
CPU time | 5.84 seconds |
Started | Mar 31 03:30:11 PM PDT 24 |
Finished | Mar 31 03:30:17 PM PDT 24 |
Peak memory | 242040 kb |
Host | smart-726cb00e-5c99-4223-9325-2e27c6f23d8b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3115507217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.3115507217 |
Directory | /workspace/22.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/22.otp_ctrl_stress_all.310823948 |
Short name | T584 |
Test name | |
Test status | |
Simulation time | 10238643688 ps |
CPU time | 95.42 seconds |
Started | Mar 31 03:30:11 PM PDT 24 |
Finished | Mar 31 03:31:47 PM PDT 24 |
Peak memory | 248700 kb |
Host | smart-fee4f2d2-5b9f-4bb2-a38c-1119902b21d2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310823948 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all. 310823948 |
Directory | /workspace/22.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/22.otp_ctrl_stress_all_with_rand_reset.2439010936 |
Short name | T843 |
Test name | |
Test status | |
Simulation time | 63512489340 ps |
CPU time | 124.54 seconds |
Started | Mar 31 03:30:12 PM PDT 24 |
Finished | Mar 31 03:32:16 PM PDT 24 |
Peak memory | 256948 kb |
Host | smart-a69668ea-9e86-4f17-a4c3-b6c3afa6cda4 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439010936 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all_with_rand_reset.2439010936 |
Directory | /workspace/22.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/22.otp_ctrl_test_access.1421485316 |
Short name | T734 |
Test name | |
Test status | |
Simulation time | 1464390873 ps |
CPU time | 18.87 seconds |
Started | Mar 31 03:30:15 PM PDT 24 |
Finished | Mar 31 03:30:35 PM PDT 24 |
Peak memory | 241680 kb |
Host | smart-0c754be4-c3fc-48b8-90e6-ff9ebee9c845 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1421485316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.1421485316 |
Directory | /workspace/22.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/220.otp_ctrl_init_fail.2780299408 |
Short name | T939 |
Test name | |
Test status | |
Simulation time | 146346978 ps |
CPU time | 3.72 seconds |
Started | Mar 31 03:33:54 PM PDT 24 |
Finished | Mar 31 03:33:57 PM PDT 24 |
Peak memory | 242048 kb |
Host | smart-ef36ea66-194f-4491-a3d6-2967f7a7074e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2780299408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.2780299408 |
Directory | /workspace/220.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/221.otp_ctrl_init_fail.3844375527 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 1712183052 ps |
CPU time | 5.21 seconds |
Started | Mar 31 03:33:52 PM PDT 24 |
Finished | Mar 31 03:33:58 PM PDT 24 |
Peak memory | 241660 kb |
Host | smart-ef46e758-a628-4214-8a94-779831778b88 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3844375527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.3844375527 |
Directory | /workspace/221.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/222.otp_ctrl_init_fail.1883824086 |
Short name | T921 |
Test name | |
Test status | |
Simulation time | 2366401750 ps |
CPU time | 8.03 seconds |
Started | Mar 31 03:33:57 PM PDT 24 |
Finished | Mar 31 03:34:05 PM PDT 24 |
Peak memory | 241876 kb |
Host | smart-2d6a776e-8117-4d18-99b2-2778034d5044 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1883824086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.1883824086 |
Directory | /workspace/222.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/223.otp_ctrl_init_fail.2637244124 |
Short name | T650 |
Test name | |
Test status | |
Simulation time | 418814253 ps |
CPU time | 3.41 seconds |
Started | Mar 31 03:33:53 PM PDT 24 |
Finished | Mar 31 03:33:56 PM PDT 24 |
Peak memory | 241980 kb |
Host | smart-941b3a65-b2f9-4151-9ae9-5975e375b9c2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2637244124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.2637244124 |
Directory | /workspace/223.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/224.otp_ctrl_init_fail.2823659406 |
Short name | T492 |
Test name | |
Test status | |
Simulation time | 614264323 ps |
CPU time | 4.46 seconds |
Started | Mar 31 03:33:54 PM PDT 24 |
Finished | Mar 31 03:33:59 PM PDT 24 |
Peak memory | 241712 kb |
Host | smart-1d41249a-a2e7-464d-abb4-28b9f3de7e78 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2823659406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.2823659406 |
Directory | /workspace/224.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/225.otp_ctrl_init_fail.1602011768 |
Short name | T724 |
Test name | |
Test status | |
Simulation time | 529175587 ps |
CPU time | 4.69 seconds |
Started | Mar 31 03:33:55 PM PDT 24 |
Finished | Mar 31 03:34:00 PM PDT 24 |
Peak memory | 241720 kb |
Host | smart-f2c926bc-5bed-4c1a-a960-d77d6b411bf5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1602011768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.1602011768 |
Directory | /workspace/225.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/226.otp_ctrl_init_fail.2239621147 |
Short name | T1073 |
Test name | |
Test status | |
Simulation time | 221265480 ps |
CPU time | 3.82 seconds |
Started | Mar 31 03:33:53 PM PDT 24 |
Finished | Mar 31 03:33:57 PM PDT 24 |
Peak memory | 241744 kb |
Host | smart-1cb82c3b-5b4d-4f4e-97d6-9d3df1b1e725 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2239621147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.2239621147 |
Directory | /workspace/226.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/227.otp_ctrl_init_fail.2817163207 |
Short name | T524 |
Test name | |
Test status | |
Simulation time | 454758006 ps |
CPU time | 3.68 seconds |
Started | Mar 31 03:33:54 PM PDT 24 |
Finished | Mar 31 03:33:58 PM PDT 24 |
Peak memory | 241744 kb |
Host | smart-146acb2c-bb64-466e-b47e-bdbfb9847bba |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2817163207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.2817163207 |
Directory | /workspace/227.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/228.otp_ctrl_init_fail.3297402833 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 2705523233 ps |
CPU time | 7.48 seconds |
Started | Mar 31 03:33:55 PM PDT 24 |
Finished | Mar 31 03:34:03 PM PDT 24 |
Peak memory | 241836 kb |
Host | smart-b6e95a2c-bca6-4a68-9d83-9066fdf5be53 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3297402833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.3297402833 |
Directory | /workspace/228.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/229.otp_ctrl_init_fail.2114233569 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 307646259 ps |
CPU time | 3.66 seconds |
Started | Mar 31 03:33:54 PM PDT 24 |
Finished | Mar 31 03:33:58 PM PDT 24 |
Peak memory | 241632 kb |
Host | smart-4a4ea50d-428a-43d3-a005-2fd2846810f1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2114233569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.2114233569 |
Directory | /workspace/229.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/23.otp_ctrl_alert_test.2793995911 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 563447290 ps |
CPU time | 1.75 seconds |
Started | Mar 31 03:30:19 PM PDT 24 |
Finished | Mar 31 03:30:21 PM PDT 24 |
Peak memory | 240408 kb |
Host | smart-035da104-33bc-4957-840e-ccde0da9f7d5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793995911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.2793995911 |
Directory | /workspace/23.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/23.otp_ctrl_dai_errs.1308457220 |
Short name | T1039 |
Test name | |
Test status | |
Simulation time | 1401513061 ps |
CPU time | 22.78 seconds |
Started | Mar 31 03:30:18 PM PDT 24 |
Finished | Mar 31 03:30:41 PM PDT 24 |
Peak memory | 241888 kb |
Host | smart-c35d70e6-9a27-4844-a457-ff38c05c4c24 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1308457220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.1308457220 |
Directory | /workspace/23.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/23.otp_ctrl_dai_lock.2546528086 |
Short name | T469 |
Test name | |
Test status | |
Simulation time | 5008747602 ps |
CPU time | 22.16 seconds |
Started | Mar 31 03:30:25 PM PDT 24 |
Finished | Mar 31 03:30:47 PM PDT 24 |
Peak memory | 242288 kb |
Host | smart-aff2f680-eeb2-44f7-8d4a-86ac02411824 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2546528086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.2546528086 |
Directory | /workspace/23.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/23.otp_ctrl_init_fail.1943167622 |
Short name | T961 |
Test name | |
Test status | |
Simulation time | 189180193 ps |
CPU time | 3.99 seconds |
Started | Mar 31 03:30:20 PM PDT 24 |
Finished | Mar 31 03:30:24 PM PDT 24 |
Peak memory | 242120 kb |
Host | smart-2a139e12-eaed-4340-a429-0f672e4c174e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1943167622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.1943167622 |
Directory | /workspace/23.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/23.otp_ctrl_macro_errs.2658931245 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 691306702 ps |
CPU time | 21.6 seconds |
Started | Mar 31 03:30:17 PM PDT 24 |
Finished | Mar 31 03:30:39 PM PDT 24 |
Peak memory | 243164 kb |
Host | smart-06c0b695-e4ac-428b-8930-2b6984076990 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2658931245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.2658931245 |
Directory | /workspace/23.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/23.otp_ctrl_parallel_key_req.3806589605 |
Short name | T867 |
Test name | |
Test status | |
Simulation time | 355611557 ps |
CPU time | 10.05 seconds |
Started | Mar 31 03:30:21 PM PDT 24 |
Finished | Mar 31 03:30:32 PM PDT 24 |
Peak memory | 241680 kb |
Host | smart-b2944e98-ab10-4406-9680-c8fbffe2b7c1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3806589605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.3806589605 |
Directory | /workspace/23.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/23.otp_ctrl_parallel_lc_esc.594702401 |
Short name | T813 |
Test name | |
Test status | |
Simulation time | 1134596758 ps |
CPU time | 19.92 seconds |
Started | Mar 31 03:30:18 PM PDT 24 |
Finished | Mar 31 03:30:38 PM PDT 24 |
Peak memory | 241648 kb |
Host | smart-6739370d-692f-4f71-a99e-ed362f58b143 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=594702401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.594702401 |
Directory | /workspace/23.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/23.otp_ctrl_parallel_lc_req.3635843362 |
Short name | T485 |
Test name | |
Test status | |
Simulation time | 4372777433 ps |
CPU time | 10.89 seconds |
Started | Mar 31 03:30:17 PM PDT 24 |
Finished | Mar 31 03:30:29 PM PDT 24 |
Peak memory | 241512 kb |
Host | smart-f9a959f5-6dbc-415b-b29b-62cd421c3766 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3635843362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.3635843362 |
Directory | /workspace/23.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/23.otp_ctrl_regwen.518997613 |
Short name | T539 |
Test name | |
Test status | |
Simulation time | 1857454883 ps |
CPU time | 5.27 seconds |
Started | Mar 31 03:30:16 PM PDT 24 |
Finished | Mar 31 03:30:22 PM PDT 24 |
Peak memory | 241740 kb |
Host | smart-21b0c7d4-e24c-459c-b4b5-076af5c59f78 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=518997613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.518997613 |
Directory | /workspace/23.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/23.otp_ctrl_smoke.3349183422 |
Short name | T559 |
Test name | |
Test status | |
Simulation time | 334148814 ps |
CPU time | 9.86 seconds |
Started | Mar 31 03:30:11 PM PDT 24 |
Finished | Mar 31 03:30:21 PM PDT 24 |
Peak memory | 241636 kb |
Host | smart-a8744919-c3cb-48a9-af78-fa65e528daa8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3349183422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.3349183422 |
Directory | /workspace/23.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/23.otp_ctrl_stress_all.3128919180 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 1439563305 ps |
CPU time | 15.36 seconds |
Started | Mar 31 03:30:25 PM PDT 24 |
Finished | Mar 31 03:30:41 PM PDT 24 |
Peak memory | 241428 kb |
Host | smart-a0cc4f56-0572-4bf6-bee7-c0c9475b6dd3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128919180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all .3128919180 |
Directory | /workspace/23.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/23.otp_ctrl_test_access.1532371473 |
Short name | T1065 |
Test name | |
Test status | |
Simulation time | 1287295369 ps |
CPU time | 21.36 seconds |
Started | Mar 31 03:30:17 PM PDT 24 |
Finished | Mar 31 03:30:38 PM PDT 24 |
Peak memory | 242640 kb |
Host | smart-cdf7e497-5eb9-4eb9-b9c8-4a9b6049d800 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1532371473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_test_access.1532371473 |
Directory | /workspace/23.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/230.otp_ctrl_init_fail.3739226813 |
Short name | T631 |
Test name | |
Test status | |
Simulation time | 276719618 ps |
CPU time | 4.1 seconds |
Started | Mar 31 03:33:57 PM PDT 24 |
Finished | Mar 31 03:34:01 PM PDT 24 |
Peak memory | 241776 kb |
Host | smart-dca8738b-0eae-4859-bfe1-542aa8dedbd1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3739226813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.3739226813 |
Directory | /workspace/230.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/231.otp_ctrl_init_fail.2268088364 |
Short name | T452 |
Test name | |
Test status | |
Simulation time | 126514076 ps |
CPU time | 4.64 seconds |
Started | Mar 31 03:33:54 PM PDT 24 |
Finished | Mar 31 03:33:59 PM PDT 24 |
Peak memory | 241980 kb |
Host | smart-27ffbe2b-8c46-4d63-9e46-ea573a15bd0b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2268088364 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.2268088364 |
Directory | /workspace/231.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/232.otp_ctrl_init_fail.2081622959 |
Short name | T525 |
Test name | |
Test status | |
Simulation time | 217757855 ps |
CPU time | 5.02 seconds |
Started | Mar 31 03:33:55 PM PDT 24 |
Finished | Mar 31 03:34:00 PM PDT 24 |
Peak memory | 241684 kb |
Host | smart-4fdb133d-160c-458d-aaa7-8822651e1e1a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2081622959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.2081622959 |
Directory | /workspace/232.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/233.otp_ctrl_init_fail.968360588 |
Short name | T573 |
Test name | |
Test status | |
Simulation time | 300700548 ps |
CPU time | 4.98 seconds |
Started | Mar 31 03:33:54 PM PDT 24 |
Finished | Mar 31 03:33:59 PM PDT 24 |
Peak memory | 242008 kb |
Host | smart-5ecb2e06-26c6-4efc-9ed0-47eff3a87450 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=968360588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.968360588 |
Directory | /workspace/233.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/234.otp_ctrl_init_fail.3599377771 |
Short name | T941 |
Test name | |
Test status | |
Simulation time | 234917114 ps |
CPU time | 4.95 seconds |
Started | Mar 31 03:33:57 PM PDT 24 |
Finished | Mar 31 03:34:02 PM PDT 24 |
Peak memory | 241600 kb |
Host | smart-31e0ca91-c5f8-4d80-b54b-805b43d7a41a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3599377771 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.3599377771 |
Directory | /workspace/234.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/235.otp_ctrl_init_fail.2160942577 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 262143020 ps |
CPU time | 5.22 seconds |
Started | Mar 31 03:33:56 PM PDT 24 |
Finished | Mar 31 03:34:02 PM PDT 24 |
Peak memory | 241848 kb |
Host | smart-765ff305-64f1-4268-8d9b-79bf6975c44b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2160942577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.2160942577 |
Directory | /workspace/235.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/236.otp_ctrl_init_fail.463546092 |
Short name | T1008 |
Test name | |
Test status | |
Simulation time | 133961660 ps |
CPU time | 4.06 seconds |
Started | Mar 31 03:33:53 PM PDT 24 |
Finished | Mar 31 03:33:58 PM PDT 24 |
Peak memory | 241768 kb |
Host | smart-c494fe78-e4ba-431e-b02e-f44039a56362 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=463546092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.463546092 |
Directory | /workspace/236.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/237.otp_ctrl_init_fail.2488395161 |
Short name | T1090 |
Test name | |
Test status | |
Simulation time | 1521060096 ps |
CPU time | 4.71 seconds |
Started | Mar 31 03:33:55 PM PDT 24 |
Finished | Mar 31 03:34:00 PM PDT 24 |
Peak memory | 241680 kb |
Host | smart-31fb899c-ea04-46ec-baa7-593f6ea12461 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2488395161 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.2488395161 |
Directory | /workspace/237.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/238.otp_ctrl_init_fail.3498049421 |
Short name | T1148 |
Test name | |
Test status | |
Simulation time | 1513937740 ps |
CPU time | 4.1 seconds |
Started | Mar 31 03:33:57 PM PDT 24 |
Finished | Mar 31 03:34:02 PM PDT 24 |
Peak memory | 241668 kb |
Host | smart-2e373c86-2e56-4621-b676-9033d473857c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3498049421 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.3498049421 |
Directory | /workspace/238.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/239.otp_ctrl_init_fail.2728368136 |
Short name | T877 |
Test name | |
Test status | |
Simulation time | 291451380 ps |
CPU time | 3.61 seconds |
Started | Mar 31 03:33:57 PM PDT 24 |
Finished | Mar 31 03:34:01 PM PDT 24 |
Peak memory | 241672 kb |
Host | smart-80acec7f-9538-4634-9ecb-2e2f92c844ce |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2728368136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.2728368136 |
Directory | /workspace/239.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/24.otp_ctrl_alert_test.1708711570 |
Short name | T726 |
Test name | |
Test status | |
Simulation time | 114730490 ps |
CPU time | 1.91 seconds |
Started | Mar 31 03:30:24 PM PDT 24 |
Finished | Mar 31 03:30:26 PM PDT 24 |
Peak memory | 240048 kb |
Host | smart-3a079eae-4766-4e98-8e9c-6caf15765a97 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708711570 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.1708711570 |
Directory | /workspace/24.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/24.otp_ctrl_check_fail.3071378702 |
Short name | T972 |
Test name | |
Test status | |
Simulation time | 1334555502 ps |
CPU time | 15.26 seconds |
Started | Mar 31 03:30:24 PM PDT 24 |
Finished | Mar 31 03:30:40 PM PDT 24 |
Peak memory | 242148 kb |
Host | smart-20f0c2ef-4512-4d0c-a9fe-50d72fca40f4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3071378702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.3071378702 |
Directory | /workspace/24.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/24.otp_ctrl_dai_errs.2656715769 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 1206209751 ps |
CPU time | 19.61 seconds |
Started | Mar 31 03:30:24 PM PDT 24 |
Finished | Mar 31 03:30:44 PM PDT 24 |
Peak memory | 241692 kb |
Host | smart-ca351f01-258e-4647-be02-f1c9961a28ab |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2656715769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.2656715769 |
Directory | /workspace/24.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/24.otp_ctrl_dai_lock.33979338 |
Short name | T993 |
Test name | |
Test status | |
Simulation time | 1237164338 ps |
CPU time | 19.52 seconds |
Started | Mar 31 03:30:24 PM PDT 24 |
Finished | Mar 31 03:30:44 PM PDT 24 |
Peak memory | 242096 kb |
Host | smart-a45fb1ef-6c7e-49f8-bac1-6cb70e456ab5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=33979338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.33979338 |
Directory | /workspace/24.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/24.otp_ctrl_init_fail.3730442634 |
Short name | T501 |
Test name | |
Test status | |
Simulation time | 351491922 ps |
CPU time | 3.78 seconds |
Started | Mar 31 03:30:25 PM PDT 24 |
Finished | Mar 31 03:30:29 PM PDT 24 |
Peak memory | 242072 kb |
Host | smart-d937cbe1-9ae0-467b-87e5-89664f5e3c66 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3730442634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.3730442634 |
Directory | /workspace/24.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/24.otp_ctrl_macro_errs.522057705 |
Short name | T455 |
Test name | |
Test status | |
Simulation time | 1706393649 ps |
CPU time | 26.49 seconds |
Started | Mar 31 03:30:22 PM PDT 24 |
Finished | Mar 31 03:30:50 PM PDT 24 |
Peak memory | 243764 kb |
Host | smart-64fdc26f-9f2c-44af-a43b-a5a772435214 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=522057705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.522057705 |
Directory | /workspace/24.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/24.otp_ctrl_parallel_key_req.4291804922 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 3563670131 ps |
CPU time | 9.87 seconds |
Started | Mar 31 03:30:23 PM PDT 24 |
Finished | Mar 31 03:30:34 PM PDT 24 |
Peak memory | 242472 kb |
Host | smart-b747a6f8-eab8-45fb-a7ad-3aa9d1030a2c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4291804922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.4291804922 |
Directory | /workspace/24.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/24.otp_ctrl_parallel_lc_esc.955039926 |
Short name | T1135 |
Test name | |
Test status | |
Simulation time | 784544260 ps |
CPU time | 9.45 seconds |
Started | Mar 31 03:30:23 PM PDT 24 |
Finished | Mar 31 03:30:33 PM PDT 24 |
Peak memory | 241532 kb |
Host | smart-9828f786-91f5-44f0-95d8-bade22d670d9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=955039926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.955039926 |
Directory | /workspace/24.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/24.otp_ctrl_parallel_lc_req.3905307837 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 205721462 ps |
CPU time | 6.54 seconds |
Started | Mar 31 03:30:24 PM PDT 24 |
Finished | Mar 31 03:30:31 PM PDT 24 |
Peak memory | 241892 kb |
Host | smart-10f5e684-f495-4815-9a3f-5b97c0225ee3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3905307837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.3905307837 |
Directory | /workspace/24.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/24.otp_ctrl_regwen.4191059397 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 442682534 ps |
CPU time | 7.29 seconds |
Started | Mar 31 03:30:23 PM PDT 24 |
Finished | Mar 31 03:30:31 PM PDT 24 |
Peak memory | 241820 kb |
Host | smart-e9379948-2d73-44b4-8c4f-27e9f16dc5c5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4191059397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.4191059397 |
Directory | /workspace/24.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/24.otp_ctrl_smoke.3492889496 |
Short name | T695 |
Test name | |
Test status | |
Simulation time | 123174915 ps |
CPU time | 3.32 seconds |
Started | Mar 31 03:30:20 PM PDT 24 |
Finished | Mar 31 03:30:23 PM PDT 24 |
Peak memory | 241776 kb |
Host | smart-117722bd-66a2-478e-bd7d-f7f5daf5d133 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3492889496 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.3492889496 |
Directory | /workspace/24.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/24.otp_ctrl_stress_all.1271346865 |
Short name | T875 |
Test name | |
Test status | |
Simulation time | 24014518829 ps |
CPU time | 242.23 seconds |
Started | Mar 31 03:30:24 PM PDT 24 |
Finished | Mar 31 03:34:27 PM PDT 24 |
Peak memory | 273492 kb |
Host | smart-ad378926-79b9-416c-9071-463a4b6ec03e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271346865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all .1271346865 |
Directory | /workspace/24.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/24.otp_ctrl_test_access.1959308105 |
Short name | T804 |
Test name | |
Test status | |
Simulation time | 3530846132 ps |
CPU time | 33.82 seconds |
Started | Mar 31 03:30:25 PM PDT 24 |
Finished | Mar 31 03:30:59 PM PDT 24 |
Peak memory | 241820 kb |
Host | smart-f92fb9bd-f5f9-48e5-b4a2-7d1b9fd5d3c2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1959308105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_test_access.1959308105 |
Directory | /workspace/24.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/240.otp_ctrl_init_fail.735569641 |
Short name | T654 |
Test name | |
Test status | |
Simulation time | 132886945 ps |
CPU time | 3.53 seconds |
Started | Mar 31 03:33:55 PM PDT 24 |
Finished | Mar 31 03:33:59 PM PDT 24 |
Peak memory | 241840 kb |
Host | smart-47e666f8-bfe6-409f-86c9-85abc4b180f5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=735569641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.735569641 |
Directory | /workspace/240.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/241.otp_ctrl_init_fail.2140775257 |
Short name | T894 |
Test name | |
Test status | |
Simulation time | 664070142 ps |
CPU time | 5.22 seconds |
Started | Mar 31 03:33:52 PM PDT 24 |
Finished | Mar 31 03:33:58 PM PDT 24 |
Peak memory | 241764 kb |
Host | smart-b1a0b7f8-25d3-47f8-97ca-27ef454386b9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2140775257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.2140775257 |
Directory | /workspace/241.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/242.otp_ctrl_init_fail.1337246445 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 242706980 ps |
CPU time | 3.8 seconds |
Started | Mar 31 03:33:55 PM PDT 24 |
Finished | Mar 31 03:33:59 PM PDT 24 |
Peak memory | 241736 kb |
Host | smart-10b01688-0e99-487b-8f46-08ecbad39fb7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1337246445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.1337246445 |
Directory | /workspace/242.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/243.otp_ctrl_init_fail.2469215261 |
Short name | T1097 |
Test name | |
Test status | |
Simulation time | 126956274 ps |
CPU time | 5.29 seconds |
Started | Mar 31 03:33:55 PM PDT 24 |
Finished | Mar 31 03:34:00 PM PDT 24 |
Peak memory | 241860 kb |
Host | smart-210f1bc4-195c-45aa-8bc4-663e29438ddb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2469215261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.2469215261 |
Directory | /workspace/243.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/244.otp_ctrl_init_fail.3412837061 |
Short name | T1136 |
Test name | |
Test status | |
Simulation time | 204606110 ps |
CPU time | 3.68 seconds |
Started | Mar 31 03:33:54 PM PDT 24 |
Finished | Mar 31 03:33:57 PM PDT 24 |
Peak memory | 242196 kb |
Host | smart-dfd1ae26-6d3d-4b4f-8223-eca4dad98113 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3412837061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.3412837061 |
Directory | /workspace/244.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/245.otp_ctrl_init_fail.3207219059 |
Short name | T496 |
Test name | |
Test status | |
Simulation time | 213254393 ps |
CPU time | 3.84 seconds |
Started | Mar 31 03:33:55 PM PDT 24 |
Finished | Mar 31 03:33:59 PM PDT 24 |
Peak memory | 241624 kb |
Host | smart-7ba4d829-abf2-4661-a9e3-6ba13f0f0706 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3207219059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.3207219059 |
Directory | /workspace/245.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/246.otp_ctrl_init_fail.1327193805 |
Short name | T950 |
Test name | |
Test status | |
Simulation time | 212816930 ps |
CPU time | 4.7 seconds |
Started | Mar 31 03:33:53 PM PDT 24 |
Finished | Mar 31 03:33:58 PM PDT 24 |
Peak memory | 241672 kb |
Host | smart-72566a64-040f-4b4a-8651-5a3639c153b9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1327193805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.1327193805 |
Directory | /workspace/246.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/247.otp_ctrl_init_fail.482949342 |
Short name | T759 |
Test name | |
Test status | |
Simulation time | 558464543 ps |
CPU time | 4.41 seconds |
Started | Mar 31 03:33:55 PM PDT 24 |
Finished | Mar 31 03:33:59 PM PDT 24 |
Peak memory | 242012 kb |
Host | smart-5446fc4d-5802-47a2-b23c-8144426210bb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=482949342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.482949342 |
Directory | /workspace/247.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/248.otp_ctrl_init_fail.2865530315 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 132029466 ps |
CPU time | 3.34 seconds |
Started | Mar 31 03:33:54 PM PDT 24 |
Finished | Mar 31 03:33:58 PM PDT 24 |
Peak memory | 242052 kb |
Host | smart-4ab1bfb4-e243-4891-a69e-3c4f63ea15ec |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2865530315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.2865530315 |
Directory | /workspace/248.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/249.otp_ctrl_init_fail.274656345 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 1760904588 ps |
CPU time | 7.12 seconds |
Started | Mar 31 03:33:54 PM PDT 24 |
Finished | Mar 31 03:34:01 PM PDT 24 |
Peak memory | 241596 kb |
Host | smart-bbec46f5-dbce-43f7-b21e-9e45e6dc04d5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=274656345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.274656345 |
Directory | /workspace/249.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/25.otp_ctrl_alert_test.2111888008 |
Short name | T683 |
Test name | |
Test status | |
Simulation time | 91817060 ps |
CPU time | 1.64 seconds |
Started | Mar 31 03:30:31 PM PDT 24 |
Finished | Mar 31 03:30:33 PM PDT 24 |
Peak memory | 240024 kb |
Host | smart-1bbf34b9-7b26-4914-9264-d086b5c81380 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111888008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.2111888008 |
Directory | /workspace/25.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/25.otp_ctrl_check_fail.2789050577 |
Short name | T856 |
Test name | |
Test status | |
Simulation time | 1292308722 ps |
CPU time | 15.06 seconds |
Started | Mar 31 03:30:26 PM PDT 24 |
Finished | Mar 31 03:30:42 PM PDT 24 |
Peak memory | 242112 kb |
Host | smart-2cc23aea-fae5-4d31-a82f-2fdb42df32a8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2789050577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.2789050577 |
Directory | /workspace/25.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/25.otp_ctrl_dai_errs.1864870511 |
Short name | T679 |
Test name | |
Test status | |
Simulation time | 16798930755 ps |
CPU time | 51.75 seconds |
Started | Mar 31 03:30:23 PM PDT 24 |
Finished | Mar 31 03:31:15 PM PDT 24 |
Peak memory | 249416 kb |
Host | smart-7a931447-283e-44d0-9773-03694fa8abbc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1864870511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_errs.1864870511 |
Directory | /workspace/25.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/25.otp_ctrl_dai_lock.2748048412 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 260032291 ps |
CPU time | 4.61 seconds |
Started | Mar 31 03:30:23 PM PDT 24 |
Finished | Mar 31 03:30:29 PM PDT 24 |
Peak memory | 241644 kb |
Host | smart-7b1a6586-b24f-41a8-bbd7-0bb05c196ef8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2748048412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.2748048412 |
Directory | /workspace/25.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/25.otp_ctrl_init_fail.752446228 |
Short name | T791 |
Test name | |
Test status | |
Simulation time | 255738331 ps |
CPU time | 4.46 seconds |
Started | Mar 31 03:30:24 PM PDT 24 |
Finished | Mar 31 03:30:29 PM PDT 24 |
Peak memory | 241804 kb |
Host | smart-812d2d19-b546-4663-9364-eb96b37896de |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=752446228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.752446228 |
Directory | /workspace/25.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/25.otp_ctrl_macro_errs.28640910 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 2958701377 ps |
CPU time | 44.82 seconds |
Started | Mar 31 03:30:29 PM PDT 24 |
Finished | Mar 31 03:31:14 PM PDT 24 |
Peak memory | 248780 kb |
Host | smart-cb8d00b1-07a2-4806-aaca-479d4751f73a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=28640910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.28640910 |
Directory | /workspace/25.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/25.otp_ctrl_parallel_key_req.3749499715 |
Short name | T1019 |
Test name | |
Test status | |
Simulation time | 6558536156 ps |
CPU time | 38.14 seconds |
Started | Mar 31 03:30:29 PM PDT 24 |
Finished | Mar 31 03:31:08 PM PDT 24 |
Peak memory | 242784 kb |
Host | smart-cb1e3b05-44d6-4e97-b931-a29086104c57 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3749499715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_key_req.3749499715 |
Directory | /workspace/25.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/25.otp_ctrl_parallel_lc_esc.1150433806 |
Short name | T443 |
Test name | |
Test status | |
Simulation time | 141768379 ps |
CPU time | 5.69 seconds |
Started | Mar 31 03:30:23 PM PDT 24 |
Finished | Mar 31 03:30:30 PM PDT 24 |
Peak memory | 241428 kb |
Host | smart-0c5fc187-6fe7-4de7-9a6c-58233eddbf5f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1150433806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.1150433806 |
Directory | /workspace/25.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/25.otp_ctrl_parallel_lc_req.297842789 |
Short name | T611 |
Test name | |
Test status | |
Simulation time | 288030202 ps |
CPU time | 4.53 seconds |
Started | Mar 31 03:30:25 PM PDT 24 |
Finished | Mar 31 03:30:30 PM PDT 24 |
Peak memory | 241624 kb |
Host | smart-13abc040-3302-48ef-b626-0162084bb955 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=297842789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_req.297842789 |
Directory | /workspace/25.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/25.otp_ctrl_regwen.3064849708 |
Short name | T495 |
Test name | |
Test status | |
Simulation time | 102841307 ps |
CPU time | 4.14 seconds |
Started | Mar 31 03:30:28 PM PDT 24 |
Finished | Mar 31 03:30:32 PM PDT 24 |
Peak memory | 241632 kb |
Host | smart-5da80d96-94f8-4bb7-a650-871abcb6fdfc |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3064849708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.3064849708 |
Directory | /workspace/25.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/25.otp_ctrl_smoke.2540711576 |
Short name | T798 |
Test name | |
Test status | |
Simulation time | 806902434 ps |
CPU time | 4.75 seconds |
Started | Mar 31 03:30:25 PM PDT 24 |
Finished | Mar 31 03:30:31 PM PDT 24 |
Peak memory | 241936 kb |
Host | smart-6db1214a-cd8b-4ec3-8ca1-a48871f23354 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2540711576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.2540711576 |
Directory | /workspace/25.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/25.otp_ctrl_stress_all.2708552287 |
Short name | T530 |
Test name | |
Test status | |
Simulation time | 6107384229 ps |
CPU time | 86.53 seconds |
Started | Mar 31 03:30:31 PM PDT 24 |
Finished | Mar 31 03:31:58 PM PDT 24 |
Peak memory | 248676 kb |
Host | smart-602d43f5-a809-4087-b822-bc488cd6fb0d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708552287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all .2708552287 |
Directory | /workspace/25.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/25.otp_ctrl_test_access.1664306766 |
Short name | T1059 |
Test name | |
Test status | |
Simulation time | 2854932934 ps |
CPU time | 16.92 seconds |
Started | Mar 31 03:30:30 PM PDT 24 |
Finished | Mar 31 03:30:47 PM PDT 24 |
Peak memory | 242472 kb |
Host | smart-80fc094f-1aa3-499c-b543-34df5c64fd27 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1664306766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.1664306766 |
Directory | /workspace/25.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/250.otp_ctrl_init_fail.2311207722 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 237022767 ps |
CPU time | 3.93 seconds |
Started | Mar 31 03:34:04 PM PDT 24 |
Finished | Mar 31 03:34:09 PM PDT 24 |
Peak memory | 241668 kb |
Host | smart-433292f8-f8ce-447e-9cf2-417f57947a10 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2311207722 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.2311207722 |
Directory | /workspace/250.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/251.otp_ctrl_init_fail.2043572255 |
Short name | T745 |
Test name | |
Test status | |
Simulation time | 193870049 ps |
CPU time | 3.25 seconds |
Started | Mar 31 03:34:01 PM PDT 24 |
Finished | Mar 31 03:34:05 PM PDT 24 |
Peak memory | 241568 kb |
Host | smart-d9dde5e2-3dd1-4871-aee7-a5210fbcc873 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2043572255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.2043572255 |
Directory | /workspace/251.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/252.otp_ctrl_init_fail.1731789117 |
Short name | T640 |
Test name | |
Test status | |
Simulation time | 618841080 ps |
CPU time | 4.46 seconds |
Started | Mar 31 03:33:58 PM PDT 24 |
Finished | Mar 31 03:34:02 PM PDT 24 |
Peak memory | 241672 kb |
Host | smart-5c530d59-f881-4eb4-a25d-1f4911229187 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1731789117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.1731789117 |
Directory | /workspace/252.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/253.otp_ctrl_init_fail.2833181326 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 447922060 ps |
CPU time | 4.78 seconds |
Started | Mar 31 03:34:00 PM PDT 24 |
Finished | Mar 31 03:34:04 PM PDT 24 |
Peak memory | 241744 kb |
Host | smart-34ee8cc8-584f-4ecf-b86d-30f17932323d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2833181326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.2833181326 |
Directory | /workspace/253.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/254.otp_ctrl_init_fail.955591387 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 303099702 ps |
CPU time | 4.54 seconds |
Started | Mar 31 03:34:02 PM PDT 24 |
Finished | Mar 31 03:34:07 PM PDT 24 |
Peak memory | 241880 kb |
Host | smart-079cb3f7-19c4-4536-8483-f3da4eefe9ff |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=955591387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.955591387 |
Directory | /workspace/254.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/255.otp_ctrl_init_fail.106605509 |
Short name | T911 |
Test name | |
Test status | |
Simulation time | 201865631 ps |
CPU time | 3.63 seconds |
Started | Mar 31 03:34:01 PM PDT 24 |
Finished | Mar 31 03:34:05 PM PDT 24 |
Peak memory | 241624 kb |
Host | smart-470b2f9f-cd03-4020-aa6f-57e20ffd6b24 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=106605509 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.106605509 |
Directory | /workspace/255.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/256.otp_ctrl_init_fail.1403561533 |
Short name | T653 |
Test name | |
Test status | |
Simulation time | 161055095 ps |
CPU time | 4.3 seconds |
Started | Mar 31 03:34:03 PM PDT 24 |
Finished | Mar 31 03:34:07 PM PDT 24 |
Peak memory | 241924 kb |
Host | smart-80c1e280-5629-4803-82da-92f08916d4ba |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1403561533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.1403561533 |
Directory | /workspace/256.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/257.otp_ctrl_init_fail.1814208299 |
Short name | T747 |
Test name | |
Test status | |
Simulation time | 136423035 ps |
CPU time | 2.97 seconds |
Started | Mar 31 03:33:58 PM PDT 24 |
Finished | Mar 31 03:34:01 PM PDT 24 |
Peak memory | 241696 kb |
Host | smart-8c0e3928-4d0d-4b48-af6e-7613f3530d6e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1814208299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.1814208299 |
Directory | /workspace/257.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/258.otp_ctrl_init_fail.1128806562 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 280122736 ps |
CPU time | 3.55 seconds |
Started | Mar 31 03:34:00 PM PDT 24 |
Finished | Mar 31 03:34:04 PM PDT 24 |
Peak memory | 241996 kb |
Host | smart-8d8d12a7-b929-4211-8f11-2eef14454801 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1128806562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.1128806562 |
Directory | /workspace/258.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/259.otp_ctrl_init_fail.3550485300 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 289219008 ps |
CPU time | 4.31 seconds |
Started | Mar 31 03:34:02 PM PDT 24 |
Finished | Mar 31 03:34:07 PM PDT 24 |
Peak memory | 241996 kb |
Host | smart-2324b5b8-9cac-4116-86e2-9de12f22c3ad |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3550485300 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.3550485300 |
Directory | /workspace/259.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/26.otp_ctrl_alert_test.2002157499 |
Short name | T754 |
Test name | |
Test status | |
Simulation time | 201072206 ps |
CPU time | 1.87 seconds |
Started | Mar 31 03:30:36 PM PDT 24 |
Finished | Mar 31 03:30:38 PM PDT 24 |
Peak memory | 240064 kb |
Host | smart-599e652d-60db-409b-93b2-00ddae11d508 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002157499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.2002157499 |
Directory | /workspace/26.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/26.otp_ctrl_dai_errs.2463791449 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 13335334593 ps |
CPU time | 21.94 seconds |
Started | Mar 31 03:30:30 PM PDT 24 |
Finished | Mar 31 03:30:52 PM PDT 24 |
Peak memory | 242060 kb |
Host | smart-3eca3971-0250-438b-b862-28c35e984672 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2463791449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.2463791449 |
Directory | /workspace/26.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/26.otp_ctrl_dai_lock.1852288903 |
Short name | T722 |
Test name | |
Test status | |
Simulation time | 2624411403 ps |
CPU time | 27.1 seconds |
Started | Mar 31 03:30:31 PM PDT 24 |
Finished | Mar 31 03:30:58 PM PDT 24 |
Peak memory | 242552 kb |
Host | smart-bff35912-6495-475f-9172-817172241f51 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1852288903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.1852288903 |
Directory | /workspace/26.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/26.otp_ctrl_init_fail.151027681 |
Short name | T1174 |
Test name | |
Test status | |
Simulation time | 130050930 ps |
CPU time | 3.54 seconds |
Started | Mar 31 03:30:32 PM PDT 24 |
Finished | Mar 31 03:30:35 PM PDT 24 |
Peak memory | 241736 kb |
Host | smart-fb6c39ed-0803-4dc4-80f8-2eb72478dfea |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=151027681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.151027681 |
Directory | /workspace/26.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/26.otp_ctrl_macro_errs.3335619814 |
Short name | T632 |
Test name | |
Test status | |
Simulation time | 1344088177 ps |
CPU time | 13.37 seconds |
Started | Mar 31 03:30:31 PM PDT 24 |
Finished | Mar 31 03:30:45 PM PDT 24 |
Peak memory | 242120 kb |
Host | smart-5820c99c-c526-4026-bb7d-4cb13d6d8c15 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3335619814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.3335619814 |
Directory | /workspace/26.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/26.otp_ctrl_parallel_key_req.1761036546 |
Short name | T1161 |
Test name | |
Test status | |
Simulation time | 1464692655 ps |
CPU time | 36.97 seconds |
Started | Mar 31 03:30:30 PM PDT 24 |
Finished | Mar 31 03:31:07 PM PDT 24 |
Peak memory | 242076 kb |
Host | smart-6ee4b299-7042-4b2a-9e18-94f6f4ce5d6b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1761036546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.1761036546 |
Directory | /workspace/26.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/26.otp_ctrl_parallel_lc_esc.1097870195 |
Short name | T553 |
Test name | |
Test status | |
Simulation time | 2359882751 ps |
CPU time | 15.94 seconds |
Started | Mar 31 03:30:30 PM PDT 24 |
Finished | Mar 31 03:30:46 PM PDT 24 |
Peak memory | 242020 kb |
Host | smart-93b3e319-1865-4714-bbbb-288a01dfa7db |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1097870195 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.1097870195 |
Directory | /workspace/26.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/26.otp_ctrl_parallel_lc_req.1728841970 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 11551890617 ps |
CPU time | 22.76 seconds |
Started | Mar 31 03:30:31 PM PDT 24 |
Finished | Mar 31 03:30:54 PM PDT 24 |
Peak memory | 241668 kb |
Host | smart-039f1c5a-5e2e-4958-8ead-7b2f6abc31b3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1728841970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.1728841970 |
Directory | /workspace/26.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/26.otp_ctrl_regwen.2359662808 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 1215033906 ps |
CPU time | 10.28 seconds |
Started | Mar 31 03:30:31 PM PDT 24 |
Finished | Mar 31 03:30:42 PM PDT 24 |
Peak memory | 242028 kb |
Host | smart-38df16df-a3da-4e86-9623-523237fb2fcb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2359662808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.2359662808 |
Directory | /workspace/26.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/26.otp_ctrl_smoke.3234382512 |
Short name | T884 |
Test name | |
Test status | |
Simulation time | 1930162575 ps |
CPU time | 11.88 seconds |
Started | Mar 31 03:30:30 PM PDT 24 |
Finished | Mar 31 03:30:42 PM PDT 24 |
Peak memory | 241572 kb |
Host | smart-8eaa85f4-5548-4acf-8f37-a3e7f20b68ae |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3234382512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.3234382512 |
Directory | /workspace/26.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/26.otp_ctrl_stress_all_with_rand_reset.3759444114 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 63687806919 ps |
CPU time | 524.93 seconds |
Started | Mar 31 03:30:36 PM PDT 24 |
Finished | Mar 31 03:39:21 PM PDT 24 |
Peak memory | 259216 kb |
Host | smart-a2722bc8-a840-4a0c-bb54-b1e2f8c9a703 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759444114 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all_with_rand_reset.3759444114 |
Directory | /workspace/26.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/26.otp_ctrl_test_access.202054936 |
Short name | T765 |
Test name | |
Test status | |
Simulation time | 545732874 ps |
CPU time | 12.01 seconds |
Started | Mar 31 03:30:38 PM PDT 24 |
Finished | Mar 31 03:30:50 PM PDT 24 |
Peak memory | 241860 kb |
Host | smart-6fa8074b-efb3-4d1a-adba-4ab62f9804bb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=202054936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.202054936 |
Directory | /workspace/26.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/261.otp_ctrl_init_fail.4231853293 |
Short name | T649 |
Test name | |
Test status | |
Simulation time | 390275286 ps |
CPU time | 3.33 seconds |
Started | Mar 31 03:34:00 PM PDT 24 |
Finished | Mar 31 03:34:04 PM PDT 24 |
Peak memory | 241704 kb |
Host | smart-8c961c10-6fed-4cdb-8222-96f7bc74e653 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4231853293 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.4231853293 |
Directory | /workspace/261.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/262.otp_ctrl_init_fail.1440893998 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 105839391 ps |
CPU time | 4.48 seconds |
Started | Mar 31 03:34:02 PM PDT 24 |
Finished | Mar 31 03:34:07 PM PDT 24 |
Peak memory | 241656 kb |
Host | smart-2bc904b9-7899-4e68-a267-2e09498b8a20 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1440893998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.1440893998 |
Directory | /workspace/262.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/263.otp_ctrl_init_fail.2224355449 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 194482555 ps |
CPU time | 3.79 seconds |
Started | Mar 31 03:33:58 PM PDT 24 |
Finished | Mar 31 03:34:02 PM PDT 24 |
Peak memory | 241704 kb |
Host | smart-1b6d90af-d439-4cc9-a575-f0c348eece81 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2224355449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.2224355449 |
Directory | /workspace/263.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/264.otp_ctrl_init_fail.2096398858 |
Short name | T449 |
Test name | |
Test status | |
Simulation time | 331680530 ps |
CPU time | 4.57 seconds |
Started | Mar 31 03:34:04 PM PDT 24 |
Finished | Mar 31 03:34:09 PM PDT 24 |
Peak memory | 241648 kb |
Host | smart-420a443c-5b5b-4777-917e-88cbd8cc20c4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2096398858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.2096398858 |
Directory | /workspace/264.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/265.otp_ctrl_init_fail.353642519 |
Short name | T999 |
Test name | |
Test status | |
Simulation time | 690047544 ps |
CPU time | 5.81 seconds |
Started | Mar 31 03:33:59 PM PDT 24 |
Finished | Mar 31 03:34:05 PM PDT 24 |
Peak memory | 242092 kb |
Host | smart-4776f27d-2121-47df-ac49-0ae01d8b4710 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=353642519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.353642519 |
Directory | /workspace/265.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/267.otp_ctrl_init_fail.1853491455 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 2817736680 ps |
CPU time | 5.83 seconds |
Started | Mar 31 03:33:59 PM PDT 24 |
Finished | Mar 31 03:34:05 PM PDT 24 |
Peak memory | 242128 kb |
Host | smart-e60f7b8e-bbbc-4b7c-8d63-70ba7b758dbd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1853491455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.1853491455 |
Directory | /workspace/267.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/268.otp_ctrl_init_fail.4115008753 |
Short name | T625 |
Test name | |
Test status | |
Simulation time | 168993938 ps |
CPU time | 3.89 seconds |
Started | Mar 31 03:34:04 PM PDT 24 |
Finished | Mar 31 03:34:09 PM PDT 24 |
Peak memory | 241576 kb |
Host | smart-bd23bef5-4484-4d5a-9252-720249c1ea50 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4115008753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.4115008753 |
Directory | /workspace/268.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/269.otp_ctrl_init_fail.2602626710 |
Short name | T622 |
Test name | |
Test status | |
Simulation time | 2578002962 ps |
CPU time | 5.41 seconds |
Started | Mar 31 03:33:57 PM PDT 24 |
Finished | Mar 31 03:34:03 PM PDT 24 |
Peak memory | 241752 kb |
Host | smart-c51591dc-a198-40c6-9cf6-85040623aa02 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2602626710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.2602626710 |
Directory | /workspace/269.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/27.otp_ctrl_alert_test.13899346 |
Short name | T914 |
Test name | |
Test status | |
Simulation time | 76864609 ps |
CPU time | 1.74 seconds |
Started | Mar 31 03:30:38 PM PDT 24 |
Finished | Mar 31 03:30:40 PM PDT 24 |
Peak memory | 240096 kb |
Host | smart-c4d2a7aa-9547-4f2a-817a-025e3b0c8936 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13899346 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.13899346 |
Directory | /workspace/27.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/27.otp_ctrl_check_fail.3270433691 |
Short name | T1184 |
Test name | |
Test status | |
Simulation time | 990570566 ps |
CPU time | 12.52 seconds |
Started | Mar 31 03:30:36 PM PDT 24 |
Finished | Mar 31 03:30:49 PM PDT 24 |
Peak memory | 242516 kb |
Host | smart-37f1194b-9ce2-4a60-b18a-d1820a701578 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3270433691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.3270433691 |
Directory | /workspace/27.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/27.otp_ctrl_dai_errs.1716306745 |
Short name | T821 |
Test name | |
Test status | |
Simulation time | 21388498751 ps |
CPU time | 75.14 seconds |
Started | Mar 31 03:30:38 PM PDT 24 |
Finished | Mar 31 03:31:53 PM PDT 24 |
Peak memory | 252752 kb |
Host | smart-6c4c3afb-6b8c-481b-98bc-5bdfdfc8374e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1716306745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_errs.1716306745 |
Directory | /workspace/27.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/27.otp_ctrl_dai_lock.2880862706 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 2945636048 ps |
CPU time | 35.35 seconds |
Started | Mar 31 03:30:37 PM PDT 24 |
Finished | Mar 31 03:31:13 PM PDT 24 |
Peak memory | 242480 kb |
Host | smart-c5c8ec6a-4a74-4e30-8d42-8684b66a67e3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2880862706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.2880862706 |
Directory | /workspace/27.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/27.otp_ctrl_init_fail.1407680195 |
Short name | T1191 |
Test name | |
Test status | |
Simulation time | 115532890 ps |
CPU time | 4.03 seconds |
Started | Mar 31 03:30:37 PM PDT 24 |
Finished | Mar 31 03:30:41 PM PDT 24 |
Peak memory | 241700 kb |
Host | smart-4f164ea3-9063-4621-96d7-0c24908000ab |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1407680195 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.1407680195 |
Directory | /workspace/27.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/27.otp_ctrl_macro_errs.243528658 |
Short name | T668 |
Test name | |
Test status | |
Simulation time | 1759686979 ps |
CPU time | 33.33 seconds |
Started | Mar 31 03:30:39 PM PDT 24 |
Finished | Mar 31 03:31:12 PM PDT 24 |
Peak memory | 248636 kb |
Host | smart-769fd938-ed37-43fb-bfe4-c9365cca76b8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=243528658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.243528658 |
Directory | /workspace/27.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/27.otp_ctrl_parallel_lc_esc.1219642641 |
Short name | T1104 |
Test name | |
Test status | |
Simulation time | 212809755 ps |
CPU time | 6 seconds |
Started | Mar 31 03:30:37 PM PDT 24 |
Finished | Mar 31 03:30:43 PM PDT 24 |
Peak memory | 241680 kb |
Host | smart-108c5bbc-3558-431b-9546-8d5aae69e673 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1219642641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.1219642641 |
Directory | /workspace/27.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/27.otp_ctrl_parallel_lc_req.2945078233 |
Short name | T1041 |
Test name | |
Test status | |
Simulation time | 4011713276 ps |
CPU time | 11.27 seconds |
Started | Mar 31 03:30:42 PM PDT 24 |
Finished | Mar 31 03:30:54 PM PDT 24 |
Peak memory | 241932 kb |
Host | smart-cecd4ab9-d837-4f09-b1c3-b03cd88201ff |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2945078233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.2945078233 |
Directory | /workspace/27.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/27.otp_ctrl_regwen.4072146428 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 1256634772 ps |
CPU time | 8.93 seconds |
Started | Mar 31 03:30:37 PM PDT 24 |
Finished | Mar 31 03:30:46 PM PDT 24 |
Peak memory | 241856 kb |
Host | smart-fca0e13e-3298-494b-9fbe-5c4c144a4016 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4072146428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.4072146428 |
Directory | /workspace/27.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/27.otp_ctrl_smoke.592782420 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 237606501 ps |
CPU time | 6.91 seconds |
Started | Mar 31 03:30:36 PM PDT 24 |
Finished | Mar 31 03:30:44 PM PDT 24 |
Peak memory | 248676 kb |
Host | smart-5c69ab8e-f968-4ae4-9a49-9730cc6b35f0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=592782420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_smoke.592782420 |
Directory | /workspace/27.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/27.otp_ctrl_stress_all_with_rand_reset.772455137 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 27683607002 ps |
CPU time | 690.17 seconds |
Started | Mar 31 03:30:42 PM PDT 24 |
Finished | Mar 31 03:42:13 PM PDT 24 |
Peak memory | 260828 kb |
Host | smart-bf23d6aa-473a-4694-aac5-51b247282666 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772455137 -assert nopo stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all_with_rand_reset.772455137 |
Directory | /workspace/27.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/27.otp_ctrl_test_access.2133034722 |
Short name | T729 |
Test name | |
Test status | |
Simulation time | 9030479041 ps |
CPU time | 26.6 seconds |
Started | Mar 31 03:30:37 PM PDT 24 |
Finished | Mar 31 03:31:05 PM PDT 24 |
Peak memory | 241788 kb |
Host | smart-285919a7-9427-4894-92e8-a9a9d0406ea9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2133034722 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_test_access.2133034722 |
Directory | /workspace/27.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/270.otp_ctrl_init_fail.4093497489 |
Short name | T861 |
Test name | |
Test status | |
Simulation time | 128089570 ps |
CPU time | 3.54 seconds |
Started | Mar 31 03:34:02 PM PDT 24 |
Finished | Mar 31 03:34:06 PM PDT 24 |
Peak memory | 242084 kb |
Host | smart-766c7577-91fd-4f8d-b79a-a501d216abc1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4093497489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.4093497489 |
Directory | /workspace/270.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/271.otp_ctrl_init_fail.3677631210 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 2233041799 ps |
CPU time | 4.43 seconds |
Started | Mar 31 03:34:03 PM PDT 24 |
Finished | Mar 31 03:34:08 PM PDT 24 |
Peak memory | 241728 kb |
Host | smart-4ac3ad04-370d-407c-ac3b-a2bcd9badf5a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3677631210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.3677631210 |
Directory | /workspace/271.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/272.otp_ctrl_init_fail.3457821170 |
Short name | T817 |
Test name | |
Test status | |
Simulation time | 175333076 ps |
CPU time | 3.6 seconds |
Started | Mar 31 03:34:05 PM PDT 24 |
Finished | Mar 31 03:34:08 PM PDT 24 |
Peak memory | 241728 kb |
Host | smart-81cf6fbd-bd78-4a5c-b1fc-6b3b26d4b78b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3457821170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.3457821170 |
Directory | /workspace/272.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/274.otp_ctrl_init_fail.2488549099 |
Short name | T1042 |
Test name | |
Test status | |
Simulation time | 364861199 ps |
CPU time | 5.76 seconds |
Started | Mar 31 03:34:05 PM PDT 24 |
Finished | Mar 31 03:34:11 PM PDT 24 |
Peak memory | 241692 kb |
Host | smart-1df63333-88b2-4a15-a92c-97311302f909 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2488549099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.2488549099 |
Directory | /workspace/274.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/275.otp_ctrl_init_fail.922626510 |
Short name | T694 |
Test name | |
Test status | |
Simulation time | 163234238 ps |
CPU time | 3.09 seconds |
Started | Mar 31 03:34:04 PM PDT 24 |
Finished | Mar 31 03:34:08 PM PDT 24 |
Peak memory | 241608 kb |
Host | smart-aebda651-4383-443b-a7a1-f312f5c2ab6b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=922626510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.922626510 |
Directory | /workspace/275.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/276.otp_ctrl_init_fail.3134213998 |
Short name | T442 |
Test name | |
Test status | |
Simulation time | 131411573 ps |
CPU time | 5.18 seconds |
Started | Mar 31 03:34:07 PM PDT 24 |
Finished | Mar 31 03:34:12 PM PDT 24 |
Peak memory | 241792 kb |
Host | smart-84fc9fc9-0306-4462-b132-3c52d1d8626a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3134213998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.3134213998 |
Directory | /workspace/276.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/278.otp_ctrl_init_fail.3711508870 |
Short name | T1050 |
Test name | |
Test status | |
Simulation time | 179259143 ps |
CPU time | 4.71 seconds |
Started | Mar 31 03:34:07 PM PDT 24 |
Finished | Mar 31 03:34:12 PM PDT 24 |
Peak memory | 241804 kb |
Host | smart-dd4690aa-eb77-495b-ae45-5ab85e06b98b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3711508870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.3711508870 |
Directory | /workspace/278.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/279.otp_ctrl_init_fail.2259972309 |
Short name | T748 |
Test name | |
Test status | |
Simulation time | 275447734 ps |
CPU time | 3.81 seconds |
Started | Mar 31 03:34:02 PM PDT 24 |
Finished | Mar 31 03:34:06 PM PDT 24 |
Peak memory | 242112 kb |
Host | smart-fa2cbb6c-55eb-4f0a-94af-01828fd1b230 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2259972309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.2259972309 |
Directory | /workspace/279.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/28.otp_ctrl_alert_test.45139249 |
Short name | T858 |
Test name | |
Test status | |
Simulation time | 64171486 ps |
CPU time | 2 seconds |
Started | Mar 31 03:30:44 PM PDT 24 |
Finished | Mar 31 03:30:46 PM PDT 24 |
Peak memory | 240156 kb |
Host | smart-11ed479c-3385-4ff3-83b2-1cfb09ee4297 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45139249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.45139249 |
Directory | /workspace/28.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/28.otp_ctrl_check_fail.2248977190 |
Short name | T1143 |
Test name | |
Test status | |
Simulation time | 618811755 ps |
CPU time | 16.59 seconds |
Started | Mar 31 03:30:45 PM PDT 24 |
Finished | Mar 31 03:31:02 PM PDT 24 |
Peak memory | 242292 kb |
Host | smart-9c70b303-07fb-49a3-8aac-fdf916771119 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2248977190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.2248977190 |
Directory | /workspace/28.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/28.otp_ctrl_dai_errs.1100307330 |
Short name | T841 |
Test name | |
Test status | |
Simulation time | 6585419595 ps |
CPU time | 20.49 seconds |
Started | Mar 31 03:30:43 PM PDT 24 |
Finished | Mar 31 03:31:04 PM PDT 24 |
Peak memory | 241872 kb |
Host | smart-db1fb3e2-fb22-4363-9972-bc6214914f18 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1100307330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.1100307330 |
Directory | /workspace/28.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/28.otp_ctrl_dai_lock.4076277117 |
Short name | T690 |
Test name | |
Test status | |
Simulation time | 10244294945 ps |
CPU time | 30.44 seconds |
Started | Mar 31 03:30:42 PM PDT 24 |
Finished | Mar 31 03:31:12 PM PDT 24 |
Peak memory | 242656 kb |
Host | smart-e093df57-ff08-4353-9be6-4d87b16cb92c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4076277117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.4076277117 |
Directory | /workspace/28.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/28.otp_ctrl_init_fail.726881367 |
Short name | T1160 |
Test name | |
Test status | |
Simulation time | 1743577651 ps |
CPU time | 5.23 seconds |
Started | Mar 31 03:30:41 PM PDT 24 |
Finished | Mar 31 03:30:47 PM PDT 24 |
Peak memory | 241672 kb |
Host | smart-55db7117-8395-4551-b479-2c8af5294088 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=726881367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.726881367 |
Directory | /workspace/28.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/28.otp_ctrl_macro_errs.1828950063 |
Short name | T719 |
Test name | |
Test status | |
Simulation time | 749105141 ps |
CPU time | 21.2 seconds |
Started | Mar 31 03:30:42 PM PDT 24 |
Finished | Mar 31 03:31:04 PM PDT 24 |
Peak memory | 244724 kb |
Host | smart-98d3fcd4-dad9-45df-a047-773fa7e1e4c5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1828950063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.1828950063 |
Directory | /workspace/28.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/28.otp_ctrl_parallel_key_req.1846581204 |
Short name | T718 |
Test name | |
Test status | |
Simulation time | 1080235844 ps |
CPU time | 12.87 seconds |
Started | Mar 31 03:30:43 PM PDT 24 |
Finished | Mar 31 03:30:56 PM PDT 24 |
Peak memory | 242048 kb |
Host | smart-960e08a9-b661-4625-ac25-b2c2916a181a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1846581204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.1846581204 |
Directory | /workspace/28.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/28.otp_ctrl_parallel_lc_esc.892762126 |
Short name | T575 |
Test name | |
Test status | |
Simulation time | 253555445 ps |
CPU time | 3.15 seconds |
Started | Mar 31 03:30:42 PM PDT 24 |
Finished | Mar 31 03:30:45 PM PDT 24 |
Peak memory | 241952 kb |
Host | smart-1c87ba5b-6480-417d-8ca1-87925454e004 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=892762126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.892762126 |
Directory | /workspace/28.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/28.otp_ctrl_parallel_lc_req.3007231209 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 530949242 ps |
CPU time | 5.1 seconds |
Started | Mar 31 03:30:44 PM PDT 24 |
Finished | Mar 31 03:30:49 PM PDT 24 |
Peak memory | 241564 kb |
Host | smart-db7dc7ad-75e4-4460-95c8-6b484ac0bc16 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3007231209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.3007231209 |
Directory | /workspace/28.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/28.otp_ctrl_regwen.664584685 |
Short name | T1156 |
Test name | |
Test status | |
Simulation time | 840515772 ps |
CPU time | 7.59 seconds |
Started | Mar 31 03:30:42 PM PDT 24 |
Finished | Mar 31 03:30:50 PM PDT 24 |
Peak memory | 241672 kb |
Host | smart-00f4ce0e-ad7b-4445-8573-1d8f74601a1b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=664584685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.664584685 |
Directory | /workspace/28.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/28.otp_ctrl_smoke.2956532898 |
Short name | T1125 |
Test name | |
Test status | |
Simulation time | 808762783 ps |
CPU time | 10.31 seconds |
Started | Mar 31 03:30:41 PM PDT 24 |
Finished | Mar 31 03:30:52 PM PDT 24 |
Peak memory | 241596 kb |
Host | smart-068d2e74-8a40-4d5c-8a82-c25408b89944 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2956532898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.2956532898 |
Directory | /workspace/28.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/28.otp_ctrl_stress_all_with_rand_reset.3373130705 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 157551891427 ps |
CPU time | 1082 seconds |
Started | Mar 31 03:30:44 PM PDT 24 |
Finished | Mar 31 03:48:46 PM PDT 24 |
Peak memory | 306212 kb |
Host | smart-af304177-a214-4911-811a-68bcc5214f55 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373130705 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all_with_rand_reset.3373130705 |
Directory | /workspace/28.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/28.otp_ctrl_test_access.3287616440 |
Short name | T909 |
Test name | |
Test status | |
Simulation time | 938293565 ps |
CPU time | 16.29 seconds |
Started | Mar 31 03:30:44 PM PDT 24 |
Finished | Mar 31 03:31:00 PM PDT 24 |
Peak memory | 242016 kb |
Host | smart-c1197992-ec73-4c6e-b801-eaf50cdaa83a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3287616440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_test_access.3287616440 |
Directory | /workspace/28.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/280.otp_ctrl_init_fail.3701202116 |
Short name | T814 |
Test name | |
Test status | |
Simulation time | 118072070 ps |
CPU time | 3.28 seconds |
Started | Mar 31 03:34:04 PM PDT 24 |
Finished | Mar 31 03:34:08 PM PDT 24 |
Peak memory | 241912 kb |
Host | smart-6d1ebd1c-4680-49d2-be77-dd3163ef6642 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3701202116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.3701202116 |
Directory | /workspace/280.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/281.otp_ctrl_init_fail.3427503580 |
Short name | T643 |
Test name | |
Test status | |
Simulation time | 458357758 ps |
CPU time | 4.58 seconds |
Started | Mar 31 03:34:06 PM PDT 24 |
Finished | Mar 31 03:34:10 PM PDT 24 |
Peak memory | 241708 kb |
Host | smart-c28bfc8e-7ed3-407e-85c0-6702f49c5cad |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3427503580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.3427503580 |
Directory | /workspace/281.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/282.otp_ctrl_init_fail.229589909 |
Short name | T493 |
Test name | |
Test status | |
Simulation time | 254514030 ps |
CPU time | 3.52 seconds |
Started | Mar 31 03:34:04 PM PDT 24 |
Finished | Mar 31 03:34:08 PM PDT 24 |
Peak memory | 241724 kb |
Host | smart-d7475050-9da0-451b-a033-343afa81f77a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=229589909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.229589909 |
Directory | /workspace/282.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/283.otp_ctrl_init_fail.2516733342 |
Short name | T1013 |
Test name | |
Test status | |
Simulation time | 1822746064 ps |
CPU time | 5.57 seconds |
Started | Mar 31 03:34:05 PM PDT 24 |
Finished | Mar 31 03:34:11 PM PDT 24 |
Peak memory | 241880 kb |
Host | smart-bfa3513a-44ab-4e04-8fa7-0db0f77a1b03 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2516733342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.2516733342 |
Directory | /workspace/283.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/284.otp_ctrl_init_fail.4055735045 |
Short name | T701 |
Test name | |
Test status | |
Simulation time | 103381546 ps |
CPU time | 3.78 seconds |
Started | Mar 31 03:34:07 PM PDT 24 |
Finished | Mar 31 03:34:11 PM PDT 24 |
Peak memory | 241736 kb |
Host | smart-5da9a03c-065c-44fd-ba27-9df1344e1368 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4055735045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.4055735045 |
Directory | /workspace/284.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/285.otp_ctrl_init_fail.1539431454 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 213551651 ps |
CPU time | 5.04 seconds |
Started | Mar 31 03:34:06 PM PDT 24 |
Finished | Mar 31 03:34:11 PM PDT 24 |
Peak memory | 241984 kb |
Host | smart-1bbcd509-9cdb-45df-a3f4-85d846ff65a2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1539431454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.1539431454 |
Directory | /workspace/285.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/286.otp_ctrl_init_fail.143050132 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 325944647 ps |
CPU time | 4.72 seconds |
Started | Mar 31 03:34:06 PM PDT 24 |
Finished | Mar 31 03:34:11 PM PDT 24 |
Peak memory | 241720 kb |
Host | smart-0d0724a5-017e-4257-a01a-fc95d8d7c142 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=143050132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.143050132 |
Directory | /workspace/286.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/287.otp_ctrl_init_fail.3871448693 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 351584343 ps |
CPU time | 4.36 seconds |
Started | Mar 31 03:34:05 PM PDT 24 |
Finished | Mar 31 03:34:10 PM PDT 24 |
Peak memory | 241796 kb |
Host | smart-d406bc8d-c18f-440a-b69e-7c0b886bf7ae |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3871448693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.3871448693 |
Directory | /workspace/287.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/288.otp_ctrl_init_fail.1421094442 |
Short name | T1089 |
Test name | |
Test status | |
Simulation time | 379728177 ps |
CPU time | 3.9 seconds |
Started | Mar 31 03:34:13 PM PDT 24 |
Finished | Mar 31 03:34:17 PM PDT 24 |
Peak memory | 241728 kb |
Host | smart-25af9f7e-940d-4f50-8584-847810f20993 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1421094442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.1421094442 |
Directory | /workspace/288.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/289.otp_ctrl_init_fail.681470871 |
Short name | T1081 |
Test name | |
Test status | |
Simulation time | 199353138 ps |
CPU time | 3.54 seconds |
Started | Mar 31 03:34:10 PM PDT 24 |
Finished | Mar 31 03:34:13 PM PDT 24 |
Peak memory | 241740 kb |
Host | smart-69241a7d-e6a1-4f0f-b44f-184589bb32ac |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=681470871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.681470871 |
Directory | /workspace/289.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/29.otp_ctrl_alert_test.2842731637 |
Short name | T742 |
Test name | |
Test status | |
Simulation time | 96445960 ps |
CPU time | 1.97 seconds |
Started | Mar 31 03:30:50 PM PDT 24 |
Finished | Mar 31 03:30:52 PM PDT 24 |
Peak memory | 240044 kb |
Host | smart-75402d05-ee2b-42ea-ab20-6a5a6907245d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842731637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.2842731637 |
Directory | /workspace/29.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/29.otp_ctrl_check_fail.1297953925 |
Short name | T905 |
Test name | |
Test status | |
Simulation time | 2513299999 ps |
CPU time | 41.46 seconds |
Started | Mar 31 03:30:41 PM PDT 24 |
Finished | Mar 31 03:31:22 PM PDT 24 |
Peak memory | 245364 kb |
Host | smart-107ed768-c6bc-4755-ba63-bb536f37ca90 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1297953925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.1297953925 |
Directory | /workspace/29.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/29.otp_ctrl_dai_errs.195580504 |
Short name | T1091 |
Test name | |
Test status | |
Simulation time | 19364776632 ps |
CPU time | 48.97 seconds |
Started | Mar 31 03:30:43 PM PDT 24 |
Finished | Mar 31 03:31:32 PM PDT 24 |
Peak memory | 251572 kb |
Host | smart-ccdb61e6-17cb-424e-8c1e-27dc7b8619ba |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=195580504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.195580504 |
Directory | /workspace/29.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/29.otp_ctrl_dai_lock.4141817016 |
Short name | T497 |
Test name | |
Test status | |
Simulation time | 2210604335 ps |
CPU time | 23.88 seconds |
Started | Mar 31 03:30:43 PM PDT 24 |
Finished | Mar 31 03:31:07 PM PDT 24 |
Peak memory | 241824 kb |
Host | smart-9859c26a-caad-43e6-9482-7aa883da0e0c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4141817016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.4141817016 |
Directory | /workspace/29.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/29.otp_ctrl_init_fail.310992477 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 2283536711 ps |
CPU time | 6.87 seconds |
Started | Mar 31 03:30:44 PM PDT 24 |
Finished | Mar 31 03:30:51 PM PDT 24 |
Peak memory | 241800 kb |
Host | smart-cdf1e209-9975-4ea6-86e4-9e205eed914d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=310992477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.310992477 |
Directory | /workspace/29.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/29.otp_ctrl_macro_errs.1825979371 |
Short name | T1180 |
Test name | |
Test status | |
Simulation time | 291697319 ps |
CPU time | 3.74 seconds |
Started | Mar 31 03:30:43 PM PDT 24 |
Finished | Mar 31 03:30:47 PM PDT 24 |
Peak memory | 241908 kb |
Host | smart-f3b042fb-5f0a-483f-b244-e082fe967093 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1825979371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.1825979371 |
Directory | /workspace/29.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/29.otp_ctrl_parallel_key_req.3098958063 |
Short name | T586 |
Test name | |
Test status | |
Simulation time | 138824474 ps |
CPU time | 5.09 seconds |
Started | Mar 31 03:30:52 PM PDT 24 |
Finished | Mar 31 03:30:58 PM PDT 24 |
Peak memory | 241700 kb |
Host | smart-e915aac3-7c83-40b7-a830-08a11c23fc55 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3098958063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.3098958063 |
Directory | /workspace/29.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/29.otp_ctrl_parallel_lc_esc.1566578246 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 215014748 ps |
CPU time | 5.11 seconds |
Started | Mar 31 03:30:42 PM PDT 24 |
Finished | Mar 31 03:30:47 PM PDT 24 |
Peak memory | 241700 kb |
Host | smart-7950c778-aa50-4aec-82b0-cbbee182464a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1566578246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.1566578246 |
Directory | /workspace/29.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/29.otp_ctrl_parallel_lc_req.152419339 |
Short name | T1063 |
Test name | |
Test status | |
Simulation time | 1455335826 ps |
CPU time | 12.4 seconds |
Started | Mar 31 03:30:45 PM PDT 24 |
Finished | Mar 31 03:30:57 PM PDT 24 |
Peak memory | 241800 kb |
Host | smart-fb45d7f9-e690-4de0-a1ee-1985818c9da8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=152419339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.152419339 |
Directory | /workspace/29.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/29.otp_ctrl_regwen.2656872611 |
Short name | T699 |
Test name | |
Test status | |
Simulation time | 594468422 ps |
CPU time | 6.38 seconds |
Started | Mar 31 03:30:51 PM PDT 24 |
Finished | Mar 31 03:30:58 PM PDT 24 |
Peak memory | 242044 kb |
Host | smart-56c49bf9-f6e9-4add-b382-1c5b0494a20b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2656872611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.2656872611 |
Directory | /workspace/29.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/29.otp_ctrl_smoke.124726683 |
Short name | T889 |
Test name | |
Test status | |
Simulation time | 482516238 ps |
CPU time | 4.44 seconds |
Started | Mar 31 03:30:43 PM PDT 24 |
Finished | Mar 31 03:30:48 PM PDT 24 |
Peak memory | 241780 kb |
Host | smart-38de3156-2429-4a8a-8eb9-3852db68fb15 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=124726683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.124726683 |
Directory | /workspace/29.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/29.otp_ctrl_stress_all.1195342752 |
Short name | T871 |
Test name | |
Test status | |
Simulation time | 11941667168 ps |
CPU time | 165.05 seconds |
Started | Mar 31 03:30:49 PM PDT 24 |
Finished | Mar 31 03:33:34 PM PDT 24 |
Peak memory | 256932 kb |
Host | smart-c4edeeb2-b4f5-493e-9a5d-2d4e4946104a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195342752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all .1195342752 |
Directory | /workspace/29.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/29.otp_ctrl_stress_all_with_rand_reset.3725802211 |
Short name | T1078 |
Test name | |
Test status | |
Simulation time | 92852927368 ps |
CPU time | 1239.8 seconds |
Started | Mar 31 03:30:51 PM PDT 24 |
Finished | Mar 31 03:51:31 PM PDT 24 |
Peak memory | 265024 kb |
Host | smart-51dfc60a-971c-4ecd-81fe-cb0fc44ea5d2 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725802211 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all_with_rand_reset.3725802211 |
Directory | /workspace/29.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/29.otp_ctrl_test_access.2376662011 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 1209742100 ps |
CPU time | 19.7 seconds |
Started | Mar 31 03:30:48 PM PDT 24 |
Finished | Mar 31 03:31:08 PM PDT 24 |
Peak memory | 242208 kb |
Host | smart-92529ebf-1657-4e24-8c46-a874c479d60f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2376662011 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.2376662011 |
Directory | /workspace/29.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/290.otp_ctrl_init_fail.2337870992 |
Short name | T658 |
Test name | |
Test status | |
Simulation time | 92649097 ps |
CPU time | 3.06 seconds |
Started | Mar 31 03:34:13 PM PDT 24 |
Finished | Mar 31 03:34:16 PM PDT 24 |
Peak memory | 242088 kb |
Host | smart-c8307aec-026a-4888-96c0-2a8ec69e267b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2337870992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.2337870992 |
Directory | /workspace/290.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/291.otp_ctrl_init_fail.3719298298 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 1935744798 ps |
CPU time | 3.81 seconds |
Started | Mar 31 03:34:09 PM PDT 24 |
Finished | Mar 31 03:34:14 PM PDT 24 |
Peak memory | 241672 kb |
Host | smart-af66e05d-42e8-436e-a9d3-867e48d97481 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3719298298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.3719298298 |
Directory | /workspace/291.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/292.otp_ctrl_init_fail.208258482 |
Short name | T689 |
Test name | |
Test status | |
Simulation time | 596391516 ps |
CPU time | 3.6 seconds |
Started | Mar 31 03:34:09 PM PDT 24 |
Finished | Mar 31 03:34:13 PM PDT 24 |
Peak memory | 241724 kb |
Host | smart-e782c6df-6d39-48fa-8aba-3ecf404af4bd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=208258482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.208258482 |
Directory | /workspace/292.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/293.otp_ctrl_init_fail.1507840094 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 560199949 ps |
CPU time | 4.28 seconds |
Started | Mar 31 03:34:10 PM PDT 24 |
Finished | Mar 31 03:34:14 PM PDT 24 |
Peak memory | 241740 kb |
Host | smart-47168214-fe82-44fc-83f8-897376e31788 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1507840094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.1507840094 |
Directory | /workspace/293.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/294.otp_ctrl_init_fail.618067274 |
Short name | T603 |
Test name | |
Test status | |
Simulation time | 112287134 ps |
CPU time | 3.75 seconds |
Started | Mar 31 03:34:10 PM PDT 24 |
Finished | Mar 31 03:34:14 PM PDT 24 |
Peak memory | 242104 kb |
Host | smart-3d240ae8-d3ff-4b63-8c95-62fd6d4c3918 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=618067274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.618067274 |
Directory | /workspace/294.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/295.otp_ctrl_init_fail.1641198625 |
Short name | T796 |
Test name | |
Test status | |
Simulation time | 110985601 ps |
CPU time | 4.08 seconds |
Started | Mar 31 03:34:10 PM PDT 24 |
Finished | Mar 31 03:34:14 PM PDT 24 |
Peak memory | 241976 kb |
Host | smart-8c0d6eb5-2019-43b7-954a-9b561c164a76 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1641198625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.1641198625 |
Directory | /workspace/295.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/296.otp_ctrl_init_fail.4226183821 |
Short name | T478 |
Test name | |
Test status | |
Simulation time | 505157760 ps |
CPU time | 3.66 seconds |
Started | Mar 31 03:34:09 PM PDT 24 |
Finished | Mar 31 03:34:13 PM PDT 24 |
Peak memory | 242068 kb |
Host | smart-e3b52898-59e8-4eaa-b75c-990943955eb1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4226183821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.4226183821 |
Directory | /workspace/296.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/297.otp_ctrl_init_fail.1292130289 |
Short name | T1145 |
Test name | |
Test status | |
Simulation time | 175404284 ps |
CPU time | 3.61 seconds |
Started | Mar 31 03:34:09 PM PDT 24 |
Finished | Mar 31 03:34:13 PM PDT 24 |
Peak memory | 242024 kb |
Host | smart-a2b51c34-affb-46c1-85ba-84c47aec22ff |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1292130289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.1292130289 |
Directory | /workspace/297.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/298.otp_ctrl_init_fail.616090582 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 143038990 ps |
CPU time | 2.86 seconds |
Started | Mar 31 03:34:08 PM PDT 24 |
Finished | Mar 31 03:34:11 PM PDT 24 |
Peak memory | 241712 kb |
Host | smart-f320e460-1e64-492a-9f0b-6933b1e07879 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=616090582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.616090582 |
Directory | /workspace/298.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/299.otp_ctrl_init_fail.2222963130 |
Short name | T1035 |
Test name | |
Test status | |
Simulation time | 120402582 ps |
CPU time | 3.62 seconds |
Started | Mar 31 03:34:10 PM PDT 24 |
Finished | Mar 31 03:34:14 PM PDT 24 |
Peak memory | 241712 kb |
Host | smart-15d58a05-7363-40d5-b876-c8cd19a96185 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2222963130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.2222963130 |
Directory | /workspace/299.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/3.otp_ctrl_alert_test.4088350740 |
Short name | T1127 |
Test name | |
Test status | |
Simulation time | 54520902 ps |
CPU time | 1.63 seconds |
Started | Mar 31 03:28:46 PM PDT 24 |
Finished | Mar 31 03:28:48 PM PDT 24 |
Peak memory | 240244 kb |
Host | smart-6bf417d1-3d0e-4900-8688-eb6e413c08a4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088350740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.4088350740 |
Directory | /workspace/3.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/3.otp_ctrl_background_chks.1467314665 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 768176332 ps |
CPU time | 18.63 seconds |
Started | Mar 31 03:28:39 PM PDT 24 |
Finished | Mar 31 03:28:58 PM PDT 24 |
Peak memory | 241904 kb |
Host | smart-880dcb05-559b-4011-a06e-f1c488caa782 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1467314665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.1467314665 |
Directory | /workspace/3.otp_ctrl_background_chks/latest |
Test location | /workspace/coverage/default/3.otp_ctrl_check_fail.333499597 |
Short name | T901 |
Test name | |
Test status | |
Simulation time | 335523810 ps |
CPU time | 5.02 seconds |
Started | Mar 31 03:28:45 PM PDT 24 |
Finished | Mar 31 03:28:51 PM PDT 24 |
Peak memory | 241684 kb |
Host | smart-397029b0-3f19-4c29-bbea-6742b87ab03a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=333499597 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.333499597 |
Directory | /workspace/3.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/3.otp_ctrl_dai_errs.1053391621 |
Short name | T876 |
Test name | |
Test status | |
Simulation time | 697526517 ps |
CPU time | 19.79 seconds |
Started | Mar 31 03:28:45 PM PDT 24 |
Finished | Mar 31 03:29:05 PM PDT 24 |
Peak memory | 241816 kb |
Host | smart-9ed925df-2ea7-409e-9514-4d25486c9263 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1053391621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.1053391621 |
Directory | /workspace/3.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/3.otp_ctrl_dai_lock.1996457296 |
Short name | T697 |
Test name | |
Test status | |
Simulation time | 272816910 ps |
CPU time | 3.8 seconds |
Started | Mar 31 03:28:42 PM PDT 24 |
Finished | Mar 31 03:28:45 PM PDT 24 |
Peak memory | 242000 kb |
Host | smart-8a1052a5-fa3f-4608-9e48-fbe339d76046 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1996457296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.1996457296 |
Directory | /workspace/3.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/3.otp_ctrl_init_fail.1654510098 |
Short name | T1023 |
Test name | |
Test status | |
Simulation time | 118114836 ps |
CPU time | 3.97 seconds |
Started | Mar 31 03:28:40 PM PDT 24 |
Finished | Mar 31 03:28:44 PM PDT 24 |
Peak memory | 241732 kb |
Host | smart-e6e4808d-4ff5-4d05-9a57-34368c707899 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1654510098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.1654510098 |
Directory | /workspace/3.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/3.otp_ctrl_macro_errs.1267456592 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 1890315283 ps |
CPU time | 12.94 seconds |
Started | Mar 31 03:28:45 PM PDT 24 |
Finished | Mar 31 03:28:58 PM PDT 24 |
Peak memory | 247744 kb |
Host | smart-5903f768-0eb4-41a9-b441-766df53752cb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1267456592 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.1267456592 |
Directory | /workspace/3.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/3.otp_ctrl_parallel_key_req.2617368585 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 547525998 ps |
CPU time | 6.17 seconds |
Started | Mar 31 03:28:47 PM PDT 24 |
Finished | Mar 31 03:28:54 PM PDT 24 |
Peak memory | 241868 kb |
Host | smart-cb1d8925-b9bb-425c-838c-f7a1d0c9a2ff |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2617368585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.2617368585 |
Directory | /workspace/3.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/3.otp_ctrl_parallel_lc_esc.3064333584 |
Short name | T448 |
Test name | |
Test status | |
Simulation time | 107662032 ps |
CPU time | 2.93 seconds |
Started | Mar 31 03:28:41 PM PDT 24 |
Finished | Mar 31 03:28:44 PM PDT 24 |
Peak memory | 241816 kb |
Host | smart-790ab990-27d9-46c1-891b-71afd32876d5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3064333584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.3064333584 |
Directory | /workspace/3.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/3.otp_ctrl_parallel_lc_req.2299709870 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 2352343486 ps |
CPU time | 5.98 seconds |
Started | Mar 31 03:28:41 PM PDT 24 |
Finished | Mar 31 03:28:47 PM PDT 24 |
Peak memory | 241648 kb |
Host | smart-c496cb2d-40f4-4e3e-a132-48d69fe1eeff |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2299709870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.2299709870 |
Directory | /workspace/3.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/3.otp_ctrl_regwen.3348311866 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 282328247 ps |
CPU time | 8.04 seconds |
Started | Mar 31 03:28:47 PM PDT 24 |
Finished | Mar 31 03:28:55 PM PDT 24 |
Peak memory | 241808 kb |
Host | smart-bc42f2a9-255c-417e-9ba3-f12d07196aa9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3348311866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.3348311866 |
Directory | /workspace/3.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/3.otp_ctrl_sec_cm.2381166441 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 38205826279 ps |
CPU time | 222.22 seconds |
Started | Mar 31 03:28:45 PM PDT 24 |
Finished | Mar 31 03:32:28 PM PDT 24 |
Peak memory | 270756 kb |
Host | smart-0a895852-d775-48e2-8043-16106be1f33e |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381166441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.2381166441 |
Directory | /workspace/3.otp_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/3.otp_ctrl_smoke.2375862544 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 401509670 ps |
CPU time | 4.71 seconds |
Started | Mar 31 03:28:41 PM PDT 24 |
Finished | Mar 31 03:28:46 PM PDT 24 |
Peak memory | 241864 kb |
Host | smart-27b7008c-d51e-4d5c-bcca-68d89729845d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2375862544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.2375862544 |
Directory | /workspace/3.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/3.otp_ctrl_stress_all.18330123 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 7249372130 ps |
CPU time | 13.25 seconds |
Started | Mar 31 03:28:46 PM PDT 24 |
Finished | Mar 31 03:29:00 PM PDT 24 |
Peak memory | 241836 kb |
Host | smart-eb1d209b-4256-432c-9f63-4165db492fc8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18330123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_ all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all.18330123 |
Directory | /workspace/3.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/3.otp_ctrl_test_access.1410005292 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 1275464245 ps |
CPU time | 28.52 seconds |
Started | Mar 31 03:28:47 PM PDT 24 |
Finished | Mar 31 03:29:16 PM PDT 24 |
Peak memory | 241976 kb |
Host | smart-17bbad01-ea9f-40d2-a7b3-b02008d9d1f7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1410005292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.1410005292 |
Directory | /workspace/3.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/30.otp_ctrl_alert_test.467808725 |
Short name | T899 |
Test name | |
Test status | |
Simulation time | 58909486 ps |
CPU time | 1.86 seconds |
Started | Mar 31 03:30:49 PM PDT 24 |
Finished | Mar 31 03:30:51 PM PDT 24 |
Peak memory | 240068 kb |
Host | smart-dd3c0319-73cb-48fb-9c3d-0485c902b7eb |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467808725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.467808725 |
Directory | /workspace/30.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/30.otp_ctrl_check_fail.1981268533 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 2352233529 ps |
CPU time | 13.94 seconds |
Started | Mar 31 03:30:50 PM PDT 24 |
Finished | Mar 31 03:31:05 PM PDT 24 |
Peak memory | 242756 kb |
Host | smart-fa3378bc-5b20-459b-a7d9-99f423c80d3d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1981268533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.1981268533 |
Directory | /workspace/30.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/30.otp_ctrl_dai_errs.3832161724 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 889790745 ps |
CPU time | 22.54 seconds |
Started | Mar 31 03:30:51 PM PDT 24 |
Finished | Mar 31 03:31:14 PM PDT 24 |
Peak memory | 242028 kb |
Host | smart-f032cd48-b520-4a58-aa9f-edba4b72a80f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3832161724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.3832161724 |
Directory | /workspace/30.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/30.otp_ctrl_dai_lock.1233402378 |
Short name | T895 |
Test name | |
Test status | |
Simulation time | 13943473759 ps |
CPU time | 52.08 seconds |
Started | Mar 31 03:30:50 PM PDT 24 |
Finished | Mar 31 03:31:42 PM PDT 24 |
Peak memory | 242240 kb |
Host | smart-16c83390-ec9e-40bf-b05d-150aafca7882 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1233402378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.1233402378 |
Directory | /workspace/30.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/30.otp_ctrl_init_fail.2294481180 |
Short name | T1173 |
Test name | |
Test status | |
Simulation time | 2826739647 ps |
CPU time | 4.35 seconds |
Started | Mar 31 03:30:49 PM PDT 24 |
Finished | Mar 31 03:30:54 PM PDT 24 |
Peak memory | 242192 kb |
Host | smart-0c81460c-5eb2-4138-86f6-4f03a79165f5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2294481180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.2294481180 |
Directory | /workspace/30.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/30.otp_ctrl_macro_errs.1942970365 |
Short name | T1129 |
Test name | |
Test status | |
Simulation time | 29635978775 ps |
CPU time | 87.08 seconds |
Started | Mar 31 03:30:50 PM PDT 24 |
Finished | Mar 31 03:32:17 PM PDT 24 |
Peak memory | 257344 kb |
Host | smart-63f8d662-dbfe-45c6-a379-126d79c69c52 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1942970365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.1942970365 |
Directory | /workspace/30.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/30.otp_ctrl_parallel_key_req.4032418799 |
Short name | T659 |
Test name | |
Test status | |
Simulation time | 576477294 ps |
CPU time | 18.55 seconds |
Started | Mar 31 03:30:50 PM PDT 24 |
Finished | Mar 31 03:31:09 PM PDT 24 |
Peak memory | 241716 kb |
Host | smart-978c2b9e-1156-4aee-92ea-eac7cfff0136 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4032418799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.4032418799 |
Directory | /workspace/30.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/30.otp_ctrl_parallel_lc_esc.1432973706 |
Short name | T1133 |
Test name | |
Test status | |
Simulation time | 229874440 ps |
CPU time | 9.81 seconds |
Started | Mar 31 03:30:49 PM PDT 24 |
Finished | Mar 31 03:30:59 PM PDT 24 |
Peak memory | 241692 kb |
Host | smart-0d9d5670-f382-4032-9ae8-95689e10fd87 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1432973706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.1432973706 |
Directory | /workspace/30.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/30.otp_ctrl_parallel_lc_req.3415075486 |
Short name | T459 |
Test name | |
Test status | |
Simulation time | 424138173 ps |
CPU time | 4.88 seconds |
Started | Mar 31 03:30:52 PM PDT 24 |
Finished | Mar 31 03:30:57 PM PDT 24 |
Peak memory | 241896 kb |
Host | smart-c9f316f2-b859-4a8e-bffb-92f77f57cfff |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3415075486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_req.3415075486 |
Directory | /workspace/30.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/30.otp_ctrl_regwen.1366061750 |
Short name | T681 |
Test name | |
Test status | |
Simulation time | 384119657 ps |
CPU time | 4.34 seconds |
Started | Mar 31 03:30:51 PM PDT 24 |
Finished | Mar 31 03:30:56 PM PDT 24 |
Peak memory | 241688 kb |
Host | smart-a7a3fd8f-9330-49df-a5cf-563b961be03b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1366061750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.1366061750 |
Directory | /workspace/30.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/30.otp_ctrl_smoke.655096793 |
Short name | T1142 |
Test name | |
Test status | |
Simulation time | 197270322 ps |
CPU time | 5.15 seconds |
Started | Mar 31 03:30:50 PM PDT 24 |
Finished | Mar 31 03:30:56 PM PDT 24 |
Peak memory | 241944 kb |
Host | smart-21c1f0ae-0688-432a-b633-7da1ee0c4d5c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=655096793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.655096793 |
Directory | /workspace/30.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/30.otp_ctrl_stress_all.2067975136 |
Short name | T840 |
Test name | |
Test status | |
Simulation time | 9229442285 ps |
CPU time | 109.32 seconds |
Started | Mar 31 03:30:49 PM PDT 24 |
Finished | Mar 31 03:32:39 PM PDT 24 |
Peak memory | 256908 kb |
Host | smart-e47cad45-13fa-42ca-8528-57be88890ff8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067975136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all .2067975136 |
Directory | /workspace/30.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/30.otp_ctrl_test_access.1558152897 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 15590247147 ps |
CPU time | 42.95 seconds |
Started | Mar 31 03:30:50 PM PDT 24 |
Finished | Mar 31 03:31:34 PM PDT 24 |
Peak memory | 242036 kb |
Host | smart-8cf5a417-be92-42c3-b5b8-8353da7991e9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1558152897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.1558152897 |
Directory | /workspace/30.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/31.otp_ctrl_alert_test.438656287 |
Short name | T1103 |
Test name | |
Test status | |
Simulation time | 79314912 ps |
CPU time | 2.12 seconds |
Started | Mar 31 03:30:58 PM PDT 24 |
Finished | Mar 31 03:31:01 PM PDT 24 |
Peak memory | 240012 kb |
Host | smart-a74ea3cc-c011-49f8-8f67-f9f64b9b504d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438656287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.438656287 |
Directory | /workspace/31.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/31.otp_ctrl_check_fail.2821490270 |
Short name | T660 |
Test name | |
Test status | |
Simulation time | 1634910461 ps |
CPU time | 18.6 seconds |
Started | Mar 31 03:30:52 PM PDT 24 |
Finished | Mar 31 03:31:11 PM PDT 24 |
Peak memory | 242136 kb |
Host | smart-039b1430-a281-412d-86ba-5ecdcf99e9a2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2821490270 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.2821490270 |
Directory | /workspace/31.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/31.otp_ctrl_dai_errs.3419025571 |
Short name | T627 |
Test name | |
Test status | |
Simulation time | 1306501775 ps |
CPU time | 31.14 seconds |
Started | Mar 31 03:30:54 PM PDT 24 |
Finished | Mar 31 03:31:26 PM PDT 24 |
Peak memory | 245132 kb |
Host | smart-866d7c77-dde4-41ac-89f4-122ba4ec8db1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3419025571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_errs.3419025571 |
Directory | /workspace/31.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/31.otp_ctrl_dai_lock.2041012699 |
Short name | T1121 |
Test name | |
Test status | |
Simulation time | 359472707 ps |
CPU time | 7.39 seconds |
Started | Mar 31 03:30:54 PM PDT 24 |
Finished | Mar 31 03:31:01 PM PDT 24 |
Peak memory | 241652 kb |
Host | smart-b85a3d2b-35c1-4642-a20c-3acb220f4780 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2041012699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.2041012699 |
Directory | /workspace/31.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/31.otp_ctrl_init_fail.3363071810 |
Short name | T979 |
Test name | |
Test status | |
Simulation time | 112255697 ps |
CPU time | 3.88 seconds |
Started | Mar 31 03:30:49 PM PDT 24 |
Finished | Mar 31 03:30:53 PM PDT 24 |
Peak memory | 241716 kb |
Host | smart-56f4f1cb-437d-4618-ac15-89abd7a8a78a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3363071810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.3363071810 |
Directory | /workspace/31.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/31.otp_ctrl_macro_errs.2847333682 |
Short name | T463 |
Test name | |
Test status | |
Simulation time | 116514356 ps |
CPU time | 4.18 seconds |
Started | Mar 31 03:30:50 PM PDT 24 |
Finished | Mar 31 03:30:55 PM PDT 24 |
Peak memory | 241836 kb |
Host | smart-597c59f7-af4b-4b18-b3c6-8d6069f84c80 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2847333682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.2847333682 |
Directory | /workspace/31.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/31.otp_ctrl_parallel_key_req.1261692140 |
Short name | T1159 |
Test name | |
Test status | |
Simulation time | 472096428 ps |
CPU time | 4.61 seconds |
Started | Mar 31 03:30:55 PM PDT 24 |
Finished | Mar 31 03:31:01 PM PDT 24 |
Peak memory | 241840 kb |
Host | smart-7796a01b-bd56-4701-b39f-fcb5c0082fc0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1261692140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.1261692140 |
Directory | /workspace/31.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/31.otp_ctrl_parallel_lc_esc.985916032 |
Short name | T761 |
Test name | |
Test status | |
Simulation time | 192105361 ps |
CPU time | 4.88 seconds |
Started | Mar 31 03:30:49 PM PDT 24 |
Finished | Mar 31 03:30:54 PM PDT 24 |
Peak memory | 241764 kb |
Host | smart-10c5ac48-75b6-492a-baf8-9d2b827526cb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=985916032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.985916032 |
Directory | /workspace/31.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/31.otp_ctrl_parallel_lc_req.1294634907 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 770126984 ps |
CPU time | 21.57 seconds |
Started | Mar 31 03:30:49 PM PDT 24 |
Finished | Mar 31 03:31:11 PM PDT 24 |
Peak memory | 241696 kb |
Host | smart-164aa630-a4b0-474a-9a5a-2fdd9ebf75f8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1294634907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_req.1294634907 |
Directory | /workspace/31.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/31.otp_ctrl_smoke.3964077881 |
Short name | T454 |
Test name | |
Test status | |
Simulation time | 5555285552 ps |
CPU time | 17.12 seconds |
Started | Mar 31 03:30:48 PM PDT 24 |
Finished | Mar 31 03:31:05 PM PDT 24 |
Peak memory | 241924 kb |
Host | smart-6e3b7824-10c0-4646-a933-11ae8cf7dc55 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3964077881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.3964077881 |
Directory | /workspace/31.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/31.otp_ctrl_stress_all_with_rand_reset.953995598 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 348188473999 ps |
CPU time | 813.55 seconds |
Started | Mar 31 03:30:58 PM PDT 24 |
Finished | Mar 31 03:44:32 PM PDT 24 |
Peak memory | 347104 kb |
Host | smart-a4aa0af0-c195-43c4-8355-eb3ce3feebc7 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953995598 -assert nopo stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all_with_rand_reset.953995598 |
Directory | /workspace/31.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/31.otp_ctrl_test_access.1570794619 |
Short name | T822 |
Test name | |
Test status | |
Simulation time | 10998430639 ps |
CPU time | 30.82 seconds |
Started | Mar 31 03:30:57 PM PDT 24 |
Finished | Mar 31 03:31:28 PM PDT 24 |
Peak memory | 242448 kb |
Host | smart-7807df6c-3c2e-41ac-a350-07cc599abaa2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1570794619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.1570794619 |
Directory | /workspace/31.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/32.otp_ctrl_alert_test.2656967659 |
Short name | T702 |
Test name | |
Test status | |
Simulation time | 661889964 ps |
CPU time | 2.25 seconds |
Started | Mar 31 03:30:58 PM PDT 24 |
Finished | Mar 31 03:31:01 PM PDT 24 |
Peak memory | 239984 kb |
Host | smart-f33daedf-056d-42ba-8018-c8ca2413d2f5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656967659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.2656967659 |
Directory | /workspace/32.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/32.otp_ctrl_check_fail.2216219492 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 1087445286 ps |
CPU time | 12.96 seconds |
Started | Mar 31 03:30:57 PM PDT 24 |
Finished | Mar 31 03:31:10 PM PDT 24 |
Peak memory | 241796 kb |
Host | smart-fbec8622-c838-43bc-b065-aca3ae872444 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2216219492 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.2216219492 |
Directory | /workspace/32.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/32.otp_ctrl_dai_errs.1683707730 |
Short name | T1012 |
Test name | |
Test status | |
Simulation time | 788034334 ps |
CPU time | 12.56 seconds |
Started | Mar 31 03:30:57 PM PDT 24 |
Finished | Mar 31 03:31:10 PM PDT 24 |
Peak memory | 241708 kb |
Host | smart-11742416-279b-48ed-9ab1-d38e97c3e46f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1683707730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.1683707730 |
Directory | /workspace/32.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/32.otp_ctrl_dai_lock.4137749634 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 9644226986 ps |
CPU time | 39.05 seconds |
Started | Mar 31 03:30:58 PM PDT 24 |
Finished | Mar 31 03:31:38 PM PDT 24 |
Peak memory | 242668 kb |
Host | smart-ac8001ed-53d2-47fd-9c93-db5942454d01 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4137749634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.4137749634 |
Directory | /workspace/32.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/32.otp_ctrl_init_fail.3806768134 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 340503252 ps |
CPU time | 4.46 seconds |
Started | Mar 31 03:30:58 PM PDT 24 |
Finished | Mar 31 03:31:03 PM PDT 24 |
Peak memory | 242088 kb |
Host | smart-af261709-8e36-46fd-bd5b-aff494cb0c3b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3806768134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.3806768134 |
Directory | /workspace/32.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/32.otp_ctrl_macro_errs.2478378039 |
Short name | T1084 |
Test name | |
Test status | |
Simulation time | 7928109089 ps |
CPU time | 76.06 seconds |
Started | Mar 31 03:30:54 PM PDT 24 |
Finished | Mar 31 03:32:12 PM PDT 24 |
Peak memory | 245236 kb |
Host | smart-ddf075e6-a4b9-48f8-9256-c4689dcad5fe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2478378039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_macro_errs.2478378039 |
Directory | /workspace/32.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/32.otp_ctrl_parallel_key_req.3623821386 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 1557111321 ps |
CPU time | 10.24 seconds |
Started | Mar 31 03:30:55 PM PDT 24 |
Finished | Mar 31 03:31:06 PM PDT 24 |
Peak memory | 241644 kb |
Host | smart-ee7328d7-e6af-4cfe-9d9f-2987c83d39b1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3623821386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.3623821386 |
Directory | /workspace/32.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/32.otp_ctrl_parallel_lc_esc.3969716828 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 5519121311 ps |
CPU time | 13.25 seconds |
Started | Mar 31 03:31:03 PM PDT 24 |
Finished | Mar 31 03:31:16 PM PDT 24 |
Peak memory | 241812 kb |
Host | smart-cf4b72c0-ac1e-4b36-9260-9508651cc500 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3969716828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.3969716828 |
Directory | /workspace/32.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/32.otp_ctrl_parallel_lc_req.1497546012 |
Short name | T934 |
Test name | |
Test status | |
Simulation time | 563925480 ps |
CPU time | 17.14 seconds |
Started | Mar 31 03:30:57 PM PDT 24 |
Finished | Mar 31 03:31:15 PM PDT 24 |
Peak memory | 241576 kb |
Host | smart-075cfdc8-2e4b-4506-9940-7888ed20041c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1497546012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.1497546012 |
Directory | /workspace/32.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/32.otp_ctrl_regwen.3998790439 |
Short name | T865 |
Test name | |
Test status | |
Simulation time | 2481559271 ps |
CPU time | 5.63 seconds |
Started | Mar 31 03:30:58 PM PDT 24 |
Finished | Mar 31 03:31:05 PM PDT 24 |
Peak memory | 242104 kb |
Host | smart-350dbfb5-3a2b-40b5-83dd-e18f97db098a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3998790439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.3998790439 |
Directory | /workspace/32.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/32.otp_ctrl_smoke.2786649945 |
Short name | T457 |
Test name | |
Test status | |
Simulation time | 526063418 ps |
CPU time | 6.13 seconds |
Started | Mar 31 03:30:57 PM PDT 24 |
Finished | Mar 31 03:31:03 PM PDT 24 |
Peak memory | 241704 kb |
Host | smart-00af35b7-7239-44b5-8853-574ffb1b9cbe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2786649945 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.2786649945 |
Directory | /workspace/32.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/32.otp_ctrl_stress_all.2310872793 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 17726929272 ps |
CPU time | 66.87 seconds |
Started | Mar 31 03:30:54 PM PDT 24 |
Finished | Mar 31 03:32:02 PM PDT 24 |
Peak memory | 249484 kb |
Host | smart-068fe690-ecca-45dc-b681-8351449ae328 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310872793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all .2310872793 |
Directory | /workspace/32.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/32.otp_ctrl_stress_all_with_rand_reset.2885624270 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 17550849973 ps |
CPU time | 245.08 seconds |
Started | Mar 31 03:30:57 PM PDT 24 |
Finished | Mar 31 03:35:02 PM PDT 24 |
Peak memory | 248776 kb |
Host | smart-97d7109f-6cdb-4d20-81aa-7a5e54efbf36 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885624270 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all_with_rand_reset.2885624270 |
Directory | /workspace/32.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/32.otp_ctrl_test_access.1490036364 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 3002910461 ps |
CPU time | 22.67 seconds |
Started | Mar 31 03:30:55 PM PDT 24 |
Finished | Mar 31 03:31:18 PM PDT 24 |
Peak memory | 242020 kb |
Host | smart-ecb2720e-a277-4353-85cf-0e5c87614ae6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1490036364 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.1490036364 |
Directory | /workspace/32.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/33.otp_ctrl_alert_test.3712089287 |
Short name | T918 |
Test name | |
Test status | |
Simulation time | 97555898 ps |
CPU time | 1.73 seconds |
Started | Mar 31 03:31:02 PM PDT 24 |
Finished | Mar 31 03:31:04 PM PDT 24 |
Peak memory | 240068 kb |
Host | smart-bcbf9333-90a9-422b-b37e-2ba1965d3958 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712089287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.3712089287 |
Directory | /workspace/33.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/33.otp_ctrl_check_fail.3732281040 |
Short name | T953 |
Test name | |
Test status | |
Simulation time | 133584205 ps |
CPU time | 5.96 seconds |
Started | Mar 31 03:31:03 PM PDT 24 |
Finished | Mar 31 03:31:09 PM PDT 24 |
Peak memory | 241704 kb |
Host | smart-382b0748-d474-43b5-b707-63fa67b39b72 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3732281040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.3732281040 |
Directory | /workspace/33.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/33.otp_ctrl_dai_errs.1785972109 |
Short name | T1006 |
Test name | |
Test status | |
Simulation time | 2992535976 ps |
CPU time | 38.59 seconds |
Started | Mar 31 03:30:56 PM PDT 24 |
Finished | Mar 31 03:31:35 PM PDT 24 |
Peak memory | 246296 kb |
Host | smart-d1b38b9d-47df-48d8-9d03-cdbf8e3804a7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1785972109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.1785972109 |
Directory | /workspace/33.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/33.otp_ctrl_dai_lock.4160734105 |
Short name | T1020 |
Test name | |
Test status | |
Simulation time | 5166137368 ps |
CPU time | 29.73 seconds |
Started | Mar 31 03:31:02 PM PDT 24 |
Finished | Mar 31 03:31:32 PM PDT 24 |
Peak memory | 242048 kb |
Host | smart-8d94af9f-ae34-4722-84c5-f9d7f7a779a2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4160734105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_lock.4160734105 |
Directory | /workspace/33.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/33.otp_ctrl_init_fail.3601768791 |
Short name | T1193 |
Test name | |
Test status | |
Simulation time | 214666799 ps |
CPU time | 3.23 seconds |
Started | Mar 31 03:30:58 PM PDT 24 |
Finished | Mar 31 03:31:02 PM PDT 24 |
Peak memory | 241796 kb |
Host | smart-02138cc3-4d3b-4995-9103-cca74b1caf53 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3601768791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.3601768791 |
Directory | /workspace/33.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/33.otp_ctrl_macro_errs.2823900433 |
Short name | T920 |
Test name | |
Test status | |
Simulation time | 3712327116 ps |
CPU time | 29.45 seconds |
Started | Mar 31 03:30:59 PM PDT 24 |
Finished | Mar 31 03:31:29 PM PDT 24 |
Peak memory | 249984 kb |
Host | smart-b6eb9ae4-8448-451e-8c20-65f6969fff43 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2823900433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.2823900433 |
Directory | /workspace/33.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/33.otp_ctrl_parallel_key_req.1729772980 |
Short name | T700 |
Test name | |
Test status | |
Simulation time | 696085481 ps |
CPU time | 22.84 seconds |
Started | Mar 31 03:31:02 PM PDT 24 |
Finished | Mar 31 03:31:25 PM PDT 24 |
Peak memory | 242248 kb |
Host | smart-2911c1b9-a5e3-4398-a2df-528f10214187 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1729772980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_key_req.1729772980 |
Directory | /workspace/33.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/33.otp_ctrl_parallel_lc_esc.4013635656 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 148032178 ps |
CPU time | 7.24 seconds |
Started | Mar 31 03:30:57 PM PDT 24 |
Finished | Mar 31 03:31:05 PM PDT 24 |
Peak memory | 241972 kb |
Host | smart-589acc3a-d020-4104-8291-662e7e7f7bc3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4013635656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.4013635656 |
Directory | /workspace/33.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/33.otp_ctrl_parallel_lc_req.2037905326 |
Short name | T789 |
Test name | |
Test status | |
Simulation time | 7633097088 ps |
CPU time | 20.68 seconds |
Started | Mar 31 03:30:57 PM PDT 24 |
Finished | Mar 31 03:31:18 PM PDT 24 |
Peak memory | 241560 kb |
Host | smart-47b7af6f-8352-47c7-ad79-2d724ef68a61 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2037905326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_req.2037905326 |
Directory | /workspace/33.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/33.otp_ctrl_regwen.271046651 |
Short name | T605 |
Test name | |
Test status | |
Simulation time | 2991857029 ps |
CPU time | 5.66 seconds |
Started | Mar 31 03:31:00 PM PDT 24 |
Finished | Mar 31 03:31:06 PM PDT 24 |
Peak memory | 241896 kb |
Host | smart-039f42f0-91af-4892-ae96-c2cdc95426a6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=271046651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.271046651 |
Directory | /workspace/33.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/33.otp_ctrl_smoke.2576535666 |
Short name | T589 |
Test name | |
Test status | |
Simulation time | 128934902 ps |
CPU time | 4.04 seconds |
Started | Mar 31 03:30:58 PM PDT 24 |
Finished | Mar 31 03:31:02 PM PDT 24 |
Peak memory | 241964 kb |
Host | smart-6f6035c3-5f84-4d08-a5e7-cf5cb660a442 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2576535666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.2576535666 |
Directory | /workspace/33.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/33.otp_ctrl_stress_all.3291920757 |
Short name | T1056 |
Test name | |
Test status | |
Simulation time | 7630474671 ps |
CPU time | 281.34 seconds |
Started | Mar 31 03:31:00 PM PDT 24 |
Finished | Mar 31 03:35:43 PM PDT 24 |
Peak memory | 261400 kb |
Host | smart-fe2fb00f-3614-491c-934c-1a38d67fbae8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291920757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all .3291920757 |
Directory | /workspace/33.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/33.otp_ctrl_test_access.659361691 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 1398319251 ps |
CPU time | 22.47 seconds |
Started | Mar 31 03:30:59 PM PDT 24 |
Finished | Mar 31 03:31:22 PM PDT 24 |
Peak memory | 242116 kb |
Host | smart-3157ce62-a62b-4f78-9eda-57a4fd201d4a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=659361691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.659361691 |
Directory | /workspace/33.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/34.otp_ctrl_alert_test.2815802519 |
Short name | T825 |
Test name | |
Test status | |
Simulation time | 81263009 ps |
CPU time | 1.61 seconds |
Started | Mar 31 03:31:10 PM PDT 24 |
Finished | Mar 31 03:31:11 PM PDT 24 |
Peak memory | 240264 kb |
Host | smart-5251e655-2c0d-4582-9356-eac32e5ff417 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815802519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.2815802519 |
Directory | /workspace/34.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/34.otp_ctrl_check_fail.3109232622 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 301243650 ps |
CPU time | 7.41 seconds |
Started | Mar 31 03:31:08 PM PDT 24 |
Finished | Mar 31 03:31:15 PM PDT 24 |
Peak memory | 248584 kb |
Host | smart-92d71f55-46c4-4d71-be0d-afb1c39a7e15 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3109232622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.3109232622 |
Directory | /workspace/34.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/34.otp_ctrl_dai_errs.1348216833 |
Short name | T1126 |
Test name | |
Test status | |
Simulation time | 5507996766 ps |
CPU time | 22.4 seconds |
Started | Mar 31 03:31:03 PM PDT 24 |
Finished | Mar 31 03:31:26 PM PDT 24 |
Peak memory | 241960 kb |
Host | smart-2a09d497-b28e-4382-a4c5-f54d02ab6544 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1348216833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.1348216833 |
Directory | /workspace/34.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/34.otp_ctrl_dai_lock.1675069514 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 580236478 ps |
CPU time | 10.7 seconds |
Started | Mar 31 03:31:00 PM PDT 24 |
Finished | Mar 31 03:31:12 PM PDT 24 |
Peak memory | 241752 kb |
Host | smart-6f5478dc-8a48-4efb-957b-08febeb25939 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1675069514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_lock.1675069514 |
Directory | /workspace/34.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/34.otp_ctrl_init_fail.742804096 |
Short name | T881 |
Test name | |
Test status | |
Simulation time | 463355593 ps |
CPU time | 5.54 seconds |
Started | Mar 31 03:31:02 PM PDT 24 |
Finished | Mar 31 03:31:07 PM PDT 24 |
Peak memory | 241632 kb |
Host | smart-78dab367-8ae2-44e2-aba8-2b9790d95b68 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=742804096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.742804096 |
Directory | /workspace/34.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/34.otp_ctrl_macro_errs.1259676531 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 3135090997 ps |
CPU time | 16.95 seconds |
Started | Mar 31 03:31:07 PM PDT 24 |
Finished | Mar 31 03:31:24 PM PDT 24 |
Peak memory | 243796 kb |
Host | smart-da125529-fb59-4caa-a590-8576dc00c8ba |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1259676531 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.1259676531 |
Directory | /workspace/34.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/34.otp_ctrl_parallel_key_req.3536860279 |
Short name | T1144 |
Test name | |
Test status | |
Simulation time | 442289677 ps |
CPU time | 7.82 seconds |
Started | Mar 31 03:31:09 PM PDT 24 |
Finished | Mar 31 03:31:17 PM PDT 24 |
Peak memory | 241804 kb |
Host | smart-aad8da8c-ac53-475a-9f43-a6f9221063a5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3536860279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.3536860279 |
Directory | /workspace/34.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/34.otp_ctrl_parallel_lc_esc.246620240 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 9414398941 ps |
CPU time | 19.84 seconds |
Started | Mar 31 03:31:01 PM PDT 24 |
Finished | Mar 31 03:31:21 PM PDT 24 |
Peak memory | 241752 kb |
Host | smart-d686a41c-b6be-4784-b4e7-abe559087231 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=246620240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.246620240 |
Directory | /workspace/34.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/34.otp_ctrl_parallel_lc_req.252874368 |
Short name | T619 |
Test name | |
Test status | |
Simulation time | 1535830445 ps |
CPU time | 24.4 seconds |
Started | Mar 31 03:31:02 PM PDT 24 |
Finished | Mar 31 03:31:27 PM PDT 24 |
Peak memory | 241700 kb |
Host | smart-858fed8a-40b1-42d3-84e8-99c4a7caf187 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=252874368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.252874368 |
Directory | /workspace/34.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/34.otp_ctrl_regwen.1106428637 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 146651435 ps |
CPU time | 6.32 seconds |
Started | Mar 31 03:31:08 PM PDT 24 |
Finished | Mar 31 03:31:15 PM PDT 24 |
Peak memory | 241852 kb |
Host | smart-96ff9297-db78-4714-948f-972337e705df |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1106428637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.1106428637 |
Directory | /workspace/34.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/34.otp_ctrl_smoke.1330377543 |
Short name | T1195 |
Test name | |
Test status | |
Simulation time | 392950515 ps |
CPU time | 4.97 seconds |
Started | Mar 31 03:31:01 PM PDT 24 |
Finished | Mar 31 03:31:07 PM PDT 24 |
Peak memory | 241656 kb |
Host | smart-51fddd92-1788-4007-9bc6-d44e96b01348 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1330377543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_smoke.1330377543 |
Directory | /workspace/34.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/34.otp_ctrl_stress_all.3711883839 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 20536427586 ps |
CPU time | 92.23 seconds |
Started | Mar 31 03:31:07 PM PDT 24 |
Finished | Mar 31 03:32:40 PM PDT 24 |
Peak memory | 257976 kb |
Host | smart-2fda5fdd-9b0d-4f7e-b212-e581c2dbb4a5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711883839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all .3711883839 |
Directory | /workspace/34.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/34.otp_ctrl_stress_all_with_rand_reset.2300520788 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 7199057873 ps |
CPU time | 204.22 seconds |
Started | Mar 31 03:31:12 PM PDT 24 |
Finished | Mar 31 03:34:36 PM PDT 24 |
Peak memory | 287020 kb |
Host | smart-a2224a55-c0e3-4fad-acfb-8618de4e71fd |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300520788 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all_with_rand_reset.2300520788 |
Directory | /workspace/34.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/34.otp_ctrl_test_access.786475837 |
Short name | T948 |
Test name | |
Test status | |
Simulation time | 536398077 ps |
CPU time | 8.91 seconds |
Started | Mar 31 03:31:09 PM PDT 24 |
Finished | Mar 31 03:31:18 PM PDT 24 |
Peak memory | 241968 kb |
Host | smart-0a919160-e1c8-4ced-afdb-fdf7b367630c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=786475837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_test_access.786475837 |
Directory | /workspace/34.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/35.otp_ctrl_alert_test.3260805958 |
Short name | T837 |
Test name | |
Test status | |
Simulation time | 579562247 ps |
CPU time | 1.58 seconds |
Started | Mar 31 03:31:09 PM PDT 24 |
Finished | Mar 31 03:31:11 PM PDT 24 |
Peak memory | 240236 kb |
Host | smart-5782d9bb-893d-476d-865f-abb6945f9ef0 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260805958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.3260805958 |
Directory | /workspace/35.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/35.otp_ctrl_check_fail.1200892355 |
Short name | T593 |
Test name | |
Test status | |
Simulation time | 4171816959 ps |
CPU time | 54.97 seconds |
Started | Mar 31 03:31:08 PM PDT 24 |
Finished | Mar 31 03:32:03 PM PDT 24 |
Peak memory | 244432 kb |
Host | smart-8e8129a1-3687-47aa-9b13-aef5332a4eb2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1200892355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.1200892355 |
Directory | /workspace/35.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/35.otp_ctrl_dai_errs.2896818984 |
Short name | T499 |
Test name | |
Test status | |
Simulation time | 997970420 ps |
CPU time | 23.89 seconds |
Started | Mar 31 03:31:08 PM PDT 24 |
Finished | Mar 31 03:31:32 PM PDT 24 |
Peak memory | 241848 kb |
Host | smart-018dc2d0-3e0b-4cff-945a-dbe354d0c14c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2896818984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_errs.2896818984 |
Directory | /workspace/35.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/35.otp_ctrl_dai_lock.1012608307 |
Short name | T1080 |
Test name | |
Test status | |
Simulation time | 8556240706 ps |
CPU time | 11.77 seconds |
Started | Mar 31 03:31:07 PM PDT 24 |
Finished | Mar 31 03:31:19 PM PDT 24 |
Peak memory | 242668 kb |
Host | smart-93ce7fae-0085-4582-80bd-41b959bbb57b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1012608307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_lock.1012608307 |
Directory | /workspace/35.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/35.otp_ctrl_init_fail.4194715006 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 280945392 ps |
CPU time | 3.76 seconds |
Started | Mar 31 03:31:09 PM PDT 24 |
Finished | Mar 31 03:31:13 PM PDT 24 |
Peak memory | 241772 kb |
Host | smart-6b235c1e-00c5-4522-b03b-882257b25409 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4194715006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.4194715006 |
Directory | /workspace/35.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/35.otp_ctrl_macro_errs.1121583354 |
Short name | T970 |
Test name | |
Test status | |
Simulation time | 1324556785 ps |
CPU time | 19.4 seconds |
Started | Mar 31 03:31:09 PM PDT 24 |
Finished | Mar 31 03:31:29 PM PDT 24 |
Peak memory | 243856 kb |
Host | smart-0d64c6c3-8e5f-4b4a-b227-ea39e92f70a2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1121583354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.1121583354 |
Directory | /workspace/35.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/35.otp_ctrl_parallel_key_req.1897148632 |
Short name | T1119 |
Test name | |
Test status | |
Simulation time | 2432164710 ps |
CPU time | 24.91 seconds |
Started | Mar 31 03:31:10 PM PDT 24 |
Finished | Mar 31 03:31:35 PM PDT 24 |
Peak memory | 242100 kb |
Host | smart-6856f7ca-6a8f-41c9-a287-9fc5b4e83a03 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1897148632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.1897148632 |
Directory | /workspace/35.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/35.otp_ctrl_parallel_lc_esc.3037672691 |
Short name | T549 |
Test name | |
Test status | |
Simulation time | 79560879 ps |
CPU time | 2.94 seconds |
Started | Mar 31 03:31:09 PM PDT 24 |
Finished | Mar 31 03:31:12 PM PDT 24 |
Peak memory | 241464 kb |
Host | smart-22ed0dad-2b1a-43e0-8fe1-aac7ce9468d1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3037672691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.3037672691 |
Directory | /workspace/35.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/35.otp_ctrl_parallel_lc_req.1940009311 |
Short name | T1110 |
Test name | |
Test status | |
Simulation time | 352614053 ps |
CPU time | 9.26 seconds |
Started | Mar 31 03:31:10 PM PDT 24 |
Finished | Mar 31 03:31:20 PM PDT 24 |
Peak memory | 241540 kb |
Host | smart-d3419534-9fc7-4737-9643-b68795f762e5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1940009311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.1940009311 |
Directory | /workspace/35.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/35.otp_ctrl_regwen.1484945529 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 1762205929 ps |
CPU time | 4.58 seconds |
Started | Mar 31 03:31:10 PM PDT 24 |
Finished | Mar 31 03:31:15 PM PDT 24 |
Peak memory | 241840 kb |
Host | smart-be903a7e-a738-4883-8566-d922a279276f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1484945529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.1484945529 |
Directory | /workspace/35.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/35.otp_ctrl_smoke.1388708661 |
Short name | T774 |
Test name | |
Test status | |
Simulation time | 793661404 ps |
CPU time | 5.48 seconds |
Started | Mar 31 03:31:09 PM PDT 24 |
Finished | Mar 31 03:31:15 PM PDT 24 |
Peak memory | 242012 kb |
Host | smart-374093c2-f52e-447e-bbd0-af79c1f82dd6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1388708661 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.1388708661 |
Directory | /workspace/35.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/35.otp_ctrl_stress_all.1073765576 |
Short name | T662 |
Test name | |
Test status | |
Simulation time | 8312408004 ps |
CPU time | 104.13 seconds |
Started | Mar 31 03:31:14 PM PDT 24 |
Finished | Mar 31 03:32:58 PM PDT 24 |
Peak memory | 256968 kb |
Host | smart-8fd72a7f-c47f-4965-a1da-00c44e377967 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073765576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all .1073765576 |
Directory | /workspace/35.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/35.otp_ctrl_stress_all_with_rand_reset.3764076422 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 91100054036 ps |
CPU time | 1649.05 seconds |
Started | Mar 31 03:31:09 PM PDT 24 |
Finished | Mar 31 03:58:38 PM PDT 24 |
Peak memory | 465384 kb |
Host | smart-d279ffa3-44a8-42fa-aa28-ead9c6296a53 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764076422 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all_with_rand_reset.3764076422 |
Directory | /workspace/35.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/35.otp_ctrl_test_access.2854386006 |
Short name | T770 |
Test name | |
Test status | |
Simulation time | 2253604757 ps |
CPU time | 14.75 seconds |
Started | Mar 31 03:31:09 PM PDT 24 |
Finished | Mar 31 03:31:24 PM PDT 24 |
Peak memory | 241832 kb |
Host | smart-e5a107f8-160a-45f0-aeef-5c0d6154cf4e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2854386006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_test_access.2854386006 |
Directory | /workspace/35.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/36.otp_ctrl_alert_test.832995463 |
Short name | T788 |
Test name | |
Test status | |
Simulation time | 93741804 ps |
CPU time | 1.83 seconds |
Started | Mar 31 03:31:15 PM PDT 24 |
Finished | Mar 31 03:31:17 PM PDT 24 |
Peak memory | 240196 kb |
Host | smart-91d1c855-8bcf-49ae-acc9-d8ebb9821759 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832995463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.832995463 |
Directory | /workspace/36.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/36.otp_ctrl_check_fail.3973692234 |
Short name | T1060 |
Test name | |
Test status | |
Simulation time | 517942535 ps |
CPU time | 5.22 seconds |
Started | Mar 31 03:31:16 PM PDT 24 |
Finished | Mar 31 03:31:22 PM PDT 24 |
Peak memory | 241764 kb |
Host | smart-dffc5bac-3eff-46c8-96d1-4d314e39a3c1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3973692234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.3973692234 |
Directory | /workspace/36.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/36.otp_ctrl_dai_errs.1387234687 |
Short name | T447 |
Test name | |
Test status | |
Simulation time | 12468250894 ps |
CPU time | 33.28 seconds |
Started | Mar 31 03:31:17 PM PDT 24 |
Finished | Mar 31 03:31:51 PM PDT 24 |
Peak memory | 243152 kb |
Host | smart-5b7e0b19-5ad9-4b56-a9ad-7306825451a7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1387234687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.1387234687 |
Directory | /workspace/36.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/36.otp_ctrl_dai_lock.4074072206 |
Short name | T692 |
Test name | |
Test status | |
Simulation time | 317037550 ps |
CPU time | 5.68 seconds |
Started | Mar 31 03:31:15 PM PDT 24 |
Finished | Mar 31 03:31:20 PM PDT 24 |
Peak memory | 241612 kb |
Host | smart-cc10114d-034d-49fb-ae52-f8bd81db1fe4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4074072206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_lock.4074072206 |
Directory | /workspace/36.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/36.otp_ctrl_init_fail.1060386008 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 387257301 ps |
CPU time | 3.68 seconds |
Started | Mar 31 03:31:10 PM PDT 24 |
Finished | Mar 31 03:31:14 PM PDT 24 |
Peak memory | 241728 kb |
Host | smart-a9067a2a-385d-4e1c-a4d3-276919de996a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1060386008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.1060386008 |
Directory | /workspace/36.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/36.otp_ctrl_macro_errs.566660226 |
Short name | T1154 |
Test name | |
Test status | |
Simulation time | 2307168376 ps |
CPU time | 20.11 seconds |
Started | Mar 31 03:31:15 PM PDT 24 |
Finished | Mar 31 03:31:35 PM PDT 24 |
Peak memory | 242312 kb |
Host | smart-e387f2ff-4859-488c-a7f9-4be8ee9734ec |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=566660226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.566660226 |
Directory | /workspace/36.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/36.otp_ctrl_parallel_key_req.965724804 |
Short name | T470 |
Test name | |
Test status | |
Simulation time | 568000749 ps |
CPU time | 9.77 seconds |
Started | Mar 31 03:31:15 PM PDT 24 |
Finished | Mar 31 03:31:25 PM PDT 24 |
Peak memory | 241840 kb |
Host | smart-3fa4290b-258d-43e7-b643-859d79538510 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=965724804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.965724804 |
Directory | /workspace/36.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/36.otp_ctrl_parallel_lc_esc.3322966525 |
Short name | T615 |
Test name | |
Test status | |
Simulation time | 540292610 ps |
CPU time | 8.26 seconds |
Started | Mar 31 03:31:09 PM PDT 24 |
Finished | Mar 31 03:31:17 PM PDT 24 |
Peak memory | 241772 kb |
Host | smart-fb1c7380-6568-47ae-85e3-63720130a12f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3322966525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.3322966525 |
Directory | /workspace/36.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/36.otp_ctrl_parallel_lc_req.1765701984 |
Short name | T1196 |
Test name | |
Test status | |
Simulation time | 912722596 ps |
CPU time | 15.87 seconds |
Started | Mar 31 03:31:10 PM PDT 24 |
Finished | Mar 31 03:31:26 PM PDT 24 |
Peak memory | 241680 kb |
Host | smart-bbd7e153-91e0-4cb5-9251-8f0d8e7b9d34 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1765701984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.1765701984 |
Directory | /workspace/36.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/36.otp_ctrl_regwen.1044982158 |
Short name | T773 |
Test name | |
Test status | |
Simulation time | 2134974314 ps |
CPU time | 6.4 seconds |
Started | Mar 31 03:31:14 PM PDT 24 |
Finished | Mar 31 03:31:20 PM PDT 24 |
Peak memory | 241904 kb |
Host | smart-2ad27ff7-914d-4af9-a370-c9febd246749 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1044982158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.1044982158 |
Directory | /workspace/36.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/36.otp_ctrl_smoke.2568957588 |
Short name | T670 |
Test name | |
Test status | |
Simulation time | 194267866 ps |
CPU time | 3.33 seconds |
Started | Mar 31 03:31:09 PM PDT 24 |
Finished | Mar 31 03:31:12 PM PDT 24 |
Peak memory | 241828 kb |
Host | smart-d2da0070-9b19-4bc5-84cf-4e7daf32ea36 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2568957588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.2568957588 |
Directory | /workspace/36.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/36.otp_ctrl_stress_all.133749250 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 40753854048 ps |
CPU time | 229.09 seconds |
Started | Mar 31 03:31:17 PM PDT 24 |
Finished | Mar 31 03:35:06 PM PDT 24 |
Peak memory | 273252 kb |
Host | smart-faa4060d-eaea-4908-aebc-20cbdb2aa5c9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133749250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all. 133749250 |
Directory | /workspace/36.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/36.otp_ctrl_stress_all_with_rand_reset.3775843766 |
Short name | T502 |
Test name | |
Test status | |
Simulation time | 165013676745 ps |
CPU time | 1127.54 seconds |
Started | Mar 31 03:31:17 PM PDT 24 |
Finished | Mar 31 03:50:05 PM PDT 24 |
Peak memory | 334248 kb |
Host | smart-ee00d955-b564-4b63-ad98-e912f239b7e5 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775843766 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all_with_rand_reset.3775843766 |
Directory | /workspace/36.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/36.otp_ctrl_test_access.1683641496 |
Short name | T923 |
Test name | |
Test status | |
Simulation time | 1287021624 ps |
CPU time | 16.43 seconds |
Started | Mar 31 03:31:16 PM PDT 24 |
Finished | Mar 31 03:31:32 PM PDT 24 |
Peak memory | 242000 kb |
Host | smart-44f9b452-4ebb-4b6b-a19d-d19e3cf1008d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1683641496 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.1683641496 |
Directory | /workspace/36.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/37.otp_ctrl_alert_test.2561584321 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 228686636 ps |
CPU time | 1.91 seconds |
Started | Mar 31 03:31:27 PM PDT 24 |
Finished | Mar 31 03:31:29 PM PDT 24 |
Peak memory | 240144 kb |
Host | smart-51d91fe4-f8a9-4e55-8537-4dd2c10561bb |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561584321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.2561584321 |
Directory | /workspace/37.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/37.otp_ctrl_check_fail.1324900357 |
Short name | T805 |
Test name | |
Test status | |
Simulation time | 2020442769 ps |
CPU time | 43.92 seconds |
Started | Mar 31 03:31:15 PM PDT 24 |
Finished | Mar 31 03:31:59 PM PDT 24 |
Peak memory | 248616 kb |
Host | smart-be3918a4-f119-4a69-8edc-e811b86bda63 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1324900357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.1324900357 |
Directory | /workspace/37.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/37.otp_ctrl_dai_errs.787694147 |
Short name | T630 |
Test name | |
Test status | |
Simulation time | 1901864451 ps |
CPU time | 35.09 seconds |
Started | Mar 31 03:31:17 PM PDT 24 |
Finished | Mar 31 03:31:52 PM PDT 24 |
Peak memory | 244504 kb |
Host | smart-2be8515f-0e38-4619-8c27-f65b61908adf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=787694147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.787694147 |
Directory | /workspace/37.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/37.otp_ctrl_dai_lock.1061961231 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 2944954108 ps |
CPU time | 33.23 seconds |
Started | Mar 31 03:31:14 PM PDT 24 |
Finished | Mar 31 03:31:47 PM PDT 24 |
Peak memory | 241640 kb |
Host | smart-ebf4f4b9-ddad-46f4-81b1-4ec580715c1b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1061961231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.1061961231 |
Directory | /workspace/37.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/37.otp_ctrl_init_fail.3280492776 |
Short name | T1087 |
Test name | |
Test status | |
Simulation time | 115372316 ps |
CPU time | 3.76 seconds |
Started | Mar 31 03:31:16 PM PDT 24 |
Finished | Mar 31 03:31:19 PM PDT 24 |
Peak memory | 241572 kb |
Host | smart-0dc6981e-636b-4680-a210-99e0a1125c23 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3280492776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.3280492776 |
Directory | /workspace/37.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/37.otp_ctrl_macro_errs.561379551 |
Short name | T646 |
Test name | |
Test status | |
Simulation time | 918259291 ps |
CPU time | 20.13 seconds |
Started | Mar 31 03:31:22 PM PDT 24 |
Finished | Mar 31 03:31:43 PM PDT 24 |
Peak memory | 242012 kb |
Host | smart-ffbb8049-7201-46a3-b7d4-02bc4e5f349b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=561379551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.561379551 |
Directory | /workspace/37.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/37.otp_ctrl_parallel_key_req.3393440426 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 781448358 ps |
CPU time | 26.91 seconds |
Started | Mar 31 03:31:25 PM PDT 24 |
Finished | Mar 31 03:31:52 PM PDT 24 |
Peak memory | 241776 kb |
Host | smart-b05477a1-5609-478f-9088-0e556ab9c68c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3393440426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_key_req.3393440426 |
Directory | /workspace/37.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/37.otp_ctrl_parallel_lc_esc.1907470660 |
Short name | T1055 |
Test name | |
Test status | |
Simulation time | 253560106 ps |
CPU time | 13.17 seconds |
Started | Mar 31 03:31:16 PM PDT 24 |
Finished | Mar 31 03:31:29 PM PDT 24 |
Peak memory | 241588 kb |
Host | smart-b2d4af2d-22bf-405e-8a31-a91d970ab8d0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1907470660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.1907470660 |
Directory | /workspace/37.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/37.otp_ctrl_parallel_lc_req.870309608 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 10754297314 ps |
CPU time | 23.14 seconds |
Started | Mar 31 03:31:16 PM PDT 24 |
Finished | Mar 31 03:31:39 PM PDT 24 |
Peak memory | 241488 kb |
Host | smart-f3573f1b-5409-49f4-8cad-e6d8a9de1f80 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=870309608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.870309608 |
Directory | /workspace/37.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/37.otp_ctrl_regwen.3969113971 |
Short name | T1066 |
Test name | |
Test status | |
Simulation time | 2691346093 ps |
CPU time | 8.07 seconds |
Started | Mar 31 03:31:19 PM PDT 24 |
Finished | Mar 31 03:31:27 PM PDT 24 |
Peak memory | 241936 kb |
Host | smart-7499e93c-250d-4ec9-85d7-d7d9964d5e6b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3969113971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.3969113971 |
Directory | /workspace/37.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/37.otp_ctrl_smoke.2964511934 |
Short name | T897 |
Test name | |
Test status | |
Simulation time | 583097916 ps |
CPU time | 8.56 seconds |
Started | Mar 31 03:31:17 PM PDT 24 |
Finished | Mar 31 03:31:25 PM PDT 24 |
Peak memory | 241840 kb |
Host | smart-997e0cfc-b5ad-4969-9afa-a65f512b70cd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2964511934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_smoke.2964511934 |
Directory | /workspace/37.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/37.otp_ctrl_stress_all.532896371 |
Short name | T565 |
Test name | |
Test status | |
Simulation time | 20277759638 ps |
CPU time | 83.04 seconds |
Started | Mar 31 03:31:23 PM PDT 24 |
Finished | Mar 31 03:32:46 PM PDT 24 |
Peak memory | 243032 kb |
Host | smart-9172bea5-c1b8-4f33-abce-edf13e6ca356 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532896371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all. 532896371 |
Directory | /workspace/37.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/37.otp_ctrl_stress_all_with_rand_reset.2869555378 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 219296499645 ps |
CPU time | 1576.47 seconds |
Started | Mar 31 03:31:24 PM PDT 24 |
Finished | Mar 31 03:57:41 PM PDT 24 |
Peak memory | 344648 kb |
Host | smart-a732e54a-9b3e-4abf-8ce1-d7414cc2c053 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869555378 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all_with_rand_reset.2869555378 |
Directory | /workspace/37.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/37.otp_ctrl_test_access.1696011114 |
Short name | T1086 |
Test name | |
Test status | |
Simulation time | 6261159001 ps |
CPU time | 12.95 seconds |
Started | Mar 31 03:31:20 PM PDT 24 |
Finished | Mar 31 03:31:33 PM PDT 24 |
Peak memory | 243016 kb |
Host | smart-12f06c07-fa27-4121-90ba-b87fb3ce02ca |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1696011114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.1696011114 |
Directory | /workspace/37.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/38.otp_ctrl_alert_test.885863247 |
Short name | T938 |
Test name | |
Test status | |
Simulation time | 87675464 ps |
CPU time | 1.66 seconds |
Started | Mar 31 03:31:24 PM PDT 24 |
Finished | Mar 31 03:31:26 PM PDT 24 |
Peak memory | 240252 kb |
Host | smart-920c1511-de38-48ae-b5e2-fcea0cebbcb8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885863247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.885863247 |
Directory | /workspace/38.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/38.otp_ctrl_check_fail.2421179223 |
Short name | T913 |
Test name | |
Test status | |
Simulation time | 3240392852 ps |
CPU time | 17.98 seconds |
Started | Mar 31 03:31:25 PM PDT 24 |
Finished | Mar 31 03:31:43 PM PDT 24 |
Peak memory | 242824 kb |
Host | smart-a707dca8-406e-45fa-bd1c-b926b32f869d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2421179223 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.2421179223 |
Directory | /workspace/38.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/38.otp_ctrl_dai_errs.110220846 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 679258968 ps |
CPU time | 11.78 seconds |
Started | Mar 31 03:31:21 PM PDT 24 |
Finished | Mar 31 03:31:33 PM PDT 24 |
Peak memory | 242016 kb |
Host | smart-43f13015-1d9d-465f-9885-2e9f459410eb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=110220846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_errs.110220846 |
Directory | /workspace/38.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/38.otp_ctrl_dai_lock.418099075 |
Short name | T1138 |
Test name | |
Test status | |
Simulation time | 1558936699 ps |
CPU time | 19.4 seconds |
Started | Mar 31 03:31:25 PM PDT 24 |
Finished | Mar 31 03:31:44 PM PDT 24 |
Peak memory | 242252 kb |
Host | smart-bf65f7cf-f6b3-4266-8628-1ad3f08ec15a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=418099075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_lock.418099075 |
Directory | /workspace/38.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/38.otp_ctrl_init_fail.424662164 |
Short name | T931 |
Test name | |
Test status | |
Simulation time | 111453535 ps |
CPU time | 3.69 seconds |
Started | Mar 31 03:31:25 PM PDT 24 |
Finished | Mar 31 03:31:28 PM PDT 24 |
Peak memory | 241640 kb |
Host | smart-0aa1a18f-40c6-409e-a1e1-67f065727194 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=424662164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.424662164 |
Directory | /workspace/38.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/38.otp_ctrl_macro_errs.1729445868 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 151182563 ps |
CPU time | 4.99 seconds |
Started | Mar 31 03:31:21 PM PDT 24 |
Finished | Mar 31 03:31:26 PM PDT 24 |
Peak memory | 242100 kb |
Host | smart-074693ad-d4a9-4ba2-ac81-8ad17a72e4d2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1729445868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.1729445868 |
Directory | /workspace/38.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/38.otp_ctrl_parallel_key_req.2321533648 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 490389422 ps |
CPU time | 14.73 seconds |
Started | Mar 31 03:31:24 PM PDT 24 |
Finished | Mar 31 03:31:39 PM PDT 24 |
Peak memory | 241880 kb |
Host | smart-079420aa-bfa9-4258-950d-33177e7613b6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2321533648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_key_req.2321533648 |
Directory | /workspace/38.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/38.otp_ctrl_parallel_lc_esc.2055186287 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 705802564 ps |
CPU time | 10.38 seconds |
Started | Mar 31 03:31:22 PM PDT 24 |
Finished | Mar 31 03:31:33 PM PDT 24 |
Peak memory | 241684 kb |
Host | smart-3db2db0d-ae22-41d5-b439-24caa15f38ec |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2055186287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.2055186287 |
Directory | /workspace/38.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/38.otp_ctrl_parallel_lc_req.1449065734 |
Short name | T842 |
Test name | |
Test status | |
Simulation time | 391823040 ps |
CPU time | 11.43 seconds |
Started | Mar 31 03:31:25 PM PDT 24 |
Finished | Mar 31 03:31:37 PM PDT 24 |
Peak memory | 241696 kb |
Host | smart-52952162-07d3-47cd-913e-66cebc46b33c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1449065734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.1449065734 |
Directory | /workspace/38.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/38.otp_ctrl_regwen.1859813130 |
Short name | T508 |
Test name | |
Test status | |
Simulation time | 538406384 ps |
CPU time | 8.39 seconds |
Started | Mar 31 03:31:24 PM PDT 24 |
Finished | Mar 31 03:31:33 PM PDT 24 |
Peak memory | 241632 kb |
Host | smart-8ae6ccbd-6453-473a-b34f-b5c4b3d32552 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1859813130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.1859813130 |
Directory | /workspace/38.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/38.otp_ctrl_smoke.2337412635 |
Short name | T556 |
Test name | |
Test status | |
Simulation time | 124344094 ps |
CPU time | 3.88 seconds |
Started | Mar 31 03:31:20 PM PDT 24 |
Finished | Mar 31 03:31:24 PM PDT 24 |
Peak memory | 241480 kb |
Host | smart-bc105f10-0c6c-4020-908f-a9268744cf4e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2337412635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.2337412635 |
Directory | /workspace/38.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/38.otp_ctrl_stress_all.1439589923 |
Short name | T1072 |
Test name | |
Test status | |
Simulation time | 19090645139 ps |
CPU time | 192.74 seconds |
Started | Mar 31 03:31:25 PM PDT 24 |
Finished | Mar 31 03:34:38 PM PDT 24 |
Peak memory | 246792 kb |
Host | smart-c200f8a6-171c-49bc-914e-59e1531564e6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439589923 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all .1439589923 |
Directory | /workspace/38.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/38.otp_ctrl_stress_all_with_rand_reset.1282717857 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 132963375059 ps |
CPU time | 1024.22 seconds |
Started | Mar 31 03:31:24 PM PDT 24 |
Finished | Mar 31 03:48:28 PM PDT 24 |
Peak memory | 264844 kb |
Host | smart-ea5e6312-9375-4e24-8d81-b30d7e8e06c8 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282717857 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all_with_rand_reset.1282717857 |
Directory | /workspace/38.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/38.otp_ctrl_test_access.435557205 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 1342831573 ps |
CPU time | 22.93 seconds |
Started | Mar 31 03:31:19 PM PDT 24 |
Finished | Mar 31 03:31:42 PM PDT 24 |
Peak memory | 241736 kb |
Host | smart-1f71492f-5a9f-4b69-90e7-76ff86707024 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=435557205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.435557205 |
Directory | /workspace/38.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/39.otp_ctrl_alert_test.3185696951 |
Short name | T1162 |
Test name | |
Test status | |
Simulation time | 82272714 ps |
CPU time | 1.85 seconds |
Started | Mar 31 03:31:26 PM PDT 24 |
Finished | Mar 31 03:31:28 PM PDT 24 |
Peak memory | 240028 kb |
Host | smart-34855e3b-cccf-4371-a973-116c8e178c00 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185696951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.3185696951 |
Directory | /workspace/39.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/39.otp_ctrl_check_fail.2542033018 |
Short name | T513 |
Test name | |
Test status | |
Simulation time | 6038675567 ps |
CPU time | 12.02 seconds |
Started | Mar 31 03:31:26 PM PDT 24 |
Finished | Mar 31 03:31:38 PM PDT 24 |
Peak memory | 243328 kb |
Host | smart-a3cd306e-186f-4328-b7da-c2ebec90b7bf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2542033018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.2542033018 |
Directory | /workspace/39.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/39.otp_ctrl_dai_errs.2311084122 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 4582296678 ps |
CPU time | 20.54 seconds |
Started | Mar 31 03:31:26 PM PDT 24 |
Finished | Mar 31 03:31:47 PM PDT 24 |
Peak memory | 241760 kb |
Host | smart-2343cf5f-4d23-4cc1-a633-54e46e7eb2cf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2311084122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.2311084122 |
Directory | /workspace/39.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/39.otp_ctrl_dai_lock.4106454443 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 4406525883 ps |
CPU time | 23.92 seconds |
Started | Mar 31 03:31:27 PM PDT 24 |
Finished | Mar 31 03:31:51 PM PDT 24 |
Peak memory | 241700 kb |
Host | smart-e1cced78-3e5d-48a7-a271-d0237f18b9d7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4106454443 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.4106454443 |
Directory | /workspace/39.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/39.otp_ctrl_init_fail.4292842132 |
Short name | T893 |
Test name | |
Test status | |
Simulation time | 237919514 ps |
CPU time | 5.11 seconds |
Started | Mar 31 03:31:27 PM PDT 24 |
Finished | Mar 31 03:31:33 PM PDT 24 |
Peak memory | 241800 kb |
Host | smart-bc586ad9-291a-4227-8926-961eb8436ec4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4292842132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.4292842132 |
Directory | /workspace/39.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/39.otp_ctrl_parallel_key_req.311445310 |
Short name | T866 |
Test name | |
Test status | |
Simulation time | 3565471232 ps |
CPU time | 24.75 seconds |
Started | Mar 31 03:31:27 PM PDT 24 |
Finished | Mar 31 03:31:52 PM PDT 24 |
Peak memory | 242156 kb |
Host | smart-b1fb62a2-3eea-4c12-be46-d232bfd7af19 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=311445310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.311445310 |
Directory | /workspace/39.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/39.otp_ctrl_parallel_lc_esc.515981284 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 259758828 ps |
CPU time | 5.05 seconds |
Started | Mar 31 03:31:33 PM PDT 24 |
Finished | Mar 31 03:31:38 PM PDT 24 |
Peak memory | 241752 kb |
Host | smart-9f31df74-6809-4833-8506-0593ee22d0a2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=515981284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.515981284 |
Directory | /workspace/39.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/39.otp_ctrl_parallel_lc_req.2227561457 |
Short name | T1141 |
Test name | |
Test status | |
Simulation time | 12910617250 ps |
CPU time | 33.12 seconds |
Started | Mar 31 03:31:25 PM PDT 24 |
Finished | Mar 31 03:31:58 PM PDT 24 |
Peak memory | 241944 kb |
Host | smart-97533895-d1a0-49f0-a1e4-5c6898539142 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2227561457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.2227561457 |
Directory | /workspace/39.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/39.otp_ctrl_regwen.4114666293 |
Short name | T824 |
Test name | |
Test status | |
Simulation time | 229582601 ps |
CPU time | 6.01 seconds |
Started | Mar 31 03:31:29 PM PDT 24 |
Finished | Mar 31 03:31:35 PM PDT 24 |
Peak memory | 241672 kb |
Host | smart-4255e347-d346-47ef-be2e-d78bbf279749 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4114666293 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.4114666293 |
Directory | /workspace/39.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/39.otp_ctrl_smoke.3802227632 |
Short name | T583 |
Test name | |
Test status | |
Simulation time | 180938369 ps |
CPU time | 4.47 seconds |
Started | Mar 31 03:31:32 PM PDT 24 |
Finished | Mar 31 03:31:37 PM PDT 24 |
Peak memory | 241648 kb |
Host | smart-9acf6e0c-5962-4180-8614-0ba92471f41b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3802227632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.3802227632 |
Directory | /workspace/39.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/39.otp_ctrl_stress_all.473144722 |
Short name | T1017 |
Test name | |
Test status | |
Simulation time | 18351273266 ps |
CPU time | 92.66 seconds |
Started | Mar 31 03:31:26 PM PDT 24 |
Finished | Mar 31 03:32:59 PM PDT 24 |
Peak memory | 248456 kb |
Host | smart-d6da6c06-48c8-41f3-b987-d29a3a6237de |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473144722 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all. 473144722 |
Directory | /workspace/39.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/39.otp_ctrl_stress_all_with_rand_reset.3109039762 |
Short name | T962 |
Test name | |
Test status | |
Simulation time | 44408562122 ps |
CPU time | 988.11 seconds |
Started | Mar 31 03:31:26 PM PDT 24 |
Finished | Mar 31 03:47:54 PM PDT 24 |
Peak memory | 319940 kb |
Host | smart-0e36cd28-4630-4dab-9176-e5fea8e3a4fc |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109039762 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all_with_rand_reset.3109039762 |
Directory | /workspace/39.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/39.otp_ctrl_test_access.1928348651 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 7568721084 ps |
CPU time | 14.41 seconds |
Started | Mar 31 03:31:26 PM PDT 24 |
Finished | Mar 31 03:31:41 PM PDT 24 |
Peak memory | 242368 kb |
Host | smart-fc1476bf-67e1-4af2-ad1e-d618010a39e7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1928348651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.1928348651 |
Directory | /workspace/39.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/4.otp_ctrl_alert_test.1532393184 |
Short name | T723 |
Test name | |
Test status | |
Simulation time | 547961572 ps |
CPU time | 2.03 seconds |
Started | Mar 31 03:28:58 PM PDT 24 |
Finished | Mar 31 03:29:00 PM PDT 24 |
Peak memory | 240064 kb |
Host | smart-e3fbb44a-dfc8-4f00-8c00-fb40041e2932 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532393184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.1532393184 |
Directory | /workspace/4.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/4.otp_ctrl_background_chks.2485056245 |
Short name | T494 |
Test name | |
Test status | |
Simulation time | 1150059111 ps |
CPU time | 23.57 seconds |
Started | Mar 31 03:28:53 PM PDT 24 |
Finished | Mar 31 03:29:17 PM PDT 24 |
Peak memory | 241740 kb |
Host | smart-c828098d-5b5d-48e2-aa0f-e2a01dfb67d8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2485056245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.2485056245 |
Directory | /workspace/4.otp_ctrl_background_chks/latest |
Test location | /workspace/coverage/default/4.otp_ctrl_check_fail.4156552965 |
Short name | T1071 |
Test name | |
Test status | |
Simulation time | 310203045 ps |
CPU time | 4.82 seconds |
Started | Mar 31 03:28:53 PM PDT 24 |
Finished | Mar 31 03:28:58 PM PDT 24 |
Peak memory | 241944 kb |
Host | smart-22bb2f61-acff-48ea-8ab7-0305bc50a78a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4156552965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.4156552965 |
Directory | /workspace/4.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/4.otp_ctrl_dai_errs.2312551426 |
Short name | T476 |
Test name | |
Test status | |
Simulation time | 432522854 ps |
CPU time | 12.16 seconds |
Started | Mar 31 03:28:52 PM PDT 24 |
Finished | Mar 31 03:29:05 PM PDT 24 |
Peak memory | 242188 kb |
Host | smart-3fdfa90e-9224-47aa-8514-5e379a8953a4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2312551426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.2312551426 |
Directory | /workspace/4.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/4.otp_ctrl_dai_lock.3993949892 |
Short name | T582 |
Test name | |
Test status | |
Simulation time | 1318984118 ps |
CPU time | 12.07 seconds |
Started | Mar 31 03:28:55 PM PDT 24 |
Finished | Mar 31 03:29:07 PM PDT 24 |
Peak memory | 242140 kb |
Host | smart-a5111496-b0b6-4357-b997-a4cf012275ca |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3993949892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.3993949892 |
Directory | /workspace/4.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/4.otp_ctrl_init_fail.3831276844 |
Short name | T771 |
Test name | |
Test status | |
Simulation time | 127469500 ps |
CPU time | 3.03 seconds |
Started | Mar 31 03:28:51 PM PDT 24 |
Finished | Mar 31 03:28:54 PM PDT 24 |
Peak memory | 241756 kb |
Host | smart-c7907b66-76db-4fb8-ab6b-4cb980281357 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3831276844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.3831276844 |
Directory | /workspace/4.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/4.otp_ctrl_macro_errs.2350058775 |
Short name | T1052 |
Test name | |
Test status | |
Simulation time | 3988970887 ps |
CPU time | 26.75 seconds |
Started | Mar 31 03:28:52 PM PDT 24 |
Finished | Mar 31 03:29:20 PM PDT 24 |
Peak memory | 244780 kb |
Host | smart-05ceff9d-2c4c-45dc-b3cd-e881a298b8a8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2350058775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.2350058775 |
Directory | /workspace/4.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/4.otp_ctrl_parallel_key_req.1536701333 |
Short name | T1043 |
Test name | |
Test status | |
Simulation time | 757958234 ps |
CPU time | 16.59 seconds |
Started | Mar 31 03:28:55 PM PDT 24 |
Finished | Mar 31 03:29:11 PM PDT 24 |
Peak memory | 241800 kb |
Host | smart-f73cfd39-634b-4b2e-9067-db10179ebfe9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1536701333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.1536701333 |
Directory | /workspace/4.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/4.otp_ctrl_parallel_lc_esc.1406829169 |
Short name | T892 |
Test name | |
Test status | |
Simulation time | 835422226 ps |
CPU time | 15.53 seconds |
Started | Mar 31 03:28:52 PM PDT 24 |
Finished | Mar 31 03:29:08 PM PDT 24 |
Peak memory | 241672 kb |
Host | smart-c7d02fb2-ef22-476d-9f08-322a9c4f6c19 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1406829169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.1406829169 |
Directory | /workspace/4.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/4.otp_ctrl_parallel_lc_req.3301374386 |
Short name | T1116 |
Test name | |
Test status | |
Simulation time | 202803889 ps |
CPU time | 6.16 seconds |
Started | Mar 31 03:28:53 PM PDT 24 |
Finished | Mar 31 03:28:59 PM PDT 24 |
Peak memory | 241964 kb |
Host | smart-21bf00df-f02c-4842-8b02-8556249ce8e5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3301374386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.3301374386 |
Directory | /workspace/4.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/4.otp_ctrl_regwen.917208249 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 471476357 ps |
CPU time | 7.6 seconds |
Started | Mar 31 03:28:53 PM PDT 24 |
Finished | Mar 31 03:29:01 PM PDT 24 |
Peak memory | 241684 kb |
Host | smart-b1af2211-a862-4c16-b549-dc28bed2d94e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=917208249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.917208249 |
Directory | /workspace/4.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/4.otp_ctrl_sec_cm.2198722737 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 11196567585 ps |
CPU time | 202.28 seconds |
Started | Mar 31 03:28:59 PM PDT 24 |
Finished | Mar 31 03:32:22 PM PDT 24 |
Peak memory | 274812 kb |
Host | smart-32f39bc3-1fe3-443a-b152-7c4d3dff361d |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198722737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.2198722737 |
Directory | /workspace/4.otp_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/4.otp_ctrl_smoke.1704641218 |
Short name | T995 |
Test name | |
Test status | |
Simulation time | 1848980899 ps |
CPU time | 4.98 seconds |
Started | Mar 31 03:28:46 PM PDT 24 |
Finished | Mar 31 03:28:51 PM PDT 24 |
Peak memory | 248408 kb |
Host | smart-1f5ac98d-58b7-4789-b55f-8bebc15be2ea |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1704641218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.1704641218 |
Directory | /workspace/4.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/4.otp_ctrl_stress_all.2739047229 |
Short name | T954 |
Test name | |
Test status | |
Simulation time | 38003097596 ps |
CPU time | 208.53 seconds |
Started | Mar 31 03:28:58 PM PDT 24 |
Finished | Mar 31 03:32:26 PM PDT 24 |
Peak memory | 263964 kb |
Host | smart-c993ea30-dda3-4ddb-a9b5-d4b9d7b258ce |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739047229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all. 2739047229 |
Directory | /workspace/4.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/4.otp_ctrl_stress_all_with_rand_reset.1260276889 |
Short name | T617 |
Test name | |
Test status | |
Simulation time | 338159055471 ps |
CPU time | 655.78 seconds |
Started | Mar 31 03:28:53 PM PDT 24 |
Finished | Mar 31 03:39:49 PM PDT 24 |
Peak memory | 258556 kb |
Host | smart-f6a8afce-c6c0-4a45-a3fc-ad9cc58af195 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260276889 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all_with_rand_reset.1260276889 |
Directory | /workspace/4.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/4.otp_ctrl_test_access.2420551712 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 1314977311 ps |
CPU time | 31.71 seconds |
Started | Mar 31 03:28:53 PM PDT 24 |
Finished | Mar 31 03:29:25 PM PDT 24 |
Peak memory | 242328 kb |
Host | smart-1916c26f-3e44-4886-b298-354130ad5ccf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2420551712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.2420551712 |
Directory | /workspace/4.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/40.otp_ctrl_alert_test.1751982797 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 58249957 ps |
CPU time | 1.77 seconds |
Started | Mar 31 03:31:32 PM PDT 24 |
Finished | Mar 31 03:31:33 PM PDT 24 |
Peak memory | 240160 kb |
Host | smart-125edd02-603e-4138-b045-eda78b689af1 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751982797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.1751982797 |
Directory | /workspace/40.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/40.otp_ctrl_dai_errs.3251198652 |
Short name | T623 |
Test name | |
Test status | |
Simulation time | 353061440 ps |
CPU time | 19.59 seconds |
Started | Mar 31 03:31:33 PM PDT 24 |
Finished | Mar 31 03:31:52 PM PDT 24 |
Peak memory | 241500 kb |
Host | smart-b4e55e75-9ea7-4681-8585-dd3093178d7e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3251198652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_errs.3251198652 |
Directory | /workspace/40.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/40.otp_ctrl_dai_lock.126074243 |
Short name | T487 |
Test name | |
Test status | |
Simulation time | 18149654322 ps |
CPU time | 40.65 seconds |
Started | Mar 31 03:31:32 PM PDT 24 |
Finished | Mar 31 03:32:13 PM PDT 24 |
Peak memory | 242340 kb |
Host | smart-722e0c71-c218-4a7a-9207-3ecdab862f06 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=126074243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.126074243 |
Directory | /workspace/40.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/40.otp_ctrl_init_fail.186194991 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 166619062 ps |
CPU time | 3.27 seconds |
Started | Mar 31 03:31:26 PM PDT 24 |
Finished | Mar 31 03:31:29 PM PDT 24 |
Peak memory | 242040 kb |
Host | smart-0c881758-4beb-4e30-98e3-b0d9384f999a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=186194991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.186194991 |
Directory | /workspace/40.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/40.otp_ctrl_macro_errs.872367767 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 553751443 ps |
CPU time | 3.97 seconds |
Started | Mar 31 03:31:28 PM PDT 24 |
Finished | Mar 31 03:31:32 PM PDT 24 |
Peak memory | 242020 kb |
Host | smart-35fc8eea-7065-4081-aae2-e73a6e5258d6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=872367767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.872367767 |
Directory | /workspace/40.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/40.otp_ctrl_parallel_key_req.4246110264 |
Short name | T1185 |
Test name | |
Test status | |
Simulation time | 440014926 ps |
CPU time | 16.38 seconds |
Started | Mar 31 03:31:26 PM PDT 24 |
Finished | Mar 31 03:31:42 PM PDT 24 |
Peak memory | 241908 kb |
Host | smart-841c5150-0044-4605-a47e-1e4a951ef7d6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4246110264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_key_req.4246110264 |
Directory | /workspace/40.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/40.otp_ctrl_parallel_lc_esc.3457852520 |
Short name | T1021 |
Test name | |
Test status | |
Simulation time | 274866439 ps |
CPU time | 4.92 seconds |
Started | Mar 31 03:31:28 PM PDT 24 |
Finished | Mar 31 03:31:33 PM PDT 24 |
Peak memory | 241532 kb |
Host | smart-0635c987-b3aa-4ca9-9142-4f1e00b93c7c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3457852520 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.3457852520 |
Directory | /workspace/40.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/40.otp_ctrl_parallel_lc_req.1895058862 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 1451525610 ps |
CPU time | 19.83 seconds |
Started | Mar 31 03:31:27 PM PDT 24 |
Finished | Mar 31 03:31:47 PM PDT 24 |
Peak memory | 241616 kb |
Host | smart-46e4a994-55bb-4ecd-990e-3c9359dac4fd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1895058862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.1895058862 |
Directory | /workspace/40.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/40.otp_ctrl_regwen.888465220 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 298361212 ps |
CPU time | 9.05 seconds |
Started | Mar 31 03:31:26 PM PDT 24 |
Finished | Mar 31 03:31:35 PM PDT 24 |
Peak memory | 242040 kb |
Host | smart-46556e86-b02d-40d9-bf3e-3e80ae154a5c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=888465220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.888465220 |
Directory | /workspace/40.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/40.otp_ctrl_smoke.2095899474 |
Short name | T552 |
Test name | |
Test status | |
Simulation time | 5148398548 ps |
CPU time | 7.98 seconds |
Started | Mar 31 03:31:27 PM PDT 24 |
Finished | Mar 31 03:31:35 PM PDT 24 |
Peak memory | 241940 kb |
Host | smart-02af5273-2e48-4021-8f88-3d26511f36dc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2095899474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_smoke.2095899474 |
Directory | /workspace/40.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/40.otp_ctrl_stress_all.1534848989 |
Short name | T1077 |
Test name | |
Test status | |
Simulation time | 23675114834 ps |
CPU time | 289.64 seconds |
Started | Mar 31 03:31:29 PM PDT 24 |
Finished | Mar 31 03:36:19 PM PDT 24 |
Peak memory | 289708 kb |
Host | smart-41054972-8634-42f2-8887-047b688700c3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534848989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all .1534848989 |
Directory | /workspace/40.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/40.otp_ctrl_stress_all_with_rand_reset.737779330 |
Short name | T696 |
Test name | |
Test status | |
Simulation time | 89518568498 ps |
CPU time | 888.47 seconds |
Started | Mar 31 03:31:33 PM PDT 24 |
Finished | Mar 31 03:46:21 PM PDT 24 |
Peak memory | 284848 kb |
Host | smart-5bc431c8-70dc-4c54-bfd0-e1abb02fb496 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737779330 -assert nopo stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all_with_rand_reset.737779330 |
Directory | /workspace/40.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/40.otp_ctrl_test_access.1994423689 |
Short name | T1165 |
Test name | |
Test status | |
Simulation time | 634057652 ps |
CPU time | 10.76 seconds |
Started | Mar 31 03:31:27 PM PDT 24 |
Finished | Mar 31 03:31:38 PM PDT 24 |
Peak memory | 241892 kb |
Host | smart-9cf205e3-56d3-4531-9eaf-92ed7c9c607f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1994423689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.1994423689 |
Directory | /workspace/40.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/41.otp_ctrl_alert_test.1288296337 |
Short name | T864 |
Test name | |
Test status | |
Simulation time | 164104458 ps |
CPU time | 2.68 seconds |
Started | Mar 31 03:31:30 PM PDT 24 |
Finished | Mar 31 03:31:33 PM PDT 24 |
Peak memory | 240284 kb |
Host | smart-58c91575-40b7-488a-a00f-ca95270cb9cf |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288296337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.1288296337 |
Directory | /workspace/41.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/41.otp_ctrl_check_fail.2747692746 |
Short name | T546 |
Test name | |
Test status | |
Simulation time | 2172405170 ps |
CPU time | 6.28 seconds |
Started | Mar 31 03:31:38 PM PDT 24 |
Finished | Mar 31 03:31:44 PM PDT 24 |
Peak memory | 241800 kb |
Host | smart-4bd7453d-9895-4f3a-b7ba-463ec5d88700 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2747692746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.2747692746 |
Directory | /workspace/41.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/41.otp_ctrl_dai_errs.1410356512 |
Short name | T980 |
Test name | |
Test status | |
Simulation time | 1264337401 ps |
CPU time | 20.15 seconds |
Started | Mar 31 03:31:30 PM PDT 24 |
Finished | Mar 31 03:31:50 PM PDT 24 |
Peak memory | 242040 kb |
Host | smart-c9da97ee-a0c1-4947-8afe-a08b4310475b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1410356512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_errs.1410356512 |
Directory | /workspace/41.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/41.otp_ctrl_dai_lock.2105776028 |
Short name | T1027 |
Test name | |
Test status | |
Simulation time | 4589786302 ps |
CPU time | 26.05 seconds |
Started | Mar 31 03:31:38 PM PDT 24 |
Finished | Mar 31 03:32:04 PM PDT 24 |
Peak memory | 242576 kb |
Host | smart-85f8160e-17d0-47fd-864c-411ce5f881e7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2105776028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.2105776028 |
Directory | /workspace/41.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/41.otp_ctrl_init_fail.2687253591 |
Short name | T1168 |
Test name | |
Test status | |
Simulation time | 2747224374 ps |
CPU time | 7.7 seconds |
Started | Mar 31 03:31:31 PM PDT 24 |
Finished | Mar 31 03:31:39 PM PDT 24 |
Peak memory | 241860 kb |
Host | smart-faac15f8-3149-4b49-ba61-90272317e424 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2687253591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.2687253591 |
Directory | /workspace/41.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/41.otp_ctrl_macro_errs.2853467557 |
Short name | T924 |
Test name | |
Test status | |
Simulation time | 1120056393 ps |
CPU time | 17.81 seconds |
Started | Mar 31 03:31:30 PM PDT 24 |
Finished | Mar 31 03:31:48 PM PDT 24 |
Peak memory | 242612 kb |
Host | smart-1a8065a6-6c5a-4f04-bb9b-5b3f24c5ebcb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2853467557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.2853467557 |
Directory | /workspace/41.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/41.otp_ctrl_parallel_key_req.2096409240 |
Short name | T915 |
Test name | |
Test status | |
Simulation time | 3384692409 ps |
CPU time | 22.99 seconds |
Started | Mar 31 03:31:32 PM PDT 24 |
Finished | Mar 31 03:31:55 PM PDT 24 |
Peak memory | 241836 kb |
Host | smart-db487568-3b67-49be-a264-200a0fd3a98e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2096409240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_key_req.2096409240 |
Directory | /workspace/41.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/41.otp_ctrl_parallel_lc_esc.2263614730 |
Short name | T510 |
Test name | |
Test status | |
Simulation time | 477026493 ps |
CPU time | 7.81 seconds |
Started | Mar 31 03:31:32 PM PDT 24 |
Finished | Mar 31 03:31:40 PM PDT 24 |
Peak memory | 241948 kb |
Host | smart-312aef98-4061-47aa-888b-cc673963639d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2263614730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.2263614730 |
Directory | /workspace/41.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/41.otp_ctrl_parallel_lc_req.3138708801 |
Short name | T1128 |
Test name | |
Test status | |
Simulation time | 831030036 ps |
CPU time | 8.4 seconds |
Started | Mar 31 03:31:30 PM PDT 24 |
Finished | Mar 31 03:31:39 PM PDT 24 |
Peak memory | 241768 kb |
Host | smart-f9afaae8-8bff-4ac7-a080-6a0f53003e91 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3138708801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.3138708801 |
Directory | /workspace/41.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/41.otp_ctrl_regwen.150086513 |
Short name | T1175 |
Test name | |
Test status | |
Simulation time | 1874633337 ps |
CPU time | 7.02 seconds |
Started | Mar 31 03:31:31 PM PDT 24 |
Finished | Mar 31 03:31:38 PM PDT 24 |
Peak memory | 241932 kb |
Host | smart-ae3fa565-4882-4250-8ba9-f712bb992dd0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=150086513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.150086513 |
Directory | /workspace/41.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/41.otp_ctrl_smoke.3842747947 |
Short name | T474 |
Test name | |
Test status | |
Simulation time | 1667257691 ps |
CPU time | 8.56 seconds |
Started | Mar 31 03:31:31 PM PDT 24 |
Finished | Mar 31 03:31:40 PM PDT 24 |
Peak memory | 241928 kb |
Host | smart-72b80ffc-ad0f-4f35-bddc-cc208e95845f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3842747947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.3842747947 |
Directory | /workspace/41.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/41.otp_ctrl_stress_all_with_rand_reset.659309561 |
Short name | T855 |
Test name | |
Test status | |
Simulation time | 804358007484 ps |
CPU time | 1249.49 seconds |
Started | Mar 31 03:31:38 PM PDT 24 |
Finished | Mar 31 03:52:27 PM PDT 24 |
Peak memory | 339060 kb |
Host | smart-92b09dcc-28d5-4bdb-be08-aeab21ce1d42 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659309561 -assert nopo stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all_with_rand_reset.659309561 |
Directory | /workspace/41.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/41.otp_ctrl_test_access.4046198976 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 2362207555 ps |
CPU time | 17.77 seconds |
Started | Mar 31 03:31:32 PM PDT 24 |
Finished | Mar 31 03:31:50 PM PDT 24 |
Peak memory | 242468 kb |
Host | smart-81841766-b1b6-4248-8dd9-69a1d42ed26e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4046198976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.4046198976 |
Directory | /workspace/41.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/42.otp_ctrl_alert_test.1093278132 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 174625636 ps |
CPU time | 2.35 seconds |
Started | Mar 31 03:31:36 PM PDT 24 |
Finished | Mar 31 03:31:38 PM PDT 24 |
Peak memory | 239984 kb |
Host | smart-ed8f2976-7fc5-418e-a09a-b5fbbc45c0b5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093278132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.1093278132 |
Directory | /workspace/42.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/42.otp_ctrl_check_fail.2480479387 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 13061767778 ps |
CPU time | 109.84 seconds |
Started | Mar 31 03:31:37 PM PDT 24 |
Finished | Mar 31 03:33:26 PM PDT 24 |
Peak memory | 243360 kb |
Host | smart-9954d6ac-4b7e-4d75-8dad-cb92627de82e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2480479387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.2480479387 |
Directory | /workspace/42.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/42.otp_ctrl_dai_errs.818871393 |
Short name | T908 |
Test name | |
Test status | |
Simulation time | 351496385 ps |
CPU time | 16.3 seconds |
Started | Mar 31 03:31:38 PM PDT 24 |
Finished | Mar 31 03:31:54 PM PDT 24 |
Peak memory | 241432 kb |
Host | smart-afcb6d42-917c-46a4-aa8d-075c6ca017aa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=818871393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_errs.818871393 |
Directory | /workspace/42.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/42.otp_ctrl_dai_lock.3628955849 |
Short name | T1061 |
Test name | |
Test status | |
Simulation time | 19777227237 ps |
CPU time | 159.1 seconds |
Started | Mar 31 03:31:36 PM PDT 24 |
Finished | Mar 31 03:34:15 PM PDT 24 |
Peak memory | 243032 kb |
Host | smart-84616bb1-1ea4-4523-bdf0-113402eee1a5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3628955849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.3628955849 |
Directory | /workspace/42.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/42.otp_ctrl_init_fail.3354673996 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 97868244 ps |
CPU time | 3.99 seconds |
Started | Mar 31 03:31:32 PM PDT 24 |
Finished | Mar 31 03:31:36 PM PDT 24 |
Peak memory | 241664 kb |
Host | smart-f21c3741-aefb-4292-abc4-33882f3c62d9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3354673996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.3354673996 |
Directory | /workspace/42.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/42.otp_ctrl_macro_errs.1963899009 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 11612930629 ps |
CPU time | 26.32 seconds |
Started | Mar 31 03:31:38 PM PDT 24 |
Finished | Mar 31 03:32:05 PM PDT 24 |
Peak memory | 247180 kb |
Host | smart-048e16bd-9ecf-477d-bc76-6ed70a45c51e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1963899009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_macro_errs.1963899009 |
Directory | /workspace/42.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/42.otp_ctrl_parallel_key_req.2156024847 |
Short name | T688 |
Test name | |
Test status | |
Simulation time | 1701860269 ps |
CPU time | 17.96 seconds |
Started | Mar 31 03:31:40 PM PDT 24 |
Finished | Mar 31 03:31:58 PM PDT 24 |
Peak memory | 242020 kb |
Host | smart-807b519d-9b32-4276-9a63-69050a7f1506 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2156024847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.2156024847 |
Directory | /workspace/42.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/42.otp_ctrl_parallel_lc_esc.1044134579 |
Short name | T1137 |
Test name | |
Test status | |
Simulation time | 547482698 ps |
CPU time | 6.86 seconds |
Started | Mar 31 03:31:36 PM PDT 24 |
Finished | Mar 31 03:31:43 PM PDT 24 |
Peak memory | 241708 kb |
Host | smart-b6f3bb40-ce70-44cb-8275-3a519a7d2f50 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1044134579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.1044134579 |
Directory | /workspace/42.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/42.otp_ctrl_parallel_lc_req.3490283362 |
Short name | T1106 |
Test name | |
Test status | |
Simulation time | 514974165 ps |
CPU time | 5.19 seconds |
Started | Mar 31 03:31:37 PM PDT 24 |
Finished | Mar 31 03:31:42 PM PDT 24 |
Peak memory | 241688 kb |
Host | smart-81398226-2d26-4c06-9edf-813d2b466570 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3490283362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.3490283362 |
Directory | /workspace/42.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/42.otp_ctrl_regwen.3986421991 |
Short name | T1082 |
Test name | |
Test status | |
Simulation time | 109948809 ps |
CPU time | 3.71 seconds |
Started | Mar 31 03:31:37 PM PDT 24 |
Finished | Mar 31 03:31:40 PM PDT 24 |
Peak memory | 241768 kb |
Host | smart-b91617a5-17d7-4861-959e-fbe2981cf524 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3986421991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.3986421991 |
Directory | /workspace/42.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/42.otp_ctrl_smoke.3120456937 |
Short name | T859 |
Test name | |
Test status | |
Simulation time | 226139734 ps |
CPU time | 5 seconds |
Started | Mar 31 03:31:33 PM PDT 24 |
Finished | Mar 31 03:31:38 PM PDT 24 |
Peak memory | 241968 kb |
Host | smart-95d4ebaf-e5e7-45c7-874b-31ac234b1626 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3120456937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_smoke.3120456937 |
Directory | /workspace/42.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/42.otp_ctrl_test_access.1648560138 |
Short name | T807 |
Test name | |
Test status | |
Simulation time | 2488583661 ps |
CPU time | 32.45 seconds |
Started | Mar 31 03:31:38 PM PDT 24 |
Finished | Mar 31 03:32:11 PM PDT 24 |
Peak memory | 241740 kb |
Host | smart-19f28266-1bc6-46cf-b262-db942dbe5437 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1648560138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.1648560138 |
Directory | /workspace/42.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/43.otp_ctrl_alert_test.3471850509 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 94031751 ps |
CPU time | 1.81 seconds |
Started | Mar 31 03:31:43 PM PDT 24 |
Finished | Mar 31 03:31:45 PM PDT 24 |
Peak memory | 239980 kb |
Host | smart-e4eaedbe-cb35-4a14-b4d3-748c4ce61d2c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471850509 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.3471850509 |
Directory | /workspace/43.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/43.otp_ctrl_check_fail.3458156347 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 2548902448 ps |
CPU time | 17.41 seconds |
Started | Mar 31 03:31:48 PM PDT 24 |
Finished | Mar 31 03:32:06 PM PDT 24 |
Peak memory | 241804 kb |
Host | smart-138dbeb8-fe06-4572-a41e-fa014dc13e96 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3458156347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.3458156347 |
Directory | /workspace/43.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/43.otp_ctrl_dai_errs.4098842024 |
Short name | T777 |
Test name | |
Test status | |
Simulation time | 1114956010 ps |
CPU time | 13.15 seconds |
Started | Mar 31 03:31:38 PM PDT 24 |
Finished | Mar 31 03:31:51 PM PDT 24 |
Peak memory | 242072 kb |
Host | smart-3678348c-b2a1-4850-99eb-c847463ad08e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4098842024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.4098842024 |
Directory | /workspace/43.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/43.otp_ctrl_dai_lock.480399234 |
Short name | T1171 |
Test name | |
Test status | |
Simulation time | 801102957 ps |
CPU time | 14.1 seconds |
Started | Mar 31 03:31:37 PM PDT 24 |
Finished | Mar 31 03:31:51 PM PDT 24 |
Peak memory | 241684 kb |
Host | smart-c6b09660-cd42-4841-a325-3288bec1f61a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=480399234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_lock.480399234 |
Directory | /workspace/43.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/43.otp_ctrl_init_fail.4267635326 |
Short name | T886 |
Test name | |
Test status | |
Simulation time | 435728399 ps |
CPU time | 3.86 seconds |
Started | Mar 31 03:31:36 PM PDT 24 |
Finished | Mar 31 03:31:40 PM PDT 24 |
Peak memory | 241812 kb |
Host | smart-a01afe3c-66fd-45f3-8927-f873d03ab68d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4267635326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.4267635326 |
Directory | /workspace/43.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/43.otp_ctrl_macro_errs.141569391 |
Short name | T1186 |
Test name | |
Test status | |
Simulation time | 3838730223 ps |
CPU time | 25.22 seconds |
Started | Mar 31 03:31:41 PM PDT 24 |
Finished | Mar 31 03:32:07 PM PDT 24 |
Peak memory | 243360 kb |
Host | smart-1ba49dd2-bb99-4884-8c25-b28ac2b9edda |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=141569391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.141569391 |
Directory | /workspace/43.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/43.otp_ctrl_parallel_key_req.3060903692 |
Short name | T673 |
Test name | |
Test status | |
Simulation time | 5093377455 ps |
CPU time | 15.76 seconds |
Started | Mar 31 03:31:42 PM PDT 24 |
Finished | Mar 31 03:31:58 PM PDT 24 |
Peak memory | 241660 kb |
Host | smart-e5d0b2bb-1a7f-4ba7-bbdd-5601454562c0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3060903692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_key_req.3060903692 |
Directory | /workspace/43.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/43.otp_ctrl_parallel_lc_esc.1426738851 |
Short name | T641 |
Test name | |
Test status | |
Simulation time | 205507519 ps |
CPU time | 5 seconds |
Started | Mar 31 03:31:37 PM PDT 24 |
Finished | Mar 31 03:31:42 PM PDT 24 |
Peak memory | 241624 kb |
Host | smart-2462dffe-1ffd-4a07-9c53-9256270fa1da |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1426738851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.1426738851 |
Directory | /workspace/43.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/43.otp_ctrl_parallel_lc_req.60097827 |
Short name | T891 |
Test name | |
Test status | |
Simulation time | 649313256 ps |
CPU time | 17.06 seconds |
Started | Mar 31 03:31:36 PM PDT 24 |
Finished | Mar 31 03:31:53 PM PDT 24 |
Peak memory | 241832 kb |
Host | smart-fd29cd4f-4d3a-4db9-9ef2-288843e03f01 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=60097827 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.60097827 |
Directory | /workspace/43.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/43.otp_ctrl_regwen.1157227321 |
Short name | T1029 |
Test name | |
Test status | |
Simulation time | 515350722 ps |
CPU time | 6.25 seconds |
Started | Mar 31 03:31:42 PM PDT 24 |
Finished | Mar 31 03:31:49 PM PDT 24 |
Peak memory | 241700 kb |
Host | smart-0fb9fa67-16f0-4b39-bc6f-634c9ca0115f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1157227321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.1157227321 |
Directory | /workspace/43.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/43.otp_ctrl_smoke.1109287798 |
Short name | T713 |
Test name | |
Test status | |
Simulation time | 1006646718 ps |
CPU time | 11.76 seconds |
Started | Mar 31 03:31:37 PM PDT 24 |
Finished | Mar 31 03:31:49 PM PDT 24 |
Peak memory | 241988 kb |
Host | smart-0b560150-0a40-4bbe-94aa-64197c931299 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1109287798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_smoke.1109287798 |
Directory | /workspace/43.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/43.otp_ctrl_stress_all.1828302731 |
Short name | T960 |
Test name | |
Test status | |
Simulation time | 1276063450 ps |
CPU time | 16.93 seconds |
Started | Mar 31 03:31:43 PM PDT 24 |
Finished | Mar 31 03:32:00 PM PDT 24 |
Peak memory | 248584 kb |
Host | smart-77445ca6-1f53-42b9-8f44-e42fad8662d2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828302731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all .1828302731 |
Directory | /workspace/43.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/43.otp_ctrl_test_access.4057821648 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 378082124 ps |
CPU time | 6.53 seconds |
Started | Mar 31 03:31:41 PM PDT 24 |
Finished | Mar 31 03:31:48 PM PDT 24 |
Peak memory | 241712 kb |
Host | smart-98f05439-a213-4ad7-9cc4-76a8bbe193c7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4057821648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.4057821648 |
Directory | /workspace/43.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/44.otp_ctrl_alert_test.1326724609 |
Short name | T557 |
Test name | |
Test status | |
Simulation time | 118596705 ps |
CPU time | 1.83 seconds |
Started | Mar 31 03:31:49 PM PDT 24 |
Finished | Mar 31 03:31:51 PM PDT 24 |
Peak memory | 240036 kb |
Host | smart-1720dcfb-ca9a-4332-853e-89b9fb0b5767 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326724609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.1326724609 |
Directory | /workspace/44.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/44.otp_ctrl_check_fail.1092510140 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 3287376424 ps |
CPU time | 30.39 seconds |
Started | Mar 31 03:31:44 PM PDT 24 |
Finished | Mar 31 03:32:15 PM PDT 24 |
Peak memory | 241768 kb |
Host | smart-7eb45e42-4b79-4e39-a5bd-ff67b253769a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1092510140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_check_fail.1092510140 |
Directory | /workspace/44.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/44.otp_ctrl_dai_errs.812373377 |
Short name | T655 |
Test name | |
Test status | |
Simulation time | 342397839 ps |
CPU time | 17.6 seconds |
Started | Mar 31 03:31:42 PM PDT 24 |
Finished | Mar 31 03:32:00 PM PDT 24 |
Peak memory | 241956 kb |
Host | smart-0723e093-4b02-429b-a053-0b1967e3267b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=812373377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_errs.812373377 |
Directory | /workspace/44.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/44.otp_ctrl_dai_lock.283248606 |
Short name | T1102 |
Test name | |
Test status | |
Simulation time | 19109464235 ps |
CPU time | 37.17 seconds |
Started | Mar 31 03:31:44 PM PDT 24 |
Finished | Mar 31 03:32:22 PM PDT 24 |
Peak memory | 243332 kb |
Host | smart-f8c67ee5-b26f-4164-b7c8-d37003d02329 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=283248606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_lock.283248606 |
Directory | /workspace/44.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/44.otp_ctrl_macro_errs.1064904088 |
Short name | T965 |
Test name | |
Test status | |
Simulation time | 895384971 ps |
CPU time | 26.49 seconds |
Started | Mar 31 03:31:43 PM PDT 24 |
Finished | Mar 31 03:32:10 PM PDT 24 |
Peak memory | 243816 kb |
Host | smart-d69c28f6-a26c-4aea-bd28-4a2b0bacd5be |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1064904088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_macro_errs.1064904088 |
Directory | /workspace/44.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/44.otp_ctrl_parallel_key_req.1345782659 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 6778706223 ps |
CPU time | 18.45 seconds |
Started | Mar 31 03:31:43 PM PDT 24 |
Finished | Mar 31 03:32:02 PM PDT 24 |
Peak memory | 242692 kb |
Host | smart-394db9c5-1408-465f-96b3-0a164121fc5d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1345782659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.1345782659 |
Directory | /workspace/44.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/44.otp_ctrl_parallel_lc_esc.916526553 |
Short name | T1105 |
Test name | |
Test status | |
Simulation time | 331908375 ps |
CPU time | 4.87 seconds |
Started | Mar 31 03:31:44 PM PDT 24 |
Finished | Mar 31 03:31:49 PM PDT 24 |
Peak memory | 241996 kb |
Host | smart-56acbb51-28cb-4e38-9c15-382c885e9bae |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=916526553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.916526553 |
Directory | /workspace/44.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/44.otp_ctrl_parallel_lc_req.1184892746 |
Short name | T1057 |
Test name | |
Test status | |
Simulation time | 733365895 ps |
CPU time | 7.78 seconds |
Started | Mar 31 03:31:43 PM PDT 24 |
Finished | Mar 31 03:31:51 PM PDT 24 |
Peak memory | 241536 kb |
Host | smart-8052c431-7cb4-4b68-94fc-723f6558330f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1184892746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.1184892746 |
Directory | /workspace/44.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/44.otp_ctrl_regwen.1139561695 |
Short name | T484 |
Test name | |
Test status | |
Simulation time | 141687469 ps |
CPU time | 5.51 seconds |
Started | Mar 31 03:31:43 PM PDT 24 |
Finished | Mar 31 03:31:48 PM PDT 24 |
Peak memory | 241724 kb |
Host | smart-4c479447-ac3c-4567-af4d-058dc5ca4cca |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1139561695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.1139561695 |
Directory | /workspace/44.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/44.otp_ctrl_smoke.4233277440 |
Short name | T818 |
Test name | |
Test status | |
Simulation time | 266236380 ps |
CPU time | 9.89 seconds |
Started | Mar 31 03:31:42 PM PDT 24 |
Finished | Mar 31 03:31:52 PM PDT 24 |
Peak memory | 241964 kb |
Host | smart-5b18d0d4-e9ad-469f-b2bd-97abd89a55d6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4233277440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.4233277440 |
Directory | /workspace/44.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/44.otp_ctrl_stress_all.7609605 |
Short name | T782 |
Test name | |
Test status | |
Simulation time | 28167105253 ps |
CPU time | 152.99 seconds |
Started | Mar 31 03:31:48 PM PDT 24 |
Finished | Mar 31 03:34:21 PM PDT 24 |
Peak memory | 265144 kb |
Host | smart-7cece695-8a32-4ce4-8155-456da5ce8106 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7609605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_a ll_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all.7609605 |
Directory | /workspace/44.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/44.otp_ctrl_stress_all_with_rand_reset.4263817043 |
Short name | T1101 |
Test name | |
Test status | |
Simulation time | 33598331707 ps |
CPU time | 242.03 seconds |
Started | Mar 31 03:31:42 PM PDT 24 |
Finished | Mar 31 03:35:45 PM PDT 24 |
Peak memory | 273372 kb |
Host | smart-ad23514b-36e2-4000-8c00-f6867b8a195f |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263817043 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all_with_rand_reset.4263817043 |
Directory | /workspace/44.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/44.otp_ctrl_test_access.3147760637 |
Short name | T566 |
Test name | |
Test status | |
Simulation time | 555075608 ps |
CPU time | 11.25 seconds |
Started | Mar 31 03:31:42 PM PDT 24 |
Finished | Mar 31 03:31:54 PM PDT 24 |
Peak memory | 242360 kb |
Host | smart-62fb7b51-1ce1-4e3f-8084-cf0169652cb4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3147760637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.3147760637 |
Directory | /workspace/44.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/45.otp_ctrl_alert_test.1007907026 |
Short name | T758 |
Test name | |
Test status | |
Simulation time | 585659214 ps |
CPU time | 1.91 seconds |
Started | Mar 31 03:31:48 PM PDT 24 |
Finished | Mar 31 03:31:50 PM PDT 24 |
Peak memory | 240136 kb |
Host | smart-07747ca1-261a-4952-90b4-8488208ab1f7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007907026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.1007907026 |
Directory | /workspace/45.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/45.otp_ctrl_check_fail.1679422688 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 1402852156 ps |
CPU time | 8.17 seconds |
Started | Mar 31 03:31:49 PM PDT 24 |
Finished | Mar 31 03:31:57 PM PDT 24 |
Peak memory | 241940 kb |
Host | smart-1ed14fd4-e8bb-433b-9a97-be380ee353b6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1679422688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.1679422688 |
Directory | /workspace/45.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/45.otp_ctrl_dai_errs.1064633960 |
Short name | T618 |
Test name | |
Test status | |
Simulation time | 4172421334 ps |
CPU time | 38.09 seconds |
Started | Mar 31 03:31:48 PM PDT 24 |
Finished | Mar 31 03:32:26 PM PDT 24 |
Peak memory | 249792 kb |
Host | smart-bec038a5-51b3-46fd-b6e9-c1d3ebdff493 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1064633960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_errs.1064633960 |
Directory | /workspace/45.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/45.otp_ctrl_dai_lock.75439348 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 349606888 ps |
CPU time | 9.59 seconds |
Started | Mar 31 03:31:48 PM PDT 24 |
Finished | Mar 31 03:31:59 PM PDT 24 |
Peak memory | 241948 kb |
Host | smart-0a4f0f2f-6aed-421e-9438-2da530cf71bf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=75439348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.75439348 |
Directory | /workspace/45.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/45.otp_ctrl_init_fail.3025358131 |
Short name | T704 |
Test name | |
Test status | |
Simulation time | 2356643650 ps |
CPU time | 5.34 seconds |
Started | Mar 31 03:31:46 PM PDT 24 |
Finished | Mar 31 03:31:52 PM PDT 24 |
Peak memory | 241812 kb |
Host | smart-a469568e-518d-4d9e-97e3-00b98a93649a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3025358131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.3025358131 |
Directory | /workspace/45.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/45.otp_ctrl_macro_errs.1666303478 |
Short name | T912 |
Test name | |
Test status | |
Simulation time | 1066733407 ps |
CPU time | 14.05 seconds |
Started | Mar 31 03:31:47 PM PDT 24 |
Finished | Mar 31 03:32:02 PM PDT 24 |
Peak memory | 244796 kb |
Host | smart-d195f19a-a0a1-4ceb-940f-7255e77708eb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1666303478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.1666303478 |
Directory | /workspace/45.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/45.otp_ctrl_parallel_key_req.3404448651 |
Short name | T874 |
Test name | |
Test status | |
Simulation time | 4006264309 ps |
CPU time | 30.34 seconds |
Started | Mar 31 03:31:48 PM PDT 24 |
Finished | Mar 31 03:32:18 PM PDT 24 |
Peak memory | 242324 kb |
Host | smart-344754da-2da3-417d-9037-d24aae3af0e7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3404448651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_key_req.3404448651 |
Directory | /workspace/45.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/45.otp_ctrl_parallel_lc_esc.399457926 |
Short name | T709 |
Test name | |
Test status | |
Simulation time | 419600049 ps |
CPU time | 4.87 seconds |
Started | Mar 31 03:31:47 PM PDT 24 |
Finished | Mar 31 03:31:53 PM PDT 24 |
Peak memory | 241756 kb |
Host | smart-bb046486-0dd1-4829-afe9-7dfed52d71d1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=399457926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.399457926 |
Directory | /workspace/45.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/45.otp_ctrl_parallel_lc_req.1927913227 |
Short name | T612 |
Test name | |
Test status | |
Simulation time | 1894742816 ps |
CPU time | 19.82 seconds |
Started | Mar 31 03:31:48 PM PDT 24 |
Finished | Mar 31 03:32:09 PM PDT 24 |
Peak memory | 241616 kb |
Host | smart-dce48763-ddc2-42f8-afb1-68eedb7d844b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1927913227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.1927913227 |
Directory | /workspace/45.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/45.otp_ctrl_smoke.2032819188 |
Short name | T900 |
Test name | |
Test status | |
Simulation time | 2236995272 ps |
CPU time | 4.58 seconds |
Started | Mar 31 03:31:49 PM PDT 24 |
Finished | Mar 31 03:31:54 PM PDT 24 |
Peak memory | 241720 kb |
Host | smart-d45be168-0207-4f9a-b791-2e815bd94bed |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2032819188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_smoke.2032819188 |
Directory | /workspace/45.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/45.otp_ctrl_stress_all_with_rand_reset.2913676843 |
Short name | T740 |
Test name | |
Test status | |
Simulation time | 971824282299 ps |
CPU time | 2056.81 seconds |
Started | Mar 31 03:31:53 PM PDT 24 |
Finished | Mar 31 04:06:11 PM PDT 24 |
Peak memory | 375332 kb |
Host | smart-d00d26d0-4d6d-44c4-bf2c-4892fde61b53 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913676843 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all_with_rand_reset.2913676843 |
Directory | /workspace/45.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/45.otp_ctrl_test_access.1688473242 |
Short name | T786 |
Test name | |
Test status | |
Simulation time | 1020930974 ps |
CPU time | 8.42 seconds |
Started | Mar 31 03:31:48 PM PDT 24 |
Finished | Mar 31 03:31:57 PM PDT 24 |
Peak memory | 241704 kb |
Host | smart-2d65b6b6-52ce-4813-836b-69c946b3be0a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1688473242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.1688473242 |
Directory | /workspace/45.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/46.otp_ctrl_alert_test.3673797165 |
Short name | T608 |
Test name | |
Test status | |
Simulation time | 209141538 ps |
CPU time | 1.81 seconds |
Started | Mar 31 03:31:54 PM PDT 24 |
Finished | Mar 31 03:31:57 PM PDT 24 |
Peak memory | 240004 kb |
Host | smart-062e38ed-5e05-4eb4-8699-4a99f0d26de5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673797165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.3673797165 |
Directory | /workspace/46.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/46.otp_ctrl_check_fail.1714622962 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 517068201 ps |
CPU time | 18.99 seconds |
Started | Mar 31 03:31:54 PM PDT 24 |
Finished | Mar 31 03:32:13 PM PDT 24 |
Peak memory | 242824 kb |
Host | smart-bd0ac6f2-4358-44be-9e02-dbd834345ef6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1714622962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.1714622962 |
Directory | /workspace/46.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/46.otp_ctrl_dai_errs.3517967989 |
Short name | T656 |
Test name | |
Test status | |
Simulation time | 4502813009 ps |
CPU time | 31.53 seconds |
Started | Mar 31 03:31:48 PM PDT 24 |
Finished | Mar 31 03:32:20 PM PDT 24 |
Peak memory | 247744 kb |
Host | smart-4c13d591-2c82-490e-a551-9ac41a83fdb9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3517967989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.3517967989 |
Directory | /workspace/46.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/46.otp_ctrl_dai_lock.4294580538 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 353924911 ps |
CPU time | 7.09 seconds |
Started | Mar 31 03:31:47 PM PDT 24 |
Finished | Mar 31 03:31:54 PM PDT 24 |
Peak memory | 242060 kb |
Host | smart-c6ea7275-d0dc-4515-9d45-d1923b3e0db9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4294580538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.4294580538 |
Directory | /workspace/46.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/46.otp_ctrl_init_fail.2182585576 |
Short name | T1130 |
Test name | |
Test status | |
Simulation time | 121357881 ps |
CPU time | 3.7 seconds |
Started | Mar 31 03:31:51 PM PDT 24 |
Finished | Mar 31 03:31:56 PM PDT 24 |
Peak memory | 241952 kb |
Host | smart-6ddbb365-c21d-47d9-a81d-bf22bb0986e6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2182585576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.2182585576 |
Directory | /workspace/46.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/46.otp_ctrl_macro_errs.513122333 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 3492226606 ps |
CPU time | 21.42 seconds |
Started | Mar 31 03:31:55 PM PDT 24 |
Finished | Mar 31 03:32:17 PM PDT 24 |
Peak memory | 241944 kb |
Host | smart-abe0d511-058d-4bdd-8932-6f1c02cefe30 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=513122333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_macro_errs.513122333 |
Directory | /workspace/46.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/46.otp_ctrl_parallel_key_req.1849475055 |
Short name | T879 |
Test name | |
Test status | |
Simulation time | 2138917132 ps |
CPU time | 23.96 seconds |
Started | Mar 31 03:31:55 PM PDT 24 |
Finished | Mar 31 03:32:19 PM PDT 24 |
Peak memory | 241708 kb |
Host | smart-9290574c-adb9-4c9a-9648-94480b4efc37 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1849475055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_key_req.1849475055 |
Directory | /workspace/46.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/46.otp_ctrl_parallel_lc_esc.2147171987 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 294978206 ps |
CPU time | 6.14 seconds |
Started | Mar 31 03:31:47 PM PDT 24 |
Finished | Mar 31 03:31:54 PM PDT 24 |
Peak memory | 241452 kb |
Host | smart-6a5e1d81-7126-445e-8334-7d0437210f26 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2147171987 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.2147171987 |
Directory | /workspace/46.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/46.otp_ctrl_parallel_lc_req.1270111121 |
Short name | T663 |
Test name | |
Test status | |
Simulation time | 10926559401 ps |
CPU time | 26.91 seconds |
Started | Mar 31 03:31:55 PM PDT 24 |
Finished | Mar 31 03:32:22 PM PDT 24 |
Peak memory | 241692 kb |
Host | smart-53568ac3-7cdd-437c-ad6b-971bdf4e439d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1270111121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.1270111121 |
Directory | /workspace/46.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/46.otp_ctrl_regwen.711753630 |
Short name | T943 |
Test name | |
Test status | |
Simulation time | 250649815 ps |
CPU time | 4.09 seconds |
Started | Mar 31 03:31:53 PM PDT 24 |
Finished | Mar 31 03:31:58 PM PDT 24 |
Peak memory | 241724 kb |
Host | smart-78d163ed-4d18-470c-bae0-95acf779a447 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=711753630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.711753630 |
Directory | /workspace/46.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/46.otp_ctrl_smoke.4165796311 |
Short name | T794 |
Test name | |
Test status | |
Simulation time | 275855431 ps |
CPU time | 5.56 seconds |
Started | Mar 31 03:31:51 PM PDT 24 |
Finished | Mar 31 03:31:58 PM PDT 24 |
Peak memory | 241580 kb |
Host | smart-fd4e8a2a-e5b9-4b5d-8c35-4967bacc2494 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4165796311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_smoke.4165796311 |
Directory | /workspace/46.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/46.otp_ctrl_stress_all_with_rand_reset.4128314886 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 155559464412 ps |
CPU time | 2331.08 seconds |
Started | Mar 31 03:31:54 PM PDT 24 |
Finished | Mar 31 04:10:46 PM PDT 24 |
Peak memory | 605488 kb |
Host | smart-2531c6a1-0f21-41bb-b724-32d380e16c41 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128314886 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all_with_rand_reset.4128314886 |
Directory | /workspace/46.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/46.otp_ctrl_test_access.124054297 |
Short name | T450 |
Test name | |
Test status | |
Simulation time | 331068463 ps |
CPU time | 5.41 seconds |
Started | Mar 31 03:31:55 PM PDT 24 |
Finished | Mar 31 03:32:01 PM PDT 24 |
Peak memory | 241744 kb |
Host | smart-1da961ad-6d7f-41c1-8de3-c3a258931bfe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=124054297 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.124054297 |
Directory | /workspace/46.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/47.otp_ctrl_alert_test.962815441 |
Short name | T1054 |
Test name | |
Test status | |
Simulation time | 122538944 ps |
CPU time | 1.92 seconds |
Started | Mar 31 03:32:00 PM PDT 24 |
Finished | Mar 31 03:32:02 PM PDT 24 |
Peak memory | 240024 kb |
Host | smart-8423bb31-4b5d-42a1-b7e5-4541ddb8c7d3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962815441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.962815441 |
Directory | /workspace/47.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/47.otp_ctrl_check_fail.3718922581 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 596283633 ps |
CPU time | 14.37 seconds |
Started | Mar 31 03:31:56 PM PDT 24 |
Finished | Mar 31 03:32:11 PM PDT 24 |
Peak memory | 241948 kb |
Host | smart-e960b44a-e7f1-4f0e-97ae-0d5acc513802 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3718922581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_check_fail.3718922581 |
Directory | /workspace/47.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/47.otp_ctrl_dai_errs.3968829800 |
Short name | T815 |
Test name | |
Test status | |
Simulation time | 516562859 ps |
CPU time | 14.12 seconds |
Started | Mar 31 03:31:53 PM PDT 24 |
Finished | Mar 31 03:32:08 PM PDT 24 |
Peak memory | 241632 kb |
Host | smart-dc1f7894-4503-4637-88fa-c3fa34c37ff3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3968829800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_errs.3968829800 |
Directory | /workspace/47.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/47.otp_ctrl_dai_lock.92429476 |
Short name | T910 |
Test name | |
Test status | |
Simulation time | 2392453657 ps |
CPU time | 24.91 seconds |
Started | Mar 31 03:31:54 PM PDT 24 |
Finished | Mar 31 03:32:20 PM PDT 24 |
Peak memory | 242136 kb |
Host | smart-208e0fca-e5c6-44b5-afd4-bcbfdd269aca |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=92429476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_lock.92429476 |
Directory | /workspace/47.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/47.otp_ctrl_init_fail.4118067608 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 1543951213 ps |
CPU time | 4.97 seconds |
Started | Mar 31 03:31:55 PM PDT 24 |
Finished | Mar 31 03:32:00 PM PDT 24 |
Peak memory | 241780 kb |
Host | smart-be0209f8-76c2-4506-af60-52d77ead0271 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4118067608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.4118067608 |
Directory | /workspace/47.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/47.otp_ctrl_macro_errs.883495692 |
Short name | T1109 |
Test name | |
Test status | |
Simulation time | 15483875009 ps |
CPU time | 29.56 seconds |
Started | Mar 31 03:31:55 PM PDT 24 |
Finished | Mar 31 03:32:25 PM PDT 24 |
Peak memory | 246248 kb |
Host | smart-c66f6864-0f26-48a5-89e4-627114e6d1cb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=883495692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_macro_errs.883495692 |
Directory | /workspace/47.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/47.otp_ctrl_parallel_key_req.1254988047 |
Short name | T601 |
Test name | |
Test status | |
Simulation time | 326201818 ps |
CPU time | 11.89 seconds |
Started | Mar 31 03:32:00 PM PDT 24 |
Finished | Mar 31 03:32:11 PM PDT 24 |
Peak memory | 248496 kb |
Host | smart-06ac608e-b62a-4556-981e-d9635ad87478 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1254988047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.1254988047 |
Directory | /workspace/47.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/47.otp_ctrl_parallel_lc_esc.2340656113 |
Short name | T775 |
Test name | |
Test status | |
Simulation time | 206085388 ps |
CPU time | 5.87 seconds |
Started | Mar 31 03:31:53 PM PDT 24 |
Finished | Mar 31 03:31:59 PM PDT 24 |
Peak memory | 241608 kb |
Host | smart-a655db2d-435a-4479-85b2-700c49141f35 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2340656113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.2340656113 |
Directory | /workspace/47.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/47.otp_ctrl_parallel_lc_req.2364204307 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 2186034862 ps |
CPU time | 30 seconds |
Started | Mar 31 03:31:54 PM PDT 24 |
Finished | Mar 31 03:32:25 PM PDT 24 |
Peak memory | 242012 kb |
Host | smart-46e06fa5-81f3-4f03-8f60-d2ba0e6f4748 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2364204307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.2364204307 |
Directory | /workspace/47.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/47.otp_ctrl_regwen.2264591273 |
Short name | T732 |
Test name | |
Test status | |
Simulation time | 170332452 ps |
CPU time | 5.71 seconds |
Started | Mar 31 03:32:00 PM PDT 24 |
Finished | Mar 31 03:32:06 PM PDT 24 |
Peak memory | 242000 kb |
Host | smart-28e08734-8208-4ae2-a366-739a8729709d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2264591273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.2264591273 |
Directory | /workspace/47.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/47.otp_ctrl_smoke.3431739932 |
Short name | T803 |
Test name | |
Test status | |
Simulation time | 166626925 ps |
CPU time | 4.44 seconds |
Started | Mar 31 03:31:54 PM PDT 24 |
Finished | Mar 31 03:31:58 PM PDT 24 |
Peak memory | 241924 kb |
Host | smart-c6e91c76-2223-4f72-abd0-d371b5ca2a07 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3431739932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_smoke.3431739932 |
Directory | /workspace/47.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/47.otp_ctrl_stress_all.3717191385 |
Short name | T1131 |
Test name | |
Test status | |
Simulation time | 11172250602 ps |
CPU time | 76.17 seconds |
Started | Mar 31 03:32:04 PM PDT 24 |
Finished | Mar 31 03:33:20 PM PDT 24 |
Peak memory | 246224 kb |
Host | smart-643d2341-d6f1-4fa7-ac3c-db1ffe14e528 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717191385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all .3717191385 |
Directory | /workspace/47.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/47.otp_ctrl_stress_all_with_rand_reset.3288590253 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 63384550369 ps |
CPU time | 840.15 seconds |
Started | Mar 31 03:32:07 PM PDT 24 |
Finished | Mar 31 03:46:07 PM PDT 24 |
Peak memory | 274324 kb |
Host | smart-cefd1a6c-8be8-445c-950f-5b50140592e8 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288590253 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all_with_rand_reset.3288590253 |
Directory | /workspace/47.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/47.otp_ctrl_test_access.2533160797 |
Short name | T852 |
Test name | |
Test status | |
Simulation time | 1112105512 ps |
CPU time | 17.7 seconds |
Started | Mar 31 03:32:02 PM PDT 24 |
Finished | Mar 31 03:32:20 PM PDT 24 |
Peak memory | 241948 kb |
Host | smart-96a17778-88a0-4b69-bc79-8033e47e41fb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2533160797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_test_access.2533160797 |
Directory | /workspace/47.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/48.otp_ctrl_alert_test.1099973611 |
Short name | T985 |
Test name | |
Test status | |
Simulation time | 103297880 ps |
CPU time | 1.72 seconds |
Started | Mar 31 03:31:59 PM PDT 24 |
Finished | Mar 31 03:32:01 PM PDT 24 |
Peak memory | 240176 kb |
Host | smart-2e809430-efe8-41a5-b0ef-d51ab25c8e8c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099973611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.1099973611 |
Directory | /workspace/48.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/48.otp_ctrl_dai_errs.4023960220 |
Short name | T597 |
Test name | |
Test status | |
Simulation time | 937407509 ps |
CPU time | 25.5 seconds |
Started | Mar 31 03:32:05 PM PDT 24 |
Finished | Mar 31 03:32:31 PM PDT 24 |
Peak memory | 241476 kb |
Host | smart-f30f82dd-4bb8-4b3d-942e-ee73f954a1b9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4023960220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.4023960220 |
Directory | /workspace/48.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/48.otp_ctrl_dai_lock.2465494811 |
Short name | T1004 |
Test name | |
Test status | |
Simulation time | 329528676 ps |
CPU time | 11.79 seconds |
Started | Mar 31 03:31:59 PM PDT 24 |
Finished | Mar 31 03:32:10 PM PDT 24 |
Peak memory | 242236 kb |
Host | smart-c7c2ff5c-d07c-43f0-97f5-d9099548e9e5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2465494811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.2465494811 |
Directory | /workspace/48.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/48.otp_ctrl_init_fail.1785769056 |
Short name | T846 |
Test name | |
Test status | |
Simulation time | 2381949898 ps |
CPU time | 5.25 seconds |
Started | Mar 31 03:32:04 PM PDT 24 |
Finished | Mar 31 03:32:09 PM PDT 24 |
Peak memory | 242088 kb |
Host | smart-b87cd86e-7a4c-4b3e-aced-d632456afe4a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1785769056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.1785769056 |
Directory | /workspace/48.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/48.otp_ctrl_macro_errs.1234152086 |
Short name | T1094 |
Test name | |
Test status | |
Simulation time | 5566591848 ps |
CPU time | 25.71 seconds |
Started | Mar 31 03:32:03 PM PDT 24 |
Finished | Mar 31 03:32:29 PM PDT 24 |
Peak memory | 243664 kb |
Host | smart-8ce27ea4-6a12-48fc-9a2a-3e48bdce3126 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1234152086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_macro_errs.1234152086 |
Directory | /workspace/48.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/48.otp_ctrl_parallel_key_req.3616774633 |
Short name | T764 |
Test name | |
Test status | |
Simulation time | 16331776320 ps |
CPU time | 30.8 seconds |
Started | Mar 31 03:32:07 PM PDT 24 |
Finished | Mar 31 03:32:38 PM PDT 24 |
Peak memory | 242468 kb |
Host | smart-6da7aeef-e419-4d10-9261-fee7bd2ad32e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3616774633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_key_req.3616774633 |
Directory | /workspace/48.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/48.otp_ctrl_parallel_lc_esc.3482908353 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 370423434 ps |
CPU time | 9.74 seconds |
Started | Mar 31 03:32:00 PM PDT 24 |
Finished | Mar 31 03:32:10 PM PDT 24 |
Peak memory | 241960 kb |
Host | smart-32349939-8458-4e29-8103-31d2c8054915 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3482908353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.3482908353 |
Directory | /workspace/48.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/48.otp_ctrl_parallel_lc_req.3530214120 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 2336416202 ps |
CPU time | 23.09 seconds |
Started | Mar 31 03:32:03 PM PDT 24 |
Finished | Mar 31 03:32:26 PM PDT 24 |
Peak memory | 242020 kb |
Host | smart-11bdb183-868a-47ac-b835-77d73262df06 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3530214120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.3530214120 |
Directory | /workspace/48.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/48.otp_ctrl_regwen.905483833 |
Short name | T498 |
Test name | |
Test status | |
Simulation time | 252599387 ps |
CPU time | 8.4 seconds |
Started | Mar 31 03:32:02 PM PDT 24 |
Finished | Mar 31 03:32:10 PM PDT 24 |
Peak memory | 241636 kb |
Host | smart-66dc2629-550f-4a52-a0b4-c70b0662673a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=905483833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.905483833 |
Directory | /workspace/48.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/48.otp_ctrl_smoke.115595471 |
Short name | T543 |
Test name | |
Test status | |
Simulation time | 258845923 ps |
CPU time | 8.95 seconds |
Started | Mar 31 03:31:59 PM PDT 24 |
Finished | Mar 31 03:32:08 PM PDT 24 |
Peak memory | 242040 kb |
Host | smart-1ea67fdf-f2a8-4aba-958a-537201d30ce5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=115595471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_smoke.115595471 |
Directory | /workspace/48.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/48.otp_ctrl_stress_all_with_rand_reset.2133925588 |
Short name | T727 |
Test name | |
Test status | |
Simulation time | 99070324714 ps |
CPU time | 554.94 seconds |
Started | Mar 31 03:32:00 PM PDT 24 |
Finished | Mar 31 03:41:16 PM PDT 24 |
Peak memory | 332944 kb |
Host | smart-d2534ed4-410b-47de-bd28-d6b1a374a7ab |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133925588 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all_with_rand_reset.2133925588 |
Directory | /workspace/48.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/48.otp_ctrl_test_access.1817942313 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 1533921627 ps |
CPU time | 10.52 seconds |
Started | Mar 31 03:32:03 PM PDT 24 |
Finished | Mar 31 03:32:14 PM PDT 24 |
Peak memory | 242140 kb |
Host | smart-b379a23c-2389-42b2-a5c3-65bb2238c0fa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1817942313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_test_access.1817942313 |
Directory | /workspace/48.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/49.otp_ctrl_alert_test.1990365704 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 172705371 ps |
CPU time | 1.81 seconds |
Started | Mar 31 03:32:06 PM PDT 24 |
Finished | Mar 31 03:32:08 PM PDT 24 |
Peak memory | 240056 kb |
Host | smart-1b18b1a7-45bd-4b3d-a019-f3a5c1208289 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990365704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.1990365704 |
Directory | /workspace/49.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/49.otp_ctrl_check_fail.1085526652 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 8450055299 ps |
CPU time | 79.38 seconds |
Started | Mar 31 03:32:12 PM PDT 24 |
Finished | Mar 31 03:33:32 PM PDT 24 |
Peak memory | 243492 kb |
Host | smart-9bf11a32-9bad-4669-9323-82f50cfcf7ec |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1085526652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.1085526652 |
Directory | /workspace/49.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/49.otp_ctrl_dai_errs.2852152099 |
Short name | T514 |
Test name | |
Test status | |
Simulation time | 4203877794 ps |
CPU time | 16.93 seconds |
Started | Mar 31 03:32:06 PM PDT 24 |
Finished | Mar 31 03:32:23 PM PDT 24 |
Peak memory | 242224 kb |
Host | smart-96a733b6-add3-4e78-a46c-38cb4a519729 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2852152099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_errs.2852152099 |
Directory | /workspace/49.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/49.otp_ctrl_dai_lock.2498882918 |
Short name | T971 |
Test name | |
Test status | |
Simulation time | 648275065 ps |
CPU time | 4.91 seconds |
Started | Mar 31 03:32:05 PM PDT 24 |
Finished | Mar 31 03:32:11 PM PDT 24 |
Peak memory | 241800 kb |
Host | smart-e4b4a8b1-8ea2-40e0-b528-6f22b474fe91 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2498882918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_lock.2498882918 |
Directory | /workspace/49.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/49.otp_ctrl_init_fail.80240833 |
Short name | T486 |
Test name | |
Test status | |
Simulation time | 1564344033 ps |
CPU time | 4.46 seconds |
Started | Mar 31 03:32:04 PM PDT 24 |
Finished | Mar 31 03:32:08 PM PDT 24 |
Peak memory | 241940 kb |
Host | smart-d84d9913-d7cc-438e-8603-d9149932b6ac |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=80240833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.80240833 |
Directory | /workspace/49.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/49.otp_ctrl_macro_errs.1132849549 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 375704675 ps |
CPU time | 4.92 seconds |
Started | Mar 31 03:32:08 PM PDT 24 |
Finished | Mar 31 03:32:13 PM PDT 24 |
Peak memory | 241772 kb |
Host | smart-4bea3abd-7ee2-443e-9a60-d0ac9268835f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1132849549 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_macro_errs.1132849549 |
Directory | /workspace/49.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/49.otp_ctrl_parallel_key_req.4150904001 |
Short name | T716 |
Test name | |
Test status | |
Simulation time | 1187827874 ps |
CPU time | 10.75 seconds |
Started | Mar 31 03:32:05 PM PDT 24 |
Finished | Mar 31 03:32:16 PM PDT 24 |
Peak memory | 241656 kb |
Host | smart-8cb00e97-eb01-4ced-a037-0a9d2803f37c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4150904001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.4150904001 |
Directory | /workspace/49.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/49.otp_ctrl_parallel_lc_esc.3103163523 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 870169797 ps |
CPU time | 13.04 seconds |
Started | Mar 31 03:32:12 PM PDT 24 |
Finished | Mar 31 03:32:26 PM PDT 24 |
Peak memory | 241988 kb |
Host | smart-7f7fc275-dec1-47a9-a0d7-a9118ecd0b03 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3103163523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.3103163523 |
Directory | /workspace/49.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/49.otp_ctrl_parallel_lc_req.4036363354 |
Short name | T1003 |
Test name | |
Test status | |
Simulation time | 968280799 ps |
CPU time | 15.38 seconds |
Started | Mar 31 03:32:05 PM PDT 24 |
Finished | Mar 31 03:32:20 PM PDT 24 |
Peak memory | 241980 kb |
Host | smart-cafa5e1f-9f6c-4e79-a968-795dd7f044db |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4036363354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_req.4036363354 |
Directory | /workspace/49.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/49.otp_ctrl_regwen.335534904 |
Short name | T811 |
Test name | |
Test status | |
Simulation time | 151546349 ps |
CPU time | 4.64 seconds |
Started | Mar 31 03:32:05 PM PDT 24 |
Finished | Mar 31 03:32:10 PM PDT 24 |
Peak memory | 242012 kb |
Host | smart-4d054e29-3ce8-4efe-bc53-d3d5d6b4ef1a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=335534904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.335534904 |
Directory | /workspace/49.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/49.otp_ctrl_smoke.143279645 |
Short name | T464 |
Test name | |
Test status | |
Simulation time | 391132009 ps |
CPU time | 3.97 seconds |
Started | Mar 31 03:32:00 PM PDT 24 |
Finished | Mar 31 03:32:04 PM PDT 24 |
Peak memory | 241620 kb |
Host | smart-101c0b79-2767-462d-af2a-f101b4a0b197 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=143279645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.143279645 |
Directory | /workspace/49.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/49.otp_ctrl_stress_all.1614099860 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 21827776504 ps |
CPU time | 213.85 seconds |
Started | Mar 31 03:32:09 PM PDT 24 |
Finished | Mar 31 03:35:43 PM PDT 24 |
Peak memory | 257260 kb |
Host | smart-89c35f26-a3f2-4478-a5a6-dda6d5d2c840 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614099860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all .1614099860 |
Directory | /workspace/49.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/49.otp_ctrl_stress_all_with_rand_reset.4272396873 |
Short name | T936 |
Test name | |
Test status | |
Simulation time | 1653042479216 ps |
CPU time | 3722.56 seconds |
Started | Mar 31 03:32:04 PM PDT 24 |
Finished | Mar 31 04:34:07 PM PDT 24 |
Peak memory | 729200 kb |
Host | smart-d887058d-4273-4da2-a702-c3d4b9e31044 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272396873 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all_with_rand_reset.4272396873 |
Directory | /workspace/49.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/49.otp_ctrl_test_access.2166460353 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 1427943187 ps |
CPU time | 13.83 seconds |
Started | Mar 31 03:32:06 PM PDT 24 |
Finished | Mar 31 03:32:20 PM PDT 24 |
Peak memory | 241732 kb |
Host | smart-76ebb344-76a4-491b-91e9-f1d5bda00ba0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2166460353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_test_access.2166460353 |
Directory | /workspace/49.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/5.otp_ctrl_alert_test.3018361772 |
Short name | T521 |
Test name | |
Test status | |
Simulation time | 120829507 ps |
CPU time | 1.79 seconds |
Started | Mar 31 03:28:58 PM PDT 24 |
Finished | Mar 31 03:29:00 PM PDT 24 |
Peak memory | 240156 kb |
Host | smart-cdb76b0e-7338-401c-8ba9-de74ec809cfa |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018361772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.3018361772 |
Directory | /workspace/5.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/5.otp_ctrl_background_chks.3687629828 |
Short name | T829 |
Test name | |
Test status | |
Simulation time | 2934247519 ps |
CPU time | 14.6 seconds |
Started | Mar 31 03:28:58 PM PDT 24 |
Finished | Mar 31 03:29:13 PM PDT 24 |
Peak memory | 242152 kb |
Host | smart-5ffa2ddb-914c-4e25-92d6-7688808e15db |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3687629828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.3687629828 |
Directory | /workspace/5.otp_ctrl_background_chks/latest |
Test location | /workspace/coverage/default/5.otp_ctrl_dai_errs.9904739 |
Short name | T1163 |
Test name | |
Test status | |
Simulation time | 708760294 ps |
CPU time | 19.95 seconds |
Started | Mar 31 03:28:58 PM PDT 24 |
Finished | Mar 31 03:29:18 PM PDT 24 |
Peak memory | 241832 kb |
Host | smart-d90f50ff-a531-4719-ba41-43bed2c1b42f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=9904739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.9904739 |
Directory | /workspace/5.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/5.otp_ctrl_dai_lock.3937648294 |
Short name | T762 |
Test name | |
Test status | |
Simulation time | 1187637064 ps |
CPU time | 7.32 seconds |
Started | Mar 31 03:29:00 PM PDT 24 |
Finished | Mar 31 03:29:07 PM PDT 24 |
Peak memory | 241876 kb |
Host | smart-0d59c42c-a2fd-41db-90f8-d54c01b4f338 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3937648294 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.3937648294 |
Directory | /workspace/5.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/5.otp_ctrl_init_fail.3440919509 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 330735289 ps |
CPU time | 4.21 seconds |
Started | Mar 31 03:28:58 PM PDT 24 |
Finished | Mar 31 03:29:03 PM PDT 24 |
Peak memory | 241640 kb |
Host | smart-b3ec4cf2-5dd7-4dd1-9214-b830011eefe4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3440919509 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.3440919509 |
Directory | /workspace/5.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/5.otp_ctrl_macro_errs.2903546575 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 25364557149 ps |
CPU time | 58.1 seconds |
Started | Mar 31 03:28:59 PM PDT 24 |
Finished | Mar 31 03:29:57 PM PDT 24 |
Peak memory | 257008 kb |
Host | smart-b34555ad-674c-4628-83e2-0bb35b2d4f4f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2903546575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.2903546575 |
Directory | /workspace/5.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/5.otp_ctrl_parallel_key_req.580810713 |
Short name | T647 |
Test name | |
Test status | |
Simulation time | 483993332 ps |
CPU time | 15.55 seconds |
Started | Mar 31 03:28:57 PM PDT 24 |
Finished | Mar 31 03:29:13 PM PDT 24 |
Peak memory | 241952 kb |
Host | smart-4060f5a0-aa48-49d3-89cf-7c62591e67cd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=580810713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.580810713 |
Directory | /workspace/5.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/5.otp_ctrl_parallel_lc_esc.4196225742 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 371545927 ps |
CPU time | 4.62 seconds |
Started | Mar 31 03:28:59 PM PDT 24 |
Finished | Mar 31 03:29:04 PM PDT 24 |
Peak memory | 241588 kb |
Host | smart-60402304-78bf-4d7f-a056-8d892cdcf03f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4196225742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.4196225742 |
Directory | /workspace/5.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/5.otp_ctrl_parallel_lc_req.2311184890 |
Short name | T968 |
Test name | |
Test status | |
Simulation time | 443930717 ps |
CPU time | 14.23 seconds |
Started | Mar 31 03:28:58 PM PDT 24 |
Finished | Mar 31 03:29:13 PM PDT 24 |
Peak memory | 241760 kb |
Host | smart-e510ea59-7030-49c3-b1d0-7b32bf65c02d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2311184890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.2311184890 |
Directory | /workspace/5.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/5.otp_ctrl_regwen.1146717660 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 364135045 ps |
CPU time | 7.79 seconds |
Started | Mar 31 03:29:00 PM PDT 24 |
Finished | Mar 31 03:29:08 PM PDT 24 |
Peak memory | 241708 kb |
Host | smart-7cfeccb4-bffa-488f-972c-781b272e21b1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1146717660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.1146717660 |
Directory | /workspace/5.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/5.otp_ctrl_smoke.4294855905 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 252108891 ps |
CPU time | 5.61 seconds |
Started | Mar 31 03:28:57 PM PDT 24 |
Finished | Mar 31 03:29:03 PM PDT 24 |
Peak memory | 241648 kb |
Host | smart-0a2c3032-2b87-4ada-8b74-bfc6198eb73c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4294855905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.4294855905 |
Directory | /workspace/5.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/5.otp_ctrl_stress_all.2879932247 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 1198524934 ps |
CPU time | 14.71 seconds |
Started | Mar 31 03:28:58 PM PDT 24 |
Finished | Mar 31 03:29:13 PM PDT 24 |
Peak memory | 248704 kb |
Host | smart-299db32e-16fe-4905-a67b-c77840d15033 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879932247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all. 2879932247 |
Directory | /workspace/5.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/5.otp_ctrl_stress_all_with_rand_reset.3780715905 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 97527475179 ps |
CPU time | 848.45 seconds |
Started | Mar 31 03:29:00 PM PDT 24 |
Finished | Mar 31 03:43:10 PM PDT 24 |
Peak memory | 369200 kb |
Host | smart-1561d48e-1437-4cb4-9d2a-66db585b5842 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780715905 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all_with_rand_reset.3780715905 |
Directory | /workspace/5.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/5.otp_ctrl_test_access.3912374069 |
Short name | T728 |
Test name | |
Test status | |
Simulation time | 244245668 ps |
CPU time | 5.54 seconds |
Started | Mar 31 03:28:57 PM PDT 24 |
Finished | Mar 31 03:29:03 PM PDT 24 |
Peak memory | 241780 kb |
Host | smart-50921752-0445-4bed-ab90-581e30bae754 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3912374069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.3912374069 |
Directory | /workspace/5.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/50.otp_ctrl_init_fail.3543046191 |
Short name | T1139 |
Test name | |
Test status | |
Simulation time | 117098568 ps |
CPU time | 4.27 seconds |
Started | Mar 31 03:32:09 PM PDT 24 |
Finished | Mar 31 03:32:14 PM PDT 24 |
Peak memory | 242048 kb |
Host | smart-bfefb878-511c-4e79-89e9-ff521a97aa34 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3543046191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.3543046191 |
Directory | /workspace/50.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/50.otp_ctrl_parallel_lc_esc.240250899 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 1628051971 ps |
CPU time | 11.56 seconds |
Started | Mar 31 03:32:08 PM PDT 24 |
Finished | Mar 31 03:32:20 PM PDT 24 |
Peak memory | 241868 kb |
Host | smart-38674ce0-feff-4641-83e7-170f3d51182a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=240250899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.240250899 |
Directory | /workspace/50.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/50.otp_ctrl_stress_all_with_rand_reset.3238537276 |
Short name | T628 |
Test name | |
Test status | |
Simulation time | 22602256531 ps |
CPU time | 641.16 seconds |
Started | Mar 31 03:32:10 PM PDT 24 |
Finished | Mar 31 03:42:51 PM PDT 24 |
Peak memory | 256824 kb |
Host | smart-d4b49097-fbc0-4921-8901-447320fee6c6 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238537276 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_stress_all_with_rand_reset.3238537276 |
Directory | /workspace/50.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/51.otp_ctrl_init_fail.797055939 |
Short name | T717 |
Test name | |
Test status | |
Simulation time | 235098515 ps |
CPU time | 3.9 seconds |
Started | Mar 31 03:32:10 PM PDT 24 |
Finished | Mar 31 03:32:14 PM PDT 24 |
Peak memory | 241612 kb |
Host | smart-19593f52-b8f6-434a-884a-28cc262e2ed1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=797055939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.797055939 |
Directory | /workspace/51.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/51.otp_ctrl_parallel_lc_esc.2642884745 |
Short name | T610 |
Test name | |
Test status | |
Simulation time | 2250003627 ps |
CPU time | 14.18 seconds |
Started | Mar 31 03:32:05 PM PDT 24 |
Finished | Mar 31 03:32:19 PM PDT 24 |
Peak memory | 242076 kb |
Host | smart-5ec52fa1-2292-40ce-a6d1-cbd0542e718c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2642884745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.2642884745 |
Directory | /workspace/51.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/51.otp_ctrl_stress_all_with_rand_reset.1331682626 |
Short name | T947 |
Test name | |
Test status | |
Simulation time | 79526118774 ps |
CPU time | 915.26 seconds |
Started | Mar 31 03:32:09 PM PDT 24 |
Finished | Mar 31 03:47:25 PM PDT 24 |
Peak memory | 347084 kb |
Host | smart-36444058-7749-4f47-ae20-ad2648caf59a |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331682626 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_stress_all_with_rand_reset.1331682626 |
Directory | /workspace/51.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/52.otp_ctrl_init_fail.3901775408 |
Short name | T757 |
Test name | |
Test status | |
Simulation time | 167526048 ps |
CPU time | 4.08 seconds |
Started | Mar 31 03:32:04 PM PDT 24 |
Finished | Mar 31 03:32:09 PM PDT 24 |
Peak memory | 241648 kb |
Host | smart-83070eb7-e29a-4b6c-9b67-37e6ec4cb609 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3901775408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.3901775408 |
Directory | /workspace/52.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/52.otp_ctrl_parallel_lc_esc.838537585 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 107951580 ps |
CPU time | 4.54 seconds |
Started | Mar 31 03:32:12 PM PDT 24 |
Finished | Mar 31 03:32:17 PM PDT 24 |
Peak memory | 241812 kb |
Host | smart-211b6300-4e1f-4850-b604-e5d74d4adc0c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=838537585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.838537585 |
Directory | /workspace/52.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/53.otp_ctrl_init_fail.170757418 |
Short name | T957 |
Test name | |
Test status | |
Simulation time | 1756486622 ps |
CPU time | 3.95 seconds |
Started | Mar 31 03:32:13 PM PDT 24 |
Finished | Mar 31 03:32:17 PM PDT 24 |
Peak memory | 241748 kb |
Host | smart-ecf796c7-d591-4f5b-93e4-138110902232 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=170757418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.170757418 |
Directory | /workspace/53.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/53.otp_ctrl_parallel_lc_esc.2937787382 |
Short name | T1009 |
Test name | |
Test status | |
Simulation time | 222616215 ps |
CPU time | 4.38 seconds |
Started | Mar 31 03:32:16 PM PDT 24 |
Finished | Mar 31 03:32:20 PM PDT 24 |
Peak memory | 241604 kb |
Host | smart-7abaa74f-81b2-4749-ae46-4a7b4c8c4ce5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2937787382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.2937787382 |
Directory | /workspace/53.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/53.otp_ctrl_stress_all_with_rand_reset.1048801447 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 381234229670 ps |
CPU time | 503.33 seconds |
Started | Mar 31 03:32:12 PM PDT 24 |
Finished | Mar 31 03:40:36 PM PDT 24 |
Peak memory | 264684 kb |
Host | smart-7e4d14b2-8870-420e-83d0-5e9bc2a5317d |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048801447 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_stress_all_with_rand_reset.1048801447 |
Directory | /workspace/53.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/54.otp_ctrl_init_fail.3218213336 |
Short name | T790 |
Test name | |
Test status | |
Simulation time | 1687313711 ps |
CPU time | 5.62 seconds |
Started | Mar 31 03:32:12 PM PDT 24 |
Finished | Mar 31 03:32:17 PM PDT 24 |
Peak memory | 241680 kb |
Host | smart-077e9428-40d8-41aa-ba32-c2f6db73e200 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3218213336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.3218213336 |
Directory | /workspace/54.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/54.otp_ctrl_parallel_lc_esc.3625249473 |
Short name | T1118 |
Test name | |
Test status | |
Simulation time | 1972193720 ps |
CPU time | 5.62 seconds |
Started | Mar 31 03:32:12 PM PDT 24 |
Finished | Mar 31 03:32:18 PM PDT 24 |
Peak memory | 241608 kb |
Host | smart-2342ec8d-c9de-4b91-b9d3-56089ccb035f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3625249473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.3625249473 |
Directory | /workspace/54.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/54.otp_ctrl_stress_all_with_rand_reset.3639535380 |
Short name | T823 |
Test name | |
Test status | |
Simulation time | 220858839098 ps |
CPU time | 493.3 seconds |
Started | Mar 31 03:32:14 PM PDT 24 |
Finished | Mar 31 03:40:27 PM PDT 24 |
Peak memory | 313584 kb |
Host | smart-013cf656-2a64-4104-93fa-68c1d9186ca6 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639535380 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_stress_all_with_rand_reset.3639535380 |
Directory | /workspace/54.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/55.otp_ctrl_init_fail.3506132944 |
Short name | T1132 |
Test name | |
Test status | |
Simulation time | 2188466662 ps |
CPU time | 4.33 seconds |
Started | Mar 31 03:32:11 PM PDT 24 |
Finished | Mar 31 03:32:16 PM PDT 24 |
Peak memory | 241868 kb |
Host | smart-3d0ff8a5-7187-4faa-8906-b63566cf3dd0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3506132944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.3506132944 |
Directory | /workspace/55.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/55.otp_ctrl_parallel_lc_esc.4074761222 |
Short name | T538 |
Test name | |
Test status | |
Simulation time | 463671830 ps |
CPU time | 7.28 seconds |
Started | Mar 31 03:32:13 PM PDT 24 |
Finished | Mar 31 03:32:21 PM PDT 24 |
Peak memory | 241660 kb |
Host | smart-d5ab9950-5042-4d63-9dc7-5e8f8f6a651b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4074761222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.4074761222 |
Directory | /workspace/55.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/55.otp_ctrl_stress_all_with_rand_reset.2423348589 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 87410372058 ps |
CPU time | 984.99 seconds |
Started | Mar 31 03:32:12 PM PDT 24 |
Finished | Mar 31 03:48:38 PM PDT 24 |
Peak memory | 342996 kb |
Host | smart-768a5fb2-7677-47ad-979c-befe97d79379 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423348589 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_stress_all_with_rand_reset.2423348589 |
Directory | /workspace/55.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/56.otp_ctrl_init_fail.1027384806 |
Short name | T743 |
Test name | |
Test status | |
Simulation time | 112421334 ps |
CPU time | 4.24 seconds |
Started | Mar 31 03:32:13 PM PDT 24 |
Finished | Mar 31 03:32:17 PM PDT 24 |
Peak memory | 241744 kb |
Host | smart-fef93f7d-0137-4e92-b38b-384732718874 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1027384806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.1027384806 |
Directory | /workspace/56.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/56.otp_ctrl_parallel_lc_esc.275360422 |
Short name | T1166 |
Test name | |
Test status | |
Simulation time | 6788708619 ps |
CPU time | 15.96 seconds |
Started | Mar 31 03:32:13 PM PDT 24 |
Finished | Mar 31 03:32:29 PM PDT 24 |
Peak memory | 241672 kb |
Host | smart-39552ffb-3c98-40be-ad68-324d57ba62bb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=275360422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.275360422 |
Directory | /workspace/56.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/56.otp_ctrl_stress_all_with_rand_reset.199937479 |
Short name | T1064 |
Test name | |
Test status | |
Simulation time | 40042126188 ps |
CPU time | 919.17 seconds |
Started | Mar 31 03:32:14 PM PDT 24 |
Finished | Mar 31 03:47:33 PM PDT 24 |
Peak memory | 284476 kb |
Host | smart-e1f91245-3156-4c02-af86-c44de6a26031 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199937479 -assert nopo stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_stress_all_with_rand_reset.199937479 |
Directory | /workspace/56.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/57.otp_ctrl_init_fail.3371600290 |
Short name | T1140 |
Test name | |
Test status | |
Simulation time | 144702465 ps |
CPU time | 3.41 seconds |
Started | Mar 31 03:32:12 PM PDT 24 |
Finished | Mar 31 03:32:16 PM PDT 24 |
Peak memory | 241708 kb |
Host | smart-be5ae0ea-ce59-401a-bfa2-d92cb76a055d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3371600290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.3371600290 |
Directory | /workspace/57.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/57.otp_ctrl_parallel_lc_esc.1954945683 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 703918291 ps |
CPU time | 13.58 seconds |
Started | Mar 31 03:32:14 PM PDT 24 |
Finished | Mar 31 03:32:28 PM PDT 24 |
Peak memory | 241808 kb |
Host | smart-0cbcca40-2555-404b-ab9d-d4131b2f1ae6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1954945683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.1954945683 |
Directory | /workspace/57.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/58.otp_ctrl_init_fail.697649074 |
Short name | T678 |
Test name | |
Test status | |
Simulation time | 249393468 ps |
CPU time | 4.06 seconds |
Started | Mar 31 03:32:13 PM PDT 24 |
Finished | Mar 31 03:32:17 PM PDT 24 |
Peak memory | 241716 kb |
Host | smart-fe6b9652-72e7-4d39-a488-2e760e96fd99 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=697649074 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.697649074 |
Directory | /workspace/58.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/58.otp_ctrl_parallel_lc_esc.3028603999 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 141969034 ps |
CPU time | 7.22 seconds |
Started | Mar 31 03:32:16 PM PDT 24 |
Finished | Mar 31 03:32:23 PM PDT 24 |
Peak memory | 241616 kb |
Host | smart-a8726a8f-8bcc-4c7c-806e-1a6a05a52fee |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3028603999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.3028603999 |
Directory | /workspace/58.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/58.otp_ctrl_stress_all_with_rand_reset.4097710240 |
Short name | T756 |
Test name | |
Test status | |
Simulation time | 154411190255 ps |
CPU time | 1374.17 seconds |
Started | Mar 31 03:32:14 PM PDT 24 |
Finished | Mar 31 03:55:08 PM PDT 24 |
Peak memory | 312036 kb |
Host | smart-89bcb98f-f48b-409a-82eb-d5b3dc8b276a |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097710240 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_stress_all_with_rand_reset.4097710240 |
Directory | /workspace/58.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/59.otp_ctrl_init_fail.4024016528 |
Short name | T600 |
Test name | |
Test status | |
Simulation time | 91587619 ps |
CPU time | 3.8 seconds |
Started | Mar 31 03:32:17 PM PDT 24 |
Finished | Mar 31 03:32:22 PM PDT 24 |
Peak memory | 241636 kb |
Host | smart-879236cf-3c69-40e5-b039-720ca773424d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4024016528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.4024016528 |
Directory | /workspace/59.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/59.otp_ctrl_parallel_lc_esc.1803753760 |
Short name | T870 |
Test name | |
Test status | |
Simulation time | 2871719452 ps |
CPU time | 20.95 seconds |
Started | Mar 31 03:32:16 PM PDT 24 |
Finished | Mar 31 03:32:37 PM PDT 24 |
Peak memory | 241816 kb |
Host | smart-5b888062-9efe-4bab-a07e-206f93392d38 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1803753760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.1803753760 |
Directory | /workspace/59.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/6.otp_ctrl_alert_test.1881394003 |
Short name | T466 |
Test name | |
Test status | |
Simulation time | 61643870 ps |
CPU time | 1.74 seconds |
Started | Mar 31 03:29:02 PM PDT 24 |
Finished | Mar 31 03:29:04 PM PDT 24 |
Peak memory | 240088 kb |
Host | smart-1b33fecc-7575-40d1-8e73-4536cc4d9906 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881394003 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.1881394003 |
Directory | /workspace/6.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/6.otp_ctrl_background_chks.3411212149 |
Short name | T951 |
Test name | |
Test status | |
Simulation time | 492746809 ps |
CPU time | 10.1 seconds |
Started | Mar 31 03:28:59 PM PDT 24 |
Finished | Mar 31 03:29:09 PM PDT 24 |
Peak memory | 242088 kb |
Host | smart-f15ac25b-7fb7-481e-abbf-9e5a9da64558 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3411212149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.3411212149 |
Directory | /workspace/6.otp_ctrl_background_chks/latest |
Test location | /workspace/coverage/default/6.otp_ctrl_check_fail.3595507539 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 1570333548 ps |
CPU time | 30.36 seconds |
Started | Mar 31 03:29:11 PM PDT 24 |
Finished | Mar 31 03:29:42 PM PDT 24 |
Peak memory | 241860 kb |
Host | smart-fcaa6af6-b74d-43a5-adb1-568d2c5ccf48 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3595507539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.3595507539 |
Directory | /workspace/6.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/6.otp_ctrl_dai_errs.636087484 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 18037784288 ps |
CPU time | 43.62 seconds |
Started | Mar 31 03:29:10 PM PDT 24 |
Finished | Mar 31 03:29:54 PM PDT 24 |
Peak memory | 249304 kb |
Host | smart-b99a22d7-9d15-4a02-9a21-b2ae2962e3ba |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=636087484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.636087484 |
Directory | /workspace/6.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/6.otp_ctrl_dai_lock.596583948 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 1098685903 ps |
CPU time | 12.49 seconds |
Started | Mar 31 03:29:03 PM PDT 24 |
Finished | Mar 31 03:29:15 PM PDT 24 |
Peak memory | 241688 kb |
Host | smart-e8dfec6c-041d-44e3-bc9f-f0d53706e726 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=596583948 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.596583948 |
Directory | /workspace/6.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/6.otp_ctrl_init_fail.1893896062 |
Short name | T1120 |
Test name | |
Test status | |
Simulation time | 1598547603 ps |
CPU time | 4.91 seconds |
Started | Mar 31 03:28:58 PM PDT 24 |
Finished | Mar 31 03:29:03 PM PDT 24 |
Peak memory | 241640 kb |
Host | smart-a98cef7e-cf85-4402-a829-5fed1aca31ca |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1893896062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.1893896062 |
Directory | /workspace/6.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/6.otp_ctrl_macro_errs.2760002085 |
Short name | T1051 |
Test name | |
Test status | |
Simulation time | 2045573170 ps |
CPU time | 15.36 seconds |
Started | Mar 31 03:29:03 PM PDT 24 |
Finished | Mar 31 03:29:18 PM PDT 24 |
Peak memory | 242020 kb |
Host | smart-8c3dd8d3-f191-4829-9f14-5b7d314bd08e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2760002085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.2760002085 |
Directory | /workspace/6.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/6.otp_ctrl_parallel_key_req.1861160460 |
Short name | T946 |
Test name | |
Test status | |
Simulation time | 1000189784 ps |
CPU time | 26.15 seconds |
Started | Mar 31 03:29:08 PM PDT 24 |
Finished | Mar 31 03:29:35 PM PDT 24 |
Peak memory | 242328 kb |
Host | smart-fe2aea8b-694c-4feb-bfeb-ec1a1130be95 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1861160460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.1861160460 |
Directory | /workspace/6.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/6.otp_ctrl_parallel_lc_esc.283323874 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 302270437 ps |
CPU time | 8.24 seconds |
Started | Mar 31 03:29:03 PM PDT 24 |
Finished | Mar 31 03:29:11 PM PDT 24 |
Peak memory | 241988 kb |
Host | smart-2b9037f2-83e6-4bde-b0fc-6c6657cb91df |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=283323874 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.283323874 |
Directory | /workspace/6.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/6.otp_ctrl_parallel_lc_req.3406796999 |
Short name | T851 |
Test name | |
Test status | |
Simulation time | 9239170508 ps |
CPU time | 21.36 seconds |
Started | Mar 31 03:29:04 PM PDT 24 |
Finished | Mar 31 03:29:25 PM PDT 24 |
Peak memory | 241944 kb |
Host | smart-11e60283-903b-45ea-9804-825e7b157227 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3406796999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.3406796999 |
Directory | /workspace/6.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/6.otp_ctrl_regwen.4243521879 |
Short name | T1190 |
Test name | |
Test status | |
Simulation time | 285108361 ps |
CPU time | 10.21 seconds |
Started | Mar 31 03:29:02 PM PDT 24 |
Finished | Mar 31 03:29:13 PM PDT 24 |
Peak memory | 241764 kb |
Host | smart-a138f989-fd12-49ff-b116-2dc4521cc4f9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4243521879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.4243521879 |
Directory | /workspace/6.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/6.otp_ctrl_smoke.99564469 |
Short name | T767 |
Test name | |
Test status | |
Simulation time | 335466821 ps |
CPU time | 7.27 seconds |
Started | Mar 31 03:29:00 PM PDT 24 |
Finished | Mar 31 03:29:07 PM PDT 24 |
Peak memory | 241656 kb |
Host | smart-1ebba4eb-0e7a-41cf-92f5-56c68b279a48 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=99564469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.99564469 |
Directory | /workspace/6.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/6.otp_ctrl_stress_all.3551842666 |
Short name | T534 |
Test name | |
Test status | |
Simulation time | 554718483 ps |
CPU time | 5.55 seconds |
Started | Mar 31 03:29:06 PM PDT 24 |
Finished | Mar 31 03:29:12 PM PDT 24 |
Peak memory | 242936 kb |
Host | smart-59aacb66-afd1-4246-9b9f-28e348aff86b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551842666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all. 3551842666 |
Directory | /workspace/6.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/6.otp_ctrl_stress_all_with_rand_reset.4087287806 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 151917971532 ps |
CPU time | 1020.68 seconds |
Started | Mar 31 03:29:03 PM PDT 24 |
Finished | Mar 31 03:46:04 PM PDT 24 |
Peak memory | 273360 kb |
Host | smart-bc3df5df-d946-40c0-964b-024d3f874ba6 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087287806 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all_with_rand_reset.4087287806 |
Directory | /workspace/6.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/6.otp_ctrl_test_access.1330494285 |
Short name | T1164 |
Test name | |
Test status | |
Simulation time | 3188600378 ps |
CPU time | 6.32 seconds |
Started | Mar 31 03:29:02 PM PDT 24 |
Finished | Mar 31 03:29:09 PM PDT 24 |
Peak memory | 241872 kb |
Host | smart-3b660eb9-ac00-4e4d-b418-81126b82a7ce |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1330494285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.1330494285 |
Directory | /workspace/6.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/60.otp_ctrl_init_fail.1489854726 |
Short name | T1075 |
Test name | |
Test status | |
Simulation time | 2421159909 ps |
CPU time | 7.16 seconds |
Started | Mar 31 03:32:11 PM PDT 24 |
Finished | Mar 31 03:32:18 PM PDT 24 |
Peak memory | 241980 kb |
Host | smart-c074e58a-d4a0-4a97-864b-deab71b6272b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1489854726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.1489854726 |
Directory | /workspace/60.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/60.otp_ctrl_parallel_lc_esc.1521301419 |
Short name | T547 |
Test name | |
Test status | |
Simulation time | 508935299 ps |
CPU time | 16.59 seconds |
Started | Mar 31 03:32:13 PM PDT 24 |
Finished | Mar 31 03:32:30 PM PDT 24 |
Peak memory | 241584 kb |
Host | smart-658f268f-5f06-428f-9f91-c80f09515a0e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1521301419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.1521301419 |
Directory | /workspace/60.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/61.otp_ctrl_init_fail.60412891 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 1747626201 ps |
CPU time | 4.61 seconds |
Started | Mar 31 03:32:18 PM PDT 24 |
Finished | Mar 31 03:32:23 PM PDT 24 |
Peak memory | 241656 kb |
Host | smart-9a8ecbad-d4d7-46d1-a9fd-0290067e2edf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=60412891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.60412891 |
Directory | /workspace/61.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/61.otp_ctrl_parallel_lc_esc.272392484 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 1345587886 ps |
CPU time | 3.37 seconds |
Started | Mar 31 03:32:17 PM PDT 24 |
Finished | Mar 31 03:32:22 PM PDT 24 |
Peak memory | 241832 kb |
Host | smart-7e563e0d-7b02-495d-bf03-5c8264cbbfc9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=272392484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.272392484 |
Directory | /workspace/61.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/61.otp_ctrl_stress_all_with_rand_reset.1788330818 |
Short name | T896 |
Test name | |
Test status | |
Simulation time | 27661005351 ps |
CPU time | 735.41 seconds |
Started | Mar 31 03:32:15 PM PDT 24 |
Finished | Mar 31 03:44:31 PM PDT 24 |
Peak memory | 379184 kb |
Host | smart-ab73650b-5bbe-4dec-aae5-d9ebd64c1de1 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788330818 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_stress_all_with_rand_reset.1788330818 |
Directory | /workspace/61.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/62.otp_ctrl_init_fail.2210208813 |
Short name | T887 |
Test name | |
Test status | |
Simulation time | 156055825 ps |
CPU time | 3.29 seconds |
Started | Mar 31 03:32:19 PM PDT 24 |
Finished | Mar 31 03:32:23 PM PDT 24 |
Peak memory | 241724 kb |
Host | smart-7cf0ff08-ea78-4e94-8353-42994ac68f5c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2210208813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.2210208813 |
Directory | /workspace/62.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/62.otp_ctrl_parallel_lc_esc.594104685 |
Short name | T784 |
Test name | |
Test status | |
Simulation time | 395238363 ps |
CPU time | 5.03 seconds |
Started | Mar 31 03:32:18 PM PDT 24 |
Finished | Mar 31 03:32:24 PM PDT 24 |
Peak memory | 241584 kb |
Host | smart-2616988e-3cf1-4bd8-a5d9-ff2af6e23aba |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=594104685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.594104685 |
Directory | /workspace/62.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/62.otp_ctrl_stress_all_with_rand_reset.1807240640 |
Short name | T1058 |
Test name | |
Test status | |
Simulation time | 16080688128 ps |
CPU time | 468.26 seconds |
Started | Mar 31 03:32:17 PM PDT 24 |
Finished | Mar 31 03:40:05 PM PDT 24 |
Peak memory | 274424 kb |
Host | smart-ee2e6af3-19d4-4586-96bb-668d2c1aebb8 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807240640 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_stress_all_with_rand_reset.1807240640 |
Directory | /workspace/62.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/63.otp_ctrl_init_fail.3121597026 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 260280671 ps |
CPU time | 4.16 seconds |
Started | Mar 31 03:32:20 PM PDT 24 |
Finished | Mar 31 03:32:24 PM PDT 24 |
Peak memory | 242052 kb |
Host | smart-16461fa5-8886-4455-80a9-5d5ba5d71ac8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3121597026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.3121597026 |
Directory | /workspace/63.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/63.otp_ctrl_parallel_lc_esc.3346016770 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 724978267 ps |
CPU time | 9.94 seconds |
Started | Mar 31 03:32:19 PM PDT 24 |
Finished | Mar 31 03:32:30 PM PDT 24 |
Peak memory | 241808 kb |
Host | smart-787baab9-edf0-488b-95be-10f8fcb24896 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3346016770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.3346016770 |
Directory | /workspace/63.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/64.otp_ctrl_init_fail.3216222390 |
Short name | T925 |
Test name | |
Test status | |
Simulation time | 142626201 ps |
CPU time | 3.76 seconds |
Started | Mar 31 03:32:22 PM PDT 24 |
Finished | Mar 31 03:32:27 PM PDT 24 |
Peak memory | 241720 kb |
Host | smart-0c526d24-0af8-416f-bd1c-c1bc27c35a3d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3216222390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.3216222390 |
Directory | /workspace/64.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/64.otp_ctrl_parallel_lc_esc.2130112441 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 11027827166 ps |
CPU time | 34.52 seconds |
Started | Mar 31 03:32:16 PM PDT 24 |
Finished | Mar 31 03:32:51 PM PDT 24 |
Peak memory | 241640 kb |
Host | smart-151b87c5-3ac6-4b3c-a32d-2935eea5a280 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2130112441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.2130112441 |
Directory | /workspace/64.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/64.otp_ctrl_stress_all_with_rand_reset.467373969 |
Short name | T613 |
Test name | |
Test status | |
Simulation time | 83875034342 ps |
CPU time | 1021.11 seconds |
Started | Mar 31 03:32:19 PM PDT 24 |
Finished | Mar 31 03:49:21 PM PDT 24 |
Peak memory | 262776 kb |
Host | smart-9133c5d0-f856-45e6-9dcb-0e047dc5f0b6 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467373969 -assert nopo stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_stress_all_with_rand_reset.467373969 |
Directory | /workspace/64.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/65.otp_ctrl_init_fail.3046796928 |
Short name | T446 |
Test name | |
Test status | |
Simulation time | 2654142183 ps |
CPU time | 5.34 seconds |
Started | Mar 31 03:32:18 PM PDT 24 |
Finished | Mar 31 03:32:24 PM PDT 24 |
Peak memory | 241792 kb |
Host | smart-81f72027-8e55-4568-a3b5-e993967df2cc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3046796928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.3046796928 |
Directory | /workspace/65.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/65.otp_ctrl_parallel_lc_esc.1814151861 |
Short name | T481 |
Test name | |
Test status | |
Simulation time | 207679131 ps |
CPU time | 4.52 seconds |
Started | Mar 31 03:32:20 PM PDT 24 |
Finished | Mar 31 03:32:25 PM PDT 24 |
Peak memory | 241504 kb |
Host | smart-8280fcdb-1a2a-405f-abb8-5f9a79f39cff |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1814151861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.1814151861 |
Directory | /workspace/65.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.1176172197 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 238631874037 ps |
CPU time | 3277.95 seconds |
Started | Mar 31 03:32:19 PM PDT 24 |
Finished | Mar 31 04:26:58 PM PDT 24 |
Peak memory | 630588 kb |
Host | smart-2032d80b-03cb-4660-817f-a6e823f4003a |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176172197 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_stress_all_with_rand_reset.1176172197 |
Directory | /workspace/65.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/66.otp_ctrl_init_fail.468136314 |
Short name | T590 |
Test name | |
Test status | |
Simulation time | 126645191 ps |
CPU time | 3.43 seconds |
Started | Mar 31 03:32:18 PM PDT 24 |
Finished | Mar 31 03:32:22 PM PDT 24 |
Peak memory | 241716 kb |
Host | smart-c2a754e3-8755-4d48-af4e-158ec4f34af1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=468136314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.468136314 |
Directory | /workspace/66.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/66.otp_ctrl_parallel_lc_esc.2147305298 |
Short name | T460 |
Test name | |
Test status | |
Simulation time | 875232221 ps |
CPU time | 12.4 seconds |
Started | Mar 31 03:32:17 PM PDT 24 |
Finished | Mar 31 03:32:31 PM PDT 24 |
Peak memory | 241772 kb |
Host | smart-bf19b757-d848-4a1a-91a0-3553185b7203 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2147305298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.2147305298 |
Directory | /workspace/66.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/66.otp_ctrl_stress_all_with_rand_reset.3193340327 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 67494035706 ps |
CPU time | 488.74 seconds |
Started | Mar 31 03:32:22 PM PDT 24 |
Finished | Mar 31 03:40:32 PM PDT 24 |
Peak memory | 265208 kb |
Host | smart-1c1413af-ce3e-4521-a417-5f3774dae58c |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193340327 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_stress_all_with_rand_reset.3193340327 |
Directory | /workspace/66.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/67.otp_ctrl_init_fail.2461075570 |
Short name | T687 |
Test name | |
Test status | |
Simulation time | 124127218 ps |
CPU time | 3.54 seconds |
Started | Mar 31 03:32:19 PM PDT 24 |
Finished | Mar 31 03:32:23 PM PDT 24 |
Peak memory | 241696 kb |
Host | smart-a8ae4365-97d2-44f7-b834-9b92652840b9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2461075570 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.2461075570 |
Directory | /workspace/67.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/67.otp_ctrl_parallel_lc_esc.4105608222 |
Short name | T664 |
Test name | |
Test status | |
Simulation time | 130705284 ps |
CPU time | 3.58 seconds |
Started | Mar 31 03:32:18 PM PDT 24 |
Finished | Mar 31 03:32:22 PM PDT 24 |
Peak memory | 241592 kb |
Host | smart-a2cf7c17-2311-44b1-8516-268cf457f2b1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4105608222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.4105608222 |
Directory | /workspace/67.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/67.otp_ctrl_stress_all_with_rand_reset.2525263895 |
Short name | T607 |
Test name | |
Test status | |
Simulation time | 24661352869 ps |
CPU time | 575.34 seconds |
Started | Mar 31 03:32:26 PM PDT 24 |
Finished | Mar 31 03:42:02 PM PDT 24 |
Peak memory | 257080 kb |
Host | smart-4090eb2a-1f63-4a39-8385-db01fca16afe |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525263895 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_stress_all_with_rand_reset.2525263895 |
Directory | /workspace/67.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/68.otp_ctrl_init_fail.754314102 |
Short name | T1045 |
Test name | |
Test status | |
Simulation time | 214616641 ps |
CPU time | 4.13 seconds |
Started | Mar 31 03:32:23 PM PDT 24 |
Finished | Mar 31 03:32:28 PM PDT 24 |
Peak memory | 241960 kb |
Host | smart-993fca82-3010-4f2a-af1e-d6547246cbba |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=754314102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.754314102 |
Directory | /workspace/68.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/68.otp_ctrl_parallel_lc_esc.4130575336 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 3397616263 ps |
CPU time | 16.07 seconds |
Started | Mar 31 03:32:23 PM PDT 24 |
Finished | Mar 31 03:32:40 PM PDT 24 |
Peak memory | 241732 kb |
Host | smart-49958928-1cdf-4863-91b8-f3fcc8832077 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4130575336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.4130575336 |
Directory | /workspace/68.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/68.otp_ctrl_stress_all_with_rand_reset.2028624887 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 452957656922 ps |
CPU time | 957.82 seconds |
Started | Mar 31 03:32:28 PM PDT 24 |
Finished | Mar 31 03:48:26 PM PDT 24 |
Peak memory | 278180 kb |
Host | smart-e7b717f8-9b63-4ec2-936b-54a0571abfc6 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028624887 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_stress_all_with_rand_reset.2028624887 |
Directory | /workspace/68.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/69.otp_ctrl_init_fail.3184858284 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 2968729893 ps |
CPU time | 8.82 seconds |
Started | Mar 31 03:32:24 PM PDT 24 |
Finished | Mar 31 03:32:33 PM PDT 24 |
Peak memory | 241776 kb |
Host | smart-98d2cb0f-f5f3-43bf-b230-3a4111cfeae5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3184858284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.3184858284 |
Directory | /workspace/69.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/69.otp_ctrl_stress_all_with_rand_reset.2017808870 |
Short name | T922 |
Test name | |
Test status | |
Simulation time | 82498450266 ps |
CPU time | 571.65 seconds |
Started | Mar 31 03:32:26 PM PDT 24 |
Finished | Mar 31 03:41:58 PM PDT 24 |
Peak memory | 337176 kb |
Host | smart-45eaadc5-1875-4e30-8022-0b4d58af5675 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017808870 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_stress_all_with_rand_reset.2017808870 |
Directory | /workspace/69.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/7.otp_ctrl_alert_test.2648297592 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 95969314 ps |
CPU time | 1.57 seconds |
Started | Mar 31 03:29:09 PM PDT 24 |
Finished | Mar 31 03:29:12 PM PDT 24 |
Peak memory | 240132 kb |
Host | smart-03a1843e-f2b7-44be-857b-0ab7c990a0f1 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648297592 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.2648297592 |
Directory | /workspace/7.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/7.otp_ctrl_background_chks.1568169715 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 14558352293 ps |
CPU time | 24.67 seconds |
Started | Mar 31 03:29:07 PM PDT 24 |
Finished | Mar 31 03:29:32 PM PDT 24 |
Peak memory | 242508 kb |
Host | smart-39cf75c2-e7d5-4ea7-9a81-445e948f78ff |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1568169715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.1568169715 |
Directory | /workspace/7.otp_ctrl_background_chks/latest |
Test location | /workspace/coverage/default/7.otp_ctrl_check_fail.885690379 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 2171994751 ps |
CPU time | 14.13 seconds |
Started | Mar 31 03:29:12 PM PDT 24 |
Finished | Mar 31 03:29:26 PM PDT 24 |
Peak memory | 245928 kb |
Host | smart-faca8303-ff74-476f-8a02-0fa6723149c0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=885690379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.885690379 |
Directory | /workspace/7.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/7.otp_ctrl_dai_errs.3832727020 |
Short name | T731 |
Test name | |
Test status | |
Simulation time | 1418222652 ps |
CPU time | 32.43 seconds |
Started | Mar 31 03:29:12 PM PDT 24 |
Finished | Mar 31 03:29:45 PM PDT 24 |
Peak memory | 242036 kb |
Host | smart-8f3afc6e-48eb-4cef-aabf-64749b8c29f5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3832727020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.3832727020 |
Directory | /workspace/7.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/7.otp_ctrl_dai_lock.4257346336 |
Short name | T853 |
Test name | |
Test status | |
Simulation time | 705738362 ps |
CPU time | 23.42 seconds |
Started | Mar 31 03:29:03 PM PDT 24 |
Finished | Mar 31 03:29:26 PM PDT 24 |
Peak memory | 241812 kb |
Host | smart-3de436bf-2418-42ec-a8b3-45fa6e712748 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4257346336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.4257346336 |
Directory | /workspace/7.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/7.otp_ctrl_init_fail.853520455 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 333483548 ps |
CPU time | 2.89 seconds |
Started | Mar 31 03:29:02 PM PDT 24 |
Finished | Mar 31 03:29:05 PM PDT 24 |
Peak memory | 241808 kb |
Host | smart-eb9eeeac-3fa0-4884-99a7-024e56627bbb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=853520455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.853520455 |
Directory | /workspace/7.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/7.otp_ctrl_macro_errs.52722340 |
Short name | T949 |
Test name | |
Test status | |
Simulation time | 1543465779 ps |
CPU time | 11.25 seconds |
Started | Mar 31 03:29:09 PM PDT 24 |
Finished | Mar 31 03:29:22 PM PDT 24 |
Peak memory | 244400 kb |
Host | smart-1b7b2cf8-be11-4e6b-b148-103d608a840a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=52722340 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.52722340 |
Directory | /workspace/7.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/7.otp_ctrl_parallel_key_req.3886975911 |
Short name | T1178 |
Test name | |
Test status | |
Simulation time | 10272407820 ps |
CPU time | 24.13 seconds |
Started | Mar 31 03:29:10 PM PDT 24 |
Finished | Mar 31 03:29:35 PM PDT 24 |
Peak memory | 242172 kb |
Host | smart-98eb5ea0-e759-487b-bb53-7ec8cfc1af0b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3886975911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.3886975911 |
Directory | /workspace/7.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/7.otp_ctrl_parallel_lc_esc.2307216349 |
Short name | T929 |
Test name | |
Test status | |
Simulation time | 381175715 ps |
CPU time | 5.19 seconds |
Started | Mar 31 03:29:09 PM PDT 24 |
Finished | Mar 31 03:29:14 PM PDT 24 |
Peak memory | 241696 kb |
Host | smart-d825fb5d-dbe4-4201-8a7b-d00c083711bf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2307216349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.2307216349 |
Directory | /workspace/7.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/7.otp_ctrl_parallel_lc_req.2535582518 |
Short name | T906 |
Test name | |
Test status | |
Simulation time | 702539937 ps |
CPU time | 9.77 seconds |
Started | Mar 31 03:29:09 PM PDT 24 |
Finished | Mar 31 03:29:21 PM PDT 24 |
Peak memory | 241816 kb |
Host | smart-7d197499-fe93-4faa-887c-946e7a236af1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2535582518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.2535582518 |
Directory | /workspace/7.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/7.otp_ctrl_smoke.1120437910 |
Short name | T955 |
Test name | |
Test status | |
Simulation time | 596044481 ps |
CPU time | 7.75 seconds |
Started | Mar 31 03:29:02 PM PDT 24 |
Finished | Mar 31 03:29:10 PM PDT 24 |
Peak memory | 241672 kb |
Host | smart-277d0630-4a5a-4dfd-879e-8f86e4a1e364 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1120437910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.1120437910 |
Directory | /workspace/7.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/7.otp_ctrl_stress_all.168636766 |
Short name | T1111 |
Test name | |
Test status | |
Simulation time | 123053492828 ps |
CPU time | 201.42 seconds |
Started | Mar 31 03:29:10 PM PDT 24 |
Finished | Mar 31 03:32:32 PM PDT 24 |
Peak memory | 261412 kb |
Host | smart-5cdf7c03-58af-4cf1-85a5-8308c3a359e4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168636766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all.168636766 |
Directory | /workspace/7.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/7.otp_ctrl_stress_all_with_rand_reset.115256854 |
Short name | T926 |
Test name | |
Test status | |
Simulation time | 117840591593 ps |
CPU time | 1054.56 seconds |
Started | Mar 31 03:29:08 PM PDT 24 |
Finished | Mar 31 03:46:43 PM PDT 24 |
Peak memory | 394596 kb |
Host | smart-796d9f69-417b-4b9f-a8f7-1d3b969fffbe |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115256854 -assert nopo stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all_with_rand_reset.115256854 |
Directory | /workspace/7.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/7.otp_ctrl_test_access.560358057 |
Short name | T1062 |
Test name | |
Test status | |
Simulation time | 1154509453 ps |
CPU time | 10.1 seconds |
Started | Mar 31 03:29:12 PM PDT 24 |
Finished | Mar 31 03:29:22 PM PDT 24 |
Peak memory | 241612 kb |
Host | smart-17796595-3d30-478a-9fbd-cd65ab5a7e15 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=560358057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.560358057 |
Directory | /workspace/7.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/70.otp_ctrl_init_fail.4136169543 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 112309857 ps |
CPU time | 4.28 seconds |
Started | Mar 31 03:32:27 PM PDT 24 |
Finished | Mar 31 03:32:32 PM PDT 24 |
Peak memory | 241972 kb |
Host | smart-c29a48c1-bfd9-4818-9201-920e71329d46 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4136169543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.4136169543 |
Directory | /workspace/70.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/70.otp_ctrl_parallel_lc_esc.1149472962 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 428482420 ps |
CPU time | 10.9 seconds |
Started | Mar 31 03:32:24 PM PDT 24 |
Finished | Mar 31 03:32:35 PM PDT 24 |
Peak memory | 241756 kb |
Host | smart-c6572fcd-84c3-42d7-826d-a017d0e716d0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1149472962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.1149472962 |
Directory | /workspace/70.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/70.otp_ctrl_stress_all_with_rand_reset.1868408703 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 50984899957 ps |
CPU time | 419.98 seconds |
Started | Mar 31 03:32:25 PM PDT 24 |
Finished | Mar 31 03:39:26 PM PDT 24 |
Peak memory | 283080 kb |
Host | smart-1a7365d3-7c89-43d1-9a2a-759f4fbac60a |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868408703 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_stress_all_with_rand_reset.1868408703 |
Directory | /workspace/70.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/71.otp_ctrl_init_fail.786152862 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 2555263607 ps |
CPU time | 8.24 seconds |
Started | Mar 31 03:32:24 PM PDT 24 |
Finished | Mar 31 03:32:33 PM PDT 24 |
Peak memory | 241860 kb |
Host | smart-5d11860f-e4f7-4c47-815c-daa45ba4be7a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=786152862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.786152862 |
Directory | /workspace/71.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/71.otp_ctrl_parallel_lc_esc.2278392753 |
Short name | T527 |
Test name | |
Test status | |
Simulation time | 634837401 ps |
CPU time | 9.08 seconds |
Started | Mar 31 03:32:24 PM PDT 24 |
Finished | Mar 31 03:32:33 PM PDT 24 |
Peak memory | 241644 kb |
Host | smart-702ec06e-363b-49c9-9672-30abef98b842 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2278392753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.2278392753 |
Directory | /workspace/71.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/72.otp_ctrl_parallel_lc_esc.417589862 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 1465828686 ps |
CPU time | 5.5 seconds |
Started | Mar 31 03:32:23 PM PDT 24 |
Finished | Mar 31 03:32:29 PM PDT 24 |
Peak memory | 242004 kb |
Host | smart-1dc81610-0e03-4f44-88ff-cd610b271dcf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=417589862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.417589862 |
Directory | /workspace/72.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/72.otp_ctrl_stress_all_with_rand_reset.1828442112 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 37867953202 ps |
CPU time | 464.93 seconds |
Started | Mar 31 03:32:30 PM PDT 24 |
Finished | Mar 31 03:40:16 PM PDT 24 |
Peak memory | 325916 kb |
Host | smart-6f8fc1b2-9779-4200-8d75-d638f33ff620 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828442112 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_stress_all_with_rand_reset.1828442112 |
Directory | /workspace/72.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/73.otp_ctrl_init_fail.3118678422 |
Short name | T975 |
Test name | |
Test status | |
Simulation time | 639194091 ps |
CPU time | 4.76 seconds |
Started | Mar 31 03:32:29 PM PDT 24 |
Finished | Mar 31 03:32:34 PM PDT 24 |
Peak memory | 241808 kb |
Host | smart-dc9551d6-fe18-49ec-b88d-4255644a29fc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3118678422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.3118678422 |
Directory | /workspace/73.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/73.otp_ctrl_parallel_lc_esc.216596594 |
Short name | T832 |
Test name | |
Test status | |
Simulation time | 122298066 ps |
CPU time | 4.16 seconds |
Started | Mar 31 03:32:35 PM PDT 24 |
Finished | Mar 31 03:32:40 PM PDT 24 |
Peak memory | 241496 kb |
Host | smart-ca58672e-e149-4b0a-897b-df9b5138936c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=216596594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.216596594 |
Directory | /workspace/73.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/74.otp_ctrl_init_fail.106089974 |
Short name | T981 |
Test name | |
Test status | |
Simulation time | 182109198 ps |
CPU time | 3.86 seconds |
Started | Mar 31 03:32:30 PM PDT 24 |
Finished | Mar 31 03:32:34 PM PDT 24 |
Peak memory | 241728 kb |
Host | smart-2624e55c-9a56-4731-bf3f-7a84f098034f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=106089974 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.106089974 |
Directory | /workspace/74.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/74.otp_ctrl_parallel_lc_esc.2573460575 |
Short name | T1112 |
Test name | |
Test status | |
Simulation time | 168965428 ps |
CPU time | 3.52 seconds |
Started | Mar 31 03:32:32 PM PDT 24 |
Finished | Mar 31 03:32:36 PM PDT 24 |
Peak memory | 241616 kb |
Host | smart-89088483-16a1-4484-82f1-ac225107c2d6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2573460575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.2573460575 |
Directory | /workspace/74.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/74.otp_ctrl_stress_all_with_rand_reset.1769565747 |
Short name | T760 |
Test name | |
Test status | |
Simulation time | 104514236738 ps |
CPU time | 782.88 seconds |
Started | Mar 31 03:32:31 PM PDT 24 |
Finished | Mar 31 03:45:34 PM PDT 24 |
Peak memory | 318296 kb |
Host | smart-e42944ec-9b54-49ff-98f3-626c20e687a1 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769565747 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_stress_all_with_rand_reset.1769565747 |
Directory | /workspace/74.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/75.otp_ctrl_init_fail.3176143801 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 157479018 ps |
CPU time | 4.79 seconds |
Started | Mar 31 03:32:31 PM PDT 24 |
Finished | Mar 31 03:32:36 PM PDT 24 |
Peak memory | 241764 kb |
Host | smart-1d5873bd-88c9-4c45-b921-d3836a743849 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3176143801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.3176143801 |
Directory | /workspace/75.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/75.otp_ctrl_parallel_lc_esc.2180715875 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 688938927 ps |
CPU time | 17.12 seconds |
Started | Mar 31 03:32:29 PM PDT 24 |
Finished | Mar 31 03:32:47 PM PDT 24 |
Peak memory | 241536 kb |
Host | smart-339ffd0c-e07d-4b9a-b9a9-2731f9863ac1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2180715875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.2180715875 |
Directory | /workspace/75.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/75.otp_ctrl_stress_all_with_rand_reset.1263158368 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 63114723034 ps |
CPU time | 1496.12 seconds |
Started | Mar 31 03:32:28 PM PDT 24 |
Finished | Mar 31 03:57:26 PM PDT 24 |
Peak memory | 265204 kb |
Host | smart-cbb0778e-fee1-44f0-9b23-240b4b0e293d |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263158368 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_stress_all_with_rand_reset.1263158368 |
Directory | /workspace/75.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/76.otp_ctrl_init_fail.627089179 |
Short name | T1096 |
Test name | |
Test status | |
Simulation time | 406842914 ps |
CPU time | 4.62 seconds |
Started | Mar 31 03:32:30 PM PDT 24 |
Finished | Mar 31 03:32:35 PM PDT 24 |
Peak memory | 241740 kb |
Host | smart-fd5f94f7-c4e4-4d35-8127-1fce11b945e7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=627089179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.627089179 |
Directory | /workspace/76.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/76.otp_ctrl_stress_all_with_rand_reset.3194576497 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 98061135359 ps |
CPU time | 770.87 seconds |
Started | Mar 31 03:32:32 PM PDT 24 |
Finished | Mar 31 03:45:23 PM PDT 24 |
Peak memory | 264668 kb |
Host | smart-ff0522be-3dc0-451f-b32e-cf576dc76b48 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194576497 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_stress_all_with_rand_reset.3194576497 |
Directory | /workspace/76.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/77.otp_ctrl_init_fail.3299905474 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 120036965 ps |
CPU time | 4.23 seconds |
Started | Mar 31 03:32:29 PM PDT 24 |
Finished | Mar 31 03:32:34 PM PDT 24 |
Peak memory | 241644 kb |
Host | smart-3ca626dc-6ab3-47ac-95a2-2c6bd3ec0179 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3299905474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.3299905474 |
Directory | /workspace/77.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/77.otp_ctrl_parallel_lc_esc.2113016381 |
Short name | T958 |
Test name | |
Test status | |
Simulation time | 2589902413 ps |
CPU time | 11.15 seconds |
Started | Mar 31 03:32:31 PM PDT 24 |
Finished | Mar 31 03:32:42 PM PDT 24 |
Peak memory | 241624 kb |
Host | smart-cb88ae60-e099-4f8f-9f52-c4715127a09a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2113016381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.2113016381 |
Directory | /workspace/77.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/77.otp_ctrl_stress_all_with_rand_reset.3397221138 |
Short name | T935 |
Test name | |
Test status | |
Simulation time | 650197510909 ps |
CPU time | 1175.04 seconds |
Started | Mar 31 03:32:30 PM PDT 24 |
Finished | Mar 31 03:52:06 PM PDT 24 |
Peak memory | 330756 kb |
Host | smart-a1570295-7fbf-4d23-abcb-84c9a1c86b38 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397221138 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_stress_all_with_rand_reset.3397221138 |
Directory | /workspace/77.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/78.otp_ctrl_init_fail.3048644446 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 2139526204 ps |
CPU time | 6.98 seconds |
Started | Mar 31 03:32:29 PM PDT 24 |
Finished | Mar 31 03:32:37 PM PDT 24 |
Peak memory | 241688 kb |
Host | smart-5bef8e26-da94-42c8-99e5-14b0a49a4ea8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3048644446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.3048644446 |
Directory | /workspace/78.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/78.otp_ctrl_parallel_lc_esc.2878511994 |
Short name | T1107 |
Test name | |
Test status | |
Simulation time | 439515250 ps |
CPU time | 4.32 seconds |
Started | Mar 31 03:32:31 PM PDT 24 |
Finished | Mar 31 03:32:36 PM PDT 24 |
Peak memory | 241616 kb |
Host | smart-597ec259-0671-4dff-9834-5612a789a9e5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2878511994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.2878511994 |
Directory | /workspace/78.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/79.otp_ctrl_init_fail.519550415 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 1868434551 ps |
CPU time | 6.42 seconds |
Started | Mar 31 03:32:30 PM PDT 24 |
Finished | Mar 31 03:32:37 PM PDT 24 |
Peak memory | 241856 kb |
Host | smart-e1332dc1-3dc4-400d-ae75-4a5611a7f239 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=519550415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.519550415 |
Directory | /workspace/79.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/79.otp_ctrl_parallel_lc_esc.1701164358 |
Short name | T916 |
Test name | |
Test status | |
Simulation time | 410156753 ps |
CPU time | 4.1 seconds |
Started | Mar 31 03:32:34 PM PDT 24 |
Finished | Mar 31 03:32:38 PM PDT 24 |
Peak memory | 241460 kb |
Host | smart-d9bb4da5-9b2b-42e3-bfe3-203cfee3ec42 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1701164358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.1701164358 |
Directory | /workspace/79.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/79.otp_ctrl_stress_all_with_rand_reset.2479220464 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 135402457403 ps |
CPU time | 3197.08 seconds |
Started | Mar 31 03:32:29 PM PDT 24 |
Finished | Mar 31 04:25:47 PM PDT 24 |
Peak memory | 492008 kb |
Host | smart-cd2bb3d1-3961-4775-8432-37ea0eb11cbe |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479220464 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_stress_all_with_rand_reset.2479220464 |
Directory | /workspace/79.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/8.otp_ctrl_alert_test.3170385936 |
Short name | T544 |
Test name | |
Test status | |
Simulation time | 51763527 ps |
CPU time | 1.73 seconds |
Started | Mar 31 03:29:14 PM PDT 24 |
Finished | Mar 31 03:29:17 PM PDT 24 |
Peak memory | 240136 kb |
Host | smart-3ad79722-1995-42ac-becd-62e68ecc2c4f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170385936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.3170385936 |
Directory | /workspace/8.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/8.otp_ctrl_background_chks.1765922090 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 21428760944 ps |
CPU time | 29.04 seconds |
Started | Mar 31 03:29:09 PM PDT 24 |
Finished | Mar 31 03:29:39 PM PDT 24 |
Peak memory | 248788 kb |
Host | smart-78d781d7-1bfe-4cb0-9e9c-89c9c0c047a2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1765922090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.1765922090 |
Directory | /workspace/8.otp_ctrl_background_chks/latest |
Test location | /workspace/coverage/default/8.otp_ctrl_check_fail.1053447845 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 2252392871 ps |
CPU time | 20.71 seconds |
Started | Mar 31 03:29:10 PM PDT 24 |
Finished | Mar 31 03:29:32 PM PDT 24 |
Peak memory | 242884 kb |
Host | smart-5860bb52-a938-443c-9fc2-7afdf8a08794 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1053447845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.1053447845 |
Directory | /workspace/8.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/8.otp_ctrl_dai_errs.612106545 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 1418567092 ps |
CPU time | 23.31 seconds |
Started | Mar 31 03:29:10 PM PDT 24 |
Finished | Mar 31 03:29:34 PM PDT 24 |
Peak memory | 242180 kb |
Host | smart-2dd00ede-ef7c-44ea-a99b-a97389d05026 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=612106545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.612106545 |
Directory | /workspace/8.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/8.otp_ctrl_dai_lock.187032511 |
Short name | T465 |
Test name | |
Test status | |
Simulation time | 683323646 ps |
CPU time | 3.9 seconds |
Started | Mar 31 03:29:11 PM PDT 24 |
Finished | Mar 31 03:29:15 PM PDT 24 |
Peak memory | 241740 kb |
Host | smart-469eab59-dec2-4f02-8cd2-cd635e9e9117 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=187032511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.187032511 |
Directory | /workspace/8.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/8.otp_ctrl_init_fail.1725557106 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 131276267 ps |
CPU time | 3.84 seconds |
Started | Mar 31 03:29:09 PM PDT 24 |
Finished | Mar 31 03:29:15 PM PDT 24 |
Peak memory | 241916 kb |
Host | smart-1c998c4e-88f7-4e27-ba00-1ed0c1c7ce56 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1725557106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.1725557106 |
Directory | /workspace/8.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/8.otp_ctrl_macro_errs.1069313707 |
Short name | T579 |
Test name | |
Test status | |
Simulation time | 745087870 ps |
CPU time | 9.82 seconds |
Started | Mar 31 03:29:10 PM PDT 24 |
Finished | Mar 31 03:29:21 PM PDT 24 |
Peak memory | 241660 kb |
Host | smart-955fbdd2-fa8d-4517-a4d9-1f23a19942e3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1069313707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.1069313707 |
Directory | /workspace/8.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/8.otp_ctrl_parallel_key_req.1764702756 |
Short name | T639 |
Test name | |
Test status | |
Simulation time | 933806014 ps |
CPU time | 20.9 seconds |
Started | Mar 31 03:29:10 PM PDT 24 |
Finished | Mar 31 03:29:32 PM PDT 24 |
Peak memory | 242136 kb |
Host | smart-13129a73-7bf1-4cf4-bc16-52eab5afca7e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1764702756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.1764702756 |
Directory | /workspace/8.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/8.otp_ctrl_parallel_lc_esc.795330903 |
Short name | T576 |
Test name | |
Test status | |
Simulation time | 909432931 ps |
CPU time | 25.42 seconds |
Started | Mar 31 03:29:11 PM PDT 24 |
Finished | Mar 31 03:29:36 PM PDT 24 |
Peak memory | 241720 kb |
Host | smart-0ec794d6-e906-4cd9-a2b6-86e7b9c23951 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=795330903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.795330903 |
Directory | /workspace/8.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/8.otp_ctrl_parallel_lc_req.3146914226 |
Short name | T621 |
Test name | |
Test status | |
Simulation time | 577604245 ps |
CPU time | 14.12 seconds |
Started | Mar 31 03:29:10 PM PDT 24 |
Finished | Mar 31 03:29:25 PM PDT 24 |
Peak memory | 241776 kb |
Host | smart-a5956e92-7e35-4603-8527-75e6e167a9a4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3146914226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.3146914226 |
Directory | /workspace/8.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/8.otp_ctrl_regwen.3753587654 |
Short name | T937 |
Test name | |
Test status | |
Simulation time | 486674696 ps |
CPU time | 7.62 seconds |
Started | Mar 31 03:29:09 PM PDT 24 |
Finished | Mar 31 03:29:17 PM PDT 24 |
Peak memory | 241828 kb |
Host | smart-8ab20f4c-39b2-479c-8d82-7dc8dacf7189 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3753587654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.3753587654 |
Directory | /workspace/8.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/8.otp_ctrl_smoke.825832311 |
Short name | T989 |
Test name | |
Test status | |
Simulation time | 2129507040 ps |
CPU time | 13.42 seconds |
Started | Mar 31 03:29:12 PM PDT 24 |
Finished | Mar 31 03:29:26 PM PDT 24 |
Peak memory | 241652 kb |
Host | smart-72dc46f8-6588-4489-b6d4-843ad7531d15 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=825832311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.825832311 |
Directory | /workspace/8.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/8.otp_ctrl_stress_all.1631656487 |
Short name | T1188 |
Test name | |
Test status | |
Simulation time | 10167497545 ps |
CPU time | 74.93 seconds |
Started | Mar 31 03:29:13 PM PDT 24 |
Finished | Mar 31 03:30:29 PM PDT 24 |
Peak memory | 273856 kb |
Host | smart-cfd4f2d1-9599-464c-9063-0827dc3cca29 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631656487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all. 1631656487 |
Directory | /workspace/8.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/8.otp_ctrl_stress_all_with_rand_reset.310187042 |
Short name | T956 |
Test name | |
Test status | |
Simulation time | 93235833270 ps |
CPU time | 786.29 seconds |
Started | Mar 31 03:29:11 PM PDT 24 |
Finished | Mar 31 03:42:18 PM PDT 24 |
Peak memory | 330664 kb |
Host | smart-2f2d710e-1d75-440e-98f5-ff434833f1d5 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310187042 -assert nopo stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all_with_rand_reset.310187042 |
Directory | /workspace/8.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/8.otp_ctrl_test_access.1647780572 |
Short name | T802 |
Test name | |
Test status | |
Simulation time | 858845212 ps |
CPU time | 19.56 seconds |
Started | Mar 31 03:29:10 PM PDT 24 |
Finished | Mar 31 03:29:30 PM PDT 24 |
Peak memory | 248592 kb |
Host | smart-2f08ba2e-4308-41d6-b513-866763e4e503 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1647780572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.1647780572 |
Directory | /workspace/8.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/80.otp_ctrl_init_fail.1531405898 |
Short name | T1192 |
Test name | |
Test status | |
Simulation time | 2263614437 ps |
CPU time | 6.51 seconds |
Started | Mar 31 03:32:30 PM PDT 24 |
Finished | Mar 31 03:32:37 PM PDT 24 |
Peak memory | 241792 kb |
Host | smart-b53fd58e-7a6f-447b-ae87-ba624d0d01d8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1531405898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.1531405898 |
Directory | /workspace/80.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/80.otp_ctrl_parallel_lc_esc.3328759554 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 200705787 ps |
CPU time | 9.64 seconds |
Started | Mar 31 03:32:34 PM PDT 24 |
Finished | Mar 31 03:32:43 PM PDT 24 |
Peak memory | 241632 kb |
Host | smart-d359c8b0-1f73-40a4-9c7d-9b6a2b612628 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3328759554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.3328759554 |
Directory | /workspace/80.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/80.otp_ctrl_stress_all_with_rand_reset.2128141403 |
Short name | T644 |
Test name | |
Test status | |
Simulation time | 174666378494 ps |
CPU time | 2383.83 seconds |
Started | Mar 31 03:32:31 PM PDT 24 |
Finished | Mar 31 04:12:15 PM PDT 24 |
Peak memory | 352568 kb |
Host | smart-7ce03da6-0ee4-4c2e-ae74-9d3bbaa73e1d |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128141403 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_stress_all_with_rand_reset.2128141403 |
Directory | /workspace/80.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/81.otp_ctrl_init_fail.1755318998 |
Short name | T746 |
Test name | |
Test status | |
Simulation time | 477483968 ps |
CPU time | 4.56 seconds |
Started | Mar 31 03:32:35 PM PDT 24 |
Finished | Mar 31 03:32:40 PM PDT 24 |
Peak memory | 241632 kb |
Host | smart-c76b9968-a8b6-4402-9b3f-cc934fc1c2de |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1755318998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.1755318998 |
Directory | /workspace/81.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/81.otp_ctrl_parallel_lc_esc.3376330264 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 481788809 ps |
CPU time | 6.29 seconds |
Started | Mar 31 03:32:33 PM PDT 24 |
Finished | Mar 31 03:32:40 PM PDT 24 |
Peak memory | 241524 kb |
Host | smart-39176b15-ef93-4609-9ac3-fb126150a580 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3376330264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.3376330264 |
Directory | /workspace/81.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/82.otp_ctrl_init_fail.1334853337 |
Short name | T1093 |
Test name | |
Test status | |
Simulation time | 124387228 ps |
CPU time | 3.61 seconds |
Started | Mar 31 03:32:35 PM PDT 24 |
Finished | Mar 31 03:32:39 PM PDT 24 |
Peak memory | 241916 kb |
Host | smart-7cd7d23e-ccde-4d44-bdc0-619ba198252b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1334853337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.1334853337 |
Directory | /workspace/82.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/82.otp_ctrl_parallel_lc_esc.3974685477 |
Short name | T1152 |
Test name | |
Test status | |
Simulation time | 1067637374 ps |
CPU time | 14.41 seconds |
Started | Mar 31 03:32:39 PM PDT 24 |
Finished | Mar 31 03:32:54 PM PDT 24 |
Peak memory | 241760 kb |
Host | smart-f2ba0d41-5083-4d90-bb72-e37ca641bea4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3974685477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.3974685477 |
Directory | /workspace/82.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/83.otp_ctrl_init_fail.251230607 |
Short name | T1015 |
Test name | |
Test status | |
Simulation time | 354526669 ps |
CPU time | 3.3 seconds |
Started | Mar 31 03:32:37 PM PDT 24 |
Finished | Mar 31 03:32:40 PM PDT 24 |
Peak memory | 242060 kb |
Host | smart-f98e97e5-9dc4-4b16-961c-cf810b535566 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=251230607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.251230607 |
Directory | /workspace/83.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/83.otp_ctrl_parallel_lc_esc.3100416825 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 612585890 ps |
CPU time | 17.48 seconds |
Started | Mar 31 03:32:36 PM PDT 24 |
Finished | Mar 31 03:32:53 PM PDT 24 |
Peak memory | 241956 kb |
Host | smart-15f4aa5a-ac7a-457f-a66f-36b56b9c08fe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3100416825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.3100416825 |
Directory | /workspace/83.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/83.otp_ctrl_stress_all_with_rand_reset.2554985442 |
Short name | T1151 |
Test name | |
Test status | |
Simulation time | 290974707758 ps |
CPU time | 1054.12 seconds |
Started | Mar 31 03:32:39 PM PDT 24 |
Finished | Mar 31 03:50:13 PM PDT 24 |
Peak memory | 306136 kb |
Host | smart-38526176-4b30-4c83-9068-ecd9c596f91d |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554985442 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_stress_all_with_rand_reset.2554985442 |
Directory | /workspace/83.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/84.otp_ctrl_init_fail.1963805910 |
Short name | T966 |
Test name | |
Test status | |
Simulation time | 374950831 ps |
CPU time | 3.51 seconds |
Started | Mar 31 03:32:36 PM PDT 24 |
Finished | Mar 31 03:32:40 PM PDT 24 |
Peak memory | 241872 kb |
Host | smart-e5dc2b38-82f6-413a-8dc4-0ee052483ac0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1963805910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.1963805910 |
Directory | /workspace/84.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/84.otp_ctrl_parallel_lc_esc.1948761277 |
Short name | T988 |
Test name | |
Test status | |
Simulation time | 1584946329 ps |
CPU time | 10.85 seconds |
Started | Mar 31 03:32:35 PM PDT 24 |
Finished | Mar 31 03:32:46 PM PDT 24 |
Peak memory | 241772 kb |
Host | smart-efe307f8-7bdb-40e2-b72a-ec482886b53f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1948761277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.1948761277 |
Directory | /workspace/84.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/84.otp_ctrl_stress_all_with_rand_reset.931071274 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 116871111902 ps |
CPU time | 777.54 seconds |
Started | Mar 31 03:32:37 PM PDT 24 |
Finished | Mar 31 03:45:35 PM PDT 24 |
Peak memory | 337376 kb |
Host | smart-b6a4bc9a-bb31-4252-b65d-8df4d0de15f8 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931071274 -assert nopo stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_stress_all_with_rand_reset.931071274 |
Directory | /workspace/84.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/85.otp_ctrl_init_fail.2982886024 |
Short name | T787 |
Test name | |
Test status | |
Simulation time | 220851693 ps |
CPU time | 3.95 seconds |
Started | Mar 31 03:32:39 PM PDT 24 |
Finished | Mar 31 03:32:43 PM PDT 24 |
Peak memory | 241756 kb |
Host | smart-96d10466-8b3e-4742-84fe-59cc4772fc56 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2982886024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.2982886024 |
Directory | /workspace/85.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/85.otp_ctrl_parallel_lc_esc.3633532182 |
Short name | T520 |
Test name | |
Test status | |
Simulation time | 367532308 ps |
CPU time | 4.43 seconds |
Started | Mar 31 03:32:34 PM PDT 24 |
Finished | Mar 31 03:32:39 PM PDT 24 |
Peak memory | 241648 kb |
Host | smart-23807812-4cca-4b6d-a854-2095013f2017 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3633532182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.3633532182 |
Directory | /workspace/85.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/85.otp_ctrl_stress_all_with_rand_reset.3978491589 |
Short name | T1099 |
Test name | |
Test status | |
Simulation time | 138200192755 ps |
CPU time | 1516.42 seconds |
Started | Mar 31 03:32:39 PM PDT 24 |
Finished | Mar 31 03:57:55 PM PDT 24 |
Peak memory | 381532 kb |
Host | smart-53c696c2-b69a-4798-a567-22cdb81e6ebf |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978491589 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_stress_all_with_rand_reset.3978491589 |
Directory | /workspace/85.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/86.otp_ctrl_init_fail.2618963555 |
Short name | T785 |
Test name | |
Test status | |
Simulation time | 252285465 ps |
CPU time | 3.67 seconds |
Started | Mar 31 03:32:38 PM PDT 24 |
Finished | Mar 31 03:32:41 PM PDT 24 |
Peak memory | 241768 kb |
Host | smart-63c9df93-7712-4e38-b8d1-5928d1d8d8eb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2618963555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.2618963555 |
Directory | /workspace/86.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/86.otp_ctrl_parallel_lc_esc.3397760293 |
Short name | T581 |
Test name | |
Test status | |
Simulation time | 511115873 ps |
CPU time | 6.71 seconds |
Started | Mar 31 03:32:36 PM PDT 24 |
Finished | Mar 31 03:32:43 PM PDT 24 |
Peak memory | 241912 kb |
Host | smart-3e9fc619-2e8f-4a47-999f-80cdf60473af |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3397760293 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.3397760293 |
Directory | /workspace/86.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/86.otp_ctrl_stress_all_with_rand_reset.467391024 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 119876442700 ps |
CPU time | 957.99 seconds |
Started | Mar 31 03:32:35 PM PDT 24 |
Finished | Mar 31 03:48:33 PM PDT 24 |
Peak memory | 342032 kb |
Host | smart-0ac35194-e41b-4b39-8d46-b8c8686c02fa |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467391024 -assert nopo stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_stress_all_with_rand_reset.467391024 |
Directory | /workspace/86.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/87.otp_ctrl_init_fail.909465868 |
Short name | T453 |
Test name | |
Test status | |
Simulation time | 1853026248 ps |
CPU time | 3.55 seconds |
Started | Mar 31 03:32:39 PM PDT 24 |
Finished | Mar 31 03:32:43 PM PDT 24 |
Peak memory | 242068 kb |
Host | smart-bdb57089-7940-46e5-8350-a7998c611098 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=909465868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.909465868 |
Directory | /workspace/87.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/87.otp_ctrl_parallel_lc_esc.1101703104 |
Short name | T769 |
Test name | |
Test status | |
Simulation time | 1281973517 ps |
CPU time | 20.89 seconds |
Started | Mar 31 03:32:34 PM PDT 24 |
Finished | Mar 31 03:32:55 PM PDT 24 |
Peak memory | 241784 kb |
Host | smart-566a1898-a14d-4dfb-ae1f-fe146121e7ee |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1101703104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.1101703104 |
Directory | /workspace/87.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/88.otp_ctrl_init_fail.877823095 |
Short name | T974 |
Test name | |
Test status | |
Simulation time | 413288608 ps |
CPU time | 3.79 seconds |
Started | Mar 31 03:32:34 PM PDT 24 |
Finished | Mar 31 03:32:38 PM PDT 24 |
Peak memory | 241748 kb |
Host | smart-7a805f8b-eee6-41d8-b51a-daf544feaf3c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=877823095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.877823095 |
Directory | /workspace/88.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/88.otp_ctrl_stress_all_with_rand_reset.3416038327 |
Short name | T505 |
Test name | |
Test status | |
Simulation time | 94240048757 ps |
CPU time | 1401.79 seconds |
Started | Mar 31 03:32:34 PM PDT 24 |
Finished | Mar 31 03:55:56 PM PDT 24 |
Peak memory | 273232 kb |
Host | smart-4350a0e8-10eb-4c73-b0f4-a1a5289f4a2c |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416038327 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_stress_all_with_rand_reset.3416038327 |
Directory | /workspace/88.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/89.otp_ctrl_init_fail.220026899 |
Short name | T930 |
Test name | |
Test status | |
Simulation time | 174186995 ps |
CPU time | 3.24 seconds |
Started | Mar 31 03:32:34 PM PDT 24 |
Finished | Mar 31 03:32:38 PM PDT 24 |
Peak memory | 241788 kb |
Host | smart-fd2e12f7-36bd-4933-9bf6-837d9b048443 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=220026899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.220026899 |
Directory | /workspace/89.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/89.otp_ctrl_parallel_lc_esc.3116105593 |
Short name | T676 |
Test name | |
Test status | |
Simulation time | 169266903 ps |
CPU time | 7.69 seconds |
Started | Mar 31 03:32:37 PM PDT 24 |
Finished | Mar 31 03:32:45 PM PDT 24 |
Peak memory | 241624 kb |
Host | smart-8dcd63d8-5c43-4c12-84ae-0e9017f095a0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3116105593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.3116105593 |
Directory | /workspace/89.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/89.otp_ctrl_stress_all_with_rand_reset.2511682872 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 123026891980 ps |
CPU time | 537.15 seconds |
Started | Mar 31 03:32:40 PM PDT 24 |
Finished | Mar 31 03:41:37 PM PDT 24 |
Peak memory | 257240 kb |
Host | smart-83821ca5-f818-4b78-9622-8fbf01b98ea6 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511682872 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_stress_all_with_rand_reset.2511682872 |
Directory | /workspace/89.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/9.otp_ctrl_alert_test.2357532028 |
Short name | T588 |
Test name | |
Test status | |
Simulation time | 246103606 ps |
CPU time | 1.96 seconds |
Started | Mar 31 03:29:24 PM PDT 24 |
Finished | Mar 31 03:29:26 PM PDT 24 |
Peak memory | 240292 kb |
Host | smart-e2a4d533-664e-4a52-8400-ab5c4e1a0ead |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357532028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.2357532028 |
Directory | /workspace/9.otp_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/9.otp_ctrl_background_chks.2914775065 |
Short name | T1011 |
Test name | |
Test status | |
Simulation time | 4800308913 ps |
CPU time | 21.01 seconds |
Started | Mar 31 03:29:13 PM PDT 24 |
Finished | Mar 31 03:29:34 PM PDT 24 |
Peak memory | 242160 kb |
Host | smart-2c276b50-29ef-406a-a0b7-1bb07b0a6fb5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2914775065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.2914775065 |
Directory | /workspace/9.otp_ctrl_background_chks/latest |
Test location | /workspace/coverage/default/9.otp_ctrl_check_fail.2582810505 |
Short name | T1083 |
Test name | |
Test status | |
Simulation time | 598132217 ps |
CPU time | 7.95 seconds |
Started | Mar 31 03:29:16 PM PDT 24 |
Finished | Mar 31 03:29:24 PM PDT 24 |
Peak memory | 247876 kb |
Host | smart-fb39ec93-23b5-4714-82a8-45d3f47fad92 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2582810505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.2582810505 |
Directory | /workspace/9.otp_ctrl_check_fail/latest |
Test location | /workspace/coverage/default/9.otp_ctrl_dai_errs.2073474045 |
Short name | T512 |
Test name | |
Test status | |
Simulation time | 281249870 ps |
CPU time | 9.94 seconds |
Started | Mar 31 03:29:14 PM PDT 24 |
Finished | Mar 31 03:29:25 PM PDT 24 |
Peak memory | 241684 kb |
Host | smart-c11144e1-1688-4b68-a8e9-81200ff919c9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2073474045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.2073474045 |
Directory | /workspace/9.otp_ctrl_dai_errs/latest |
Test location | /workspace/coverage/default/9.otp_ctrl_dai_lock.2633976065 |
Short name | T693 |
Test name | |
Test status | |
Simulation time | 302090584 ps |
CPU time | 10 seconds |
Started | Mar 31 03:29:15 PM PDT 24 |
Finished | Mar 31 03:29:25 PM PDT 24 |
Peak memory | 242232 kb |
Host | smart-43b988ad-16e5-43c8-b4cc-86195a54bf73 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2633976065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.2633976065 |
Directory | /workspace/9.otp_ctrl_dai_lock/latest |
Test location | /workspace/coverage/default/9.otp_ctrl_init_fail.3621660675 |
Short name | T992 |
Test name | |
Test status | |
Simulation time | 388319190 ps |
CPU time | 3.5 seconds |
Started | Mar 31 03:29:14 PM PDT 24 |
Finished | Mar 31 03:29:18 PM PDT 24 |
Peak memory | 241736 kb |
Host | smart-b7e874ac-f4bf-4c2f-86ad-f837f72a09f0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3621660675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.3621660675 |
Directory | /workspace/9.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/9.otp_ctrl_macro_errs.857988099 |
Short name | T735 |
Test name | |
Test status | |
Simulation time | 9804685359 ps |
CPU time | 31.09 seconds |
Started | Mar 31 03:29:15 PM PDT 24 |
Finished | Mar 31 03:29:46 PM PDT 24 |
Peak memory | 242116 kb |
Host | smart-e09d03ca-7317-49a8-9a04-638af09678b8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=857988099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.857988099 |
Directory | /workspace/9.otp_ctrl_macro_errs/latest |
Test location | /workspace/coverage/default/9.otp_ctrl_parallel_key_req.2501606643 |
Short name | T844 |
Test name | |
Test status | |
Simulation time | 617612195 ps |
CPU time | 16.71 seconds |
Started | Mar 31 03:29:17 PM PDT 24 |
Finished | Mar 31 03:29:34 PM PDT 24 |
Peak memory | 242180 kb |
Host | smart-78b7869f-75b2-40f7-bc3a-98eed14d375c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2501606643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.2501606643 |
Directory | /workspace/9.otp_ctrl_parallel_key_req/latest |
Test location | /workspace/coverage/default/9.otp_ctrl_parallel_lc_esc.3771162617 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 451156007 ps |
CPU time | 6.24 seconds |
Started | Mar 31 03:29:14 PM PDT 24 |
Finished | Mar 31 03:29:21 PM PDT 24 |
Peak memory | 241620 kb |
Host | smart-8283ff7c-a458-47fd-8cbc-d0d2abe18d54 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3771162617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.3771162617 |
Directory | /workspace/9.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/9.otp_ctrl_parallel_lc_req.3739244842 |
Short name | T710 |
Test name | |
Test status | |
Simulation time | 725200831 ps |
CPU time | 23.36 seconds |
Started | Mar 31 03:29:16 PM PDT 24 |
Finished | Mar 31 03:29:40 PM PDT 24 |
Peak memory | 241896 kb |
Host | smart-ab1e1e77-8f4b-4bc2-9a46-dd8ba91389e6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3739244842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.3739244842 |
Directory | /workspace/9.otp_ctrl_parallel_lc_req/latest |
Test location | /workspace/coverage/default/9.otp_ctrl_regwen.1455160547 |
Short name | T944 |
Test name | |
Test status | |
Simulation time | 724668586 ps |
CPU time | 8.18 seconds |
Started | Mar 31 03:29:14 PM PDT 24 |
Finished | Mar 31 03:29:23 PM PDT 24 |
Peak memory | 241864 kb |
Host | smart-5b61d2ee-47d4-4913-a8e0-bea7316641b8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1455160547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.1455160547 |
Directory | /workspace/9.otp_ctrl_regwen/latest |
Test location | /workspace/coverage/default/9.otp_ctrl_smoke.2592498473 |
Short name | T558 |
Test name | |
Test status | |
Simulation time | 753666823 ps |
CPU time | 12.06 seconds |
Started | Mar 31 03:29:17 PM PDT 24 |
Finished | Mar 31 03:29:29 PM PDT 24 |
Peak memory | 242032 kb |
Host | smart-790894d6-ca7b-41ae-89da-b164a4e40aca |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2592498473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.2592498473 |
Directory | /workspace/9.otp_ctrl_smoke/latest |
Test location | /workspace/coverage/default/9.otp_ctrl_stress_all.1179717786 |
Short name | T708 |
Test name | |
Test status | |
Simulation time | 10799751216 ps |
CPU time | 97.54 seconds |
Started | Mar 31 03:29:21 PM PDT 24 |
Finished | Mar 31 03:30:59 PM PDT 24 |
Peak memory | 256824 kb |
Host | smart-77836dbd-31f6-43b3-9ee5-c2b68a3a6c4c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179717786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all. 1179717786 |
Directory | /workspace/9.otp_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/9.otp_ctrl_stress_all_with_rand_reset.1410941524 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 63517134508 ps |
CPU time | 1695.16 seconds |
Started | Mar 31 03:29:19 PM PDT 24 |
Finished | Mar 31 03:57:34 PM PDT 24 |
Peak memory | 347152 kb |
Host | smart-56678556-d589-43d3-b516-636e6c1ed5a5 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410941524 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all_with_rand_reset.1410941524 |
Directory | /workspace/9.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/9.otp_ctrl_test_access.3453962479 |
Short name | T984 |
Test name | |
Test status | |
Simulation time | 2026856393 ps |
CPU time | 24.38 seconds |
Started | Mar 31 03:29:14 PM PDT 24 |
Finished | Mar 31 03:29:39 PM PDT 24 |
Peak memory | 243124 kb |
Host | smart-fa986c45-0b46-4ee2-8052-1ff7b922c3e5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3453962479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.3453962479 |
Directory | /workspace/9.otp_ctrl_test_access/latest |
Test location | /workspace/coverage/default/90.otp_ctrl_init_fail.2294852721 |
Short name | T873 |
Test name | |
Test status | |
Simulation time | 328308051 ps |
CPU time | 4.03 seconds |
Started | Mar 31 03:32:45 PM PDT 24 |
Finished | Mar 31 03:32:49 PM PDT 24 |
Peak memory | 241988 kb |
Host | smart-66601fed-9250-42da-ab50-9f587cb92e06 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2294852721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.2294852721 |
Directory | /workspace/90.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/90.otp_ctrl_parallel_lc_esc.221223460 |
Short name | T783 |
Test name | |
Test status | |
Simulation time | 1997723872 ps |
CPU time | 22.21 seconds |
Started | Mar 31 03:32:41 PM PDT 24 |
Finished | Mar 31 03:33:04 PM PDT 24 |
Peak memory | 241828 kb |
Host | smart-bc134585-9bbd-4473-aa22-27cd80bf72c4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=221223460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.221223460 |
Directory | /workspace/90.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/90.otp_ctrl_stress_all_with_rand_reset.4149210781 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 1114490184441 ps |
CPU time | 2049.12 seconds |
Started | Mar 31 03:32:42 PM PDT 24 |
Finished | Mar 31 04:06:51 PM PDT 24 |
Peak memory | 260368 kb |
Host | smart-48a98b73-b2a1-430a-a090-06016385d51e |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149210781 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_stress_all_with_rand_reset.4149210781 |
Directory | /workspace/90.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/91.otp_ctrl_init_fail.1585681095 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 2110523409 ps |
CPU time | 4.57 seconds |
Started | Mar 31 03:32:43 PM PDT 24 |
Finished | Mar 31 03:32:47 PM PDT 24 |
Peak memory | 241812 kb |
Host | smart-3ebe2660-f06d-475d-85b9-39171fc1a5a8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1585681095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.1585681095 |
Directory | /workspace/91.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/91.otp_ctrl_stress_all_with_rand_reset.783294069 |
Short name | T1014 |
Test name | |
Test status | |
Simulation time | 15785504651 ps |
CPU time | 479.87 seconds |
Started | Mar 31 03:32:42 PM PDT 24 |
Finished | Mar 31 03:40:42 PM PDT 24 |
Peak memory | 256976 kb |
Host | smart-fdc8f536-c5cb-4264-9576-efdbb3e2c4c0 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783294069 -assert nopo stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_stress_all_with_rand_reset.783294069 |
Directory | /workspace/91.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/92.otp_ctrl_init_fail.3516268176 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 253283751 ps |
CPU time | 3.96 seconds |
Started | Mar 31 03:32:44 PM PDT 24 |
Finished | Mar 31 03:32:48 PM PDT 24 |
Peak memory | 242004 kb |
Host | smart-7a00fbd9-db73-409a-873b-9193314dd281 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3516268176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.3516268176 |
Directory | /workspace/92.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/92.otp_ctrl_parallel_lc_esc.3579860229 |
Short name | T919 |
Test name | |
Test status | |
Simulation time | 3027896102 ps |
CPU time | 9.81 seconds |
Started | Mar 31 03:32:42 PM PDT 24 |
Finished | Mar 31 03:32:52 PM PDT 24 |
Peak memory | 241776 kb |
Host | smart-180b31dc-da37-479c-bb96-e300d3157ca6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3579860229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.3579860229 |
Directory | /workspace/92.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/92.otp_ctrl_stress_all_with_rand_reset.1771741348 |
Short name | T959 |
Test name | |
Test status | |
Simulation time | 24319659972 ps |
CPU time | 600.67 seconds |
Started | Mar 31 03:32:42 PM PDT 24 |
Finished | Mar 31 03:42:43 PM PDT 24 |
Peak memory | 256972 kb |
Host | smart-cc5164af-67d8-4bac-a64b-2897467840b8 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771741348 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_stress_all_with_rand_reset.1771741348 |
Directory | /workspace/92.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/93.otp_ctrl_init_fail.4121971916 |
Short name | T983 |
Test name | |
Test status | |
Simulation time | 427279866 ps |
CPU time | 4.22 seconds |
Started | Mar 31 03:32:44 PM PDT 24 |
Finished | Mar 31 03:32:48 PM PDT 24 |
Peak memory | 241656 kb |
Host | smart-a508b43f-794a-4123-82eb-00c41e4f7095 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4121971916 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.4121971916 |
Directory | /workspace/93.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/93.otp_ctrl_parallel_lc_esc.4019812708 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 5288367127 ps |
CPU time | 14.38 seconds |
Started | Mar 31 03:32:42 PM PDT 24 |
Finished | Mar 31 03:32:57 PM PDT 24 |
Peak memory | 241788 kb |
Host | smart-8a2b098f-aca4-41ec-abee-cd0512bfe7db |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4019812708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.4019812708 |
Directory | /workspace/93.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/93.otp_ctrl_stress_all_with_rand_reset.1856591241 |
Short name | T776 |
Test name | |
Test status | |
Simulation time | 43058657280 ps |
CPU time | 619.16 seconds |
Started | Mar 31 03:32:43 PM PDT 24 |
Finished | Mar 31 03:43:02 PM PDT 24 |
Peak memory | 263956 kb |
Host | smart-c41297f2-45d7-4922-b84d-ec4f5d875c94 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856591241 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_stress_all_with_rand_reset.1856591241 |
Directory | /workspace/93.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/94.otp_ctrl_init_fail.1519671961 |
Short name | T766 |
Test name | |
Test status | |
Simulation time | 2019017665 ps |
CPU time | 6.05 seconds |
Started | Mar 31 03:32:51 PM PDT 24 |
Finished | Mar 31 03:32:58 PM PDT 24 |
Peak memory | 241740 kb |
Host | smart-4cd4ca8c-9cd9-4b55-a705-42ce56083c3e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1519671961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.1519671961 |
Directory | /workspace/94.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/94.otp_ctrl_parallel_lc_esc.1070568134 |
Short name | T633 |
Test name | |
Test status | |
Simulation time | 219183221 ps |
CPU time | 12.45 seconds |
Started | Mar 31 03:32:53 PM PDT 24 |
Finished | Mar 31 03:33:05 PM PDT 24 |
Peak memory | 241624 kb |
Host | smart-5d7c3206-6b4b-46c9-a3a9-6e466fc4bdfa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1070568134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.1070568134 |
Directory | /workspace/94.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.2315811177 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 97438047657 ps |
CPU time | 764.51 seconds |
Started | Mar 31 03:32:51 PM PDT 24 |
Finished | Mar 31 03:45:35 PM PDT 24 |
Peak memory | 259724 kb |
Host | smart-09c5f144-a5da-4916-a33b-5800900c4310 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315811177 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_stress_all_with_rand_reset.2315811177 |
Directory | /workspace/94.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/95.otp_ctrl_init_fail.3755016311 |
Short name | T572 |
Test name | |
Test status | |
Simulation time | 408113120 ps |
CPU time | 3.73 seconds |
Started | Mar 31 03:32:51 PM PDT 24 |
Finished | Mar 31 03:32:54 PM PDT 24 |
Peak memory | 242080 kb |
Host | smart-ab53cbf9-c3ca-4079-bab7-8dd2e8bea7fb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3755016311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.3755016311 |
Directory | /workspace/95.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/95.otp_ctrl_parallel_lc_esc.2973410826 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 8468829899 ps |
CPU time | 19.42 seconds |
Started | Mar 31 03:32:52 PM PDT 24 |
Finished | Mar 31 03:33:12 PM PDT 24 |
Peak memory | 241756 kb |
Host | smart-3524ebab-ca3c-4508-b6d7-dab0ff82f620 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2973410826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.2973410826 |
Directory | /workspace/95.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/95.otp_ctrl_stress_all_with_rand_reset.573539104 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 37791912617 ps |
CPU time | 895.46 seconds |
Started | Mar 31 03:32:51 PM PDT 24 |
Finished | Mar 31 03:47:46 PM PDT 24 |
Peak memory | 444496 kb |
Host | smart-930a7313-5610-4ee3-a426-0342f5189c27 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573539104 -assert nopo stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_stress_all_with_rand_reset.573539104 |
Directory | /workspace/95.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/96.otp_ctrl_init_fail.662733999 |
Short name | T519 |
Test name | |
Test status | |
Simulation time | 282713193 ps |
CPU time | 4.24 seconds |
Started | Mar 31 03:32:51 PM PDT 24 |
Finished | Mar 31 03:32:55 PM PDT 24 |
Peak memory | 241704 kb |
Host | smart-799f3fc5-d536-4d68-8200-caf384ad26b3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=662733999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.662733999 |
Directory | /workspace/96.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/96.otp_ctrl_parallel_lc_esc.1705343367 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 274333988 ps |
CPU time | 7.66 seconds |
Started | Mar 31 03:32:52 PM PDT 24 |
Finished | Mar 31 03:33:00 PM PDT 24 |
Peak memory | 242044 kb |
Host | smart-a71f7777-63b3-4fda-b44b-7623dccf3b6d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1705343367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.1705343367 |
Directory | /workspace/96.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/96.otp_ctrl_stress_all_with_rand_reset.1134669983 |
Short name | T839 |
Test name | |
Test status | |
Simulation time | 109573039535 ps |
CPU time | 932.17 seconds |
Started | Mar 31 03:32:53 PM PDT 24 |
Finished | Mar 31 03:48:26 PM PDT 24 |
Peak memory | 361792 kb |
Host | smart-c3b97618-aca1-4c55-b7c9-3957820eec60 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134669983 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_stress_all_with_rand_reset.1134669983 |
Directory | /workspace/96.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/97.otp_ctrl_init_fail.238240073 |
Short name | T657 |
Test name | |
Test status | |
Simulation time | 265545248 ps |
CPU time | 4.91 seconds |
Started | Mar 31 03:32:52 PM PDT 24 |
Finished | Mar 31 03:32:57 PM PDT 24 |
Peak memory | 241648 kb |
Host | smart-7a18e118-6c64-42a5-b1f8-ee50e4c82551 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=238240073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.238240073 |
Directory | /workspace/97.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/97.otp_ctrl_parallel_lc_esc.1781339883 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 250403609 ps |
CPU time | 9.87 seconds |
Started | Mar 31 03:32:51 PM PDT 24 |
Finished | Mar 31 03:33:01 PM PDT 24 |
Peak memory | 241784 kb |
Host | smart-c2cd11e3-dae2-4168-9af5-ce6a893ef443 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1781339883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.1781339883 |
Directory | /workspace/97.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/97.otp_ctrl_stress_all_with_rand_reset.178386888 |
Short name | T997 |
Test name | |
Test status | |
Simulation time | 44089811250 ps |
CPU time | 954.78 seconds |
Started | Mar 31 03:32:51 PM PDT 24 |
Finished | Mar 31 03:48:46 PM PDT 24 |
Peak memory | 250460 kb |
Host | smart-aa665279-d013-46a9-b7aa-a214e2c03943 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178386888 -assert nopo stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_stress_all_with_rand_reset.178386888 |
Directory | /workspace/97.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/98.otp_ctrl_init_fail.313997504 |
Short name | T733 |
Test name | |
Test status | |
Simulation time | 124465925 ps |
CPU time | 3.46 seconds |
Started | Mar 31 03:32:52 PM PDT 24 |
Finished | Mar 31 03:32:55 PM PDT 24 |
Peak memory | 242044 kb |
Host | smart-c539d249-256c-4096-88a7-ca2a8a809083 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=313997504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.313997504 |
Directory | /workspace/98.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/98.otp_ctrl_parallel_lc_esc.3054581690 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 1369902389 ps |
CPU time | 12.67 seconds |
Started | Mar 31 03:32:53 PM PDT 24 |
Finished | Mar 31 03:33:06 PM PDT 24 |
Peak memory | 241964 kb |
Host | smart-f7876c19-128f-4a44-90d3-44c8d27d14f2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3054581690 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.3054581690 |
Directory | /workspace/98.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.899985251 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 156898874189 ps |
CPU time | 2307.18 seconds |
Started | Mar 31 03:32:52 PM PDT 24 |
Finished | Mar 31 04:11:20 PM PDT 24 |
Peak memory | 362180 kb |
Host | smart-c2d091d5-fb12-4e91-827e-88d761574628 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899985251 -assert nopo stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_stress_all_with_rand_reset.899985251 |
Directory | /workspace/98.otp_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/99.otp_ctrl_init_fail.4090946113 |
Short name | T1092 |
Test name | |
Test status | |
Simulation time | 554612786 ps |
CPU time | 5.15 seconds |
Started | Mar 31 03:32:52 PM PDT 24 |
Finished | Mar 31 03:32:57 PM PDT 24 |
Peak memory | 241600 kb |
Host | smart-6780c18c-d921-44e5-807d-17b20eda8e53 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4090946113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.4090946113 |
Directory | /workspace/99.otp_ctrl_init_fail/latest |
Test location | /workspace/coverage/default/99.otp_ctrl_parallel_lc_esc.2032641207 |
Short name | T1095 |
Test name | |
Test status | |
Simulation time | 138163311 ps |
CPU time | 4.81 seconds |
Started | Mar 31 03:32:53 PM PDT 24 |
Finished | Mar 31 03:32:58 PM PDT 24 |
Peak memory | 242000 kb |
Host | smart-9067148d-60da-4ea0-9edc-3974af27171a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2032641207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.2032641207 |
Directory | /workspace/99.otp_ctrl_parallel_lc_esc/latest |
Test location | /workspace/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.3043647403 |
Short name | T529 |
Test name | |
Test status | |
Simulation time | 77988208010 ps |
CPU time | 2036.36 seconds |
Started | Mar 31 03:32:51 PM PDT 24 |
Finished | Mar 31 04:06:48 PM PDT 24 |
Peak memory | 357600 kb |
Host | smart-0cf85f80-3c25-4e2d-8a91-bd84dadb301e |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043647403 -assert nop ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_stress_all_with_rand_reset.3043647403 |
Directory | /workspace/99.otp_ctrl_stress_all_with_rand_reset/latest |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |