Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

28741040

1

T1

3457

T2

3961

T3

1076

full_word

9197790

1

T1

2305

T2

923

T3

598

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	37938540	1			T1	5762		T2	4884		T3	1674
auto[TlIntgErrCmd]	97	1			T273	3		T274	8		T275	2
auto[TlIntgErrData]	92	1			T273	3		T274	3		T275	4
auto[TlIntgErrBoth]	101	1			T273	4		T274	9		T275	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10182751

1

T1

5275

T2

4341

T3

1515

auto[1]

27756079

1

T1

487

T2

543

T3

159

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6372104	1			T1	3196		T2	3653		T3	997
auto[TlIntgErrNone]	partial	auto[1]	22368667	1			T1	261		T2	308		T3	79
auto[TlIntgErrNone]	full_word	auto[0]	3810522	1			T1	2079		T2	688		T3	518
auto[TlIntgErrNone]	full_word	auto[1]	5387247	1			T1	226		T2	235		T3	80
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T273	2		T274	5		T282	2
auto[TlIntgErrCmd]	partial	auto[1]	54	1			T273	1		T274	2		T275	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T386	1		T387	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T274	1		T386	1		T384	1
auto[TlIntgErrData]	partial	auto[0]	39	1			T273	2		T274	1		T282	1
auto[TlIntgErrData]	partial	auto[1]	47	1			T273	1		T274	2		T275	3
auto[TlIntgErrData]	full_word	auto[0]	1	1			T388	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1			T275	1		T282	1		T281	1
auto[TlIntgErrBoth]	partial	auto[0]	46	1			T273	2		T274	4		T275	2
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T273	2		T274	4		T275	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T274	1		T389	1		T388	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T282	1		T384	1		T390	1