Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.87	97.40	96.15	97.18		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	512366123	9365977	0	0
check_regwen_rd_A	512366123	2202	0	0
check_timeout_rd_A	512366123	1863	0	0
check_trigger_regwen_rd_A	512366123	2228	0	0
consistency_check_period_rd_A	512366123	2357	0	0
creator_sw_cfg_read_lock_rd_A	512366123	1821	0	0
direct_access_address_rd_A	512366123	1600	0	0
direct_access_wdata_0_rd_A	512366123	1057	0	0
direct_access_wdata_1_rd_A	512366123	1210	0	0
integrity_check_period_rd_A	512366123	2188	0	0
intr_enable_rd_A	512366123	3203	0	0
owner_sw_cfg_read_lock_rd_A	512366123	1738	0	0
rot_creator_auth_codesign_read_lock_rd_A	512366123	1781	0	0
rot_creator_auth_state_read_lock_rd_A	512366123	1852	0	0
vendor_test_read_lock_rd_A	512366123	1829	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512366123	9365977	0	0
T5	680511	152518	0	0
T6	0	101931	0	0
T8	14826	0	0	0
T9	35394	0	0	0
T10	28216	0	0	0
T11	24404	0	0	0
T12	0	106818	0	0
T15	0	26788	0	0
T16	0	237218	0	0
T17	0	60811	0	0
T60	8637	0	0	0
T73	0	23635	0	0
T102	129607	0	0	0
T110	21045	0	0	0
T111	30133	0	0	0
T116	31845	0	0	0
T141	0	308258	0	0
T172	0	104687	0	0
T231	0	90788	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512366123	2202	0	0
T19	0	153	0	0
T51	13204	0	0	0
T84	14597	0	0	0
T183	84024	0	0	0
T189	0	75	0	0
T232	31152	0	0	0
T234	13525	0	0	0
T258	21823	0	0	0
T260	547191	112	0	0
T291	0	44	0	0
T292	0	41	0	0
T351	0	18	0	0
T355	0	55	0	0
T356	0	32	0	0
T357	0	83	0	0
T358	0	76	0	0
T359	12740	0	0	0
T360	35807	0	0	0
T361	10704	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512366123	1863	0	0
T19	0	137	0	0
T51	13204	0	0	0
T84	14597	0	0	0
T183	84024	0	0	0
T189	0	105	0	0
T232	31152	0	0	0
T234	13525	0	0	0
T258	21823	0	0	0
T260	547191	83	0	0
T291	0	70	0	0
T292	0	19	0	0
T351	0	46	0	0
T355	0	23	0	0
T356	0	61	0	0
T357	0	54	0	0
T358	0	51	0	0
T359	12740	0	0	0
T360	35807	0	0	0
T361	10704	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512366123	2228	0	0
T19	0	147	0	0
T51	13204	0	0	0
T84	14597	0	0	0
T183	84024	0	0	0
T189	0	115	0	0
T232	31152	0	0	0
T234	13525	0	0	0
T258	21823	0	0	0
T260	547191	105	0	0
T291	0	71	0	0
T292	0	46	0	0
T351	0	59	0	0
T355	0	34	0	0
T356	0	89	0	0
T357	0	42	0	0
T358	0	31	0	0
T359	12740	0	0	0
T360	35807	0	0	0
T361	10704	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512366123	2357	0	0
T19	0	173	0	0
T51	13204	0	0	0
T84	14597	0	0	0
T183	84024	0	0	0
T189	0	76	0	0
T232	31152	0	0	0
T234	13525	0	0	0
T258	21823	0	0	0
T260	547191	131	0	0
T291	0	57	0	0
T292	0	39	0	0
T351	0	57	0	0
T355	0	52	0	0
T356	0	83	0	0
T357	0	68	0	0
T358	0	73	0	0
T359	12740	0	0	0
T360	35807	0	0	0
T361	10704	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512366123	1821	0	0
T19	0	136	0	0
T51	13204	0	0	0
T84	14597	0	0	0
T183	84024	0	0	0
T189	0	101	0	0
T232	31152	0	0	0
T234	13525	0	0	0
T258	21823	0	0	0
T260	547191	105	0	0
T291	0	80	0	0
T292	0	71	0	0
T351	0	24	0	0
T355	0	32	0	0
T356	0	92	0	0
T357	0	60	0	0
T358	0	63	0	0
T359	12740	0	0	0
T360	35807	0	0	0
T361	10704	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512366123	1600	0	0
T19	0	174	0	0
T51	13204	0	0	0
T84	14597	0	0	0
T183	84024	0	0	0
T189	0	69	0	0
T232	31152	0	0	0
T234	13525	0	0	0
T258	21823	0	0	0
T260	547191	156	0	0
T291	0	69	0	0
T292	0	35	0	0
T351	0	57	0	0
T355	0	26	0	0
T356	0	58	0	0
T357	0	89	0	0
T358	0	70	0	0
T359	12740	0	0	0
T360	35807	0	0	0
T361	10704	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512366123	1057	0	0
T19	0	173	0	0
T51	13204	0	0	0
T84	14597	0	0	0
T183	84024	0	0	0
T189	0	68	0	0
T232	31152	0	0	0
T234	13525	0	0	0
T258	21823	0	0	0
T260	547191	82	0	0
T291	0	48	0	0
T292	0	13	0	0
T351	0	20	0	0
T355	0	13	0	0
T356	0	43	0	0
T357	0	58	0	0
T358	0	33	0	0
T359	12740	0	0	0
T360	35807	0	0	0
T361	10704	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512366123	1210	0	0
T19	0	178	0	0
T51	13204	0	0	0
T84	14597	0	0	0
T183	84024	0	0	0
T189	0	102	0	0
T232	31152	0	0	0
T234	13525	0	0	0
T258	21823	0	0	0
T260	547191	113	0	0
T291	0	50	0	0
T292	0	19	0	0
T351	0	62	0	0
T355	0	24	0	0
T356	0	45	0	0
T357	0	74	0	0
T358	0	37	0	0
T359	12740	0	0	0
T360	35807	0	0	0
T361	10704	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512366123	2188	0	0
T19	0	106	0	0
T51	13204	0	0	0
T84	14597	0	0	0
T183	84024	0	0	0
T189	0	41	0	0
T232	31152	0	0	0
T234	13525	0	0	0
T258	21823	0	0	0
T260	547191	135	0	0
T291	0	82	0	0
T292	0	31	0	0
T351	0	77	0	0
T355	0	38	0	0
T356	0	65	0	0
T357	0	52	0	0
T358	0	27	0	0
T359	12740	0	0	0
T360	35807	0	0	0
T361	10704	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512366123	3203	0	0
T12	466100	0	0	0
T15	848118	0	0	0
T19	0	120	0	0
T66	138408	31	0	0
T67	94022	0	0	0
T103	141580	0	0	0
T104	181967	0	0	0
T172	461199	0	0	0
T189	0	92	0	0
T194	0	19	0	0
T240	23745	0	0	0
T244	5522	0	0	0
T245	6683	0	0	0
T260	0	121	0	0
T261	0	20	0	0
T351	0	113	0	0
T362	0	65	0	0
T363	0	31	0	0
T364	0	10	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512366123	1738	0	0
T19	0	164	0	0
T51	13204	0	0	0
T84	14597	0	0	0
T183	84024	0	0	0
T189	0	93	0	0
T232	31152	0	0	0
T234	13525	0	0	0
T258	21823	0	0	0
T260	547191	147	0	0
T291	0	43	0	0
T292	0	27	0	0
T351	0	79	0	0
T355	0	21	0	0
T356	0	51	0	0
T357	0	102	0	0
T358	0	60	0	0
T359	12740	0	0	0
T360	35807	0	0	0
T361	10704	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512366123	1781	0	0
T19	0	136	0	0
T51	13204	0	0	0
T84	14597	0	0	0
T183	84024	0	0	0
T189	0	115	0	0
T232	31152	0	0	0
T234	13525	0	0	0
T258	21823	0	0	0
T260	547191	168	0	0
T291	0	65	0	0
T292	0	39	0	0
T351	0	37	0	0
T355	0	40	0	0
T356	0	72	0	0
T357	0	68	0	0
T358	0	54	0	0
T359	12740	0	0	0
T360	35807	0	0	0
T361	10704	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512366123	1852	0	0
T19	0	155	0	0
T51	13204	0	0	0
T84	14597	0	0	0
T183	84024	0	0	0
T189	0	64	0	0
T232	31152	0	0	0
T234	13525	0	0	0
T258	21823	0	0	0
T260	547191	146	0	0
T291	0	47	0	0
T292	0	44	0	0
T351	0	46	0	0
T355	0	31	0	0
T356	0	72	0	0
T357	0	76	0	0
T358	0	40	0	0
T359	12740	0	0	0
T360	35807	0	0	0
T361	10704	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512366123	1829	0	0
T19	0	127	0	0
T51	13204	0	0	0
T84	14597	0	0	0
T183	84024	0	0	0
T189	0	80	0	0
T232	31152	0	0	0
T234	13525	0	0	0
T258	21823	0	0	0
T260	547191	113	0	0
T291	0	65	0	0
T292	0	22	0	0
T351	0	40	0	0
T355	0	48	0	0
T356	0	59	0	0
T357	0	69	0	0
T358	0	51	0	0
T359	12740	0	0	0
T360	35807	0	0	0
T361	10704	0	0	0