Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.23	100.00	100.00		90.00	100.00	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.56	100.00	100.00	100.00	90.00	98.15	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.87	97.40	96.15	97.18		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.87	97.40	96.15	97.18		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.87	97.40	96.15	97.18		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		86	86	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	61	61	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
153	1	1
154	1	1
156	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			==> MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
224		excluded
			Exclude Annotation: VC_COV_UNR
225		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
276		excluded
			Exclude Annotation: VC_COV_UNR
277		excluded
			Exclude Annotation: VC_COV_UNR
279		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
339	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T20,T21,T22

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T175,T176
1	Covered	T175,T176

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T7

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T7

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	11	84.62
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T4,T5
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T4,T5
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T214,T215
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T216,T217,T218
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T2,T4,T7
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Not Covered
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T75,T76,T77
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests	Exclude Annotation
AccessError	256	Covered	T2,T4,T7
CheckFailError	317	Covered	T175,T176
FsmStateError	289	Covered	T1,T4,T5
MacroEccCorrError	221	Excluded		VC_COV_UNR
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded
AccessError->FsmStateError	325	Covered	T4,T6,T13
AccessError->MacroEccCorrError	221	Excluded
AccessError->NoError	235	Covered	T2,T4,T7
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded
CheckFailError->NoError	235	Covered	T175,T176
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded
FsmStateError->NoError	235	Covered	T1,T4,T5
MacroEccCorrError->AccessError	256	Excluded
MacroEccCorrError->CheckFailError	317	Excluded
MacroEccCorrError->FsmStateError	325	Excluded
MacroEccCorrError->NoError	235	Excluded
NoError->AccessError	256	Covered	T2,T4,T7
NoError->CheckFailError	317	Covered	T175,T176
NoError->FsmStateError	289	Covered	T1,T4,T5
NoError->MacroEccCorrError	221	Excluded

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	18	18	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests	Exclude Annotation
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T2,T116,T14
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T4,T7
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T21,T22
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T4,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T4,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T4,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T4,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T175,T176
1	0	Covered	T175,T176
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:

-1-	Status	Tests
1	Covered	T4,T60,T61
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	509547780	508684599	0	0
DigestKnown_A	509547780	508684599	0	0
DigestOffsetMustBeRepresentable_A	1155	1155	0	0
EccErrorState_A	509547780	5344	0	0
ErrorKnown_A	509547780	508684599	0	0
FsmStateKnown_A	509547780	508684599	0	0
InitDoneKnown_A	509547780	508684599	0	0
InitReadLocksPartition_A	509547780	103092509	0	0
InitWriteLocksPartition_A	509547780	103092509	0	0
OffsetMustBeBlockAligned_A	1155	1155	0	0
OtpAddrKnown_A	509547780	508684599	0	0
OtpCmdKnown_A	509547780	508684599	0	0
OtpErrorState_A	509547780	0	0	0
OtpReqKnown_A	509547780	508684599	0	0
OtpSizeKnown_A	509547780	508684599	0	0
OtpWdataKnown_A	509547780	508684599	0	0
ReadLockPropagation_A	509547780	218156459	0	0
SizeMustBeBlockAligned_A	1155	1155	0	0
TlulGntKnown_A	509547780	508684599	0	0
TlulRdataKnown_A	509547780	508684599	0	0
TlulReadOnReadLock_A	509547780	7751	0	0
TlulRerrorKnown_A	509547780	508684599	0	0
TlulRvalidKnown_A	509547780	508684599	0	0
WriteLockPropagation_A	509547780	3054781	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	509547780	38899082	0	0
u_state_regs_A	509547780	508684599	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	5344	0	0
T27	73932	0	0	0
T48	56729	0	0	0
T52	13067	0	0	0
T92	10769	0	0	0
T175	14236	2593	0	0
T176	0	2751	0	0
T192	20515	0	0	0
T193	13250	0	0	0
T194	106830	0	0	0
T195	4704	0	0	0
T196	9558	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	103092509	0	0
T1	20059	10779	0	0
T2	50350	686	0	0
T3	22720	120	0	0
T4	702871	70797	0	0
T5	680511	42799	0	0
T7	182916	696	0	0
T8	14826	7666	0	0
T9	35394	473	0	0
T10	28216	266	0	0
T11	24404	391	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	103092509	0	0
T1	20059	10779	0	0
T2	50350	686	0	0
T3	22720	120	0	0
T4	702871	70797	0	0
T5	680511	42799	0	0
T7	182916	696	0	0
T8	14826	7666	0	0
T9	35394	473	0	0
T10	28216	266	0	0
T11	24404	391	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	218156459	0	0
T2	50350	3240	0	0
T3	22720	0	0	0
T4	702871	132665	0	0
T5	680511	530511	0	0
T6	0	228176	0	0
T7	182916	102548	0	0
T8	14826	0	0	0
T9	35394	4804	0	0
T10	28216	0	0	0
T11	24404	7595	0	0
T13	0	40042	0	0
T14	0	102840	0	0
T102	0	13669	0	0
T110	21045	0	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	7751	0	0
T1	20059	7	0	0
T2	50350	3	0	0
T3	22720	0	0	0
T4	702871	34	0	0
T5	680511	21	0	0
T7	182916	14	0	0
T8	14826	1	0	0
T9	35394	7	0	0
T10	28216	0	0	0
T11	24404	0	0	0
T102	0	1	0	0
T110	0	8	0	0
T210	0	13	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	3054781	0	0
T4	702871	33937	0	0
T5	680511	0	0	0
T7	182916	29628	0	0
T8	14826	0	0	0
T9	35394	4112	0	0
T10	28216	0	0	0
T11	24404	0	0	0
T14	0	20447	0	0
T60	8637	0	0	0
T66	0	41498	0	0
T74	0	4077	0	0
T102	0	13763	0	0
T104	0	35819	0	0
T107	0	2253	0	0
T110	21045	0	0	0
T111	30133	0	0	0
T113	0	4678	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	38899082	0	0
T2	50350	43479	0	0
T3	22720	0	0	0
T4	702871	342695	0	0
T5	680511	0	0	0
T7	182916	159396	0	0
T8	14826	0	0	0
T9	35394	25697	0	0
T10	28216	0	0	0
T11	24404	8124	0	0
T14	0	300362	0	0
T62	0	4006	0	0
T66	0	729888	0	0
T102	0	116530	0	0
T110	21045	0	0	0
T182	0	3145	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T60,T177,T83

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T113,T130,T174

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T20,T21,T22

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T165,T175,T178
1	Covered	T165,T175,T178

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T7

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T7

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T4,T5
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T3,T4
ReadWaitSt	252	Covered	T2,T3,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T4,T5
IdleSt->ReadSt	236	Covered	T2,T3,T4
InitSt->ErrorSt	315	Covered	T216,T217,T218
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T61,T62,T182
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T2,T4,T7
ReadSt->ReadWaitSt	252	Covered	T2,T3,T4
ReadWaitSt->ErrorSt	276	Covered	T144,T145,T183
ReadWaitSt->IdleSt	270	Covered	T2,T3,T4
ResetSt->ErrorSt	315	Covered	T75,T76,T77
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T2,T4,T7
CheckFailError	317	Covered	T165,T175,T178
FsmStateError	289	Covered	T1,T4,T5
MacroEccCorrError	221	Covered	T60,T177,T113
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T6,T13,T14
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T2,T4,T7
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T165,T175,T178
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T4,T5
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T60,T177,T83
MacroEccCorrError->NoError	235	Covered	T113,T130,T85
NoError->AccessError	256	Covered	T2,T4,T7
NoError->CheckFailError	317	Covered	T165,T175,T178
NoError->FsmStateError	289	Covered	T1,T4,T5
NoError->MacroEccCorrError	221	Covered	T60,T177,T113

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T60,T177,T83
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T61,T62,T182
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T2,T14,T66
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T4,T7
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T113,T130,T174
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T144,T145,T183
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T21,T22
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T4,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T4,T110
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T4,T110
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T4,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T165,T175,T178
1	0	Covered	T165,T175,T178
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	509547780	508684599	0	0
DigestKnown_A	509547780	508684599	0	0
DigestOffsetMustBeRepresentable_A	1155	1155	0	0
EccErrorState_A	509547780	13037	0	0
ErrorKnown_A	509547780	508684599	0	0
FsmStateKnown_A	509547780	508684599	0	0
InitDoneKnown_A	509547780	508684599	0	0
InitReadLocksPartition_A	509547780	103274918	0	0
InitWriteLocksPartition_A	509547780	103274918	0	0
OffsetMustBeBlockAligned_A	1155	1155	0	0
OtpAddrKnown_A	509547780	508684599	0	0
OtpCmdKnown_A	509547780	508684599	0	0
OtpErrorState_A	509547780	77	0	0
OtpReqKnown_A	509547780	508684599	0	0
OtpSizeKnown_A	509547780	508684599	0	0
OtpWdataKnown_A	509547780	508684599	0	0
ReadLockPropagation_A	509547780	221025197	0	0
SizeMustBeBlockAligned_A	1155	1155	0	0
TlulGntKnown_A	509547780	508684599	0	0
TlulRdataKnown_A	509547780	508684599	0	0
TlulReadOnReadLock_A	509547780	8277	0	0
TlulRerrorKnown_A	509547780	508684599	0	0
TlulRvalidKnown_A	509547780	508684599	0	0
WriteLockPropagation_A	509547780	2875446	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	509547780	38009002	0	0
u_state_regs_A	509547780	508684599	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	13037	0	0
T47	13819	0	0	0
T165	16841	2532	0	0
T175	0	2593	0	0
T176	0	2751	0	0
T178	0	2777	0	0
T181	0	2384	0	0
T184	17536	0	0	0
T185	15841	0	0	0
T186	493571	0	0	0
T187	17111	0	0	0
T188	84456	0	0	0
T189	995350	0	0	0
T190	11373	0	0	0
T191	27007	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	103274918	0	0
T1	20059	10847	0	0
T2	50350	890	0	0
T3	22720	154	0	0
T4	702871	72395	0	0
T5	680511	42901	0	0
T7	182916	917	0	0
T8	14826	7700	0	0
T9	35394	626	0	0
T10	28216	368	0	0
T11	24404	442	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	103274918	0	0
T1	20059	10847	0	0
T2	50350	890	0	0
T3	22720	154	0	0
T4	702871	72395	0	0
T5	680511	42901	0	0
T7	182916	917	0	0
T8	14826	7700	0	0
T9	35394	626	0	0
T10	28216	368	0	0
T11	24404	442	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	77	0	0
T6	400463	0	0	0
T13	46542	0	0	0
T14	592874	0	0	0
T49	13882	0	0	0
T61	12333	1	0	0
T62	10562	1	0	0
T63	11267	0	0	0
T119	28127	0	0	0
T144	13223	1	0	0
T145	0	1	0	0
T182	11744	1	0	0
T197	0	1	0	0
T199	0	1	0	0
T200	0	1	0	0
T201	0	1	0	0
T202	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	221025197	0	0
T2	50350	1925	0	0
T3	22720	0	0	0
T4	702871	66257	0	0
T5	680511	532823	0	0
T6	0	228205	0	0
T7	182916	70116	0	0
T8	14826	0	0	0
T9	35394	4210	0	0
T10	28216	0	0	0
T11	24404	7589	0	0
T13	0	40033	0	0
T102	0	24197	0	0
T110	21045	0	0	0
T116	0	1542	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	8277	0	0
T1	20059	10	0	0
T2	50350	1	0	0
T3	22720	0	0	0
T4	702871	33	0	0
T5	680511	25	0	0
T7	182916	15	0	0
T8	14826	0	0	0
T9	35394	4	0	0
T10	28216	0	0	0
T11	24404	2	0	0
T102	0	2	0	0
T110	0	5	0	0
T210	0	8	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	2875446	0	0
T4	702871	37319	0	0
T5	680511	0	0	0
T7	182916	13671	0	0
T8	14826	0	0	0
T9	35394	0	0	0
T10	28216	0	0	0
T11	24404	0	0	0
T14	0	19000	0	0
T26	0	8923	0	0
T60	8637	0	0	0
T66	0	51364	0	0
T71	0	2677	0	0
T102	0	11447	0	0
T103	0	10314	0	0
T104	0	18165	0	0
T106	0	5804	0	0
T110	21045	0	0	0
T111	30133	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	38009002	0	0
T2	50350	43309	0	0
T3	22720	0	0	0
T4	702871	403080	0	0
T5	680511	0	0	0
T7	182916	159209	0	0
T8	14826	0	0	0
T9	35394	25578	0	0
T10	28216	0	0	0
T11	24404	8107	0	0
T61	0	2573	0	0
T62	0	4001	0	0
T102	0	116377	0	0
T110	21045	0	0	0
T116	0	23443	0	0
T182	0	3140	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T63,T65,T179

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T67,T145,T81

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T20,T21,T22

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T175,T180,T181
1	Covered	T175,T180,T181

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00111101000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T7

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T7

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T4,T5
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T3,T4
ReadWaitSt	252	Covered	T2,T3,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T4,T5
IdleSt->ReadSt	236	Covered	T2,T3,T4
InitSt->ErrorSt	315	Covered	T216,T217,T218
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T60,T61,T62
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T2,T4,T7
ReadSt->ReadWaitSt	252	Covered	T2,T3,T4
ReadWaitSt->ErrorSt	276	Covered	T205,T219,T220
ReadWaitSt->IdleSt	270	Covered	T2,T3,T4
ResetSt->ErrorSt	315	Covered	T75,T76,T77
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T2,T4,T7
CheckFailError	317	Covered	T175,T180,T181
FsmStateError	289	Covered	T1,T4,T5
MacroEccCorrError	221	Covered	T63,T67,T145
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T4,T6,T14
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T2,T4,T7
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T175,T180,T181
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T4,T5
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T63,T145,T65
MacroEccCorrError->NoError	235	Covered	T67,T81,T113
NoError->AccessError	256	Covered	T2,T4,T7
NoError->CheckFailError	317	Covered	T175,T180,T181
NoError->FsmStateError	289	Covered	T1,T4,T5
NoError->MacroEccCorrError	221	Covered	T63,T67,T145

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T63,T65,T179
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T60,T198,T177
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T2,T5,T116
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T4,T7
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T67,T145,T81
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T205,T219,T220
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T21,T22
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T4,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T4,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T4,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T4,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T175,T180,T181
1	0	Covered	T175,T180,T181
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	509547780	508684599	0	0
DigestKnown_A	509547780	508684599	0	0
DigestOffsetMustBeRepresentable_A	1155	1155	0	0
EccErrorState_A	509547780	10191	0	0
ErrorKnown_A	509547780	508684599	0	0
FsmStateKnown_A	509547780	508684599	0	0
InitDoneKnown_A	509547780	508684599	0	0
InitReadLocksPartition_A	509547780	103456092	0	0
InitWriteLocksPartition_A	509547780	103456092	0	0
OffsetMustBeBlockAligned_A	1155	1155	0	0
OtpAddrKnown_A	509547780	508684599	0	0
OtpCmdKnown_A	509547780	508684599	0	0
OtpErrorState_A	509547780	44	0	0
OtpReqKnown_A	509547780	508684599	0	0
OtpSizeKnown_A	509547780	508684599	0	0
OtpWdataKnown_A	509547780	508684599	0	0
ReadLockPropagation_A	509547780	221588562	0	0
SizeMustBeBlockAligned_A	1155	1155	0	0
TlulGntKnown_A	509547780	508684599	0	0
TlulRdataKnown_A	509547780	508684599	0	0
TlulReadOnReadLock_A	509547780	8286	0	0
TlulRerrorKnown_A	509547780	508684599	0	0
TlulRvalidKnown_A	509547780	508684599	0	0
WriteLockPropagation_A	509547780	2891201	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	509547780	27692776	0	0
u_state_regs_A	509547780	508684599	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	10191	0	0
T27	73932	0	0	0
T48	56729	0	0	0
T52	13067	0	0	0
T92	10769	0	0	0
T175	14236	2593	0	0
T176	0	2751	0	0
T180	0	2463	0	0
T181	0	2384	0	0
T192	20515	0	0	0
T193	13250	0	0	0
T194	106830	0	0	0
T195	4704	0	0	0
T196	9558	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	103456092	0	0
T1	20059	10915	0	0
T2	50350	1094	0	0
T3	22720	188	0	0
T4	702871	73991	0	0
T5	680511	43003	0	0
T7	182916	1138	0	0
T8	14826	7734	0	0
T9	35394	779	0	0
T10	28216	470	0	0
T11	24404	493	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	103456092	0	0
T1	20059	10915	0	0
T2	50350	1094	0	0
T3	22720	188	0	0
T4	702871	73991	0	0
T5	680511	43003	0	0
T7	182916	1138	0	0
T8	14826	7734	0	0
T9	35394	779	0	0
T10	28216	470	0	0
T11	24404	493	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	44	0	0
T60	8637	1	0	0
T61	12333	0	0	0
T102	129607	0	0	0
T111	30133	0	0	0
T116	31845	0	0	0
T117	13964	0	0	0
T118	32380	0	0	0
T169	98105	0	0	0
T177	0	1	0	0
T198	0	1	0	0
T203	0	1	0	0
T204	0	1	0	0
T205	0	1	0	0
T206	0	1	0	0
T207	0	1	0	0
T208	0	1	0	0
T209	0	1	0	0
T210	60921	0	0	0
T211	12163	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	221588562	0	0
T2	50350	3290	0	0
T3	22720	0	0	0
T4	702871	133212	0	0
T5	680511	533059	0	0
T6	0	228519	0	0
T7	182916	105660	0	0
T8	14826	0	0	0
T9	35394	4386	0	0
T10	28216	0	0	0
T11	24404	7578	0	0
T13	0	35635	0	0
T102	0	20996	0	0
T110	21045	0	0	0
T116	0	1275	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	8286	0	0
T1	20059	11	0	0
T2	50350	3	0	0
T3	22720	0	0	0
T4	702871	38	0	0
T5	680511	17	0	0
T7	182916	15	0	0
T8	14826	1	0	0
T9	35394	1	0	0
T10	28216	0	0	0
T11	24404	2	0	0
T102	0	6	0	0
T110	0	6	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	2891201	0	0
T2	50350	3161	0	0
T3	22720	0	0	0
T4	702871	14697	0	0
T5	680511	0	0	0
T7	182916	0	0	0
T8	14826	0	0	0
T9	35394	0	0	0
T10	28216	0	0	0
T11	24404	0	0	0
T14	0	1730	0	0
T66	0	75143	0	0
T74	0	19108	0	0
T104	0	14183	0	0
T106	0	2452	0	0
T107	0	1262	0	0
T110	21045	0	0	0
T112	0	10123	0	0
T213	0	17544	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	27692776	0	0
T2	50350	43139	0	0
T3	22720	0	0	0
T4	702871	217361	0	0
T5	680511	0	0	0
T7	182916	159022	0	0
T8	14826	0	0	0
T9	35394	18881	0	0
T10	28216	0	0	0
T11	24404	0	0	0
T14	0	130150	0	0
T60	0	3524	0	0
T64	0	6758	0	0
T66	0	728426	0	0
T102	0	116224	0	0
T104	0	148141	0	0
T110	21045	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509547780	508684599	0	0
T1	20059	19787	0	0
T2	50350	49535	0	0
T3	22720	22539	0	0
T4	702871	694880	0	0
T5	680511	680502	0	0
T7	182916	181757	0	0
T8	14826	14606	0	0
T9	35394	34724	0	0
T10	28216	27685	0	0
T11	24404	24161	0	0