Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

26217490

1

T1

1440

T2

3553

T3

5722

full_word

8476596

1

T1

200

T2

1047

T3

684

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	34693776	1			T1	1640		T2	4600		T3	6406
auto[TlIntgErrCmd]	100	1			T276	5		T277	8		T278	4
auto[TlIntgErrData]	104	1			T276	7		T277	6		T278	7
auto[TlIntgErrBoth]	106	1			T276	8		T277	6		T278	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9680536

1

T1

1550

T2

4313

T3

5963

auto[1]

25013550

1

T1

90

T2

287

T3

443

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6091650	1			T1	1389		T2	3397		T3	5463
auto[TlIntgErrNone]	partial	auto[1]	20125558	1			T1	51		T2	156		T3	259
auto[TlIntgErrNone]	full_word	auto[0]	3588741	1			T1	161		T2	916		T3	500
auto[TlIntgErrNone]	full_word	auto[1]	4887827	1			T1	39		T2	131		T3	184
auto[TlIntgErrCmd]	partial	auto[0]	47	1			T276	4		T277	1		T278	2
auto[TlIntgErrCmd]	partial	auto[1]	45	1			T276	1		T277	6		T278	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T277	1		T371	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T278	1		T286	1		T372	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T276	3		T277	1		T278	3
auto[TlIntgErrData]	partial	auto[1]	42	1			T276	3		T277	3		T278	4
auto[TlIntgErrData]	full_word	auto[0]	6	1			T277	1		T283	1		T373	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T276	1		T277	1		T286	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T277	4		T278	4		T286	2
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T276	6		T277	2		T278	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T276	1		T373	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T276	1		T278	2		T372	1