Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.93	98.05	96.15	96.83		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	459508376	8400578	0	0
check_regwen_rd_A	459508376	3183	0	0
check_timeout_rd_A	459508376	2659	0	0
check_trigger_regwen_rd_A	459508376	2991	0	0
consistency_check_period_rd_A	459508376	3497	0	0
creator_sw_cfg_read_lock_rd_A	459508376	2560	0	0
direct_access_address_rd_A	459508376	2409	0	0
direct_access_wdata_0_rd_A	459508376	1625	0	0
direct_access_wdata_1_rd_A	459508376	1731	0	0
integrity_check_period_rd_A	459508376	3421	0	0
intr_enable_rd_A	459508376	4194	0	0
owner_sw_cfg_read_lock_rd_A	459508376	2550	0	0
rot_creator_auth_codesign_read_lock_rd_A	459508376	2741	0	0
rot_creator_auth_state_read_lock_rd_A	459508376	2470	0	0
vendor_test_read_lock_rd_A	459508376	2514	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459508376	8400578	0	0
T4	271386	52443	0	0
T8	58009	0	0	0
T9	19724	0	0	0
T10	28826	0	0	0
T11	17700	0	0	0
T12	68623	0	0	0
T13	0	68733	0	0
T14	0	100402	0	0
T18	16739	0	0	0
T22	0	79352	0	0
T23	0	125334	0	0
T24	0	244734	0	0
T25	0	36026	0	0
T73	0	77640	0	0
T77	28477	0	0	0
T116	16067	0	0	0
T117	31668	0	0	0
T267	0	64598	0	0
T288	0	69057	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459508376	3183	0	0
T4	271386	76	0	0
T8	58009	0	0	0
T9	19724	0	0	0
T10	28826	0	0	0
T11	17700	0	0	0
T12	68623	0	0	0
T18	16739	0	0	0
T22	0	44	0	0
T26	0	100	0	0
T73	0	78	0	0
T77	28477	0	0	0
T116	16067	0	0	0
T117	31668	0	0	0
T267	0	104	0	0
T298	0	121	0	0
T350	0	157	0	0
T351	0	64	0	0
T352	0	109	0	0
T353	0	49	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459508376	2659	0	0
T4	271386	79	0	0
T8	58009	0	0	0
T9	19724	0	0	0
T10	28826	0	0	0
T11	17700	0	0	0
T12	68623	0	0	0
T18	16739	0	0	0
T22	0	59	0	0
T26	0	88	0	0
T73	0	120	0	0
T77	28477	0	0	0
T116	16067	0	0	0
T117	31668	0	0	0
T267	0	98	0	0
T298	0	74	0	0
T350	0	245	0	0
T351	0	53	0	0
T352	0	107	0	0
T353	0	52	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459508376	2991	0	0
T4	271386	75	0	0
T8	58009	0	0	0
T9	19724	0	0	0
T10	28826	0	0	0
T11	17700	0	0	0
T12	68623	0	0	0
T18	16739	0	0	0
T22	0	77	0	0
T26	0	67	0	0
T73	0	74	0	0
T77	28477	0	0	0
T116	16067	0	0	0
T117	31668	0	0	0
T267	0	47	0	0
T298	0	94	0	0
T350	0	132	0	0
T351	0	58	0	0
T352	0	81	0	0
T353	0	45	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459508376	3497	0	0
T4	271386	82	0	0
T8	58009	0	0	0
T9	19724	0	0	0
T10	28826	0	0	0
T11	17700	0	0	0
T12	68623	0	0	0
T18	16739	0	0	0
T22	0	64	0	0
T26	0	92	0	0
T73	0	137	0	0
T77	28477	0	0	0
T116	16067	0	0	0
T117	31668	0	0	0
T267	0	68	0	0
T298	0	129	0	0
T350	0	274	0	0
T351	0	84	0	0
T352	0	82	0	0
T353	0	55	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459508376	2560	0	0
T4	271386	84	0	0
T8	58009	0	0	0
T9	19724	0	0	0
T10	28826	0	0	0
T11	17700	0	0	0
T12	68623	0	0	0
T18	16739	0	0	0
T22	0	61	0	0
T26	0	64	0	0
T73	0	79	0	0
T77	28477	0	0	0
T116	16067	0	0	0
T117	31668	0	0	0
T267	0	65	0	0
T298	0	152	0	0
T350	0	157	0	0
T351	0	73	0	0
T352	0	95	0	0
T353	0	60	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459508376	2409	0	0
T4	271386	89	0	0
T8	58009	0	0	0
T9	19724	0	0	0
T10	28826	0	0	0
T11	17700	0	0	0
T12	68623	0	0	0
T18	16739	0	0	0
T22	0	82	0	0
T26	0	68	0	0
T73	0	111	0	0
T77	28477	0	0	0
T116	16067	0	0	0
T117	31668	0	0	0
T267	0	65	0	0
T298	0	172	0	0
T350	0	173	0	0
T351	0	97	0	0
T352	0	64	0	0
T353	0	61	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459508376	1625	0	0
T4	271386	40	0	0
T8	58009	0	0	0
T9	19724	0	0	0
T10	28826	0	0	0
T11	17700	0	0	0
T12	68623	0	0	0
T18	16739	0	0	0
T22	0	52	0	0
T26	0	49	0	0
T73	0	63	0	0
T77	28477	0	0	0
T116	16067	0	0	0
T117	31668	0	0	0
T267	0	55	0	0
T298	0	53	0	0
T350	0	112	0	0
T351	0	96	0	0
T352	0	97	0	0
T353	0	42	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459508376	1731	0	0
T4	271386	81	0	0
T8	58009	0	0	0
T9	19724	0	0	0
T10	28826	0	0	0
T11	17700	0	0	0
T12	68623	0	0	0
T18	16739	0	0	0
T22	0	35	0	0
T26	0	57	0	0
T73	0	77	0	0
T77	28477	0	0	0
T116	16067	0	0	0
T117	31668	0	0	0
T267	0	88	0	0
T298	0	82	0	0
T350	0	147	0	0
T351	0	46	0	0
T352	0	65	0	0
T353	0	28	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459508376	3421	0	0
T4	271386	104	0	0
T8	58009	0	0	0
T9	19724	0	0	0
T10	28826	0	0	0
T11	17700	0	0	0
T12	68623	0	0	0
T18	16739	0	0	0
T22	0	38	0	0
T26	0	109	0	0
T73	0	87	0	0
T77	28477	0	0	0
T116	16067	0	0	0
T117	31668	0	0	0
T267	0	78	0	0
T298	0	109	0	0
T350	0	170	0	0
T351	0	99	0	0
T352	0	78	0	0
T353	0	64	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459508376	4194	0	0
T4	271386	68	0	0
T8	58009	0	0	0
T9	19724	0	0	0
T10	28826	0	0	0
T11	17700	0	0	0
T12	68623	0	0	0
T18	16739	0	0	0
T22	0	51	0	0
T73	0	95	0	0
T74	0	27	0	0
T77	28477	0	0	0
T116	16067	0	0	0
T117	31668	0	0	0
T236	0	69	0	0
T246	0	28	0	0
T267	0	112	0	0
T282	0	13	0	0
T354	0	28	0	0
T355	0	26	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459508376	2550	0	0
T4	271386	62	0	0
T8	58009	0	0	0
T9	19724	0	0	0
T10	28826	0	0	0
T11	17700	0	0	0
T12	68623	0	0	0
T18	16739	0	0	0
T22	0	79	0	0
T26	0	62	0	0
T73	0	90	0	0
T77	28477	0	0	0
T116	16067	0	0	0
T117	31668	0	0	0
T267	0	55	0	0
T298	0	101	0	0
T350	0	194	0	0
T351	0	86	0	0
T352	0	90	0	0
T353	0	52	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459508376	2741	0	0
T4	271386	48	0	0
T8	58009	0	0	0
T9	19724	0	0	0
T10	28826	0	0	0
T11	17700	0	0	0
T12	68623	0	0	0
T18	16739	0	0	0
T22	0	62	0	0
T26	0	103	0	0
T73	0	118	0	0
T77	28477	0	0	0
T116	16067	0	0	0
T117	31668	0	0	0
T267	0	73	0	0
T298	0	102	0	0
T350	0	215	0	0
T351	0	71	0	0
T352	0	88	0	0
T353	0	63	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459508376	2470	0	0
T4	271386	84	0	0
T8	58009	0	0	0
T9	19724	0	0	0
T10	28826	0	0	0
T11	17700	0	0	0
T12	68623	0	0	0
T18	16739	0	0	0
T22	0	63	0	0
T26	0	70	0	0
T73	0	107	0	0
T77	28477	0	0	0
T116	16067	0	0	0
T117	31668	0	0	0
T267	0	64	0	0
T298	0	100	0	0
T350	0	171	0	0
T351	0	70	0	0
T352	0	67	0	0
T353	0	58	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459508376	2514	0	0
T4	271386	112	0	0
T8	58009	0	0	0
T9	19724	0	0	0
T10	28826	0	0	0
T11	17700	0	0	0
T12	68623	0	0	0
T18	16739	0	0	0
T22	0	70	0	0
T26	0	77	0	0
T73	0	76	0	0
T77	28477	0	0	0
T116	16067	0	0	0
T117	31668	0	0	0
T267	0	79	0	0
T298	0	72	0	0
T350	0	210	0	0
T351	0	66	0	0
T352	0	120	0	0
T353	0	58	0	0