Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.93	98.05	96.15	96.83		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.93	98.05	96.15	96.83		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T32,T76,T149

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T79,T144,T150

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T9,T18
1	Covered	T29,T30,T31

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T151,T152
1	Covered	T151,T152

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T9,T18
1	Covered	T4,T9,T18

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T8
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T8,T11

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T8,T11

---

FSM Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T4,T9,T18
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T4,T9,T18
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T127,T109,T194
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T78,T173,T156
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T3,T4,T8
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Covered	T158,T197,T198
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T84,T86,T87
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T3,T4,T8
CheckFailError	317	Covered	T151,T152
FsmStateError	289	Covered	T4,T9,T18
MacroEccCorrError	221	Covered	T32,T79,T76
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T17,T154,T84
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T3,T4,T8
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T151,T152
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T4,T9,T18
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T32,T76,T149
MacroEccCorrError->NoError	235	Covered	T79,T144,T150
NoError->AccessError	256	Covered	T3,T4,T8
NoError->CheckFailError	317	Covered	T151,T152
NoError->FsmStateError	289	Covered	T4,T9,T18
NoError->MacroEccCorrError	221	Covered	T32,T79,T76

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T32,T76,T149
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T173,T156,T157
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T8,T12,T111
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T4,T8
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T79,T144,T150
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T158,T197,T198
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T29,T30,T31
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T4,T9,T18
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T4,T9,T18
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T4,T9,T18
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T4,T9,T18
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T151,T152
1	0	Covered	T151,T152
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T4,T9,T18
1	0	Covered	T4,T9,T18
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	456392311	455538305	0	0
DigestKnown_A	456392311	455538305	0	0
DigestOffsetMustBeRepresentable_A	1149	1149	0	0
EccErrorState_A	456392311	6967	0	0
ErrorKnown_A	456392311	455538305	0	0
FsmStateKnown_A	456392311	455538305	0	0
InitDoneKnown_A	456392311	455538305	0	0
InitReadLocksPartition_A	456392311	84711115	0	0
InitWriteLocksPartition_A	456392311	84711115	0	0
OffsetMustBeBlockAligned_A	1149	1149	0	0
OtpAddrKnown_A	456392311	455538305	0	0
OtpCmdKnown_A	456392311	455538305	0	0
OtpErrorState_A	456392311	46	0	0
OtpReqKnown_A	456392311	455538305	0	0
OtpSizeKnown_A	456392311	455538305	0	0
OtpWdataKnown_A	456392311	455538305	0	0
ReadLockPropagation_A	456392311	190893527	0	0
SizeMustBeBlockAligned_A	1149	1149	0	0
TlulGntKnown_A	456392311	455538305	0	0
TlulRdataKnown_A	456392311	455538305	0	0
TlulReadOnReadLock_A	456392311	8013	0	0
TlulRerrorKnown_A	456392311	455538305	0	0
TlulRvalidKnown_A	456392311	455538305	0	0
WriteLockPropagation_A	456392311	2023713	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	456392311	25024893	0	0
u_state_regs_A	456392311	455538305	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	455538305	0	0
T1	9162	8772	0	0
T2	29294	28790	0	0
T3	113810	112571	0	0
T4	271386	271375	0	0
T5	6289	6233	0	0
T8	58009	56885	0	0
T9	19724	19504	0	0
T10	28826	28250	0	0
T11	17700	17262	0	0
T12	68623	67593	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	455538305	0	0
T1	9162	8772	0	0
T2	29294	28790	0	0
T3	113810	112571	0	0
T4	271386	271375	0	0
T5	6289	6233	0	0
T8	58009	56885	0	0
T9	19724	19504	0	0
T10	28826	28250	0	0
T11	17700	17262	0	0
T12	68623	67593	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	6967	0	0
T151	12075	3336	0	0
T152	12204	3631	0	0
T164	537026	0	0	0
T165	94480	0	0	0
T166	12002	0	0	0
T167	39898	0	0	0
T168	9198	0	0	0
T169	18858	0	0	0
T170	13742	0	0	0
T199	15357	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	455538305	0	0
T1	9162	8772	0	0
T2	29294	28790	0	0
T3	113810	112571	0	0
T4	271386	271375	0	0
T5	6289	6233	0	0
T8	58009	56885	0	0
T9	19724	19504	0	0
T10	28826	28250	0	0
T11	17700	17262	0	0
T12	68623	67593	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	455538305	0	0
T1	9162	8772	0	0
T2	29294	28790	0	0
T3	113810	112571	0	0
T4	271386	271375	0	0
T5	6289	6233	0	0
T8	58009	56885	0	0
T9	19724	19504	0	0
T10	28826	28250	0	0
T11	17700	17262	0	0
T12	68623	67593	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	455538305	0	0
T1	9162	8772	0	0
T2	29294	28790	0	0
T3	113810	112571	0	0
T4	271386	271375	0	0
T5	6289	6233	0	0
T8	58009	56885	0	0
T9	19724	19504	0	0
T10	28826	28250	0	0
T11	17700	17262	0	0
T12	68623	67593	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	84711115	0	0
T1	9162	365	0	0
T2	29294	717	0	0
T3	113810	19393	0	0
T4	271386	538999	0	0
T5	6289	192	0	0
T8	58009	1355	0	0
T9	19724	11870	0	0
T10	28826	1357	0	0
T11	17700	320	0	0
T12	68623	1595	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	84711115	0	0
T1	9162	365	0	0
T2	29294	717	0	0
T3	113810	19393	0	0
T4	271386	538999	0	0
T5	6289	192	0	0
T8	58009	1355	0	0
T9	19724	11870	0	0
T10	28826	1357	0	0
T11	17700	320	0	0
T12	68623	1595	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	455538305	0	0
T1	9162	8772	0	0
T2	29294	28790	0	0
T3	113810	112571	0	0
T4	271386	271375	0	0
T5	6289	6233	0	0
T8	58009	56885	0	0
T9	19724	19504	0	0
T10	28826	28250	0	0
T11	17700	17262	0	0
T12	68623	67593	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	455538305	0	0
T1	9162	8772	0	0
T2	29294	28790	0	0
T3	113810	112571	0	0
T4	271386	271375	0	0
T5	6289	6233	0	0
T8	58009	56885	0	0
T9	19724	19504	0	0
T10	28826	28250	0	0
T11	17700	17262	0	0
T12	68623	67593	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	46	0	0
T13	326814	0	0	0
T52	10759	0	0	0
T85	18404	0	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T168	0	1	0	0
T173	19568	1	0	0
T194	16896	0	0	0
T197	0	1	0	0
T198	0	1	0	0
T200	0	1	0	0
T201	0	1	0	0
T202	0	1	0	0
T203	3864	0	0	0
T204	26075	0	0	0
T205	18999	0	0	0
T206	69848	0	0	0
T207	18582	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	455538305	0	0
T1	9162	8772	0	0
T2	29294	28790	0	0
T3	113810	112571	0	0
T4	271386	271375	0	0
T5	6289	6233	0	0
T8	58009	56885	0	0
T9	19724	19504	0	0
T10	28826	28250	0	0
T11	17700	17262	0	0
T12	68623	67593	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	455538305	0	0
T1	9162	8772	0	0
T2	29294	28790	0	0
T3	113810	112571	0	0
T4	271386	271375	0	0
T5	6289	6233	0	0
T8	58009	56885	0	0
T9	19724	19504	0	0
T10	28826	28250	0	0
T11	17700	17262	0	0
T12	68623	67593	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	455538305	0	0
T1	9162	8772	0	0
T2	29294	28790	0	0
T3	113810	112571	0	0
T4	271386	271375	0	0
T5	6289	6233	0	0
T8	58009	56885	0	0
T9	19724	19504	0	0
T10	28826	28250	0	0
T11	17700	17262	0	0
T12	68623	67593	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	190893527	0	0
T3	113810	2310	0	0
T4	271386	730628	0	0
T5	6289	0	0	0
T8	58009	7110	0	0
T9	19724	0	0	0
T10	28826	0	0	0
T11	17700	1788	0	0
T12	68623	6974	0	0
T16	0	52282	0	0
T17	0	44381	0	0
T18	16739	0	0	0
T77	0	2540	0	0
T111	0	5282	0	0
T116	16067	9636	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	455538305	0	0
T1	9162	8772	0	0
T2	29294	28790	0	0
T3	113810	112571	0	0
T4	271386	271375	0	0
T5	6289	6233	0	0
T8	58009	56885	0	0
T9	19724	19504	0	0
T10	28826	28250	0	0
T11	17700	17262	0	0
T12	68623	67593	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	455538305	0	0
T1	9162	8772	0	0
T2	29294	28790	0	0
T3	113810	112571	0	0
T4	271386	271375	0	0
T5	6289	6233	0	0
T8	58009	56885	0	0
T9	19724	19504	0	0
T10	28826	28250	0	0
T11	17700	17262	0	0
T12	68623	67593	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	8013	0	0
T3	113810	1	0	0
T4	271386	29	0	0
T5	6289	0	0	0
T8	58009	11	0	0
T9	19724	13	0	0
T10	28826	0	0	0
T11	17700	0	0	0
T12	68623	5	0	0
T16	0	15	0	0
T17	0	17	0	0
T18	16739	2	0	0
T77	0	18	0	0
T116	16067	4	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	455538305	0	0
T1	9162	8772	0	0
T2	29294	28790	0	0
T3	113810	112571	0	0
T4	271386	271375	0	0
T5	6289	6233	0	0
T8	58009	56885	0	0
T9	19724	19504	0	0
T10	28826	28250	0	0
T11	17700	17262	0	0
T12	68623	67593	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	455538305	0	0
T1	9162	8772	0	0
T2	29294	28790	0	0
T3	113810	112571	0	0
T4	271386	271375	0	0
T5	6289	6233	0	0
T8	58009	56885	0	0
T9	19724	19504	0	0
T10	28826	28250	0	0
T11	17700	17262	0	0
T12	68623	67593	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	2023713	0	0
T3	113810	19067	0	0
T4	271386	0	0	0
T5	6289	0	0	0
T7	0	13458	0	0
T8	58009	3035	0	0
T9	19724	0	0	0
T10	28826	0	0	0
T11	17700	0	0	0
T12	68623	3488	0	0
T16	0	25329	0	0
T18	16739	0	0	0
T20	0	1961	0	0
T21	0	45821	0	0
T104	0	1043	0	0
T106	0	7711	0	0
T113	0	6303	0	0
T116	16067	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	25024893	0	0
T3	113810	88864	0	0
T4	271386	0	0	0
T5	6289	0	0	0
T8	58009	47939	0	0
T9	19724	0	0	0
T10	28826	0	0	0
T11	17700	11161	0	0
T12	68623	61013	0	0
T16	0	120571	0	0
T17	0	2647	0	0
T18	16739	0	0	0
T75	0	5119	0	0
T77	0	20076	0	0
T111	0	40330	0	0
T116	16067	2543	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	455538305	0	0
T1	9162	8772	0	0
T2	29294	28790	0	0
T3	113810	112571	0	0
T4	271386	271375	0	0
T5	6289	6233	0	0
T8	58009	56885	0	0
T9	19724	19504	0	0
T10	28826	28250	0	0
T11	17700	17262	0	0
T12	68623	67593	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T67,T92,T128

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T113,T154,T64

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T9,T18
1	Covered	T29,T30,T31

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T151,T155
1	Covered	T151,T155

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T9,T18
1	Covered	T4,T9,T18

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T8
1	1	Covered	T2,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T3,T4

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T8,T77

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T8,T77

---

FSM Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T4,T9,T18
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T3,T4
ReadWaitSt	252	Covered	T2,T3,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T4,T9,T18
IdleSt->ReadSt	236	Covered	T2,T3,T4
InitSt->ErrorSt	315	Covered	T78,T127,T109
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T173,T156,T157
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T3,T4,T8
ReadSt->ReadWaitSt	252	Covered	T2,T3,T4
ReadWaitSt->ErrorSt	276	Covered	T113,T197,T208
ReadWaitSt->IdleSt	270	Covered	T2,T3,T4
ResetSt->ErrorSt	315	Covered	T84,T86,T87
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T3,T4,T8
CheckFailError	317	Covered	T151,T155
FsmStateError	289	Covered	T4,T9,T18
MacroEccCorrError	221	Covered	T113,T154,T64
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T116,T17,T6
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T3,T4,T8
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T151,T155
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T4,T9,T18
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T154,T67,T92
MacroEccCorrError->NoError	235	Covered	T113,T64,T65
NoError->AccessError	256	Covered	T3,T4,T8
NoError->CheckFailError	317	Covered	T151,T155
NoError->FsmStateError	289	Covered	T4,T9,T18
NoError->MacroEccCorrError	221	Covered	T113,T154,T64

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T77
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T67,T92,T128
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T149,T209,T210
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T3,T4,T8
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T4,T8
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T113,T154,T64
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T113,T197,T208
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T29,T30,T31
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T4,T9,T18
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T4,T9,T116
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T4,T9,T116
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T4,T9,T18
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T151,T155
1	0	Covered	T151,T155
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T4,T9,T18
1	0	Covered	T4,T9,T18
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	456392311	455538305	0	0
DigestKnown_A	456392311	455538305	0	0
DigestOffsetMustBeRepresentable_A	1149	1149	0	0
EccErrorState_A	456392311	6406	0	0
ErrorKnown_A	456392311	455538305	0	0
FsmStateKnown_A	456392311	455538305	0	0
InitDoneKnown_A	456392311	455538305	0	0
InitReadLocksPartition_A	456392311	84888022	0	0
InitWriteLocksPartition_A	456392311	84888022	0	0
OffsetMustBeBlockAligned_A	1149	1149	0	0
OtpAddrKnown_A	456392311	455538305	0	0
OtpCmdKnown_A	456392311	455538305	0	0
OtpErrorState_A	456392311	40	0	0
OtpReqKnown_A	456392311	455538305	0	0
OtpSizeKnown_A	456392311	455538305	0	0
OtpWdataKnown_A	456392311	455538305	0	0
ReadLockPropagation_A	456392311	186958190	0	0
SizeMustBeBlockAligned_A	1149	1149	0	0
TlulGntKnown_A	456392311	455538305	0	0
TlulRdataKnown_A	456392311	455538305	0	0
TlulReadOnReadLock_A	456392311	7539	0	0
TlulRerrorKnown_A	456392311	455538305	0	0
TlulRvalidKnown_A	456392311	455538305	0	0
WriteLockPropagation_A	456392311	862554	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	456392311	8549065	0	0
u_state_regs_A	456392311	455538305	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	455538305	0	0
T1	9162	8772	0	0
T2	29294	28790	0	0
T3	113810	112571	0	0
T4	271386	271375	0	0
T5	6289	6233	0	0
T8	58009	56885	0	0
T9	19724	19504	0	0
T10	28826	28250	0	0
T11	17700	17262	0	0
T12	68623	67593	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	455538305	0	0
T1	9162	8772	0	0
T2	29294	28790	0	0
T3	113810	112571	0	0
T4	271386	271375	0	0
T5	6289	6233	0	0
T8	58009	56885	0	0
T9	19724	19504	0	0
T10	28826	28250	0	0
T11	17700	17262	0	0
T12	68623	67593	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	6406	0	0
T151	12075	3336	0	0
T152	12204	0	0	0
T155	0	3070	0	0
T164	537026	0	0	0
T165	94480	0	0	0
T166	12002	0	0	0
T167	39898	0	0	0
T168	9198	0	0	0
T169	18858	0	0	0
T170	13742	0	0	0
T199	15357	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	455538305	0	0
T1	9162	8772	0	0
T2	29294	28790	0	0
T3	113810	112571	0	0
T4	271386	271375	0	0
T5	6289	6233	0	0
T8	58009	56885	0	0
T9	19724	19504	0	0
T10	28826	28250	0	0
T11	17700	17262	0	0
T12	68623	67593	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	455538305	0	0
T1	9162	8772	0	0
T2	29294	28790	0	0
T3	113810	112571	0	0
T4	271386	271375	0	0
T5	6289	6233	0	0
T8	58009	56885	0	0
T9	19724	19504	0	0
T10	28826	28250	0	0
T11	17700	17262	0	0
T12	68623	67593	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	455538305	0	0
T1	9162	8772	0	0
T2	29294	28790	0	0
T3	113810	112571	0	0
T4	271386	271375	0	0
T5	6289	6233	0	0
T8	58009	56885	0	0
T9	19724	19504	0	0
T10	28826	28250	0	0
T11	17700	17262	0	0
T12	68623	67593	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	84888022	0	0
T1	9162	399	0	0
T2	29294	836	0	0
T3	113810	19614	0	0
T4	271386	539186	0	0
T5	6289	209	0	0
T8	58009	1593	0	0
T9	19724	11921	0	0
T10	28826	1476	0	0
T11	17700	371	0	0
T12	68623	1816	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	84888022	0	0
T1	9162	399	0	0
T2	29294	836	0	0
T3	113810	19614	0	0
T4	271386	539186	0	0
T5	6289	209	0	0
T8	58009	1593	0	0
T9	19724	11921	0	0
T10	28826	1476	0	0
T11	17700	371	0	0
T12	68623	1816	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	455538305	0	0
T1	9162	8772	0	0
T2	29294	28790	0	0
T3	113810	112571	0	0
T4	271386	271375	0	0
T5	6289	6233	0	0
T8	58009	56885	0	0
T9	19724	19504	0	0
T10	28826	28250	0	0
T11	17700	17262	0	0
T12	68623	67593	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	455538305	0	0
T1	9162	8772	0	0
T2	29294	28790	0	0
T3	113810	112571	0	0
T4	271386	271375	0	0
T5	6289	6233	0	0
T8	58009	56885	0	0
T9	19724	19504	0	0
T10	28826	28250	0	0
T11	17700	17262	0	0
T12	68623	67593	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	40	0	0
T7	512867	0	0	0
T20	28504	0	0	0
T37	14074	0	0	0
T76	12691	0	0	0
T79	59174	0	0	0
T104	38224	0	0	0
T105	14859	0	0	0
T113	78390	1	0	0
T127	16571	0	0	0
T149	0	1	0	0
T154	227593	0	0	0
T197	0	1	0	0
T209	0	1	0	0
T210	0	1	0	0
T211	0	1	0	0
T212	0	1	0	0
T213	0	1	0	0
T214	0	1	0	0
T215	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	455538305	0	0
T1	9162	8772	0	0
T2	29294	28790	0	0
T3	113810	112571	0	0
T4	271386	271375	0	0
T5	6289	6233	0	0
T8	58009	56885	0	0
T9	19724	19504	0	0
T10	28826	28250	0	0
T11	17700	17262	0	0
T12	68623	67593	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	455538305	0	0
T1	9162	8772	0	0
T2	29294	28790	0	0
T3	113810	112571	0	0
T4	271386	271375	0	0
T5	6289	6233	0	0
T8	58009	56885	0	0
T9	19724	19504	0	0
T10	28826	28250	0	0
T11	17700	17262	0	0
T12	68623	67593	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	455538305	0	0
T1	9162	8772	0	0
T2	29294	28790	0	0
T3	113810	112571	0	0
T4	271386	271375	0	0
T5	6289	6233	0	0
T8	58009	56885	0	0
T9	19724	19504	0	0
T10	28826	28250	0	0
T11	17700	17262	0	0
T12	68623	67593	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	186958190	0	0
T1	9162	652	0	0
T2	29294	0	0	0
T3	113810	3457	0	0
T4	271386	772502	0	0
T5	6289	0	0	0
T8	58009	6827	0	0
T9	19724	0	0	0
T10	28826	0	0	0
T11	17700	1730	0	0
T12	68623	6847	0	0
T16	0	44511	0	0
T17	0	42761	0	0
T77	0	1976	0	0
T116	0	9634	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	455538305	0	0
T1	9162	8772	0	0
T2	29294	28790	0	0
T3	113810	112571	0	0
T4	271386	271375	0	0
T5	6289	6233	0	0
T8	58009	56885	0	0
T9	19724	19504	0	0
T10	28826	28250	0	0
T11	17700	17262	0	0
T12	68623	67593	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	455538305	0	0
T1	9162	8772	0	0
T2	29294	28790	0	0
T3	113810	112571	0	0
T4	271386	271375	0	0
T5	6289	6233	0	0
T8	58009	56885	0	0
T9	19724	19504	0	0
T10	28826	28250	0	0
T11	17700	17262	0	0
T12	68623	67593	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	7539	0	0
T3	113810	1	0	0
T4	271386	28	0	0
T5	6289	0	0	0
T8	58009	9	0	0
T9	19724	12	0	0
T10	28826	0	0	0
T11	17700	0	0	0
T12	68623	8	0	0
T16	0	11	0	0
T17	0	14	0	0
T18	16739	0	0	0
T77	0	11	0	0
T111	0	6	0	0
T116	16067	5	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	455538305	0	0
T1	9162	8772	0	0
T2	29294	28790	0	0
T3	113810	112571	0	0
T4	271386	271375	0	0
T5	6289	6233	0	0
T8	58009	56885	0	0
T9	19724	19504	0	0
T10	28826	28250	0	0
T11	17700	17262	0	0
T12	68623	67593	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	455538305	0	0
T1	9162	8772	0	0
T2	29294	28790	0	0
T3	113810	112571	0	0
T4	271386	271375	0	0
T5	6289	6233	0	0
T8	58009	56885	0	0
T9	19724	19504	0	0
T10	28826	28250	0	0
T11	17700	17262	0	0
T12	68623	67593	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	862554	0	0
T3	113810	11904	0	0
T4	271386	0	0	0
T5	6289	0	0	0
T8	58009	0	0	0
T9	19724	0	0	0
T10	28826	0	0	0
T11	17700	0	0	0
T12	68623	0	0	0
T16	0	28917	0	0
T18	16739	0	0	0
T21	0	45955	0	0
T74	0	4325	0	0
T84	0	6876	0	0
T116	16067	0	0	0
T118	0	33238	0	0
T131	0	2508	0	0
T160	0	5229	0	0
T190	0	6165	0	0
T216	0	54778	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	8549065	0	0
T3	113810	88660	0	0
T4	271386	0	0	0
T5	6289	0	0	0
T7	0	5814	0	0
T8	58009	47735	0	0
T9	19724	0	0	0
T10	28826	0	0	0
T11	17700	0	0	0
T12	68623	0	0	0
T16	0	120333	0	0
T17	0	2630	0	0
T18	16739	0	0	0
T21	0	201042	0	0
T77	0	20025	0	0
T84	0	48037	0	0
T113	0	33658	0	0
T116	16067	0	0	0
T191	0	2881	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456392311	455538305	0	0
T1	9162	8772	0	0
T2	29294	28790	0	0
T3	113810	112571	0	0
T4	271386	271375	0	0
T5	6289	6233	0	0
T8	58009	56885	0	0
T9	19724	19504	0	0
T10	28826	28250	0	0
T11	17700	17262	0	0
T12	68623	67593	0	0