Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

26469298

1

T1

1307

T2

4947

T3

173564

full_word

8561321

1

T1

788

T2

3392

T3

51056

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	35030309	1			T1	2095		T2	8339		T3	224620
auto[TlIntgErrCmd]	109	1			T260	8		T261	7		T262	3
auto[TlIntgErrData]	99	1			T260	10		T261	7		T262	6
auto[TlIntgErrBoth]	102	1			T260	2		T261	6		T262	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9915226

1

T1

1842

T2

7458

T3

27425

auto[1]

25115393

1

T1

253

T2

881

T3

197195

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6261873	1			T1	1160		T2	4382		T3	14314
auto[TlIntgErrNone]	partial	auto[1]	20207149	1			T1	147		T2	565		T3	159250
auto[TlIntgErrNone]	full_word	auto[0]	3653207	1			T1	682		T2	3076		T3	13111
auto[TlIntgErrNone]	full_word	auto[1]	4908080	1			T1	106		T2	316		T3	37945
auto[TlIntgErrCmd]	partial	auto[0]	47	1			T260	5		T261	3		T262	2
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T260	3		T261	3		T262	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T266	1		T356	2		T354	2
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T261	1		T357	2		T356	1
auto[TlIntgErrData]	partial	auto[0]	46	1			T260	6		T261	2		T262	1
auto[TlIntgErrData]	partial	auto[1]	44	1			T260	2		T261	4		T262	4
auto[TlIntgErrData]	full_word	auto[0]	4	1			T260	1		T262	1		T355	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T260	1		T261	1		T350	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T260	1		T261	4		T351	3
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T260	1		T261	2		T262	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T351	1		T357	1		T353	2
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T351	1		T266	1		T350	2