Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.84	97.40	96.15	97.06		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	491578502	8396026	0	0
check_regwen_rd_A	491578502	3096	0	0
check_timeout_rd_A	491578502	2364	0	0
check_trigger_regwen_rd_A	491578502	3382	0	0
consistency_check_period_rd_A	491578502	3622	0	0
creator_sw_cfg_read_lock_rd_A	491578502	2508	0	0
direct_access_address_rd_A	491578502	2254	0	0
direct_access_wdata_0_rd_A	491578502	1618	0	0
direct_access_wdata_1_rd_A	491578502	2013	0	0
integrity_check_period_rd_A	491578502	3263	0	0
intr_enable_rd_A	491578502	4049	0	0
owner_sw_cfg_read_lock_rd_A	491578502	2427	0	0
rot_creator_auth_codesign_read_lock_rd_A	491578502	2676	0	0
rot_creator_auth_state_read_lock_rd_A	491578502	2308	0	0
vendor_test_read_lock_rd_A	491578502	2240	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491578502	8396026	0	0
T3	360168	68081	0	0
T4	0	42491	0	0
T6	22898	0	0	0
T7	55813	0	0	0
T8	20419	0	0	0
T9	42406	0	0	0
T10	12578	0	0	0
T11	10577	0	0	0
T12	40807	0	0	0
T13	0	70960	0	0
T15	0	145379	0	0
T21	0	99361	0	0
T34	0	151318	0	0
T64	10548	0	0	0
T99	25766	0	0	0
T128	0	135658	0	0
T130	0	171530	0	0
T149	0	188977	0	0
T243	0	74464	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491578502	3096	0	0
T3	360168	57	0	0
T4	0	41	0	0
T6	22898	0	0	0
T7	55813	0	0	0
T8	20419	0	0	0
T9	42406	0	0	0
T10	12578	0	0	0
T11	10577	0	0	0
T12	40807	0	0	0
T34	0	133	0	0
T64	10548	0	0	0
T99	25766	0	0	0
T210	0	175	0	0
T242	0	39	0	0
T243	0	137	0	0
T274	0	88	0	0
T277	0	93	0	0
T278	0	19	0	0
T336	0	84	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491578502	2364	0	0
T3	360168	71	0	0
T4	0	13	0	0
T6	22898	0	0	0
T7	55813	0	0	0
T8	20419	0	0	0
T9	42406	0	0	0
T10	12578	0	0	0
T11	10577	0	0	0
T12	40807	0	0	0
T34	0	157	0	0
T64	10548	0	0	0
T99	25766	0	0	0
T210	0	210	0	0
T242	0	27	0	0
T243	0	103	0	0
T274	0	124	0	0
T277	0	100	0	0
T278	0	62	0	0
T336	0	110	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491578502	3382	0	0
T3	360168	116	0	0
T4	0	29	0	0
T6	22898	0	0	0
T7	55813	0	0	0
T8	20419	0	0	0
T9	42406	0	0	0
T10	12578	0	0	0
T11	10577	0	0	0
T12	40807	0	0	0
T34	0	148	0	0
T64	10548	0	0	0
T99	25766	0	0	0
T210	0	220	0	0
T242	0	53	0	0
T243	0	95	0	0
T274	0	139	0	0
T277	0	117	0	0
T278	0	29	0	0
T336	0	94	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491578502	3622	0	0
T3	360168	121	0	0
T4	0	43	0	0
T6	22898	0	0	0
T7	55813	0	0	0
T8	20419	0	0	0
T9	42406	0	0	0
T10	12578	0	0	0
T11	10577	0	0	0
T12	40807	0	0	0
T34	0	185	0	0
T64	10548	0	0	0
T99	25766	0	0	0
T210	0	288	0	0
T242	0	74	0	0
T243	0	109	0	0
T274	0	79	0	0
T277	0	116	0	0
T278	0	54	0	0
T336	0	126	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491578502	2508	0	0
T3	360168	78	0	0
T4	0	20	0	0
T6	22898	0	0	0
T7	55813	0	0	0
T8	20419	0	0	0
T9	42406	0	0	0
T10	12578	0	0	0
T11	10577	0	0	0
T12	40807	0	0	0
T34	0	203	0	0
T64	10548	0	0	0
T99	25766	0	0	0
T210	0	280	0	0
T242	0	64	0	0
T243	0	96	0	0
T274	0	113	0	0
T277	0	102	0	0
T278	0	85	0	0
T336	0	95	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491578502	2254	0	0
T3	360168	90	0	0
T4	0	25	0	0
T6	22898	0	0	0
T7	55813	0	0	0
T8	20419	0	0	0
T9	42406	0	0	0
T10	12578	0	0	0
T11	10577	0	0	0
T12	40807	0	0	0
T34	0	214	0	0
T64	10548	0	0	0
T99	25766	0	0	0
T210	0	196	0	0
T242	0	31	0	0
T243	0	125	0	0
T274	0	91	0	0
T277	0	137	0	0
T278	0	73	0	0
T336	0	98	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491578502	1618	0	0
T3	360168	48	0	0
T4	0	39	0	0
T6	22898	0	0	0
T7	55813	0	0	0
T8	20419	0	0	0
T9	42406	0	0	0
T10	12578	0	0	0
T11	10577	0	0	0
T12	40807	0	0	0
T34	0	75	0	0
T64	10548	0	0	0
T99	25766	0	0	0
T210	0	124	0	0
T242	0	30	0	0
T243	0	67	0	0
T274	0	119	0	0
T277	0	67	0	0
T278	0	39	0	0
T336	0	102	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491578502	2013	0	0
T3	360168	86	0	0
T4	0	10	0	0
T6	22898	0	0	0
T7	55813	0	0	0
T8	20419	0	0	0
T9	42406	0	0	0
T10	12578	0	0	0
T11	10577	0	0	0
T12	40807	0	0	0
T34	0	199	0	0
T64	10548	0	0	0
T99	25766	0	0	0
T210	0	215	0	0
T242	0	45	0	0
T243	0	88	0	0
T274	0	131	0	0
T277	0	41	0	0
T278	0	37	0	0
T336	0	84	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491578502	3263	0	0
T3	360168	65	0	0
T4	0	28	0	0
T6	22898	0	0	0
T7	55813	0	0	0
T8	20419	0	0	0
T9	42406	0	0	0
T10	12578	0	0	0
T11	10577	0	0	0
T12	40807	0	0	0
T34	0	161	0	0
T64	10548	0	0	0
T99	25766	0	0	0
T210	0	244	0	0
T242	0	63	0	0
T243	0	109	0	0
T274	0	87	0	0
T277	0	72	0	0
T278	0	61	0	0
T336	0	108	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491578502	4049	0	0
T3	360168	87	0	0
T4	0	29	0	0
T6	22898	0	0	0
T7	55813	0	0	0
T8	20419	0	0	0
T9	42406	0	0	0
T10	12578	0	0	0
T11	10577	0	0	0
T12	40807	0	0	0
T34	0	167	0	0
T64	10548	0	0	0
T72	0	24	0	0
T97	0	21	0	0
T99	25766	0	0	0
T210	0	235	0	0
T243	0	168	0	0
T274	0	76	0	0
T336	0	125	0	0
T337	0	39	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491578502	2427	0	0
T3	360168	92	0	0
T4	0	25	0	0
T6	22898	0	0	0
T7	55813	0	0	0
T8	20419	0	0	0
T9	42406	0	0	0
T10	12578	0	0	0
T11	10577	0	0	0
T12	40807	0	0	0
T34	0	153	0	0
T64	10548	0	0	0
T99	25766	0	0	0
T210	0	200	0	0
T242	0	49	0	0
T243	0	81	0	0
T274	0	86	0	0
T277	0	110	0	0
T278	0	71	0	0
T336	0	102	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491578502	2676	0	0
T3	360168	101	0	0
T4	0	34	0	0
T6	22898	0	0	0
T7	55813	0	0	0
T8	20419	0	0	0
T9	42406	0	0	0
T10	12578	0	0	0
T11	10577	0	0	0
T12	40807	0	0	0
T34	0	151	0	0
T64	10548	0	0	0
T99	25766	0	0	0
T210	0	219	0	0
T242	0	57	0	0
T243	0	130	0	0
T274	0	130	0	0
T277	0	144	0	0
T278	0	63	0	0
T336	0	103	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491578502	2308	0	0
T3	360168	63	0	0
T4	0	17	0	0
T6	22898	0	0	0
T7	55813	0	0	0
T8	20419	0	0	0
T9	42406	0	0	0
T10	12578	0	0	0
T11	10577	0	0	0
T12	40807	0	0	0
T34	0	158	0	0
T64	10548	0	0	0
T99	25766	0	0	0
T210	0	218	0	0
T242	0	46	0	0
T243	0	116	0	0
T274	0	102	0	0
T277	0	179	0	0
T278	0	57	0	0
T336	0	95	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491578502	2240	0	0
T3	360168	77	0	0
T4	0	25	0	0
T6	22898	0	0	0
T7	55813	0	0	0
T8	20419	0	0	0
T9	42406	0	0	0
T10	12578	0	0	0
T11	10577	0	0	0
T12	40807	0	0	0
T34	0	169	0	0
T64	10548	0	0	0
T99	25766	0	0	0
T210	0	206	0	0
T242	0	55	0	0
T243	0	74	0	0
T274	0	62	0	0
T277	0	118	0	0
T278	0	66	0	0
T336	0	85	0	0