Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.23	100.00	100.00		90.00	100.00	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.56	100.00	100.00	100.00	90.00	98.15	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.84	97.40	96.15	97.06		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.12	96.70	93.94		83.33	95.45	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.27	97.83	93.94	98.55	83.33	94.74	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.84	97.40	96.15	97.06		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	94.64	100.00		98.55		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.84	97.40	96.15	97.06		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		86	86	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	61	61	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
153	1	1
154	1	1
156	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			==> MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
224		excluded
			Exclude Annotation: VC_COV_UNR
225		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
276		excluded
			Exclude Annotation: VC_COV_UNR
277		excluded
			Exclude Annotation: VC_COV_UNR
279		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
339	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T2,T3,T6
1	Excluded		VC_COV_UNR

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T6,T7
1	Covered	T29,T30,T31

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T137,T138
1	Covered	T137,T138

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T6,T7
1	Covered	T3,T6,T7

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T6

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T6

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	11	84.62
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T3,T6,T7
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T2,T3,T6
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T3,T6,T7
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T180,T181
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T91,T182,T183
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T2,T3
ReadSt->ReadWaitSt	252	Covered	T2,T3,T6
ReadWaitSt->ErrorSt	276	Not Covered
ReadWaitSt->IdleSt	270	Covered	T2,T3,T6
ResetSt->ErrorSt	315	Covered	T73,T74,T75
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests	Exclude Annotation
AccessError	256	Covered	T1,T2,T3
CheckFailError	317	Covered	T137,T138
FsmStateError	289	Covered	T3,T6,T7
MacroEccCorrError	221	Excluded		VC_COV_UNR
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded
AccessError->FsmStateError	325	Covered	T99,T4,T14
AccessError->MacroEccCorrError	221	Excluded
AccessError->NoError	235	Covered	T1,T2,T3
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded
CheckFailError->NoError	235	Covered	T137,T138
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded
FsmStateError->NoError	235	Covered	T3,T6,T7
MacroEccCorrError->AccessError	256	Excluded
MacroEccCorrError->CheckFailError	317	Excluded
MacroEccCorrError->FsmStateError	325	Excluded
MacroEccCorrError->NoError	235	Excluded
NoError->AccessError	256	Covered	T1,T2,T3
NoError->CheckFailError	317	Covered	T137,T138
NoError->FsmStateError	289	Covered	T3,T6,T7
NoError->MacroEccCorrError	221	Excluded

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	18	18	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests	Exclude Annotation
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T6
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T3,T9,T22
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T29,T30,T31
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T3,T6,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T6,T7,T99
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T6,T7,T99
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T3,T6,T7
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T137,T138
1	0	Covered	T137,T138
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T3,T6,T7
1	0	Covered	T3,T6,T7
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	488485003	487595921	0	0
DigestKnown_A	488485003	487595921	0	0
DigestOffsetMustBeRepresentable_A	1151	1151	0	0
EccErrorState_A	488485003	7473	0	0
ErrorKnown_A	488485003	487595921	0	0
FsmStateKnown_A	488485003	487595921	0	0
InitDoneKnown_A	488485003	487595921	0	0
InitReadLocksPartition_A	488485003	105377427	0	0
InitWriteLocksPartition_A	488485003	105377427	0	0
OffsetMustBeBlockAligned_A	1151	1151	0	0
OtpAddrKnown_A	488485003	487595921	0	0
OtpCmdKnown_A	488485003	487595921	0	0
OtpErrorState_A	488485003	0	0	0
OtpReqKnown_A	488485003	487595921	0	0
OtpSizeKnown_A	488485003	487595921	0	0
OtpWdataKnown_A	488485003	487595921	0	0
ReadLockPropagation_A	488485003	206984003	0	0
SizeMustBeBlockAligned_A	1151	1151	0	0
TlulGntKnown_A	488485003	487595921	0	0
TlulRdataKnown_A	488485003	487595921	0	0
TlulReadOnReadLock_A	488485003	7723	0	0
TlulRerrorKnown_A	488485003	487595921	0	0
TlulRvalidKnown_A	488485003	487595921	0	0
WriteLockPropagation_A	488485003	2922417	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	488485003	29600950	0	0
u_state_regs_A	488485003	487595921	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	7473	0	0
T136	16850	0	0	0
T137	13728	3760	0	0
T138	0	3713	0	0
T150	20187	0	0	0
T151	76249	0	0	0
T152	413121	0	0	0
T153	16722	0	0	0
T154	18041	0	0	0
T155	11842	0	0	0
T156	17083	0	0	0
T157	81931	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	105377427	0	0
T1	40031	259	0	0
T2	101700	612	0	0
T3	360168	766190	0	0
T6	22898	5385	0	0
T7	55813	11294	0	0
T8	20419	4886	0	0
T9	42406	645	0	0
T10	12578	4960	0	0
T11	10577	3691	0	0
T12	40807	5523	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	105377427	0	0
T1	40031	259	0	0
T2	101700	612	0	0
T3	360168	766190	0	0
T6	22898	5385	0	0
T7	55813	11294	0	0
T8	20419	4886	0	0
T9	42406	645	0	0
T10	12578	4960	0	0
T11	10577	3691	0	0
T12	40807	5523	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	206984003	0	0
T1	40031	15925	0	0
T2	101700	42743	0	0
T3	360168	860636	0	0
T4	0	123925	0	0
T6	22898	1100	0	0
T7	55813	0	0	0
T8	20419	0	0	0
T9	42406	4363	0	0
T10	12578	0	0	0
T11	10577	0	0	0
T12	40807	0	0	0
T22	0	2304	0	0
T99	0	14117	0	0
T106	0	2394	0	0
T107	0	5222	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	7723	0	0
T1	40031	2	0	0
T2	101700	14	0	0
T3	360168	6	0	0
T4	0	5	0	0
T5	0	10	0	0
T6	22898	8	0	0
T7	55813	2	0	0
T8	20419	0	0	0
T9	42406	7	0	0
T10	12578	0	0	0
T11	10577	0	0	0
T12	40807	0	0	0
T23	0	1	0	0
T99	0	3	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	2922417	0	0
T2	101700	8994	0	0
T3	360168	0	0	0
T6	22898	0	0	0
T7	55813	0	0	0
T8	20419	0	0	0
T9	42406	3031	0	0
T10	12578	0	0	0
T11	10577	0	0	0
T12	40807	0	0	0
T22	0	2811	0	0
T35	0	2181	0	0
T36	0	12478	0	0
T65	0	7944	0	0
T72	0	121490	0	0
T77	0	6933	0	0
T96	0	4047	0	0
T99	25766	0	0	0
T103	0	21726	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	29600950	0	0
T1	40031	23202	0	0
T2	101700	83645	0	0
T3	360168	0	0	0
T6	22898	13924	0	0
T7	55813	0	0	0
T8	20419	0	0	0
T9	42406	33250	0	0
T10	12578	0	0	0
T11	10577	0	0	0
T12	40807	0	0	0
T16	0	4441	0	0
T99	0	3801	0	0
T105	0	2445	0	0
T106	0	15225	0	0
T107	0	17952	0	0
T174	0	3641	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	88	96.70
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	65	95.59
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	0	1
316	0	1
317	0	1
			==> MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	31	93.94
Logical	33	31	93.94
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T10,T64

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T8
1	Covered	T23,T35,T139

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T6,T7
1	Covered	T29,T30,T31

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T6,T7
1	Covered	T3,T6,T7

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T8

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T6

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T6

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T3,T6,T7
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T2,T3,T7
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T3,T6,T7
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T91,T182,T183
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T11,T113,T100
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T2,T3
ReadSt->ReadWaitSt	252	Covered	T2,T3,T7
ReadWaitSt->ErrorSt	276	Covered	T7,T184,T185
ReadWaitSt->IdleSt	270	Covered	T2,T3,T8
ResetSt->ErrorSt	315	Covered	T73,T74,T75
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	4	80.00	(Not included in score)
Transitions	11	8	72.73
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T2,T3
CheckFailError	317	Not Covered
FsmStateError	289	Covered	T3,T6,T7
MacroEccCorrError	221	Covered	T8,T10,T64
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T3,T99,T4
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T1,T2,T3
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Not Covered
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T3,T6,T7
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T8,T10,T64
MacroEccCorrError->NoError	235	Covered	T23,T35,T139
NoError->AccessError	256	Covered	T1,T2,T3
NoError->CheckFailError	317	Not Covered
NoError->FsmStateError	289	Covered	T6,T7,T4
NoError->MacroEccCorrError	221	Covered	T8,T10,T64

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	42	95.45
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	1	33.33
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T7

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T7

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T8,T10,T64
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T11,T113,T100
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T7
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T9,T36,T65
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T23,T35,T139
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T8
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T7,T184,T185
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T29,T30,T31
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T3,T6,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T6,T7,T99
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T6,T7,T99
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T3,T6,T7
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T3,T6,T7
1	0	Covered	T3,T6,T7
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	488485003	487595921	0	0
DigestKnown_A	488485003	487595921	0	0
DigestOffsetMustBeRepresentable_A	1151	1151	0	0
EccErrorState_A	488485003	0	0	0
ErrorKnown_A	488485003	487595921	0	0
FsmStateKnown_A	488485003	487595921	0	0
InitDoneKnown_A	488485003	487595921	0	0
InitReadLocksPartition_A	488485003	105565904	0	0
InitWriteLocksPartition_A	488485003	105565904	0	0
OffsetMustBeBlockAligned_A	1151	1151	0	0
OtpAddrKnown_A	488485003	487595921	0	0
OtpCmdKnown_A	488485003	487595921	0	0
OtpErrorState_A	488485003	78	0	0
OtpReqKnown_A	488485003	487595921	0	0
OtpSizeKnown_A	488485003	487595921	0	0
OtpWdataKnown_A	488485003	487595921	0	0
ReadLockPropagation_A	488485003	196635855	0	0
SizeMustBeBlockAligned_A	1151	1151	0	0
TlulGntKnown_A	488485003	487595921	0	0
TlulRdataKnown_A	488485003	487595921	0	0
TlulReadOnReadLock_A	488485003	8027	0	0
TlulRerrorKnown_A	488485003	487595921	0	0
TlulRvalidKnown_A	488485003	487595921	0	0
WriteLockPropagation_A	488485003	2299883	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	488485003	28482585	0	0
u_state_regs_A	488485003	487595921	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	105565904	0	0
T1	40031	344	0	0
T2	101700	765	0	0
T3	360168	766292	0	0
T6	22898	5487	0	0
T7	55813	11517	0	0
T8	20419	4937	0	0
T9	42406	832	0	0
T10	12578	5011	0	0
T11	10577	3732	0	0
T12	40807	5608	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	105565904	0	0
T1	40031	344	0	0
T2	101700	765	0	0
T3	360168	766292	0	0
T6	22898	5487	0	0
T7	55813	11517	0	0
T8	20419	4937	0	0
T9	42406	832	0	0
T10	12578	5011	0	0
T11	10577	3732	0	0
T12	40807	5608	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	78	0	0
T4	199250	0	0	0
T7	55813	1	0	0
T8	20419	0	0	0
T9	42406	0	0	0
T10	12578	0	0	0
T11	10577	1	0	0
T12	40807	0	0	0
T58	14775	0	0	0
T64	10548	0	0	0
T99	25766	0	0	0
T100	0	1	0	0
T113	0	1	0	0
T158	0	1	0	0
T161	0	1	0	0
T164	0	1	0	0
T165	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	196635855	0	0
T1	40031	15908	0	0
T2	101700	29767	0	0
T3	360168	183025	0	0
T4	0	106158	0	0
T6	22898	2050	0	0
T7	55813	0	0	0
T8	20419	0	0	0
T9	42406	3958	0	0
T10	12578	0	0	0
T11	10577	0	0	0
T12	40807	0	0	0
T23	0	854	0	0
T99	0	15529	0	0
T106	0	3130	0	0
T174	0	18645	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	8027	0	0
T1	40031	2	0	0
T2	101700	8	0	0
T3	360168	3	0	0
T4	0	7	0	0
T6	22898	3	0	0
T7	55813	1	0	0
T8	20419	0	0	0
T9	42406	7	0	0
T10	12578	0	0	0
T11	10577	0	0	0
T12	40807	0	0	0
T23	0	1	0	0
T99	0	7	0	0
T106	0	2	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	2299883	0	0
T2	101700	9711	0	0
T3	360168	0	0	0
T6	22898	0	0	0
T7	55813	0	0	0
T8	20419	0	0	0
T9	42406	1861	0	0
T10	12578	0	0	0
T11	10577	0	0	0
T12	40807	0	0	0
T22	0	3557	0	0
T35	0	1141	0	0
T36	0	103295	0	0
T65	0	21180	0	0
T77	0	3394	0	0
T93	0	17636	0	0
T94	0	1021	0	0
T99	25766	0	0	0
T104	0	1343	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	28482585	0	0
T1	40031	23151	0	0
T2	101700	83526	0	0
T3	360168	0	0	0
T6	22898	13856	0	0
T7	55813	0	0	0
T8	20419	0	0	0
T9	42406	33080	0	0
T10	12578	0	0	0
T11	10577	2788	0	0
T12	40807	0	0	0
T22	0	49616	0	0
T35	0	51989	0	0
T99	0	3767	0	0
T106	0	15157	0	0
T107	0	6943	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T16,T140

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T7,T35

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T6,T7
1	Covered	T29,T30,T31

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T73,T137
1	Covered	T73,T137

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T6,T7
1	Covered	T3,T6,T7

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00111101000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T6

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T6

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T3,T6,T7
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T3,T6,T7
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T91,T182,T183
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T11,T113,T100
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T2,T3
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Covered	T142,T143,T185
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T73,T74,T75
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T2,T3
CheckFailError	317	Covered	T73,T137
FsmStateError	289	Covered	T3,T6,T7
MacroEccCorrError	221	Covered	T1,T7,T8
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T3,T99,T4
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T1,T2,T3
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T73,T137
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T3,T6,T7
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T7,T8,T16
MacroEccCorrError->NoError	235	Covered	T1,T35,T77
NoError->AccessError	256	Covered	T1,T2,T3
NoError->CheckFailError	317	Covered	T73,T137
NoError->FsmStateError	289	Covered	T6,T7,T10
NoError->MacroEccCorrError	221	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T8,T16,T140
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T159,T160,T162
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T9,T36,T72
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T1,T7,T35
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T142,T143,T185
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T29,T30,T31
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T3,T6,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T6,T7,T99
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T6,T7,T99
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T3,T6,T7
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T73,T137
1	0	Covered	T73,T137
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T3,T6,T7
1	0	Covered	T3,T6,T7
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	488485003	487595921	0	0
DigestKnown_A	488485003	487595921	0	0
DigestOffsetMustBeRepresentable_A	1151	1151	0	0
EccErrorState_A	488485003	6480	0	0
ErrorKnown_A	488485003	487595921	0	0
FsmStateKnown_A	488485003	487595921	0	0
InitDoneKnown_A	488485003	487595921	0	0
InitReadLocksPartition_A	488485003	105753115	0	0
InitWriteLocksPartition_A	488485003	105753115	0	0
OffsetMustBeBlockAligned_A	1151	1151	0	0
OtpAddrKnown_A	488485003	487595921	0	0
OtpCmdKnown_A	488485003	487595921	0	0
OtpErrorState_A	488485003	64	0	0
OtpReqKnown_A	488485003	487595921	0	0
OtpSizeKnown_A	488485003	487595921	0	0
OtpWdataKnown_A	488485003	487595921	0	0
ReadLockPropagation_A	488485003	204798034	0	0
SizeMustBeBlockAligned_A	1151	1151	0	0
TlulGntKnown_A	488485003	487595921	0	0
TlulRdataKnown_A	488485003	487595921	0	0
TlulReadOnReadLock_A	488485003	8107	0	0
TlulRerrorKnown_A	488485003	487595921	0	0
TlulRvalidKnown_A	488485003	487595921	0	0
WriteLockPropagation_A	488485003	1951449	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	488485003	19999801	0	0
u_state_regs_A	488485003	487595921	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	6480	0	0
T73	10962	2720	0	0
T110	12413	0	0	0
T126	9787	0	0	0
T137	0	3760	0	0
T140	11027	0	0	0
T144	4059	0	0	0
T145	15372	0	0	0
T146	9100	0	0	0
T147	55897	0	0	0
T148	101943	0	0	0
T149	970451	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	105753115	0	0
T1	40031	429	0	0
T2	101700	904	0	0
T3	360168	766394	0	0
T6	22898	5589	0	0
T7	55813	11736	0	0
T8	20419	4988	0	0
T9	42406	1019	0	0
T10	12578	5062	0	0
T11	10577	3766	0	0
T12	40807	5693	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	105753115	0	0
T1	40031	429	0	0
T2	101700	904	0	0
T3	360168	766394	0	0
T6	22898	5589	0	0
T7	55813	11736	0	0
T8	20419	4988	0	0
T9	42406	1019	0	0
T10	12578	5062	0	0
T11	10577	3766	0	0
T12	40807	5693	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	64	0	0
T26	12202	0	0	0
T34	772900	0	0	0
T77	52847	0	0	0
T93	193031	0	0	0
T103	231178	0	0	0
T130	549621	0	0	0
T142	0	1	0	0
T146	0	1	0	0
T159	12973	1	0	0
T160	12100	1	0	0
T162	0	1	0	0
T163	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	12770	0	0	0
T173	7688	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	204798034	0	0
T1	40031	7706	0	0
T2	101700	29019	0	0
T3	360168	185858	0	0
T4	0	123253	0	0
T6	22898	569	0	0
T7	55813	0	0	0
T8	20419	0	0	0
T9	42406	4115	0	0
T10	12578	0	0	0
T11	10577	0	0	0
T12	40807	0	0	0
T23	0	851	0	0
T99	0	15516	0	0
T106	0	2799	0	0
T107	0	2878	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	8107	0	0
T1	40031	1	0	0
T2	101700	7	0	0
T3	360168	5	0	0
T4	0	3	0	0
T5	0	10	0	0
T6	22898	3	0	0
T7	55813	2	0	0
T8	20419	0	0	0
T9	42406	7	0	0
T10	12578	0	0	0
T11	10577	0	0	0
T12	40807	0	0	0
T99	0	7	0	0
T106	0	2	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	1951449	0	0
T4	199250	0	0	0
T9	42406	1020	0	0
T10	12578	0	0	0
T11	10577	0	0	0
T12	40807	0	0	0
T23	39449	0	0	0
T36	0	43646	0	0
T58	14775	0	0	0
T64	10548	0	0	0
T65	0	15146	0	0
T72	0	68748	0	0
T77	0	1857	0	0
T93	0	17636	0	0
T96	0	5499	0	0
T99	25766	0	0	0
T103	0	19204	0	0
T105	10447	0	0	0
T106	0	4544	0	0
T175	0	2137	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	19999801	0	0
T1	40031	23100	0	0
T2	101700	83421	0	0
T3	360168	0	0	0
T6	22898	13788	0	0
T7	55813	0	0	0
T8	20419	0	0	0
T9	42406	32910	0	0
T10	12578	0	0	0
T11	10577	0	0	0
T12	40807	0	0	0
T35	0	51768	0	0
T36	0	442566	0	0
T99	0	3733	0	0
T106	0	15089	0	0
T107	0	17850	0	0
T174	0	3573	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0