Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.84	97.40	96.15	97.06		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.84	97.40	96.15	97.06		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T58,T16,T110

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T23,T35,T77

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T6,T7
1	Covered	T29,T30,T31

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T73,T135,T136
1	Covered	T73,T135,T136

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T6,T7
1	Covered	T3,T6,T7

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T6

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T6

---

FSM Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T3,T6,T7
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T2,T3,T6
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T3,T6,T7
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T11,T113,T91
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T105,T186,T159
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T2,T3
ReadSt->ReadWaitSt	252	Covered	T2,T3,T6
ReadWaitSt->ErrorSt	276	Covered	T142,T143,T184
ReadWaitSt->IdleSt	270	Covered	T2,T3,T6
ResetSt->ErrorSt	315	Covered	T73,T74,T75
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T2,T3
CheckFailError	317	Covered	T73,T135,T136
FsmStateError	289	Covered	T3,T6,T7
MacroEccCorrError	221	Covered	T58,T23,T16
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T3,T99,T4
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T1,T2,T3
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T73,T135,T136
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T3,T6,T7
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T58,T16,T142
MacroEccCorrError->NoError	235	Covered	T23,T35,T77
NoError->AccessError	256	Covered	T1,T2,T3
NoError->CheckFailError	317	Covered	T73,T135,T136
NoError->FsmStateError	289	Covered	T6,T7,T8
NoError->MacroEccCorrError	221	Covered	T58,T23,T16

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T58,T16,T110
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T105,T186,T187
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T6
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T9,T36,T65
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T23,T35,T77
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T142,T143,T184
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T29,T30,T31
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T3,T6,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T6,T99,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T6,T99,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T3,T6,T7
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T73,T135,T136
1	0	Covered	T73,T135,T136
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T3,T6,T7
1	0	Covered	T3,T6,T7
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	488485003	487595921	0	0
DigestKnown_A	488485003	487595921	0	0
DigestOffsetMustBeRepresentable_A	1151	1151	0	0
EccErrorState_A	488485003	9751	0	0
ErrorKnown_A	488485003	487595921	0	0
FsmStateKnown_A	488485003	487595921	0	0
InitDoneKnown_A	488485003	487595921	0	0
InitReadLocksPartition_A	488485003	105939272	0	0
InitWriteLocksPartition_A	488485003	105939272	0	0
OffsetMustBeBlockAligned_A	1151	1151	0	0
OtpAddrKnown_A	488485003	487595921	0	0
OtpCmdKnown_A	488485003	487595921	0	0
OtpErrorState_A	488485003	46	0	0
OtpReqKnown_A	488485003	487595921	0	0
OtpSizeKnown_A	488485003	487595921	0	0
OtpWdataKnown_A	488485003	487595921	0	0
ReadLockPropagation_A	488485003	202859340	0	0
SizeMustBeBlockAligned_A	1151	1151	0	0
TlulGntKnown_A	488485003	487595921	0	0
TlulRdataKnown_A	488485003	487595921	0	0
TlulReadOnReadLock_A	488485003	8050	0	0
TlulRerrorKnown_A	488485003	487595921	0	0
TlulRvalidKnown_A	488485003	487595921	0	0
WriteLockPropagation_A	488485003	2348890	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	488485003	27862119	0	0
u_state_regs_A	488485003	487595921	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	9751	0	0
T73	10962	2720	0	0
T110	12413	0	0	0
T126	9787	0	0	0
T135	0	3491	0	0
T136	0	3540	0	0
T140	11027	0	0	0
T144	4059	0	0	0
T145	15372	0	0	0
T146	9100	0	0	0
T147	55897	0	0	0
T148	101943	0	0	0
T149	970451	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	105939272	0	0
T1	40031	514	0	0
T2	101700	1040	0	0
T3	360168	766496	0	0
T6	22898	5691	0	0
T7	55813	11957	0	0
T8	20419	5039	0	0
T9	42406	1206	0	0
T10	12578	5113	0	0
T11	10577	3800	0	0
T12	40807	5778	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	105939272	0	0
T1	40031	514	0	0
T2	101700	1040	0	0
T3	360168	766496	0	0
T6	22898	5691	0	0
T7	55813	11957	0	0
T8	20419	5039	0	0
T9	42406	1206	0	0
T10	12578	5113	0	0
T11	10577	3800	0	0
T12	40807	5778	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	46	0	0
T5	23605	0	0	0
T16	11534	0	0	0
T22	56989	0	0	0
T23	39449	0	0	0
T105	10447	1	0	0
T106	23878	0	0	0
T107	29319	0	0	0
T108	23466	0	0	0
T142	0	1	0	0
T143	0	1	0	0
T174	27082	0	0	0
T178	5051	0	0	0
T184	0	1	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0
T189	0	1	0	0
T190	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	202859340	0	0
T1	40031	15885	0	0
T2	101700	32240	0	0
T3	360168	868712	0	0
T4	0	104060	0	0
T6	22898	2046	0	0
T7	55813	0	0	0
T8	20419	0	0	0
T9	42406	6286	0	0
T10	12578	0	0	0
T11	10577	0	0	0
T12	40807	0	0	0
T22	0	2543	0	0
T99	0	13196	0	0
T106	0	2454	0	0
T107	0	3562	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	8050	0	0
T1	40031	3	0	0
T2	101700	5	0	0
T3	360168	5	0	0
T4	0	4	0	0
T5	0	11	0	0
T6	22898	5	0	0
T7	55813	0	0	0
T8	20419	0	0	0
T9	42406	11	0	0
T10	12578	0	0	0
T11	10577	0	0	0
T12	40807	0	0	0
T99	0	4	0	0
T106	0	1	0	0
T174	0	17	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	2348890	0	0
T4	199250	0	0	0
T9	42406	3031	0	0
T10	12578	0	0	0
T11	10577	0	0	0
T12	40807	0	0	0
T22	0	474	0	0
T23	39449	0	0	0
T36	0	53718	0	0
T58	14775	0	0	0
T64	10548	0	0	0
T65	0	19979	0	0
T72	0	72646	0	0
T77	0	3539	0	0
T99	25766	0	0	0
T105	10447	0	0	0
T142	0	4748	0	0
T147	0	648	0	0
T175	0	3500	0	0
T176	0	3874	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	27862119	0	0
T1	40031	23049	0	0
T2	101700	83319	0	0
T3	360168	0	0	0
T6	22898	9414	0	0
T7	55813	0	0	0
T8	20419	0	0	0
T9	42406	24709	0	0
T10	12578	0	0	0
T11	10577	0	0	0
T12	40807	0	0	0
T22	0	49242	0	0
T35	0	51547	0	0
T36	0	554244	0	0
T99	0	3699	0	0
T106	0	15021	0	0
T107	0	17799	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T16,T41

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T8
1	Covered	T1,T23,T35

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T6,T7
1	Covered	T29,T30,T31

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T141,T138
1	Covered	T141,T138

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T6,T7
1	Covered	T3,T6,T7

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T23,T22,T36

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T23,T22,T36

---

FSM Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T3,T6,T7
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T3,T6,T7
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T11,T113,T91
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T105,T186,T110
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T2,T3
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Covered	T191,T142,T192
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T73,T74,T75
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T2,T3
CheckFailError	317	Covered	T141,T138
FsmStateError	289	Covered	T3,T6,T7
MacroEccCorrError	221	Covered	T1,T8,T23
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T3,T99,T4
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T1,T2,T3
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T141,T138
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T3,T6,T7
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T8,T16,T191
MacroEccCorrError->NoError	235	Covered	T1,T23,T35
NoError->AccessError	256	Covered	T1,T2,T3
NoError->CheckFailError	317	Covered	T141,T138
NoError->FsmStateError	289	Covered	T6,T7,T10
NoError->MacroEccCorrError	221	Covered	T1,T8,T23

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T23,T22,T36
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T8,T16,T41
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T110,T140,T193
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T9,T22,T36
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T1,T23,T35
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T8
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T191,T142,T192
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T29,T30,T31
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T3,T6,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T6,T7,T99
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T6,T7,T99
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T3,T6,T7
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T141,T138
1	0	Covered	T141,T138
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T3,T6,T7
1	0	Covered	T3,T6,T7
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	488485003	487595921	0	0
DigestKnown_A	488485003	487595921	0	0
DigestOffsetMustBeRepresentable_A	1151	1151	0	0
EccErrorState_A	488485003	7239	0	0
ErrorKnown_A	488485003	487595921	0	0
FsmStateKnown_A	488485003	487595921	0	0
InitDoneKnown_A	488485003	487595921	0	0
InitReadLocksPartition_A	488485003	106124770	0	0
InitWriteLocksPartition_A	488485003	106124770	0	0
OffsetMustBeBlockAligned_A	1151	1151	0	0
OtpAddrKnown_A	488485003	487595921	0	0
OtpCmdKnown_A	488485003	487595921	0	0
OtpErrorState_A	488485003	28	0	0
OtpReqKnown_A	488485003	487595921	0	0
OtpSizeKnown_A	488485003	487595921	0	0
OtpWdataKnown_A	488485003	487595921	0	0
ReadLockPropagation_A	488485003	205414212	0	0
SizeMustBeBlockAligned_A	1151	1151	0	0
TlulGntKnown_A	488485003	487595921	0	0
TlulRdataKnown_A	488485003	487595921	0	0
TlulReadOnReadLock_A	488485003	7832	0	0
TlulRerrorKnown_A	488485003	487595921	0	0
TlulRvalidKnown_A	488485003	487595921	0	0
WriteLockPropagation_A	488485003	1008545	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	488485003	10038050	0	0
u_state_regs_A	488485003	487595921	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	7239	0	0
T20	19331	0	0	0
T138	0	3713	0	0
T141	15596	3526	0	0
T194	120949	0	0	0
T195	22481	0	0	0
T196	54178	0	0	0
T197	27471	0	0	0
T198	29571	0	0	0
T199	19367	0	0	0
T200	38971	0	0	0
T201	18838	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	106124770	0	0
T1	40031	599	0	0
T2	101700	1176	0	0
T3	360168	766598	0	0
T6	22898	5793	0	0
T7	55813	12178	0	0
T8	20419	5090	0	0
T9	42406	1393	0	0
T10	12578	5164	0	0
T11	10577	3834	0	0
T12	40807	5863	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	106124770	0	0
T1	40031	599	0	0
T2	101700	1176	0	0
T3	360168	766598	0	0
T6	22898	5793	0	0
T7	55813	12178	0	0
T8	20419	5090	0	0
T9	42406	1393	0	0
T10	12578	5164	0	0
T11	10577	3834	0	0
T12	40807	5863	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	28	0	0
T29	931294	0	0	0
T72	120744	0	0	0
T95	31510	0	0	0
T104	28620	0	0	0
T110	0	1	0	0
T140	0	1	0	0
T142	108037	1	0	0
T179	183101	0	0	0
T184	0	1	0	0
T191	28232	1	0	0
T192	0	1	0	0
T193	0	1	0	0
T202	0	1	0	0
T203	0	1	0	0
T204	0	1	0	0
T205	12863	0	0	0
T206	26920	0	0	0
T207	14919	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	205414212	0	0
T1	40031	15866	0	0
T2	101700	29814	0	0
T3	360168	183608	0	0
T4	0	744302	0	0
T6	22898	1301	0	0
T7	55813	0	0	0
T8	20419	0	0	0
T9	42406	6512	0	0
T10	12578	0	0	0
T11	10577	0	0	0
T12	40807	0	0	0
T23	0	842	0	0
T99	0	14078	0	0
T106	0	3124	0	0
T174	0	18643	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	7832	0	0
T1	40031	4	0	0
T2	101700	8	0	0
T3	360168	8	0	0
T4	0	6	0	0
T5	0	12	0	0
T6	22898	3	0	0
T7	55813	3	0	0
T8	20419	0	0	0
T9	42406	7	0	0
T10	12578	0	0	0
T11	10577	0	0	0
T12	40807	0	0	0
T99	0	8	0	0
T174	0	27	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	1008545	0	0
T5	23605	0	0	0
T16	11534	0	0	0
T22	56989	543	0	0
T23	39449	7331	0	0
T36	0	7107	0	0
T65	0	3671	0	0
T72	0	37963	0	0
T97	0	35981	0	0
T104	0	904	0	0
T106	23878	0	0	0
T107	29319	0	0	0
T108	23466	0	0	0
T113	11763	0	0	0
T147	0	300	0	0
T174	27082	0	0	0
T177	0	22720	0	0
T178	5051	0	0	0
T208	0	2677	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	10038050	0	0
T5	23605	0	0	0
T16	11534	0	0	0
T22	56989	49055	0	0
T23	39449	29271	0	0
T36	0	131841	0	0
T65	0	116019	0	0
T72	0	358515	0	0
T91	0	2646	0	0
T95	0	22476	0	0
T104	0	18338	0	0
T106	23878	0	0	0
T107	29319	0	0	0
T108	23466	0	0	0
T113	11763	0	0	0
T174	27082	0	0	0
T176	0	10408	0	0
T178	5051	0	0	0
T179	0	22647	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0