Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.97	100.00	71.88			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp_rsp_fifo	98.68	100.00	94.74			100.00	100.00
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_tlul_adapter_sram.u_reqfifo	100.00	100.00	100.00			100.00	100.00
tb.dut.u_tlul_adapter_sram.u_sramreqfifo	100.00	100.00	100.00			100.00	100.00
tb.dut.u_tlul_adapter_sram.u_rspfifo	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_otp_rsp_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.68	100.00	94.74			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.83	100.00	92.31			95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.84	97.40	96.15	97.06		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	93.64	100.00	90.00			90.91

---

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.36	95.00	87.10			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	100.00	97.03			100.00	100.00	u_tlul_adapter_sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

---

Module Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.36	95.00	87.10			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	100.00	97.03			100.00	100.00	u_tlul_adapter_sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

---

Module Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.37	95.00	89.47			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	100.00	97.03			100.00	100.00	u_tlul_adapter_sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Line Coverage for Module : prim_fifo_sync ( parameter Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=4,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
98.68	100.00

tb.dut.u_otp_rsp_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_rspfifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=4,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
98.68	94.74

tb.dut.u_otp_rsp_fifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=4,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_rspfifo

SCORE	BRANCH
98.68	100.00

tb.dut.u_otp_rsp_fifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_reqfifo

SCORE	BRANCH
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	272780662	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	1953940012	44015112	0	0
gen_passthru_fifo.paramCheckPass	7956	7956	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	272780662	0	0
T1	400310	29069	0	0
T2	1017000	47020	0	0
T3	3601680	2678633	0	0
T6	228980	23287	0	0
T7	558130	25021	0	0
T8	204190	10767	0	0
T9	424060	44152	0	0
T10	125780	7161	0	0
T11	105770	7996	0	0
T12	408070	14608	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	400310	395980	0	0
T2	1017000	1008380	0	0
T3	3601680	3601580	0	0
T6	228980	224300	0	0
T7	558130	549530	0	0
T8	204190	201770	0	0
T9	424060	415180	0	0
T10	125780	122940	0	0
T11	105770	103070	0	0
T12	408070	402320	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	400310	395980	0	0
T2	1017000	1008380	0	0
T3	3601680	3601580	0	0
T6	228980	224300	0	0
T7	558130	549530	0	0
T8	204190	201770	0	0
T9	424060	415180	0	0
T10	125780	122940	0	0
T11	105770	103070	0	0
T12	408070	402320	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	400310	395980	0	0
T2	1017000	1008380	0	0
T3	3601680	3601580	0	0
T6	228980	224300	0	0
T7	558130	549530	0	0
T8	204190	201770	0	0
T9	424060	415180	0	0
T10	125780	122940	0	0
T11	105770	103070	0	0
T12	408070	402320	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	1953940012	44015112	0	0
T1	160124	6485	0	0
T2	406800	13496	0	0
T3	1440672	581346	0	0
T6	91592	6503	0	0
T7	223252	13569	0	0
T8	81676	4719	0	0
T9	169624	22616	0	0
T10	50312	3309	0	0
T11	42308	3364	0	0
T12	163228	7362	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	7956	7956	0	0
T1	6	6	0	0
T2	6	6	0	0
T3	6	6	0	0
T6	6	6	0	0
T7	6	6	0	0
T8	6	6	0	0
T9	6	6	0	0
T10	6	6	0	0
T11	6	6	0	0
T12	6	6	0	0

Line Coverage for Instance : tb.dut.u_otp_rsp_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_otp_rsp_fifo

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Covered	T1,T2,T3
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_otp_rsp_fifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_otp_rsp_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	488485003	17695690	0	0
DepthKnown_A	488485003	487595921	0	0
RvalidKnown_A	488485003	487595921	0	0
WreadyKnown_A	488485003	487595921	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	488485003	17695690	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	17695690	0	0
T1	40031	6244	0	0
T2	101700	12572	0	0
T3	360168	51237	0	0
T6	22898	6374	0	0
T7	55813	13362	0	0
T8	20419	4251	0	0
T9	42406	22085	0	0
T10	12578	2994	0	0
T11	10577	2944	0	0
T12	40807	7036	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	17695690	0	0
T1	40031	6244	0	0
T2	101700	12572	0	0
T3	360168	51237	0	0
T6	22898	6374	0	0
T7	55813	13362	0	0
T8	20419	4251	0	0
T9	42406	22085	0	0
T10	12578	2994	0	0
T11	10577	2944	0	0
T12	40807	7036	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	491578502	55161527	0	0
DepthKnown_A	491578502	490635532	0	0
RvalidKnown_A	491578502	490635532	0	0
WreadyKnown_A	491578502	490635532	0	0
gen_passthru_fifo.paramCheckPass	1326	1326	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491578502	55161527	0	0
T1	40031	2095	0	0
T2	101700	8339	0	0
T3	360168	517904	0	0
T6	22898	4196	0	0
T7	55813	2852	0	0
T8	20419	563	0	0
T9	42406	5384	0	0
T10	12578	963	0	0
T11	10577	1158	0	0
T12	40807	1793	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491578502	490635532	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491578502	490635532	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491578502	490635532	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1326	1326	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	491578502	64189150	0	0
DepthKnown_A	491578502	490635532	0	0
RvalidKnown_A	491578502	490635532	0	0
WreadyKnown_A	491578502	490635532	0	0
gen_passthru_fifo.paramCheckPass	1326	1326	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491578502	64189150	0	0
T1	40031	9197	0	0
T2	101700	8423	0	0
T3	360168	109557	0	0
T6	22898	4196	0	0
T7	55813	2874	0	0
T8	20419	2461	0	0
T9	42406	5384	0	0
T10	12578	963	0	0
T11	10577	1158	0	0
T12	40807	1830	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491578502	490635532	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491578502	490635532	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491578502	490635532	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1326	1326	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	491578502	18277271	0	0
DepthKnown_A	491578502	490635532	0	0
RvalidKnown_A	491578502	490635532	0	0
WreadyKnown_A	491578502	490635532	0	0
gen_passthru_fifo.paramCheckPass	1326	1326	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491578502	18277271	0	0
T1	40031	17	0	0
T2	101700	72	0	0
T3	360168	181643	0	0
T6	22898	25	0	0
T7	55813	15	0	0
T8	20419	16	0	0
T9	42406	57	0	0
T10	12578	15	0	0
T11	10577	20	0	0
T12	40807	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491578502	490635532	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491578502	490635532	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491578502	490635532	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1326	1326	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	491578502	24868399	0	0
DepthKnown_A	491578502	490635532	0	0
RvalidKnown_A	491578502	490635532	0	0
WreadyKnown_A	491578502	490635532	0	0
gen_passthru_fifo.paramCheckPass	1326	1326	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491578502	24868399	0	0
T1	40031	67	0	0
T2	101700	156	0	0
T3	360168	529545	0	0
T6	22898	25	0	0
T7	55813	37	0	0
T8	20419	82	0	0
T9	42406	57	0	0
T10	12578	15	0	0
T11	10577	20	0	0
T12	40807	49	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491578502	490635532	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491578502	490635532	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491578502	490635532	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1326	1326	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	491578502	26948452	0	0
DepthKnown_A	491578502	490635532	0	0
RvalidKnown_A	491578502	490635532	0	0
WreadyKnown_A	491578502	490635532	0	0
gen_passthru_fifo.paramCheckPass	1326	1326	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491578502	26948452	0	0
T1	40031	2078	0	0
T2	101700	8267	0	0
T3	360168	192604	0	0
T6	22898	4171	0	0
T7	55813	2837	0	0
T8	20419	547	0	0
T9	42406	5327	0	0
T10	12578	948	0	0
T11	10577	1138	0	0
T12	40807	1781	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491578502	490635532	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491578502	490635532	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491578502	490635532	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1326	1326	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	491578502	39320751	0	0
DepthKnown_A	491578502	490635532	0	0
RvalidKnown_A	491578502	490635532	0	0
WreadyKnown_A	491578502	490635532	0	0
gen_passthru_fifo.paramCheckPass	1326	1326	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491578502	39320751	0	0
T1	40031	9130	0	0
T2	101700	8267	0	0
T3	360168	566034	0	0
T6	22898	4171	0	0
T7	55813	2837	0	0
T8	20419	2379	0	0
T9	42406	5327	0	0
T10	12578	948	0	0
T11	10577	1138	0	0
T12	40807	1781	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491578502	490635532	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491578502	490635532	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491578502	490635532	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1326	1326	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo

	Total	Covered	Percent
Conditions	11	11	100.00
Logical	11	11	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Covered	T1,T2,T3
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	488485003	25404960	0	0
DepthKnown_A	488485003	487595921	0	0
RvalidKnown_A	488485003	487595921	0	0
WreadyKnown_A	488485003	487595921	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	488485003	25404960	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	25404960	0	0
T1	40031	112	0	0
T2	101700	426	0	0
T3	360168	529701	0	0
T6	22898	52	0	0
T7	55813	96	0	0
T8	20419	226	0	0
T9	42406	237	0	0
T10	12578	150	0	0
T11	10577	200	0	0
T12	40807	157	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	25404960	0	0
T1	40031	112	0	0
T2	101700	426	0	0
T3	360168	529701	0	0
T6	22898	52	0	0
T7	55813	96	0	0
T8	20419	226	0	0
T9	42406	237	0	0
T10	12578	150	0	0
T11	10577	200	0	0
T12	40807	157	0	0

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	11	11	100.00
Logical	11	11	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Covered	T1,T2,T3
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	488485003	658164	0	0
DepthKnown_A	488485003	487595921	0	0
RvalidKnown_A	488485003	487595921	0	0
WreadyKnown_A	488485003	487595921	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	488485003	658164	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	658164	0	0
T1	40031	62	0	0
T2	101700	342	0	0
T3	360168	200	0	0
T6	22898	52	0	0
T7	55813	74	0	0
T8	20419	160	0	0
T9	42406	237	0	0
T10	12578	150	0	0
T11	10577	200	0	0
T12	40807	120	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	658164	0	0
T1	40031	62	0	0
T2	101700	342	0	0
T3	360168	200	0	0
T6	22898	52	0	0
T7	55813	74	0	0
T8	20419	160	0	0
T9	42406	237	0	0
T10	12578	150	0	0
T11	10577	200	0	0
T12	40807	120	0	0

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo

	Total	Covered	Percent
Conditions	18	18	100.00
Logical	18	18	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Covered	T1,T2,T3
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	488485003	256298	0	0
DepthKnown_A	488485003	487595921	0	0
RvalidKnown_A	488485003	487595921	0	0
WreadyKnown_A	488485003	487595921	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	488485003	256298	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	256298	0	0
T1	40031	67	0	0
T2	101700	156	0	0
T3	360168	208	0	0
T6	22898	25	0	0
T7	55813	37	0	0
T8	20419	82	0	0
T9	42406	57	0	0
T10	12578	15	0	0
T11	10577	20	0	0
T12	40807	49	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	487595921	0	0
T1	40031	39598	0	0
T2	101700	100838	0	0
T3	360168	360158	0	0
T6	22898	22430	0	0
T7	55813	54953	0	0
T8	20419	20177	0	0
T9	42406	41518	0	0
T10	12578	12294	0	0
T11	10577	10307	0	0
T12	40807	40232	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	488485003	256298	0	0
T1	40031	67	0	0
T2	101700	156	0	0
T3	360168	208	0	0
T6	22898	25	0	0
T7	55813	37	0	0
T8	20419	82	0	0
T9	42406	57	0	0
T10	12578	15	0	0
T11	10577	20	0	0
T12	40807	49	0	0