Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

28596781

1

T1

723

T2

15834

T3

766

full_word

9246929

1

T1

192

T2

12373

T3

331

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	37843390	1			T1	915		T2	28207		T3	1097
auto[TlIntgErrCmd]	115	1			T247	5		T248	2		T249	5
auto[TlIntgErrData]	103	1			T247	4		T248	3		T249	10
auto[TlIntgErrBoth]	102	1			T247	1		T248	5		T249	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10459459

1

T1

711

T2

23618

T3

987

auto[1]

27384251

1

T1

204

T2

4589

T3

110

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6561111	1			T1	618		T2	13259		T3	694
auto[TlIntgErrNone]	partial	auto[1]	22035382	1			T1	105		T2	2575		T3	72
auto[TlIntgErrNone]	full_word	auto[0]	3898198	1			T1	93		T2	10359		T3	293
auto[TlIntgErrNone]	full_word	auto[1]	5348699	1			T1	99		T2	2014		T3	38
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T247	2		T248	1		T249	2
auto[TlIntgErrCmd]	partial	auto[1]	61	1			T247	2		T248	1		T249	3
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T345	1		T353	1		T350	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T247	1		T347	1		T354	1
auto[TlIntgErrData]	partial	auto[0]	51	1			T247	2		T248	3		T249	4
auto[TlIntgErrData]	partial	auto[1]	39	1			T247	1		T249	5		T345	3
auto[TlIntgErrData]	full_word	auto[0]	8	1			T249	1		T349	1		T348	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T247	1		T346	1		T352	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T248	2		T249	1		T345	2
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T247	1		T248	3		T249	2
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T345	1		T347	1		T348	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T249	2		T353	1		T355	1