Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.68	96.75	96.15	96.90		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	521678968	9184397	0	0
check_regwen_rd_A	521678968	3600	0	0
check_timeout_rd_A	521678968	2799	0	0
check_trigger_regwen_rd_A	521678968	3672	0	0
consistency_check_period_rd_A	521678968	3940	0	0
creator_sw_cfg_read_lock_rd_A	521678968	2971	0	0
direct_access_address_rd_A	521678968	1901	0	0
direct_access_wdata_0_rd_A	521678968	1248	0	0
direct_access_wdata_1_rd_A	521678968	1627	0	0
integrity_check_period_rd_A	521678968	3783	0	0
intr_enable_rd_A	521678968	4610	0	0
owner_sw_cfg_read_lock_rd_A	521678968	2621	0	0
rot_creator_auth_codesign_read_lock_rd_A	521678968	2857	0	0
rot_creator_auth_state_read_lock_rd_A	521678968	2530	0	0
vendor_test_read_lock_rd_A	521678968	2411	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521678968	9184397	0	0
T13	427323	98704	0	0
T14	0	101731	0	0
T15	0	14254	0	0
T19	0	55663	0	0
T20	0	145607	0	0
T28	9074	0	0	0
T31	110268	0	0	0
T72	15798	0	0	0
T100	132493	0	0	0
T101	73213	0	0	0
T120	73714	0	0	0
T132	92599	0	0	0
T173	121434	0	0	0
T194	0	86377	0	0
T200	0	56454	0	0
T253	0	126838	0	0
T254	0	80228	0	0
T255	0	125965	0	0
T256	27795	0	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521678968	3600	0	0
T15	707482	43	0	0
T19	259971	0	0	0
T30	17232	0	0	0
T61	146903	0	0	0
T116	113649	0	0	0
T154	8083	0	0	0
T155	9612	0	0	0
T192	0	111	0	0
T214	0	95	0	0
T221	0	81	0	0
T231	0	127	0	0
T265	0	174	0	0
T316	4483	0	0	0
T325	0	153	0	0
T326	0	44	0	0
T327	0	45	0	0
T328	0	111	0	0
T329	9274	0	0	0
T330	9374	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521678968	2799	0	0
T15	707482	22	0	0
T19	259971	0	0	0
T30	17232	0	0	0
T61	146903	0	0	0
T116	113649	0	0	0
T154	8083	0	0	0
T155	9612	0	0	0
T192	0	122	0	0
T214	0	58	0	0
T221	0	146	0	0
T231	0	141	0	0
T265	0	140	0	0
T316	4483	0	0	0
T325	0	174	0	0
T326	0	36	0	0
T327	0	17	0	0
T328	0	111	0	0
T329	9274	0	0	0
T330	9374	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521678968	3672	0	0
T15	707482	33	0	0
T19	259971	0	0	0
T30	17232	0	0	0
T61	146903	0	0	0
T116	113649	0	0	0
T154	8083	0	0	0
T155	9612	0	0	0
T192	0	140	0	0
T214	0	120	0	0
T221	0	91	0	0
T231	0	139	0	0
T265	0	119	0	0
T316	4483	0	0	0
T325	0	163	0	0
T326	0	55	0	0
T327	0	4	0	0
T328	0	120	0	0
T329	9274	0	0	0
T330	9374	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521678968	3940	0	0
T15	707482	36	0	0
T19	259971	0	0	0
T30	17232	0	0	0
T61	146903	0	0	0
T116	113649	0	0	0
T154	8083	0	0	0
T155	9612	0	0	0
T192	0	146	0	0
T214	0	143	0	0
T221	0	135	0	0
T231	0	161	0	0
T265	0	206	0	0
T316	4483	0	0	0
T325	0	238	0	0
T326	0	54	0	0
T327	0	26	0	0
T328	0	98	0	0
T329	9274	0	0	0
T330	9374	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521678968	2971	0	0
T15	707482	35	0	0
T19	259971	0	0	0
T30	17232	0	0	0
T61	146903	0	0	0
T116	113649	0	0	0
T154	8083	0	0	0
T155	9612	0	0	0
T192	0	148	0	0
T214	0	95	0	0
T221	0	130	0	0
T231	0	139	0	0
T265	0	142	0	0
T316	4483	0	0	0
T325	0	244	0	0
T326	0	54	0	0
T327	0	20	0	0
T328	0	153	0	0
T329	9274	0	0	0
T330	9374	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521678968	1901	0	0
T15	707482	31	0	0
T19	259971	0	0	0
T30	17232	0	0	0
T61	146903	0	0	0
T116	113649	0	0	0
T154	8083	0	0	0
T155	9612	0	0	0
T192	0	196	0	0
T214	0	51	0	0
T221	0	68	0	0
T231	0	132	0	0
T265	0	165	0	0
T316	4483	0	0	0
T325	0	184	0	0
T326	0	26	0	0
T327	0	39	0	0
T328	0	76	0	0
T329	9274	0	0	0
T330	9374	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521678968	1248	0	0
T15	707482	23	0	0
T19	259971	0	0	0
T30	17232	0	0	0
T61	146903	0	0	0
T116	113649	0	0	0
T154	8083	0	0	0
T155	9612	0	0	0
T192	0	119	0	0
T214	0	48	0	0
T221	0	98	0	0
T231	0	90	0	0
T265	0	87	0	0
T316	4483	0	0	0
T325	0	125	0	0
T326	0	27	0	0
T327	0	22	0	0
T328	0	45	0	0
T329	9274	0	0	0
T330	9374	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521678968	1627	0	0
T15	707482	10	0	0
T19	259971	0	0	0
T30	17232	0	0	0
T61	146903	0	0	0
T116	113649	0	0	0
T154	8083	0	0	0
T155	9612	0	0	0
T192	0	94	0	0
T214	0	51	0	0
T221	0	108	0	0
T231	0	130	0	0
T265	0	104	0	0
T316	4483	0	0	0
T325	0	179	0	0
T326	0	17	0	0
T327	0	9	0	0
T328	0	57	0	0
T329	9274	0	0	0
T330	9374	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521678968	3783	0	0
T15	707482	16	0	0
T19	259971	0	0	0
T30	17232	0	0	0
T61	146903	0	0	0
T116	113649	0	0	0
T154	8083	0	0	0
T155	9612	0	0	0
T192	0	91	0	0
T214	0	91	0	0
T221	0	160	0	0
T231	0	80	0	0
T265	0	125	0	0
T316	4483	0	0	0
T325	0	297	0	0
T326	0	24	0	0
T327	0	56	0	0
T328	0	81	0	0
T329	9274	0	0	0
T330	9374	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521678968	4610	0	0
T2	507787	40	0	0
T3	17891	0	0	0
T4	13156	0	0	0
T5	25666	0	0	0
T7	0	39	0	0
T8	11548	0	0	0
T9	77887	0	0	0
T10	15818	0	0	0
T11	25459	0	0	0
T12	132921	0	0	0
T15	0	40	0	0
T16	0	24	0	0
T67	15186	0	0	0
T147	0	36	0	0
T206	0	13	0	0
T214	0	58	0	0
T231	0	112	0	0
T265	0	155	0	0
T325	0	215	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521678968	2621	0	0
T15	707482	50	0	0
T19	259971	0	0	0
T30	17232	0	0	0
T61	146903	0	0	0
T116	113649	0	0	0
T154	8083	0	0	0
T155	9612	0	0	0
T192	0	179	0	0
T214	0	80	0	0
T221	0	102	0	0
T231	0	148	0	0
T265	0	118	0	0
T316	4483	0	0	0
T325	0	193	0	0
T326	0	53	0	0
T327	0	5	0	0
T328	0	84	0	0
T329	9274	0	0	0
T330	9374	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521678968	2857	0	0
T15	707482	40	0	0
T19	259971	0	0	0
T30	17232	0	0	0
T61	146903	0	0	0
T116	113649	0	0	0
T154	8083	0	0	0
T155	9612	0	0	0
T192	0	184	0	0
T214	0	72	0	0
T221	0	132	0	0
T231	0	129	0	0
T265	0	144	0	0
T316	4483	0	0	0
T325	0	205	0	0
T326	0	56	0	0
T327	0	5	0	0
T328	0	147	0	0
T329	9274	0	0	0
T330	9374	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521678968	2530	0	0
T15	707482	29	0	0
T19	259971	0	0	0
T30	17232	0	0	0
T61	146903	0	0	0
T116	113649	0	0	0
T154	8083	0	0	0
T155	9612	0	0	0
T192	0	174	0	0
T214	0	68	0	0
T221	0	79	0	0
T231	0	118	0	0
T265	0	130	0	0
T316	4483	0	0	0
T325	0	153	0	0
T326	0	38	0	0
T327	0	35	0	0
T328	0	70	0	0
T329	9274	0	0	0
T330	9374	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521678968	2411	0	0
T15	707482	26	0	0
T19	259971	0	0	0
T30	17232	0	0	0
T61	146903	0	0	0
T116	113649	0	0	0
T154	8083	0	0	0
T155	9612	0	0	0
T192	0	120	0	0
T214	0	98	0	0
T221	0	76	0	0
T231	0	140	0	0
T265	0	100	0	0
T316	4483	0	0	0
T325	0	171	0	0
T326	0	50	0	0
T327	0	27	0	0
T328	0	70	0	0
T329	9274	0	0	0
T330	9374	0	0	0