Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.23	100.00	100.00		90.00	100.00	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.56	100.00	100.00	100.00	90.00	98.15	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.68	96.75	96.15	96.90		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.68	96.75	96.15	96.90		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.68	96.75	96.15	96.90		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		86	86	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	61	61	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
153	1	1
154	1	1
156	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			==> MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
224		excluded
			Exclude Annotation: VC_COV_UNR
225		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
276		excluded
			Exclude Annotation: VC_COV_UNR
277		excluded
			Exclude Annotation: VC_COV_UNR
279		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
339	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T4
1	Excluded		VC_COV_UNR

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T24,T25,T26

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T71,T127,T128
1	Covered	T71,T127,T128

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T9

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T9

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	11	84.62
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T3
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T4
ReadWaitSt	252	Covered	T1,T2,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T2,T3
IdleSt->ReadSt	236	Covered	T1,T2,T4
InitSt->ErrorSt	315	Covered	T169
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T16,T170,T116
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T2,T9,T6
ReadSt->ReadWaitSt	252	Covered	T1,T2,T4
ReadWaitSt->ErrorSt	276	Not Covered
ReadWaitSt->IdleSt	270	Covered	T1,T2,T4
ResetSt->ErrorSt	315	Covered	T71,T72,T73
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests	Exclude Annotation
AccessError	256	Covered	T2,T9,T6
CheckFailError	317	Covered	T71,T127,T128
FsmStateError	289	Covered	T1,T2,T3
MacroEccCorrError	221	Excluded		VC_COV_UNR
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded
AccessError->FsmStateError	325	Covered	T6,T7,T16
AccessError->MacroEccCorrError	221	Excluded
AccessError->NoError	235	Covered	T2,T9,T7
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded
CheckFailError->NoError	235	Covered	T71,T127,T128
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded
FsmStateError->NoError	235	Covered	T1,T2,T3
MacroEccCorrError->AccessError	256	Excluded
MacroEccCorrError->CheckFailError	317	Excluded
MacroEccCorrError->FsmStateError	325	Excluded
MacroEccCorrError->NoError	235	Excluded
NoError->AccessError	256	Covered	T2,T9,T6
NoError->CheckFailError	317	Covered	T71,T127,T128
NoError->FsmStateError	289	Covered	T1,T2,T3
NoError->MacroEccCorrError	221	Excluded

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	18	18	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests	Exclude Annotation
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T2,T9,T16
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T9,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T24,T25,T26
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T3,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T3,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T24,T25,T26

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T71,T127,T128
1	0	Covered	T71,T127,T128
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	518661565	517802780	0	0
DigestKnown_A	518661565	517802780	0	0
DigestOffsetMustBeRepresentable_A	1156	1156	0	0
EccErrorState_A	518661565	10274	0	0
ErrorKnown_A	518661565	517802780	0	0
FsmStateKnown_A	518661565	517802780	0	0
InitDoneKnown_A	518661565	517802780	0	0
InitReadLocksPartition_A	518661565	105703900	0	0
InitWriteLocksPartition_A	518661565	105703900	0	0
OffsetMustBeBlockAligned_A	1156	1156	0	0
OtpAddrKnown_A	518661565	517802780	0	0
OtpCmdKnown_A	518661565	517802780	0	0
OtpErrorState_A	518661565	0	0	0
OtpReqKnown_A	518661565	517802780	0	0
OtpSizeKnown_A	518661565	517802780	0	0
OtpWdataKnown_A	518661565	517802780	0	0
ReadLockPropagation_A	518661565	234314709	0	0
SizeMustBeBlockAligned_A	1156	1156	0	0
TlulGntKnown_A	518661565	517802780	0	0
TlulRdataKnown_A	518661565	517802780	0	0
TlulReadOnReadLock_A	518661565	8270	0	0
TlulRerrorKnown_A	518661565	517802780	0	0
TlulRvalidKnown_A	518661565	517802780	0	0
WriteLockPropagation_A	518661565	2468084	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	518661565	27073027	0	0
u_state_regs_A	518661565	517802780	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1156	1156	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	10274	0	0
T44	194124	0	0	0
T45	164675	0	0	0
T71	15893	4027	0	0
T82	40862	0	0	0
T97	50373	0	0	0
T98	124275	0	0	0
T127	0	3702	0	0
T128	0	2545	0	0
T137	13210	0	0	0
T138	134975	0	0	0
T139	11983	0	0	0
T140	8686	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	105703900	0	0
T1	8832	3824	0	0
T2	507787	196447	0	0
T3	17891	6738	0	0
T4	13156	171	0	0
T5	25666	2221	0	0
T8	11548	4679	0	0
T9	77887	1874	0	0
T10	15818	3421	0	0
T11	25459	1393	0	0
T12	132921	10078	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	105703900	0	0
T1	8832	3824	0	0
T2	507787	196447	0	0
T3	17891	6738	0	0
T4	13156	171	0	0
T5	25666	2221	0	0
T8	11548	4679	0	0
T9	77887	1874	0	0
T10	15818	3421	0	0
T11	25459	1393	0	0
T12	132921	10078	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1156	1156	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	234314709	0	0
T2	507787	33503	0	0
T3	17891	0	0	0
T4	13156	0	0	0
T5	25666	0	0	0
T6	0	12332	0	0
T7	0	376381	0	0
T8	11548	0	0	0
T9	77887	6446	0	0
T10	15818	0	0	0
T11	25459	0	0	0
T12	132921	0	0	0
T16	0	214511	0	0
T17	0	2525	0	0
T66	0	5096	0	0
T67	15186	0	0	0
T96	0	7079	0	0
T97	0	8485	0	0
T162	0	1383	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1156	1156	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	8270	0	0
T2	507787	41	0	0
T3	17891	1	0	0
T4	13156	0	0	0
T5	25666	0	0	0
T6	0	9	0	0
T7	0	80	0	0
T8	11548	0	0	0
T9	77887	7	0	0
T10	15818	0	0	0
T11	25459	0	0	0
T12	132921	0	0	0
T16	0	69	0	0
T17	0	2	0	0
T67	15186	0	0	0
T90	0	18	0	0
T104	0	1	0	0
T163	0	14	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	2468084	0	0
T2	507787	22184	0	0
T3	17891	0	0	0
T4	13156	0	0	0
T5	25666	0	0	0
T7	0	128973	0	0
T8	11548	0	0	0
T9	77887	5256	0	0
T10	15818	0	0	0
T11	25459	0	0	0
T12	132921	0	0	0
T16	0	62191	0	0
T17	0	6560	0	0
T31	0	9974	0	0
T67	15186	0	0	0
T99	0	59699	0	0
T100	0	31661	0	0
T101	0	2642	0	0
T120	0	3005	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	27073027	0	0
T1	8832	2367	0	0
T2	507787	209595	0	0
T3	17891	0	0	0
T4	13156	0	0	0
T5	25666	0	0	0
T7	0	138510	0	0
T8	11548	0	0	0
T9	77887	66754	0	0
T10	15818	0	0	0
T11	25459	0	0	0
T12	132921	26836	0	0
T16	0	495372	0	0
T17	0	58313	0	0
T27	0	4088	0	0
T43	0	3215	0	0
T67	0	3728	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T93,T28,T129

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T44,T45,T31

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T24,T25,T26

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T71,T72,T128
1	Covered	T71,T72,T128

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T9,T6
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T9

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T9

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T3
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T3,T8
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T16,T170,T116
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T1,T67,T135
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T2,T9,T7
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Covered	T133,T171,T172
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T71,T72,T73
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T2,T9,T7
CheckFailError	317	Covered	T71,T72,T128
FsmStateError	289	Covered	T2,T3,T8
MacroEccCorrError	221	Covered	T93,T44,T45
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T138,T173,T147
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T2,T9,T7
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T71,T72,T128
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T3,T8
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T93,T28,T129
MacroEccCorrError->NoError	235	Covered	T44,T45,T31
NoError->AccessError	256	Covered	T2,T9,T7
NoError->CheckFailError	317	Covered	T71,T72,T128
NoError->FsmStateError	289	Covered	T2,T3,T8
NoError->MacroEccCorrError	221	Covered	T93,T44,T45

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T93,T28,T129
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T67,T135
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T9,T7,T16
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T9,T7
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T44,T45,T31
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T133,T171,T172
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T24,T25,T26
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T6,T104
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T6,T104
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T24,T25,T26

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T71,T72,T128
1	0	Covered	T71,T72,T128
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T8
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	518661565	517802780	0	0
DigestKnown_A	518661565	517802780	0	0
DigestOffsetMustBeRepresentable_A	1156	1156	0	0
EccErrorState_A	518661565	10954	0	0
ErrorKnown_A	518661565	517802780	0	0
FsmStateKnown_A	518661565	517802780	0	0
InitDoneKnown_A	518661565	517802780	0	0
InitReadLocksPartition_A	518661565	105886378	0	0
InitWriteLocksPartition_A	518661565	105886378	0	0
OffsetMustBeBlockAligned_A	1156	1156	0	0
OtpAddrKnown_A	518661565	517802780	0	0
OtpCmdKnown_A	518661565	517802780	0	0
OtpErrorState_A	518661565	77	0	0
OtpReqKnown_A	518661565	517802780	0	0
OtpSizeKnown_A	518661565	517802780	0	0
OtpWdataKnown_A	518661565	517802780	0	0
ReadLockPropagation_A	518661565	231674719	0	0
SizeMustBeBlockAligned_A	1156	1156	0	0
TlulGntKnown_A	518661565	517802780	0	0
TlulRdataKnown_A	518661565	517802780	0	0
TlulReadOnReadLock_A	518661565	8683	0	0
TlulRerrorKnown_A	518661565	517802780	0	0
TlulRvalidKnown_A	518661565	517802780	0	0
WriteLockPropagation_A	518661565	2386853	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	518661565	26667143	0	0
u_state_regs_A	518661565	517802780	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1156	1156	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	10954	0	0
T44	194124	0	0	0
T45	164675	0	0	0
T71	15893	4027	0	0
T72	0	2092	0	0
T82	40862	0	0	0
T97	50373	0	0	0
T98	124275	0	0	0
T128	0	2545	0	0
T136	0	2290	0	0
T137	13210	0	0	0
T138	134975	0	0	0
T139	11983	0	0	0
T140	8686	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	105886378	0	0
T1	8832	3848	0	0
T2	507787	197382	0	0
T3	17891	6806	0	0
T4	13156	205	0	0
T5	25666	2340	0	0
T8	11548	4713	0	0
T9	77887	2197	0	0
T10	15818	3455	0	0
T11	25459	1512	0	0
T12	132921	10214	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	105886378	0	0
T1	8832	3848	0	0
T2	507787	197382	0	0
T3	17891	6806	0	0
T4	13156	205	0	0
T5	25666	2340	0	0
T8	11548	4713	0	0
T9	77887	2197	0	0
T10	15818	3455	0	0
T11	25459	1512	0	0
T12	132921	10214	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1156	1156	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	77	0	0
T1	8832	1	0	0
T2	507787	0	0	0
T3	17891	0	0	0
T4	13156	0	0	0
T5	25666	0	0	0
T8	11548	0	0	0
T9	77887	0	0	0
T10	15818	0	0	0
T11	25459	0	0	0
T12	132921	0	0	0
T67	0	1	0	0
T135	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	231674719	0	0
T2	507787	52136	0	0
T3	17891	0	0	0
T4	13156	0	0	0
T5	25666	0	0	0
T6	0	10021	0	0
T7	0	196618	0	0
T8	11548	0	0	0
T9	77887	6300	0	0
T10	15818	0	0	0
T11	25459	0	0	0
T12	132921	0	0	0
T16	0	215258	0	0
T17	0	3446	0	0
T66	0	5539	0	0
T67	15186	0	0	0
T96	0	9211	0	0
T97	0	9223	0	0
T162	0	922	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1156	1156	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	8683	0	0
T2	507787	44	0	0
T3	17891	0	0	0
T4	13156	0	0	0
T5	25666	0	0	0
T6	0	4	0	0
T7	0	85	0	0
T8	11548	0	0	0
T9	77887	10	0	0
T10	15818	0	0	0
T11	25459	0	0	0
T12	132921	0	0	0
T16	0	59	0	0
T17	0	5	0	0
T67	15186	0	0	0
T90	0	12	0	0
T91	0	23	0	0
T104	0	4	0	0
T163	0	6	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	2386853	0	0
T2	507787	16712	0	0
T3	17891	0	0	0
T4	13156	0	0	0
T5	25666	0	0	0
T7	0	125230	0	0
T8	11548	0	0	0
T9	77887	2570	0	0
T10	15818	0	0	0
T11	25459	0	0	0
T12	132921	0	0	0
T16	0	45881	0	0
T31	0	14901	0	0
T67	15186	0	0	0
T99	0	59526	0	0
T100	0	8082	0	0
T101	0	4219	0	0
T120	0	6661	0	0
T146	0	2694	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	26667143	0	0
T1	8832	2362	0	0
T2	507787	213772	0	0
T3	17891	0	0	0
T4	13156	0	0	0
T5	25666	0	0	0
T7	0	148774	0	0
T8	11548	0	0	0
T9	77887	66465	0	0
T10	15818	0	0	0
T11	25459	0	0	0
T12	132921	26802	0	0
T16	0	468190	0	0
T17	0	52694	0	0
T67	0	3723	0	0
T135	0	2436	0	0
T162	0	7559	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T130,T123

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T66,T45,T31

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T24,T25,T26

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T72,T127,T131
1	Covered	T72,T127,T131

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00111101000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T9,T7

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T9,T7

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T3
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T4
ReadWaitSt	252	Covered	T1,T2,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T3,T8
IdleSt->ReadSt	236	Covered	T1,T2,T4
InitSt->ErrorSt	315	Covered	T16,T170,T116
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T1,T67,T7
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T2,T9,T12
ReadSt->ReadWaitSt	252	Covered	T1,T2,T4
ReadWaitSt->ErrorSt	276	Covered	T132,T133,T174
ReadWaitSt->IdleSt	270	Covered	T1,T2,T4
ResetSt->ErrorSt	315	Covered	T71,T72,T73
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T2,T9,T12
CheckFailError	317	Covered	T72,T127,T131
FsmStateError	289	Covered	T1,T2,T3
MacroEccCorrError	221	Covered	T8,T66,T45
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T6,T7,T138
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T2,T9,T12
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T72,T127,T131
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T2,T3
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T8,T130,T123
MacroEccCorrError->NoError	235	Covered	T66,T45,T31
NoError->AccessError	256	Covered	T2,T9,T12
NoError->CheckFailError	317	Covered	T72,T127,T131
NoError->FsmStateError	289	Covered	T1,T2,T3
NoError->MacroEccCorrError	221	Covered	T8,T66,T45

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T8,T130,T123
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T148,T145,T129
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T2,T9,T16
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T9,T12
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T66,T45,T31
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T132,T133,T174
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T24,T25,T26
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T3,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T3,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T24,T25,T26

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T72,T127,T131
1	0	Covered	T72,T127,T131
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	518661565	517802780	0	0
DigestKnown_A	518661565	517802780	0	0
DigestOffsetMustBeRepresentable_A	1156	1156	0	0
EccErrorState_A	518661565	8344	0	0
ErrorKnown_A	518661565	517802780	0	0
FsmStateKnown_A	518661565	517802780	0	0
InitDoneKnown_A	518661565	517802780	0	0
InitReadLocksPartition_A	518661565	106067642	0	0
InitWriteLocksPartition_A	518661565	106067642	0	0
OffsetMustBeBlockAligned_A	1156	1156	0	0
OtpAddrKnown_A	518661565	517802780	0	0
OtpCmdKnown_A	518661565	517802780	0	0
OtpErrorState_A	518661565	45	0	0
OtpReqKnown_A	518661565	517802780	0	0
OtpSizeKnown_A	518661565	517802780	0	0
OtpWdataKnown_A	518661565	517802780	0	0
ReadLockPropagation_A	518661565	235239902	0	0
SizeMustBeBlockAligned_A	1156	1156	0	0
TlulGntKnown_A	518661565	517802780	0	0
TlulRdataKnown_A	518661565	517802780	0	0
TlulReadOnReadLock_A	518661565	8744	0	0
TlulRerrorKnown_A	518661565	517802780	0	0
TlulRvalidKnown_A	518661565	517802780	0	0
WriteLockPropagation_A	518661565	1450752	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	518661565	16448885	0	0
u_state_regs_A	518661565	517802780	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1156	1156	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	8344	0	0
T14	450942	0	0	0
T72	15798	2092	0	0
T127	0	3702	0	0
T131	0	2550	0	0
T132	92599	0	0	0
T141	16842	0	0	0
T142	20599	0	0	0
T143	25677	0	0	0
T144	24974	0	0	0
T145	13988	0	0	0
T146	50287	0	0	0
T147	523013	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	106067642	0	0
T1	8832	3865	0	0
T2	507787	198317	0	0
T3	17891	6874	0	0
T4	13156	239	0	0
T5	25666	2459	0	0
T8	11548	4747	0	0
T9	77887	2520	0	0
T10	15818	3489	0	0
T11	25459	1631	0	0
T12	132921	10350	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	106067642	0	0
T1	8832	3865	0	0
T2	507787	198317	0	0
T3	17891	6874	0	0
T4	13156	239	0	0
T5	25666	2459	0	0
T8	11548	4747	0	0
T9	77887	2520	0	0
T10	15818	3489	0	0
T11	25459	1631	0	0
T12	132921	10350	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1156	1156	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	45	0	0
T44	194124	0	0	0
T71	15893	0	0	0
T82	40862	0	0	0
T97	50373	0	0	0
T98	124275	0	0	0
T129	0	1	0	0
T132	0	2	0	0
T137	13210	0	0	0
T138	134975	0	0	0
T139	11983	0	0	0
T140	8686	0	0	0
T145	0	1	0	0
T148	12822	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T157	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	235239902	0	0
T2	507787	35589	0	0
T3	17891	0	0	0
T4	13156	0	0	0
T5	25666	0	0	0
T6	0	12330	0	0
T7	0	356734	0	0
T8	11548	0	0	0
T9	77887	4817	0	0
T10	15818	0	0	0
T11	25459	0	0	0
T12	132921	7887	0	0
T16	0	193224	0	0
T17	0	2808	0	0
T66	0	5535	0	0
T67	15186	0	0	0
T96	0	6769	0	0
T162	0	1381	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1156	1156	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	8744	0	0
T2	507787	41	0	0
T3	17891	1	0	0
T4	13156	0	0	0
T5	25666	0	0	0
T6	0	7	0	0
T7	0	88	0	0
T8	11548	0	0	0
T9	77887	8	0	0
T10	15818	0	0	0
T11	25459	0	0	0
T12	132921	1	0	0
T16	0	85	0	0
T17	0	3	0	0
T67	15186	0	0	0
T104	0	2	0	0
T163	0	17	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	1450752	0	0
T2	507787	3557	0	0
T3	17891	0	0	0
T4	13156	0	0	0
T5	25666	0	0	0
T7	0	94812	0	0
T8	11548	0	0	0
T9	77887	1126	0	0
T10	15818	0	0	0
T11	25459	0	0	0
T12	132921	0	0	0
T16	0	29350	0	0
T39	0	67350	0	0
T67	15186	0	0	0
T98	0	9709	0	0
T144	0	5698	0	0
T165	0	6069	0	0
T166	0	11127	0	0
T167	0	2082	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	16448885	0	0
T2	507787	63601	0	0
T3	17891	0	0	0
T4	13156	0	0	0
T5	25666	0	0	0
T7	0	702951	0	0
T8	11548	0	0	0
T9	77887	66176	0	0
T10	15818	0	0	0
T11	25459	0	0	0
T12	132921	0	0	0
T16	0	304335	0	0
T17	0	52507	0	0
T67	15186	0	0	0
T98	0	106298	0	0
T100	0	114604	0	0
T101	0	55702	0	0
T120	0	55450	0	0
T148	0	3549	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518661565	517802780	0	0
T1	8832	8590	0	0
T2	507787	503197	0	0
T3	17891	17641	0	0
T4	13156	12972	0	0
T5	25666	25149	0	0
T8	11548	11318	0	0
T9	77887	76249	0	0
T10	15818	15513	0	0
T11	25459	24934	0	0
T12	132921	132372	0	0