Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 7891091 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 7655549 1 T1 649 T2 1072 T3 177



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 9102312 1 T1 1820 T2 2183 T3 397
values[0x0] 2443653 1 T1 110 T2 113 T3 99
values[0x1] 4000675 1 T1 99 T2 153 T3 118



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 5116938 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 10429702 1 T1 1004 T2 1423 T3 272



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 51310 1 T1 3 T2 21 T10 16
valid_sources[0x01] 51414 1 T1 2 T2 3 T10 7
valid_sources[0x02] 54818 1 T1 8 T2 9 T10 12
valid_sources[0x03] 63603 1 T1 12 T2 18 T10 10
valid_sources[0x04] 79158 1 T1 4 T2 7 T10 10
valid_sources[0x05] 65783 1 T1 7 T2 6 T10 4
valid_sources[0x06] 56990 1 T1 10 T2 7 T10 19
valid_sources[0x07] 64962 1 T1 8 T2 10 T10 12
valid_sources[0x08] 64519 1 T1 21 T2 18 T10 10
valid_sources[0x09] 54155 1 T1 10 T2 13 T10 5
valid_sources[0x0a] 53611 1 T1 5 T2 11 T10 11
valid_sources[0x0b] 54163 1 T1 13 T2 12 T10 15
valid_sources[0x0c] 57868 1 T1 2 T2 9 T10 15
valid_sources[0x0d] 54883 1 T1 8 T2 15 T10 11
valid_sources[0x0e] 59290 1 T1 13 T2 26 T10 16
valid_sources[0x0f] 56177 1 T1 26 T2 14 T10 11
valid_sources[0x10] 61201 1 T1 3 T2 7 T10 16
valid_sources[0x11] 58560 1 T1 8 T2 6 T10 7
valid_sources[0x12] 93653 1 T1 8 T2 11 T10 12
valid_sources[0x13] 63366 1 T1 1 T2 10 T10 11
valid_sources[0x14] 57956 1 T1 1 T2 15 T10 18
valid_sources[0x15] 57626 1 T2 6 T10 13 T11 21
valid_sources[0x16] 57820 1 T1 9 T2 18 T10 8
valid_sources[0x17] 51884 1 T1 6 T2 6 T10 6
valid_sources[0x18] 58291 1 T1 10 T2 6 T10 17
valid_sources[0x19] 78765 1 T1 2 T2 5 T10 10
valid_sources[0x1a] 50849 1 T1 18 T2 2 T10 13
valid_sources[0x1b] 57498 1 T1 10 T2 14 T10 7
valid_sources[0x1c] 55172 1 T1 15 T2 4 T10 17
valid_sources[0x1d] 55637 1 T1 9 T2 23 T10 17
valid_sources[0x1e] 63529 1 T1 4 T2 18 T10 11
valid_sources[0x1f] 82317 1 T1 5 T2 4 T10 13
valid_sources[0x20] 67099 1 T1 9 T2 10 T10 12
valid_sources[0x21] 67028 1 T1 13 T2 8 T10 11
valid_sources[0x22] 66568 1 T1 3 T2 6 T10 4
valid_sources[0x23] 64284 1 T1 10 T2 7 T10 12
valid_sources[0x24] 55626 1 T1 18 T2 9 T10 9
valid_sources[0x25] 64459 1 T1 1 T2 10 T8 968
valid_sources[0x26] 64588 1 T1 18 T2 7 T10 5
valid_sources[0x27] 149888 1 T2 16 T10 7 T11 25
valid_sources[0x28] 60480 1 T1 13 T2 3 T10 6
valid_sources[0x29] 56740 1 T2 11 T10 10 T11 27
valid_sources[0x2a] 54559 1 T2 14 T10 10 T11 33
valid_sources[0x2b] 67910 1 T1 15 T2 9 T9 10710
valid_sources[0x2c] 53770 1 T1 8 T2 12 T10 14
valid_sources[0x2d] 57557 1 T1 7 T2 13 T10 12
valid_sources[0x2e] 52475 1 T2 10 T10 10 T11 20
valid_sources[0x2f] 53319 1 T1 12 T2 7 T10 11
valid_sources[0x30] 52439 1 T1 12 T2 9 T10 14
valid_sources[0x31] 73761 1 T1 7 T2 15 T10 20
valid_sources[0x32] 58104 1 T1 28 T2 6 T10 12
valid_sources[0x33] 53235 1 T1 6 T2 13 T10 9
valid_sources[0x34] 59810 1 T1 34 T2 13 T10 10
valid_sources[0x35] 54671 1 T1 1 T10 8 T11 35
valid_sources[0x36] 53817 1 T1 6 T2 11 T10 6
valid_sources[0x37] 55622 1 T1 5 T2 7 T10 7
valid_sources[0x38] 56738 1 T1 3 T2 2 T10 12
valid_sources[0x39] 54720 1 T1 6 T2 16 T10 11
valid_sources[0x3a] 61775 1 T1 10 T2 10 T10 11
valid_sources[0x3b] 52626 1 T1 2 T2 17 T10 8
valid_sources[0x3c] 59057 1 T1 4 T2 5 T10 10
valid_sources[0x3d] 58925 1 T1 17 T2 6 T10 24
valid_sources[0x3e] 56503 1 T1 1 T2 9 T10 7
valid_sources[0x3f] 69336 1 T1 13 T2 9 T10 19
valid_sources[0x40] 55217 1 T1 10 T2 9 T10 11
valid_sources[0x41] 61524 1 T1 9 T2 4 T10 14
valid_sources[0x42] 62073 1 T1 13 T2 1 T10 8
valid_sources[0x43] 53182 1 T1 42 T2 10 T10 9
valid_sources[0x44] 53224 1 T1 3 T2 2 T10 11
valid_sources[0x45] 56674 1 T1 26 T2 3 T10 6
valid_sources[0x46] 57850 1 T1 6 T2 4 T10 14
valid_sources[0x47] 61203 1 T1 2 T2 1 T10 16
valid_sources[0x48] 51443 1 T1 22 T2 13 T10 19
valid_sources[0x49] 55925 1 T2 3 T10 12 T11 26
valid_sources[0x4a] 53082 1 T1 3 T2 11 T10 10
valid_sources[0x4b] 60878 1 T1 3 T2 8 T10 12
valid_sources[0x4c] 52187 1 T1 1 T2 1 T10 14
valid_sources[0x4d] 53861 1 T1 18 T2 13 T10 8
valid_sources[0x4e] 56305 1 T1 8 T2 15 T10 7
valid_sources[0x4f] 59417 1 T1 3 T2 6 T10 8
valid_sources[0x50] 52261 1 T1 3 T2 5 T10 7
valid_sources[0x51] 58720 1 T1 25 T2 11 T10 11
valid_sources[0x52] 56837 1 T1 5 T2 13 T10 16
valid_sources[0x53] 60559 1 T1 19 T2 3 T10 12
valid_sources[0x54] 50760 1 T1 14 T2 8 T10 11
valid_sources[0x55] 50587 1 T1 6 T2 20 T10 10
valid_sources[0x56] 56994 1 T1 4 T2 7 T10 5
valid_sources[0x57] 54629 1 T1 8 T2 12 T10 5
valid_sources[0x58] 57574 1 T1 17 T2 11 T10 5
valid_sources[0x59] 51596 1 T1 2 T2 7 T10 10
valid_sources[0x5a] 58470 1 T1 9 T2 14 T10 8
valid_sources[0x5b] 60544 1 T1 5 T2 11 T10 11
valid_sources[0x5c] 60316 1 T1 13 T2 4 T10 18
valid_sources[0x5d] 59904 1 T1 4 T2 33 T10 18
valid_sources[0x5e] 58907 1 T1 12 T2 6 T10 16
valid_sources[0x5f] 100614 1 T1 6 T2 4 T10 9
valid_sources[0x60] 54948 1 T1 9 T2 9 T10 20
valid_sources[0x61] 54740 1 T1 12 T2 13 T10 10
valid_sources[0x62] 53187 1 T1 15 T2 3 T10 14
valid_sources[0x63] 58143 1 T1 5 T2 16 T10 8
valid_sources[0x64] 52946 1 T1 11 T2 4 T10 11
valid_sources[0x65] 54517 1 T1 8 T2 23 T10 12
valid_sources[0x66] 65644 1 T1 2 T2 2 T10 14
valid_sources[0x67] 57861 1 T1 2 T2 11 T10 13
valid_sources[0x68] 51579 1 T1 3 T2 28 T10 7
valid_sources[0x69] 56914 1 T1 12 T2 3 T10 9
valid_sources[0x6a] 55017 1 T1 2 T2 17 T10 11
valid_sources[0x6b] 51327 1 T1 16 T2 1 T10 4
valid_sources[0x6c] 54059 1 T2 10 T10 7 T11 24
valid_sources[0x6d] 66002 1 T1 4 T2 5 T10 9
valid_sources[0x6e] 61671 1 T1 9 T2 2 T10 10
valid_sources[0x6f] 52530 1 T2 7 T10 15 T11 25
valid_sources[0x70] 54367 1 T1 4 T2 2 T10 14
valid_sources[0x71] 58215 1 T1 4 T2 5 T10 14
valid_sources[0x72] 65142 1 T1 14 T2 17 T10 13
valid_sources[0x73] 66990 1 T1 5 T2 6 T10 7
valid_sources[0x74] 55916 1 T1 1 T2 15 T10 12
valid_sources[0x75] 65537 1 T1 7 T2 11 T10 8
valid_sources[0x76] 59594 1 T1 4 T2 7 T10 15
valid_sources[0x77] 52439 1 T1 1 T2 17 T10 13
valid_sources[0x78] 56129 1 T1 13 T2 8 T10 16
valid_sources[0x79] 58672 1 T1 23 T2 4 T10 13
valid_sources[0x7a] 106332 1 T1 15 T2 13 T10 10
valid_sources[0x7b] 57812 1 T1 29 T2 16 T10 8
valid_sources[0x7c] 54077 1 T1 7 T2 15 T10 11
valid_sources[0x7d] 59405 1 T1 32 T2 9 T10 10
valid_sources[0x7e] 114073 1 T1 8 T2 7 T10 13
valid_sources[0x7f] 59341 1 T1 3 T2 3 T10 10
valid_sources[0x80] 68528 1 T1 10 T2 4 T10 14



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 3694514 1 T1 573 T2 952 T3 93
values[0x0] all_enables biggest_size 2021999 1 T1 43 T2 63 T3 39
values[0x1] all_enables biggest_size 1939036 1 T1 33 T2 57 T3 45


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 267195 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 9444608 1 T1 40 T2 140 T4 20



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 2416632 1 T1 20 T2 70 T4 10
values[0x0] 3537500 1 T1 11 T2 32 T4 6
values[0x1] 3757671 1 T1 9 T2 38 T4 4



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 96534 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 9615269 1 T1 40 T2 140 T4 20



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 35611 1 T5 5 T68 10 T38 1
valid_sources[0x01] 38157 1 T5 5 T11 4 T29 1
valid_sources[0x02] 40093 1 T5 3 T39 1 T201 4
valid_sources[0x03] 35730 1 T5 9 T39 1 T157 1
valid_sources[0x04] 39239 1 T5 7 T39 1 T139 1
valid_sources[0x05] 36804 1 T5 11 T10 1 T29 1
valid_sources[0x06] 37642 1 T5 2 T11 1 T17 3
valid_sources[0x07] 36388 1 T5 7 T39 1 T139 2
valid_sources[0x08] 37144 1 T5 4 T106 2 T17 2
valid_sources[0x09] 35968 1 T1 2 T5 4 T106 1
valid_sources[0x0a] 35466 1 T5 8 T9 1 T11 1
valid_sources[0x0b] 39389 1 T5 2 T157 1 T139 1
valid_sources[0x0c] 35350 1 T2 24 T5 4 T106 1
valid_sources[0x0d] 34983 1 T5 5 T9 6 T139 1
valid_sources[0x0e] 38602 1 T5 6 T139 2 T17 1
valid_sources[0x0f] 35700 1 T1 1 T5 4 T39 1
valid_sources[0x10] 36464 1 T5 5 T29 1 T17 1
valid_sources[0x11] 39096 1 T5 6 T39 1 T139 1
valid_sources[0x12] 38919 1 T5 5 T17 2 T38 2
valid_sources[0x13] 38758 1 T5 1 T9 5 T17 4
valid_sources[0x14] 40608 1 T5 4 T29 3 T39 2
valid_sources[0x15] 40308 1 T5 2 T11 2 T139 1
valid_sources[0x16] 37536 1 T5 7 T17 3 T38 2
valid_sources[0x17] 40152 1 T5 9 T17 2 T13 1284
valid_sources[0x18] 39867 1 T5 6 T139 1 T68 3
valid_sources[0x19] 37246 1 T5 6 T139 2 T38 2
valid_sources[0x1a] 36285 1 T5 6 T9 3 T10 2
valid_sources[0x1b] 40838 1 T5 3 T106 1 T139 2
valid_sources[0x1c] 36577 1 T5 5 T39 1 T157 8
valid_sources[0x1d] 40626 1 T5 4 T11 4 T201 2
valid_sources[0x1e] 37208 1 T5 1 T10 2 T106 1
valid_sources[0x1f] 39001 1 T5 5 T139 1 T17 6
valid_sources[0x20] 35266 1 T5 1 T39 3 T106 5
valid_sources[0x21] 35866 1 T5 5 T10 1 T39 1
valid_sources[0x22] 39604 1 T5 8 T139 2 T17 3
valid_sources[0x23] 40591 1 T1 1 T5 6 T10 2
valid_sources[0x24] 38694 1 T5 3 T29 1 T39 1
valid_sources[0x25] 38986 1 T5 5 T11 2 T29 1
valid_sources[0x26] 38346 1 T1 1 T5 5 T29 2
valid_sources[0x27] 38728 1 T5 12 T139 1 T17 1
valid_sources[0x28] 40347 1 T5 2 T11 4 T38 1
valid_sources[0x29] 41349 1 T5 8 T17 2 T112 1
valid_sources[0x2a] 41473 1 T5 4 T10 5 T39 3
valid_sources[0x2b] 37603 1 T5 6 T29 2 T39 1
valid_sources[0x2c] 40808 1 T5 6 T10 2 T17 2
valid_sources[0x2d] 37397 1 T5 6 T17 3 T13 1194
valid_sources[0x2e] 35886 1 T5 10 T11 1 T17 6
valid_sources[0x2f] 36326 1 T5 1 T11 15 T39 2
valid_sources[0x30] 37807 1 T5 6 T39 2 T106 1
valid_sources[0x31] 36634 1 T5 10 T39 1 T139 1
valid_sources[0x32] 36144 1 T5 5 T39 2 T106 1
valid_sources[0x33] 39428 1 T5 11 T29 2 T139 2
valid_sources[0x34] 38301 1 T5 5 T39 1 T106 2
valid_sources[0x35] 36813 1 T1 2 T5 7 T39 1
valid_sources[0x36] 36398 1 T5 5 T106 1 T139 1
valid_sources[0x37] 36653 1 T5 2 T29 1 T39 1
valid_sources[0x38] 38699 1 T5 3 T11 1 T29 1
valid_sources[0x39] 36557 1 T1 2 T5 1 T10 1
valid_sources[0x3a] 36462 1 T5 6 T39 1 T17 1
valid_sources[0x3b] 38792 1 T5 12 T13 1549 T110 1
valid_sources[0x3c] 39874 1 T5 5 T29 2 T39 1
valid_sources[0x3d] 39400 1 T2 4 T5 4 T29 1
valid_sources[0x3e] 38200 1 T1 1 T5 4 T11 1
valid_sources[0x3f] 36765 1 T5 6 T29 3 T39 1
valid_sources[0x40] 38671 1 T5 5 T39 3 T139 3
valid_sources[0x41] 33366 1 T5 8 T11 2 T39 1
valid_sources[0x42] 37009 1 T5 13 T39 1 T17 2
valid_sources[0x43] 38668 1 T5 5 T29 1 T17 1
valid_sources[0x44] 37424 1 T5 4 T139 5 T17 2
valid_sources[0x45] 37847 1 T5 6 T29 2 T39 2
valid_sources[0x46] 34757 1 T5 4 T39 1 T42 40
valid_sources[0x47] 38726 1 T5 4 T29 1 T39 1
valid_sources[0x48] 36282 1 T5 4 T139 1 T13 1887
valid_sources[0x49] 38921 1 T5 1 T39 1 T106 1
valid_sources[0x4a] 39880 1 T5 4 T39 1 T17 1
valid_sources[0x4b] 39597 1 T5 6 T29 1 T39 1
valid_sources[0x4c] 35237 1 T5 5 T29 1 T139 1
valid_sources[0x4d] 36856 1 T5 5 T9 8 T11 1
valid_sources[0x4e] 38405 1 T5 3 T39 2 T139 1
valid_sources[0x4f] 38406 1 T5 8 T39 1 T17 1
valid_sources[0x50] 39020 1 T5 6 T9 1 T39 2
valid_sources[0x51] 36409 1 T5 1 T11 5 T157 1
valid_sources[0x52] 39252 1 T5 6 T39 1 T139 2
valid_sources[0x53] 35326 1 T5 7 T29 3 T39 1
valid_sources[0x54] 40213 1 T5 5 T9 3 T10 1
valid_sources[0x55] 37760 1 T5 3 T11 7 T39 1
valid_sources[0x56] 37299 1 T5 1 T10 2 T106 2
valid_sources[0x57] 38654 1 T5 2 T11 2 T39 2
valid_sources[0x58] 38225 1 T5 5 T39 2 T106 1
valid_sources[0x59] 37663 1 T5 7 T17 2 T38 2
valid_sources[0x5a] 40360 1 T5 4 T29 1 T39 1
valid_sources[0x5b] 37910 1 T5 8 T139 2 T17 1
valid_sources[0x5c] 40686 1 T5 7 T11 3 T29 4
valid_sources[0x5d] 38870 1 T1 1 T5 6 T13 1682
valid_sources[0x5e] 38309 1 T5 9 T39 2 T17 2
valid_sources[0x5f] 39643 1 T5 4 T11 4 T39 1
valid_sources[0x60] 37692 1 T5 2 T9 8 T29 1
valid_sources[0x61] 39444 1 T1 1 T5 3 T10 2
valid_sources[0x62] 36833 1 T5 6 T11 2 T139 1
valid_sources[0x63] 36105 1 T1 1 T5 8 T10 1
valid_sources[0x64] 40242 1 T5 9 T17 4 T13 2124
valid_sources[0x65] 40469 1 T5 3 T139 1 T17 3
valid_sources[0x66] 37647 1 T5 3 T29 2 T39 1
valid_sources[0x67] 35845 1 T5 5 T9 1 T29 1
valid_sources[0x68] 37420 1 T5 3 T11 1 T39 1
valid_sources[0x69] 37315 1 T5 6 T29 1 T39 1
valid_sources[0x6a] 36509 1 T5 4 T139 4 T17 1
valid_sources[0x6b] 37453 1 T5 6 T39 2 T201 2
valid_sources[0x6c] 39362 1 T1 1 T5 2 T9 6
valid_sources[0x6d] 38881 1 T5 3 T106 1 T157 3
valid_sources[0x6e] 36438 1 T5 4 T39 1 T139 1
valid_sources[0x6f] 38913 1 T5 5 T29 1 T17 4
valid_sources[0x70] 38337 1 T5 7 T39 1 T106 7
valid_sources[0x71] 36313 1 T5 4 T39 2 T13 1045
valid_sources[0x72] 37230 1 T5 6 T10 4 T11 5
valid_sources[0x73] 36308 1 T5 6 T10 1 T201 10
valid_sources[0x74] 40263 1 T5 10 T139 1 T17 1
valid_sources[0x75] 38375 1 T5 15 T11 2 T29 1
valid_sources[0x76] 40551 1 T2 18 T5 5 T39 3
valid_sources[0x77] 38942 1 T5 1 T10 6 T11 1
valid_sources[0x78] 34111 1 T5 6 T39 1 T13 330
valid_sources[0x79] 36176 1 T1 1 T5 3 T11 1
valid_sources[0x7a] 41693 1 T5 5 T29 2 T39 1
valid_sources[0x7b] 38705 1 T5 4 T9 16 T17 1
valid_sources[0x7c] 38146 1 T5 1 T29 1 T39 1
valid_sources[0x7d] 35348 1 T2 33 T5 5 T39 1
valid_sources[0x7e] 40701 1 T5 6 T201 17 T139 2
valid_sources[0x7f] 40107 1 T1 1 T5 4 T11 2
valid_sources[0x80] 40656 1 T1 1 T5 4 T29 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 2402345 1 T1 20 T2 70 T4 10
values[0x0] all_enables biggest_size 3519157 1 T1 11 T2 32 T4 6
values[0x1] all_enables biggest_size 3523106 1 T1 9 T2 38 T4 4

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%