Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

27244207

1

T1

1380

T2

1377

T3

437

full_word

8826857

1

T1

649

T2

1072

T3

177

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	36070764	1			T1	2029		T2	2449		T3	614
auto[TlIntgErrCmd]	103	1			T261	5		T262	4		T263	4
auto[TlIntgErrData]	102	1			T261	4		T262	2		T263	2
auto[TlIntgErrBoth]	95	1			T261	1		T262	4		T263	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10507684

1

T1

1820

T2

2183

T3

397

auto[1]

25563380

1

T1

209

T2

266

T3

217

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6670002	1			T1	1247		T2	1231		T3	304
auto[TlIntgErrNone]	partial	auto[1]	20573932	1			T1	133		T2	146		T3	133
auto[TlIntgErrNone]	full_word	auto[0]	3837554	1			T1	573		T2	952		T3	93
auto[TlIntgErrNone]	full_word	auto[1]	4989276	1			T1	76		T2	120		T3	84
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T261	3		T262	1		T263	4
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T261	2		T262	3		T266	6
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T339	1		T343	2		T344	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T345	1		T346	1		T347	1
auto[TlIntgErrData]	partial	auto[0]	42	1			T261	2		T262	1		T263	2
auto[TlIntgErrData]	partial	auto[1]	50	1			T261	1		T262	1		T266	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T261	1		T340	2		T346	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T341	1		T339	1		T342	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T262	2		T263	3		T266	3
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T261	1		T262	1		T263	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T340	1		T348	1		T349	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T262	1		T338	1		T339	1